2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9480 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
52 #define AR5416_AR9100_DEVID 0x000b
54 #define AR_SUBVENDOR_ID_NOG 0x0e11
55 #define AR_SUBVENDOR_ID_NEW_A 0x7065
56 #define AR5416_MAGIC 0x19641014
58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
62 #define AR9300_NUM_BT_WEIGHTS 4
63 #define AR9300_NUM_WLAN_WEIGHTS 4
65 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
67 #define ATH_DEFAULT_NOISE_FLOOR -95
69 #define ATH9K_RSSI_BAD -128
71 #define ATH9K_NUM_CHANNELS 38
73 /* Register read/write primitives */
74 #define REG_WRITE(_ah, _reg, _val) \
75 (_ah)->reg_ops.write((_ah), (_val), (_reg))
77 #define REG_READ(_ah, _reg) \
78 (_ah)->reg_ops.read((_ah), (_reg))
80 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
81 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
83 #define REG_RMW(_ah, _reg, _set, _clr) \
84 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
86 #define ENABLE_REGWRITE_BUFFER(_ah) \
88 if ((_ah)->reg_ops.enable_write_buffer) \
89 (_ah)->reg_ops.enable_write_buffer((_ah)); \
92 #define REGWRITE_BUFFER_FLUSH(_ah) \
94 if ((_ah)->reg_ops.write_flush) \
95 (_ah)->reg_ops.write_flush((_ah)); \
98 #define PR_EEP(_s, _val) \
100 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
104 #define SM(_v, _f) (((_v) << _f##_S) & _f)
105 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
106 #define REG_RMW_FIELD(_a, _r, _f, _v) \
107 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
108 #define REG_READ_FIELD(_a, _r, _f) \
109 (((REG_READ(_a, _r) & _f) >> _f##_S))
110 #define REG_SET_BIT(_a, _r, _f) \
111 REG_RMW(_a, _r, (_f), 0)
112 #define REG_CLR_BIT(_a, _r, _f) \
113 REG_RMW(_a, _r, 0, (_f))
115 #define DO_DELAY(x) do { \
116 if (((++(x) % 64) == 0) && \
117 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
122 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
123 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
125 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
128 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
129 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133 #define AR_GPIOD_MASK 0x00001FFF
134 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
136 #define BASE_ACTIVATE_DELAY 100
137 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
138 #define COEF_SCALE_S 24
139 #define HT40_CHANNEL_CENTER_SHIFT 10
141 #define ATH9K_ANTENNA0_CHAINMASK 0x1
142 #define ATH9K_ANTENNA1_CHAINMASK 0x2
144 #define ATH9K_NUM_DMA_DEBUG_REGS 8
145 #define ATH9K_NUM_QUEUES 10
147 #define MAX_RATE_POWER 63
148 #define AH_WAIT_TIMEOUT 100000 /* (us) */
149 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
150 #define AH_TIME_QUANTUM 10
151 #define AR_KEYTABLE_SIZE 128
152 #define POWER_UP_TIME 10000
153 #define SPUR_RSSI_THRESH 40
154 #define UPPER_5G_SUB_BAND_START 5700
155 #define MID_5G_SUB_BAND_START 5400
157 #define CAB_TIMEOUT_VAL 10
158 #define BEACON_TIMEOUT_VAL 10
159 #define MIN_BEACON_TIMEOUT_VAL 1
162 #define INIT_CONFIG_STATUS 0x00000000
163 #define INIT_RSSI_THR 0x00000700
164 #define INIT_BCON_CNTRL_REG 0x00000000
166 #define TU_TO_USEC(_tu) ((_tu) << 10)
168 #define ATH9K_HW_RX_HP_QDEPTH 16
169 #define ATH9K_HW_RX_LP_QDEPTH 128
171 #define PAPRD_GAIN_TABLE_ENTRIES 32
172 #define PAPRD_TABLE_SZ 24
173 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
175 enum ath_hw_txq_subtype
{
182 enum ath_ini_subsys
{
190 ATH9K_HW_CAP_HT
= BIT(0),
191 ATH9K_HW_CAP_RFSILENT
= BIT(1),
192 ATH9K_HW_CAP_CST
= BIT(2),
193 ATH9K_HW_CAP_AUTOSLEEP
= BIT(4),
194 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(5),
195 ATH9K_HW_CAP_EDMA
= BIT(6),
196 ATH9K_HW_CAP_RAC_SUPPORTED
= BIT(7),
197 ATH9K_HW_CAP_LDPC
= BIT(8),
198 ATH9K_HW_CAP_FASTCLOCK
= BIT(9),
199 ATH9K_HW_CAP_SGI_20
= BIT(10),
200 ATH9K_HW_CAP_PAPRD
= BIT(11),
201 ATH9K_HW_CAP_ANT_DIV_COMB
= BIT(12),
202 ATH9K_HW_CAP_2GHZ
= BIT(13),
203 ATH9K_HW_CAP_5GHZ
= BIT(14),
204 ATH9K_HW_CAP_APM
= BIT(15),
207 struct ath9k_hw_capabilities
{
208 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
221 bool pcie_lcr_extsync_en
;
224 struct ath9k_ops_config
{
225 int dma_beacon_response_time
;
226 int sw_beacon_response_time
;
227 int additional_swba_backoff
;
229 u32 cwm_ignore_extcca
;
230 bool pcieSerDesWrite
;
240 int serialize_regmode
;
241 bool rx_intr_mitigation
;
242 bool tx_intr_mitigation
;
243 #define SPUR_DISABLE 0
244 #define SPUR_ENABLE_IOCTL 1
245 #define SPUR_ENABLE_EEPROM 2
246 #define AR_SPUR_5413_1 1640
247 #define AR_SPUR_5413_2 1200
248 #define AR_NO_SPUR 0x8000
249 #define AR_BASE_FREQ_2GHZ 2300
250 #define AR_BASE_FREQ_5GHZ 4900
251 #define AR_SPUR_FEEQ_BOUND_HT40 19
252 #define AR_SPUR_FEEQ_BOUND_HT20 10
254 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
256 u16 ani_poll_interval
; /* ANI poll interval in ms */
260 ATH9K_INT_RX
= 0x00000001,
261 ATH9K_INT_RXDESC
= 0x00000002,
262 ATH9K_INT_RXHP
= 0x00000001,
263 ATH9K_INT_RXLP
= 0x00000002,
264 ATH9K_INT_RXNOFRM
= 0x00000008,
265 ATH9K_INT_RXEOL
= 0x00000010,
266 ATH9K_INT_RXORN
= 0x00000020,
267 ATH9K_INT_TX
= 0x00000040,
268 ATH9K_INT_TXDESC
= 0x00000080,
269 ATH9K_INT_TIM_TIMER
= 0x00000100,
270 ATH9K_INT_BB_WATCHDOG
= 0x00000400,
271 ATH9K_INT_TXURN
= 0x00000800,
272 ATH9K_INT_MIB
= 0x00001000,
273 ATH9K_INT_RXPHY
= 0x00004000,
274 ATH9K_INT_RXKCM
= 0x00008000,
275 ATH9K_INT_SWBA
= 0x00010000,
276 ATH9K_INT_BMISS
= 0x00040000,
277 ATH9K_INT_BNR
= 0x00100000,
278 ATH9K_INT_TIM
= 0x00200000,
279 ATH9K_INT_DTIM
= 0x00400000,
280 ATH9K_INT_DTIMSYNC
= 0x00800000,
281 ATH9K_INT_GPIO
= 0x01000000,
282 ATH9K_INT_CABEND
= 0x02000000,
283 ATH9K_INT_TSFOOR
= 0x04000000,
284 ATH9K_INT_GENTIMER
= 0x08000000,
285 ATH9K_INT_CST
= 0x10000000,
286 ATH9K_INT_GTT
= 0x20000000,
287 ATH9K_INT_FATAL
= 0x40000000,
288 ATH9K_INT_GLOBAL
= 0x80000000,
289 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
294 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
306 ATH9K_INT_NOCARD
= 0xffffffff
309 #define CHANNEL_CW_INT 0x00002
310 #define CHANNEL_CCK 0x00020
311 #define CHANNEL_OFDM 0x00040
312 #define CHANNEL_2GHZ 0x00080
313 #define CHANNEL_5GHZ 0x00100
314 #define CHANNEL_PASSIVE 0x00200
315 #define CHANNEL_DYN 0x00400
316 #define CHANNEL_HALF 0x04000
317 #define CHANNEL_QUARTER 0x08000
318 #define CHANNEL_HT20 0x10000
319 #define CHANNEL_HT40PLUS 0x20000
320 #define CHANNEL_HT40MINUS 0x40000
322 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
323 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
324 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
325 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
326 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
327 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
328 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
329 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
330 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
331 #define CHANNEL_ALL \
340 struct ath9k_hw_cal_data
{
348 bool nfcal_interference
;
349 u16 small_signal_gain
[AR9300_MAX_CHAINS
];
350 u32 pa_table
[AR9300_MAX_CHAINS
][PAPRD_TABLE_SZ
];
351 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
354 struct ath9k_channel
{
355 struct ieee80211_channel
*chan
;
356 struct ar5416AniState ani
;
363 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
364 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
365 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
367 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
368 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
369 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
370 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
371 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
372 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
373 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
374 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
376 /* These macros check chanmode and not channelFlags */
377 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
378 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
379 ((_c)->chanmode == CHANNEL_G_HT20))
380 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
381 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
382 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
384 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
386 enum ath9k_power_mode
{
389 ATH9K_PM_NETWORK_SLEEP
,
394 SER_REG_MODE_OFF
= 0,
396 SER_REG_MODE_AUTO
= 2,
399 enum ath9k_rx_qtype
{
405 struct ath9k_beacon_state
{
409 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
412 u16 bs_cfpmaxduration
;
415 u16 bs_bmissthreshold
;
416 u32 bs_sleepduration
;
417 u32 bs_tsfoor_threshold
;
420 struct chan_centers
{
427 ATH9K_RESET_POWER_ON
,
432 struct ath9k_hw_version
{
441 enum ath_usb_dev usbdev
;
444 /* Generic TSF timer definitions */
446 #define ATH_MAX_GEN_TIMER 16
448 #define AR_GENTMR_BIT(_index) (1 << (_index))
451 * Using de Bruijin sequence to look up 1's index in a 32 bit number
452 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
454 #define debruijn32 0x077CB531U
456 struct ath_gen_timer_configuration
{
463 struct ath_gen_timer
{
464 void (*trigger
)(void *arg
);
465 void (*overflow
)(void *arg
);
470 struct ath_gen_timer_table
{
471 u32 gen_timer_index
[32];
472 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
474 unsigned long timer_bits
;
479 struct ath_hw_antcomb_conf
{
490 * struct ath_hw_radar_conf - radar detection initialization parameters
492 * @pulse_inband: threshold for checking the ratio of in-band power
493 * to total power for short radar pulses (half dB steps)
494 * @pulse_inband_step: threshold for checking an in-band power to total
495 * power ratio increase for short radar pulses (half dB steps)
496 * @pulse_height: threshold for detecting the beginning of a short
497 * radar pulse (dB step)
498 * @pulse_rssi: threshold for detecting if a short radar pulse is
500 * @pulse_maxlen: maximum pulse length (0.8 us steps)
502 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
503 * @radar_inband: threshold for checking the ratio of in-band power
504 * to total power for long radar pulses (half dB steps)
505 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
507 * @ext_channel: enable extension channel radar detection
509 struct ath_hw_radar_conf
{
510 unsigned int pulse_inband
;
511 unsigned int pulse_inband_step
;
512 unsigned int pulse_height
;
513 unsigned int pulse_rssi
;
514 unsigned int pulse_maxlen
;
516 unsigned int radar_rssi
;
517 unsigned int radar_inband
;
524 * struct ath_hw_private_ops - callbacks used internally by hardware code
526 * This structure contains private callbacks designed to only be used internally
527 * by the hardware core.
529 * @init_cal_settings: setup types of calibrations supported
530 * @init_cal: starts actual calibration
532 * @init_mode_regs: Initializes mode registers
533 * @init_mode_gain_regs: Initialize TX/RX gain registers
535 * @rf_set_freq: change frequency
536 * @spur_mitigate_freq: spur mitigation
537 * @rf_alloc_ext_banks:
538 * @rf_free_ext_banks:
540 * @compute_pll_control: compute the PLL control value to use for
541 * AR_RTC_PLL_CONTROL for a given channel
542 * @setup_calibration: set up calibration
543 * @iscal_supported: used to query if a type of calibration is supported
545 * @ani_cache_ini_regs: cache the values for ANI from the initial
546 * register settings through the register initialization.
548 struct ath_hw_private_ops
{
549 /* Calibration ops */
550 void (*init_cal_settings
)(struct ath_hw
*ah
);
551 bool (*init_cal
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
553 void (*init_mode_regs
)(struct ath_hw
*ah
);
554 void (*init_mode_gain_regs
)(struct ath_hw
*ah
);
555 void (*setup_calibration
)(struct ath_hw
*ah
,
556 struct ath9k_cal_list
*currCal
);
559 int (*rf_set_freq
)(struct ath_hw
*ah
,
560 struct ath9k_channel
*chan
);
561 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
562 struct ath9k_channel
*chan
);
563 int (*rf_alloc_ext_banks
)(struct ath_hw
*ah
);
564 void (*rf_free_ext_banks
)(struct ath_hw
*ah
);
565 bool (*set_rf_regs
)(struct ath_hw
*ah
,
566 struct ath9k_channel
*chan
,
568 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
569 void (*init_bb
)(struct ath_hw
*ah
,
570 struct ath9k_channel
*chan
);
571 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
572 void (*olc_init
)(struct ath_hw
*ah
);
573 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
574 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
575 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
576 bool (*rfbus_req
)(struct ath_hw
*ah
);
577 void (*rfbus_done
)(struct ath_hw
*ah
);
578 void (*restore_chainmask
)(struct ath_hw
*ah
);
579 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
580 struct ath9k_channel
*chan
);
581 bool (*ani_control
)(struct ath_hw
*ah
, enum ath9k_ani_cmd cmd
,
583 void (*do_getnf
)(struct ath_hw
*ah
, int16_t nfarray
[NUM_NF_READINGS
]);
584 void (*set_radar_params
)(struct ath_hw
*ah
,
585 struct ath_hw_radar_conf
*conf
);
588 void (*ani_cache_ini_regs
)(struct ath_hw
*ah
);
592 * struct ath_hw_ops - callbacks used by hardware code and driver code
594 * This structure contains callbacks designed to to be used internally by
595 * hardware code and also by the lower level driver.
597 * @config_pci_powersave:
598 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
601 void (*config_pci_powersave
)(struct ath_hw
*ah
,
603 void (*rx_enable
)(struct ath_hw
*ah
);
604 void (*set_desc_link
)(void *ds
, u32 link
);
605 bool (*calibrate
)(struct ath_hw
*ah
,
606 struct ath9k_channel
*chan
,
609 bool (*get_isr
)(struct ath_hw
*ah
, enum ath9k_int
*masked
);
610 void (*set_txdesc
)(struct ath_hw
*ah
, void *ds
,
611 struct ath_tx_info
*i
);
612 int (*proc_txdesc
)(struct ath_hw
*ah
, void *ds
,
613 struct ath_tx_status
*ts
);
614 void (*antdiv_comb_conf_get
)(struct ath_hw
*ah
,
615 struct ath_hw_antcomb_conf
*antconf
);
616 void (*antdiv_comb_conf_set
)(struct ath_hw
*ah
,
617 struct ath_hw_antcomb_conf
*antconf
);
621 struct ath_nf_limits
{
628 #define AH_USE_EEPROM 0x1
629 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
632 struct ath_ops reg_ops
;
634 struct ieee80211_hw
*hw
;
635 struct ath_common common
;
636 struct ath9k_hw_version hw_version
;
637 struct ath9k_ops_config config
;
638 struct ath9k_hw_capabilities caps
;
639 struct ath9k_channel channels
[ATH9K_NUM_CHANNELS
];
640 struct ath9k_channel
*curchan
;
643 struct ar5416_eeprom_def def
;
644 struct ar5416_eeprom_4k map4k
;
645 struct ar9287_eeprom map9287
;
646 struct ar9300_eeprom ar9300_eep
;
648 const struct eeprom_ops
*eep_ops
;
654 bool need_an_top2_fixup
;
658 struct ath_nf_limits nf_2g
;
659 struct ath_nf_limits nf_5g
;
667 enum nl80211_iftype opmode
;
668 enum ath9k_power_mode power_mode
;
671 struct ath9k_hw_cal_data
*caldata
;
672 struct ath9k_pacal_info pacal_info
;
673 struct ar5416Stats stats
;
674 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
676 int16_t curchan_rad_index
;
677 enum ath9k_int imask
;
679 u32 txok_interrupt_mask
;
680 u32 txerr_interrupt_mask
;
681 u32 txdesc_interrupt_mask
;
682 u32 txeol_interrupt_mask
;
683 u32 txurn_interrupt_mask
;
684 atomic_t intr_ref_cnt
;
690 struct ath9k_cal_list iq_caldata
;
691 struct ath9k_cal_list adcgain_caldata
;
692 struct ath9k_cal_list adcdc_caldata
;
693 struct ath9k_cal_list tempCompCalData
;
694 struct ath9k_cal_list
*cal_list
;
695 struct ath9k_cal_list
*cal_list_last
;
696 struct ath9k_cal_list
*cal_list_curr
;
697 #define totalPowerMeasI meas0.unsign
698 #define totalPowerMeasQ meas1.unsign
699 #define totalIqCorrMeas meas2.sign
700 #define totalAdcIOddPhase meas0.unsign
701 #define totalAdcIEvenPhase meas1.unsign
702 #define totalAdcQOddPhase meas2.unsign
703 #define totalAdcQEvenPhase meas3.unsign
704 #define totalAdcDcOffsetIOddPhase meas0.sign
705 #define totalAdcDcOffsetIEvenPhase meas1.sign
706 #define totalAdcDcOffsetQOddPhase meas2.sign
707 #define totalAdcDcOffsetQEvenPhase meas3.sign
709 u32 unsign
[AR5416_MAX_CHAINS
];
710 int32_t sign
[AR5416_MAX_CHAINS
];
713 u32 unsign
[AR5416_MAX_CHAINS
];
714 int32_t sign
[AR5416_MAX_CHAINS
];
717 u32 unsign
[AR5416_MAX_CHAINS
];
718 int32_t sign
[AR5416_MAX_CHAINS
];
721 u32 unsign
[AR5416_MAX_CHAINS
];
722 int32_t sign
[AR5416_MAX_CHAINS
];
726 u32 sta_id1_defaults
;
732 } enable_32kHz_clock
;
734 /* Private to hardware code */
735 struct ath_hw_private_ops private_ops
;
736 /* Accessed by the lower level driver */
737 struct ath_hw_ops ops
;
739 /* Used to program the radio on non single-chip devices */
740 u32
*analogBank0Data
;
741 u32
*analogBank1Data
;
742 u32
*analogBank2Data
;
743 u32
*analogBank3Data
;
744 u32
*analogBank6Data
;
745 u32
*analogBank6TPCData
;
746 u32
*analogBank7Data
;
758 int totalSizeDesired
[5];
762 enum ath9k_ani_cmd ani_function
;
764 /* Bluetooth coexistance */
765 struct ath_btcoex_hw btcoex_hw
;
766 u32 bt_coex_bt_weight
[AR9300_NUM_BT_WEIGHTS
];
767 u32 bt_coex_wlan_weight
[AR9300_NUM_WLAN_WEIGHTS
];
773 struct ath_hw_radar_conf radar_conf
;
775 u32 originalGain
[22];
782 struct ar5416IniArray iniModes
;
783 struct ar5416IniArray iniCommon
;
784 struct ar5416IniArray iniBank0
;
785 struct ar5416IniArray iniBB_RfGain
;
786 struct ar5416IniArray iniBank1
;
787 struct ar5416IniArray iniBank2
;
788 struct ar5416IniArray iniBank3
;
789 struct ar5416IniArray iniBank6
;
790 struct ar5416IniArray iniBank6TPC
;
791 struct ar5416IniArray iniBank7
;
792 struct ar5416IniArray iniAddac
;
793 struct ar5416IniArray iniPcieSerdes
;
794 struct ar5416IniArray iniPcieSerdesLowPower
;
795 struct ar5416IniArray iniModesAdditional
;
796 struct ar5416IniArray iniModesAdditional_40M
;
797 struct ar5416IniArray iniModesRxGain
;
798 struct ar5416IniArray iniModesTxGain
;
799 struct ar5416IniArray iniModes_9271_1_0_only
;
800 struct ar5416IniArray iniCckfirNormal
;
801 struct ar5416IniArray iniCckfirJapan2484
;
802 struct ar5416IniArray ini_japan2484
;
803 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271
;
804 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271
;
805 struct ar5416IniArray iniModes_9271_ANI_reg
;
806 struct ar5416IniArray iniModes_high_power_tx_gain_9271
;
807 struct ar5416IniArray iniModes_normal_power_tx_gain_9271
;
808 struct ar5416IniArray ini_radio_post_sys2ant
;
809 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR
;
811 struct ar5416IniArray iniMac
[ATH_INI_NUM_SPLIT
];
812 struct ar5416IniArray iniBB
[ATH_INI_NUM_SPLIT
];
813 struct ar5416IniArray iniRadio
[ATH_INI_NUM_SPLIT
];
814 struct ar5416IniArray iniSOC
[ATH_INI_NUM_SPLIT
];
816 u32 intr_gen_timer_trigger
;
817 u32 intr_gen_timer_thresh
;
818 struct ath_gen_timer_table hw_gen_timers
;
820 struct ar9003_txs
*ts_ring
;
827 u32 bb_watchdog_last_status
;
828 u32 bb_watchdog_timeout_ms
; /* in ms, 0 to disable */
829 u8 bb_hang_rx_ofdm
; /* true if bb hang due to rx_ofdm */
831 unsigned int paprd_target_power
;
832 unsigned int paprd_training_power
;
833 unsigned int paprd_ratemask
;
834 unsigned int paprd_ratemask_ht40
;
835 bool paprd_table_write_done
;
836 u32 paprd_gain_table_entries
[PAPRD_GAIN_TABLE_ENTRIES
];
837 u8 paprd_gain_table_index
[PAPRD_GAIN_TABLE_ENTRIES
];
839 * Store the permanent value of Reg 0x4004in WARegVal
840 * so we dont have to R/M/W. We should not be reading
841 * this register when in sleep states.
845 /* Enterprise mode cap */
849 int (*get_mac_revision
)(void);
850 int (*external_reset
)(void);
854 enum ath_bus_type ath_bus_type
;
855 void (*read_cachesize
)(struct ath_common
*common
, int *csz
);
856 bool (*eeprom_read
)(struct ath_common
*common
, u32 off
, u16
*data
);
857 void (*bt_coex_prep
)(struct ath_common
*common
);
858 void (*extn_synch_en
)(struct ath_common
*common
);
859 void (*aspm_init
)(struct ath_common
*common
);
862 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
867 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
869 return &(ath9k_hw_common(ah
)->regulatory
);
872 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
874 return &ah
->private_ops
;
877 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
882 static inline u8
get_streams(int mask
)
884 return !!(mask
& BIT(0)) + !!(mask
& BIT(1)) + !!(mask
& BIT(2));
887 /* Initialization, Detach, Reset */
888 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
889 void ath9k_hw_deinit(struct ath_hw
*ah
);
890 int ath9k_hw_init(struct ath_hw
*ah
);
891 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
892 struct ath9k_hw_cal_data
*caldata
, bool bChannelChange
);
893 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
894 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
896 /* GPIO / RFKILL / Antennae */
897 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
898 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
899 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
901 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
902 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
903 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
905 /* General Operation */
906 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
907 void ath9k_hw_write_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
908 int column
, unsigned int *writecnt
);
909 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
910 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
912 u32 frameLen
, u16 rateix
, bool shortPreamble
);
913 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
914 struct ath9k_channel
*chan
,
915 struct chan_centers
*centers
);
916 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
917 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
918 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
919 bool ath9k_hw_disable(struct ath_hw
*ah
);
920 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
);
921 void ath9k_hw_setopmode(struct ath_hw
*ah
);
922 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
923 void ath9k_hw_setbssidmask(struct ath_hw
*ah
);
924 void ath9k_hw_write_associd(struct ath_hw
*ah
);
925 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
926 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
927 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
928 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
929 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
930 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
931 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
);
932 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
933 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
934 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
935 const struct ath9k_beacon_state
*bs
);
936 bool ath9k_hw_check_alive(struct ath_hw
*ah
);
938 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
940 /* Generic hw timer primitives */
941 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
942 void (*trigger
)(void *),
943 void (*overflow
)(void *),
946 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
947 struct ath_gen_timer
*timer
,
950 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
952 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
953 void ath_gen_timer_isr(struct ath_hw
*hw
);
955 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
958 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
);
961 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
962 u32
*coef_mantissa
, u32
*coef_exponent
);
963 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
966 * Code Specific to AR5008, AR9001 or AR9002,
967 * we stuff these here to avoid callbacks for AR9003.
969 void ar9002_hw_cck_chan14_spread(struct ath_hw
*ah
);
970 int ar9002_hw_rf_claim(struct ath_hw
*ah
);
971 void ar9002_hw_enable_async_fifo(struct ath_hw
*ah
);
974 * Code specific to AR9003, we stuff these here to avoid callbacks
977 void ar9003_hw_bb_watchdog_config(struct ath_hw
*ah
);
978 void ar9003_hw_bb_watchdog_read(struct ath_hw
*ah
);
979 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw
*ah
);
980 void ar9003_hw_disable_phy_restart(struct ath_hw
*ah
);
981 void ar9003_paprd_enable(struct ath_hw
*ah
, bool val
);
982 void ar9003_paprd_populate_single_table(struct ath_hw
*ah
,
983 struct ath9k_hw_cal_data
*caldata
,
985 int ar9003_paprd_create_curve(struct ath_hw
*ah
,
986 struct ath9k_hw_cal_data
*caldata
, int chain
);
987 int ar9003_paprd_setup_gain_table(struct ath_hw
*ah
, int chain
);
988 int ar9003_paprd_init_table(struct ath_hw
*ah
);
989 bool ar9003_paprd_is_done(struct ath_hw
*ah
);
990 void ar9003_hw_set_paprd_txdesc(struct ath_hw
*ah
, void *ds
, u8 chains
);
992 /* Hardware family op attach helpers */
993 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
994 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
995 void ar9003_hw_attach_phy_ops(struct ath_hw
*ah
);
997 void ar9002_hw_attach_calib_ops(struct ath_hw
*ah
);
998 void ar9003_hw_attach_calib_ops(struct ath_hw
*ah
);
1000 void ar9002_hw_attach_ops(struct ath_hw
*ah
);
1001 void ar9003_hw_attach_ops(struct ath_hw
*ah
);
1003 void ar9002_hw_load_ani_reg(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1005 * ANI work can be shared between all families but a next
1006 * generation implementation of ANI will be used only for AR9003 only
1007 * for now as the other families still need to be tested with the same
1008 * next generation ANI. Feel free to start testing it though for the
1009 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1011 extern int modparam_force_new_ani
;
1012 void ath9k_ani_reset(struct ath_hw
*ah
, bool is_scanning
);
1013 void ath9k_hw_proc_mib_event(struct ath_hw
*ah
);
1014 void ath9k_hw_ani_monitor(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1016 #define ATH9K_CLOCK_RATE_CCK 22
1017 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1018 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1019 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44