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ath9k_hw: clean up tx power handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
blobe175e2078a3921b0d7aa5df9757305f1534d8f43
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9002_phy.h"
20
21 static void ath9k_get_txgain_index(struct ath_hw *ah,
22 struct ath9k_channel *chan,
23 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
24 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
25 {
26 u8 pcdac, i = 0;
27 u16 idxL = 0, idxR = 0, numPiers;
28 bool match;
29 struct chan_centers centers;
30
31 ath9k_hw_get_channel_centers(ah, chan, &centers);
32
33 for (numPiers = 0; numPiers < availPiers; numPiers++)
34 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
35 break;
36
37 match = ath9k_hw_get_lower_upper_index(
38 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
39 calChans, numPiers, &idxL, &idxR);
40 if (match) {
41 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
42 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
43 } else {
44 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
45 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
46 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
47 }
48
49 while (pcdac > ah->originalGain[i] &&
50 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
51 i++;
52
53 *pcdacIdx = i;
54 }
55
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
57 u32 initTxGain,
58 int txPower,
59 u8 *pPDADCValues)
60 {
61 u32 i;
62 u32 offset;
63
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
67 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
68
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
70 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
71
72 offset = txPower;
73 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
74 if (i < offset)
75 pPDADCValues[i] = 0x0;
76 else
77 pPDADCValues[i] = 0xFF;
78 }
79
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
81 {
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
83 }
84
85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
86 {
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
88 }
89
90 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
91
92 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
93 {
94 struct ath_common *common = ath9k_hw_common(ah);
95 u16 *eep_data = (u16 *)&ah->eeprom.def;
96 int addr, ar5416_eep_start_loc = 0x100;
97
98 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
99 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
100 eep_data)) {
101 ath_err(ath9k_hw_common(ah),
102 "Unable to read eeprom region\n");
103 return false;
104 }
105 eep_data++;
106 }
107 return true;
108 }
109
110 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
111 {
112 u16 *eep_data = (u16 *)&ah->eeprom.def;
113
114 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
115 0x100, SIZE_EEPROM_DEF);
116 return true;
117 }
118
119 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
120 {
121 struct ath_common *common = ath9k_hw_common(ah);
122
123 if (!ath9k_hw_use_flash(ah)) {
124 ath_dbg(common, ATH_DBG_EEPROM,
125 "Reading from EEPROM, not flash\n");
126 }
127
128 if (common->bus_ops->ath_bus_type == ATH_USB)
129 return __ath9k_hw_usb_def_fill_eeprom(ah);
130 else
131 return __ath9k_hw_def_fill_eeprom(ah);
132 }
133
134 #undef SIZE_EEPROM_DEF
135
136 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
137 static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
138 struct modal_eep_header *modal_hdr)
139 {
140 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
141 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
142 PR_EEP("Chain2 Ant. Control", modal_hdr->antCtrlChain[2]);
143 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
144 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
145 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
146 PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]);
147 PR_EEP("Switch Settle", modal_hdr->switchSettling);
148 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
149 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
150 PR_EEP("Chain2 TxRxAtten", modal_hdr->txRxAttenCh[2]);
151 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
152 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
153 PR_EEP("Chain2 RxTxMargin", modal_hdr->rxTxMarginCh[2]);
154 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
155 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
156 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
157 PR_EEP("Chain1 xlna Gain", modal_hdr->xlnaGainCh[1]);
158 PR_EEP("Chain2 xlna Gain", modal_hdr->xlnaGainCh[2]);
159 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
160 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
161 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
162 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
163 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
164 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
165 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
166 PR_EEP("xpdGain", modal_hdr->xpdGain);
167 PR_EEP("External PD", modal_hdr->xpd);
168 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
169 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
170 PR_EEP("Chain2 I Coefficient", modal_hdr->iqCalICh[2]);
171 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
172 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
173 PR_EEP("Chain2 Q Coefficient", modal_hdr->iqCalQCh[2]);
174 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
175 PR_EEP("Chain0 OutputBias", modal_hdr->ob);
176 PR_EEP("Chain0 DriverBias", modal_hdr->db);
177 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
178 PR_EEP("2chain pwr decrease", modal_hdr->pwrDecreaseFor2Chain);
179 PR_EEP("3chain pwr decrease", modal_hdr->pwrDecreaseFor3Chain);
180 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
181 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
182 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
183 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
184 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
185 PR_EEP("Chain2 bswAtten", modal_hdr->bswAtten[2]);
186 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
187 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
188 PR_EEP("Chain2 bswMargin", modal_hdr->bswMargin[2]);
189 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
190 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
191 PR_EEP("Chain1 xatten2Db", modal_hdr->xatten2Db[1]);
192 PR_EEP("Chain2 xatten2Db", modal_hdr->xatten2Db[2]);
193 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
194 PR_EEP("Chain1 xatten2Margin", modal_hdr->xatten2Margin[1]);
195 PR_EEP("Chain2 xatten2Margin", modal_hdr->xatten2Margin[2]);
196 PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1);
197 PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1);
198 PR_EEP("LNA Control", modal_hdr->lna_ctl);
199 PR_EEP("XPA Bias Freq0", modal_hdr->xpaBiasLvlFreq[0]);
200 PR_EEP("XPA Bias Freq1", modal_hdr->xpaBiasLvlFreq[1]);
201 PR_EEP("XPA Bias Freq2", modal_hdr->xpaBiasLvlFreq[2]);
202
203 return len;
204 }
205
206 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
207 u8 *buf, u32 len, u32 size)
208 {
209 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
210 struct base_eep_header *pBase = &eep->baseEepHeader;
211
212 if (!dump_base_hdr) {
213 len += snprintf(buf + len, size - len,
214 "%20s :\n", "2GHz modal Header");
215 len += ath9k_def_dump_modal_eeprom(buf, len, size,
216 &eep->modalHeader[0]);
217 len += snprintf(buf + len, size - len,
218 "%20s :\n", "5GHz modal Header");
219 len += ath9k_def_dump_modal_eeprom(buf, len, size,
220 &eep->modalHeader[1]);
221 goto out;
222 }
223
224 PR_EEP("Major Version", pBase->version >> 12);
225 PR_EEP("Minor Version", pBase->version & 0xFFF);
226 PR_EEP("Checksum", pBase->checksum);
227 PR_EEP("Length", pBase->length);
228 PR_EEP("RegDomain1", pBase->regDmn[0]);
229 PR_EEP("RegDomain2", pBase->regDmn[1]);
230 PR_EEP("TX Mask", pBase->txMask);
231 PR_EEP("RX Mask", pBase->rxMask);
232 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
233 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
234 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
235 AR5416_OPFLAGS_N_2G_HT20));
236 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
237 AR5416_OPFLAGS_N_2G_HT40));
238 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
239 AR5416_OPFLAGS_N_5G_HT20));
240 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
241 AR5416_OPFLAGS_N_5G_HT40));
242 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
243 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
244 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
245 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
246 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
247
248 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
249 pBase->macAddr);
250
251 out:
252 if (len > size)
253 len = size;
254
255 return len;
256 }
257 #else
258 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
259 u8 *buf, u32 len, u32 size)
260 {
261 return 0;
262 }
263 #endif
264
265
266 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
267 {
268 struct ar5416_eeprom_def *eep =
269 (struct ar5416_eeprom_def *) &ah->eeprom.def;
270 struct ath_common *common = ath9k_hw_common(ah);
271 u16 *eepdata, temp, magic, magic2;
272 u32 sum = 0, el;
273 bool need_swap = false;
274 int i, addr, size;
275
276 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
277 ath_err(common, "Reading Magic # failed\n");
278 return false;
279 }
280
281 if (!ath9k_hw_use_flash(ah)) {
282 ath_dbg(common, ATH_DBG_EEPROM,
283 "Read Magic = 0x%04X\n", magic);
284
285 if (magic != AR5416_EEPROM_MAGIC) {
286 magic2 = swab16(magic);
287
288 if (magic2 == AR5416_EEPROM_MAGIC) {
289 size = sizeof(struct ar5416_eeprom_def);
290 need_swap = true;
291 eepdata = (u16 *) (&ah->eeprom);
292
293 for (addr = 0; addr < size / sizeof(u16); addr++) {
294 temp = swab16(*eepdata);
295 *eepdata = temp;
296 eepdata++;
297 }
298 } else {
299 ath_err(common,
300 "Invalid EEPROM Magic. Endianness mismatch.\n");
301 return -EINVAL;
302 }
303 }
304 }
305
306 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
307 need_swap ? "True" : "False");
308
309 if (need_swap)
310 el = swab16(ah->eeprom.def.baseEepHeader.length);
311 else
312 el = ah->eeprom.def.baseEepHeader.length;
313
314 if (el > sizeof(struct ar5416_eeprom_def))
315 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
316 else
317 el = el / sizeof(u16);
318
319 eepdata = (u16 *)(&ah->eeprom);
320
321 for (i = 0; i < el; i++)
322 sum ^= *eepdata++;
323
324 if (need_swap) {
325 u32 integer, j;
326 u16 word;
327
328 ath_dbg(common, ATH_DBG_EEPROM,
329 "EEPROM Endianness is not native.. Changing.\n");
330
331 word = swab16(eep->baseEepHeader.length);
332 eep->baseEepHeader.length = word;
333
334 word = swab16(eep->baseEepHeader.checksum);
335 eep->baseEepHeader.checksum = word;
336
337 word = swab16(eep->baseEepHeader.version);
338 eep->baseEepHeader.version = word;
339
340 word = swab16(eep->baseEepHeader.regDmn[0]);
341 eep->baseEepHeader.regDmn[0] = word;
342
343 word = swab16(eep->baseEepHeader.regDmn[1]);
344 eep->baseEepHeader.regDmn[1] = word;
345
346 word = swab16(eep->baseEepHeader.rfSilent);
347 eep->baseEepHeader.rfSilent = word;
348
349 word = swab16(eep->baseEepHeader.blueToothOptions);
350 eep->baseEepHeader.blueToothOptions = word;
351
352 word = swab16(eep->baseEepHeader.deviceCap);
353 eep->baseEepHeader.deviceCap = word;
354
355 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
356 struct modal_eep_header *pModal =
357 &eep->modalHeader[j];
358 integer = swab32(pModal->antCtrlCommon);
359 pModal->antCtrlCommon = integer;
360
361 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
362 integer = swab32(pModal->antCtrlChain[i]);
363 pModal->antCtrlChain[i] = integer;
364 }
365 for (i = 0; i < 3; i++) {
366 word = swab16(pModal->xpaBiasLvlFreq[i]);
367 pModal->xpaBiasLvlFreq[i] = word;
368 }
369
370 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
371 word = swab16(pModal->spurChans[i].spurChan);
372 pModal->spurChans[i].spurChan = word;
373 }
374 }
375 }
376
377 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
378 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
379 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
380 sum, ah->eep_ops->get_eeprom_ver(ah));
381 return -EINVAL;
382 }
383
384 /* Enable fixup for AR_AN_TOP2 if necessary */
385 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
386 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
387 (eep->baseEepHeader.pwdclkind == 0))
388 ah->need_an_top2_fixup = 1;
389
390 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
391 (AR_SREV_9280(ah)))
392 eep->modalHeader[0].xpaBiasLvl = 0;
393
394 return 0;
395 }
396
397 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
398 enum eeprom_param param)
399 {
400 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
401 struct modal_eep_header *pModal = eep->modalHeader;
402 struct base_eep_header *pBase = &eep->baseEepHeader;
403 int band = 0;
404
405 switch (param) {
406 case EEP_NFTHRESH_5:
407 return pModal[0].noiseFloorThreshCh[0];
408 case EEP_NFTHRESH_2:
409 return pModal[1].noiseFloorThreshCh[0];
410 case EEP_MAC_LSW:
411 return get_unaligned_be16(pBase->macAddr);
412 case EEP_MAC_MID:
413 return get_unaligned_be16(pBase->macAddr + 2);
414 case EEP_MAC_MSW:
415 return get_unaligned_be16(pBase->macAddr + 4);
416 case EEP_REG_0:
417 return pBase->regDmn[0];
418 case EEP_REG_1:
419 return pBase->regDmn[1];
420 case EEP_OP_CAP:
421 return pBase->deviceCap;
422 case EEP_OP_MODE:
423 return pBase->opCapFlags;
424 case EEP_RF_SILENT:
425 return pBase->rfSilent;
426 case EEP_OB_5:
427 return pModal[0].ob;
428 case EEP_DB_5:
429 return pModal[0].db;
430 case EEP_OB_2:
431 return pModal[1].ob;
432 case EEP_DB_2:
433 return pModal[1].db;
434 case EEP_MINOR_REV:
435 return AR5416_VER_MASK;
436 case EEP_TX_MASK:
437 return pBase->txMask;
438 case EEP_RX_MASK:
439 return pBase->rxMask;
440 case EEP_FSTCLK_5G:
441 return pBase->fastClk5g;
442 case EEP_RXGAIN_TYPE:
443 return pBase->rxGainType;
444 case EEP_TXGAIN_TYPE:
445 return pBase->txGainType;
446 case EEP_OL_PWRCTRL:
447 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
448 return pBase->openLoopPwrCntl ? true : false;
449 else
450 return false;
451 case EEP_RC_CHAIN_MASK:
452 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
453 return pBase->rcChainMask;
454 else
455 return 0;
456 case EEP_DAC_HPWR_5G:
457 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
458 return pBase->dacHiPwrMode_5G;
459 else
460 return 0;
461 case EEP_FRAC_N_5G:
462 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
463 return pBase->frac_n_5g;
464 else
465 return 0;
466 case EEP_PWR_TABLE_OFFSET:
467 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
468 return pBase->pwr_table_offset;
469 else
470 return AR5416_PWR_TABLE_OFFSET_DB;
471 case EEP_ANTENNA_GAIN_2G:
472 band = 1;
473 /* fall through */
474 case EEP_ANTENNA_GAIN_5G:
475 return max_t(u8, max_t(u8,
476 pModal[band].antennaGainCh[0],
477 pModal[band].antennaGainCh[1]),
478 pModal[band].antennaGainCh[2]);
479 default:
480 return 0;
481 }
482 }
483
484 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
485 struct modal_eep_header *pModal,
486 struct ar5416_eeprom_def *eep,
487 u8 txRxAttenLocal, int regChainOffset, int i)
488 {
489 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
490 txRxAttenLocal = pModal->txRxAttenCh[i];
491
492 if (AR_SREV_9280_20_OR_LATER(ah)) {
493 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
494 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
495 pModal->bswMargin[i]);
496 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
497 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
498 pModal->bswAtten[i]);
499 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
500 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
501 pModal->xatten2Margin[i]);
502 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
503 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
504 pModal->xatten2Db[i]);
505 } else {
506 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
507 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
508 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
509 | SM(pModal-> bswMargin[i],
510 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
511 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
512 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
513 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
514 | SM(pModal->bswAtten[i],
515 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
516 }
517 }
518
519 if (AR_SREV_9280_20_OR_LATER(ah)) {
520 REG_RMW_FIELD(ah,
521 AR_PHY_RXGAIN + regChainOffset,
522 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
523 REG_RMW_FIELD(ah,
524 AR_PHY_RXGAIN + regChainOffset,
525 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
526 } else {
527 REG_WRITE(ah,
528 AR_PHY_RXGAIN + regChainOffset,
529 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
530 ~AR_PHY_RXGAIN_TXRX_ATTEN)
531 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
532 REG_WRITE(ah,
533 AR_PHY_GAIN_2GHZ + regChainOffset,
534 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
535 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
536 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
537 }
538 }
539
540 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
541 struct ath9k_channel *chan)
542 {
543 struct modal_eep_header *pModal;
544 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
545 int i, regChainOffset;
546 u8 txRxAttenLocal;
547
548 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
549 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
550
551 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
552
553 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
554 if (AR_SREV_9280(ah)) {
555 if (i >= 2)
556 break;
557 }
558
559 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
560 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
561 else
562 regChainOffset = i * 0x1000;
563
564 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
565 pModal->antCtrlChain[i]);
566
567 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
568 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
569 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
570 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
571 SM(pModal->iqCalICh[i],
572 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
573 SM(pModal->iqCalQCh[i],
574 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
575
576 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
577 regChainOffset, i);
578 }
579
580 if (AR_SREV_9280_20_OR_LATER(ah)) {
581 if (IS_CHAN_2GHZ(chan)) {
582 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
583 AR_AN_RF2G1_CH0_OB,
584 AR_AN_RF2G1_CH0_OB_S,
585 pModal->ob);
586 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
587 AR_AN_RF2G1_CH0_DB,
588 AR_AN_RF2G1_CH0_DB_S,
589 pModal->db);
590 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
591 AR_AN_RF2G1_CH1_OB,
592 AR_AN_RF2G1_CH1_OB_S,
593 pModal->ob_ch1);
594 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
595 AR_AN_RF2G1_CH1_DB,
596 AR_AN_RF2G1_CH1_DB_S,
597 pModal->db_ch1);
598 } else {
599 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
600 AR_AN_RF5G1_CH0_OB5,
601 AR_AN_RF5G1_CH0_OB5_S,
602 pModal->ob);
603 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
604 AR_AN_RF5G1_CH0_DB5,
605 AR_AN_RF5G1_CH0_DB5_S,
606 pModal->db);
607 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
608 AR_AN_RF5G1_CH1_OB5,
609 AR_AN_RF5G1_CH1_OB5_S,
610 pModal->ob_ch1);
611 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
612 AR_AN_RF5G1_CH1_DB5,
613 AR_AN_RF5G1_CH1_DB5_S,
614 pModal->db_ch1);
615 }
616 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
617 AR_AN_TOP2_XPABIAS_LVL,
618 AR_AN_TOP2_XPABIAS_LVL_S,
619 pModal->xpaBiasLvl);
620 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
621 AR_AN_TOP2_LOCALBIAS,
622 AR_AN_TOP2_LOCALBIAS_S,
623 !!(pModal->lna_ctl &
624 LNA_CTL_LOCAL_BIAS));
625 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
626 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
627 }
628
629 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
630 pModal->switchSettling);
631 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
632 pModal->adcDesiredSize);
633
634 if (!AR_SREV_9280_20_OR_LATER(ah))
635 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
636 AR_PHY_DESIRED_SZ_PGA,
637 pModal->pgaDesiredSize);
638
639 REG_WRITE(ah, AR_PHY_RF_CTL4,
640 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
641 | SM(pModal->txEndToXpaOff,
642 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
643 | SM(pModal->txFrameToXpaOn,
644 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
645 | SM(pModal->txFrameToXpaOn,
646 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
647
648 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
649 pModal->txEndToRxOn);
650
651 if (AR_SREV_9280_20_OR_LATER(ah)) {
652 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
653 pModal->thresh62);
654 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
655 AR_PHY_EXT_CCA0_THRESH62,
656 pModal->thresh62);
657 } else {
658 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
659 pModal->thresh62);
660 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
661 AR_PHY_EXT_CCA_THRESH62,
662 pModal->thresh62);
663 }
664
665 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
666 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
667 AR_PHY_TX_END_DATA_START,
668 pModal->txFrameToDataStart);
669 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
670 pModal->txFrameToPaOn);
671 }
672
673 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
674 if (IS_CHAN_HT40(chan))
675 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
676 AR_PHY_SETTLING_SWITCH,
677 pModal->swSettleHt40);
678 }
679
680 if (AR_SREV_9280_20_OR_LATER(ah) &&
681 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
682 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
683 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
684 pModal->miscBits);
685
686
687 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
688 if (IS_CHAN_2GHZ(chan))
689 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
690 eep->baseEepHeader.dacLpMode);
691 else if (eep->baseEepHeader.dacHiPwrMode_5G)
692 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
693 else
694 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
695 eep->baseEepHeader.dacLpMode);
696
697 udelay(100);
698
699 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
700 pModal->miscBits >> 2);
701
702 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
703 AR_PHY_TX_DESIRED_SCALE_CCK,
704 eep->baseEepHeader.desiredScaleCCK);
705 }
706 }
707
708 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
709 struct ath9k_channel *chan)
710 {
711 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
712 struct modal_eep_header *pModal;
713 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
714 u8 biaslevel;
715
716 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
717 return;
718
719 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
720 return;
721
722 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
723
724 if (pModal->xpaBiasLvl != 0xff) {
725 biaslevel = pModal->xpaBiasLvl;
726 } else {
727 u16 resetFreqBin, freqBin, freqCount = 0;
728 struct chan_centers centers;
729
730 ath9k_hw_get_channel_centers(ah, chan, &centers);
731
732 resetFreqBin = FREQ2FBIN(centers.synth_center,
733 IS_CHAN_2GHZ(chan));
734 freqBin = XPA_LVL_FREQ(0) & 0xff;
735 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
736
737 freqCount++;
738
739 while (freqCount < 3) {
740 if (XPA_LVL_FREQ(freqCount) == 0x0)
741 break;
742
743 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
744 if (resetFreqBin >= freqBin)
745 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
746 else
747 break;
748 freqCount++;
749 }
750 }
751
752 if (IS_CHAN_2GHZ(chan)) {
753 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
754 7, 1) & (~0x18)) | biaslevel << 3;
755 } else {
756 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
757 6, 1) & (~0xc0)) | biaslevel << 6;
758 }
759 #undef XPA_LVL_FREQ
760 }
761
762 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
763 u16 *gb,
764 u16 numXpdGain,
765 u16 pdGainOverlap_t2,
766 int8_t pwr_table_offset,
767 int16_t *diff)
768
769 {
770 u16 k;
771
772 /* Prior to writing the boundaries or the pdadc vs. power table
773 * into the chip registers the default starting point on the pdadc
774 * vs. power table needs to be checked and the curve boundaries
775 * adjusted accordingly
776 */
777 if (AR_SREV_9280_20_OR_LATER(ah)) {
778 u16 gb_limit;
779
780 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
781 /* get the difference in dB */
782 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
783 /* get the number of half dB steps */
784 *diff *= 2;
785 /* change the original gain boundary settings
786 * by the number of half dB steps
787 */
788 for (k = 0; k < numXpdGain; k++)
789 gb[k] = (u16)(gb[k] - *diff);
790 }
791 /* Because of a hardware limitation, ensure the gain boundary
792 * is not larger than (63 - overlap)
793 */
794 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
795
796 for (k = 0; k < numXpdGain; k++)
797 gb[k] = (u16)min(gb_limit, gb[k]);
798 }
799
800 return *diff;
801 }
802
803 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
804 int8_t pwr_table_offset,
805 int16_t diff,
806 u8 *pdadcValues)
807 {
808 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
809 u16 k;
810
811 /* If this is a board that has a pwrTableOffset that differs from
812 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
813 * pdadc vs pwr table needs to be adjusted prior to writing to the
814 * chip.
815 */
816 if (AR_SREV_9280_20_OR_LATER(ah)) {
817 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
818 /* shift the table to start at the new offset */
819 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
820 pdadcValues[k] = pdadcValues[k + diff];
821 }
822
823 /* fill the back of the table */
824 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
825 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
826 }
827 }
828 }
829 #undef NUM_PDADC
830 }
831
832 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
833 struct ath9k_channel *chan)
834 {
835 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
836 #define SM_PDGAIN_B(x, y) \
837 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
838 struct ath_common *common = ath9k_hw_common(ah);
839 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
840 struct cal_data_per_freq *pRawDataset;
841 u8 *pCalBChans = NULL;
842 u16 pdGainOverlap_t2;
843 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
844 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
845 u16 numPiers, i, j;
846 int16_t diff = 0;
847 u16 numXpdGain, xpdMask;
848 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
849 u32 reg32, regOffset, regChainOffset;
850 int16_t modalIdx;
851 int8_t pwr_table_offset;
852
853 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
854 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
855
856 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
857
858 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
859 AR5416_EEP_MINOR_VER_2) {
860 pdGainOverlap_t2 =
861 pEepData->modalHeader[modalIdx].pdGainOverlap;
862 } else {
863 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
864 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
865 }
866
867 if (IS_CHAN_2GHZ(chan)) {
868 pCalBChans = pEepData->calFreqPier2G;
869 numPiers = AR5416_NUM_2G_CAL_PIERS;
870 } else {
871 pCalBChans = pEepData->calFreqPier5G;
872 numPiers = AR5416_NUM_5G_CAL_PIERS;
873 }
874
875 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
876 pRawDataset = pEepData->calPierData2G[0];
877 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
878 pRawDataset)->vpdPdg[0][0];
879 }
880
881 numXpdGain = 0;
882
883 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
884 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
885 if (numXpdGain >= AR5416_NUM_PD_GAINS)
886 break;
887 xpdGainValues[numXpdGain] =
888 (u16)(AR5416_PD_GAINS_IN_MASK - i);
889 numXpdGain++;
890 }
891 }
892
893 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
894 (numXpdGain - 1) & 0x3);
895 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
896 xpdGainValues[0]);
897 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
898 xpdGainValues[1]);
899 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
900 xpdGainValues[2]);
901
902 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
903 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
904 (i != 0)) {
905 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
906 } else
907 regChainOffset = i * 0x1000;
908
909 if (pEepData->baseEepHeader.txMask & (1 << i)) {
910 if (IS_CHAN_2GHZ(chan))
911 pRawDataset = pEepData->calPierData2G[i];
912 else
913 pRawDataset = pEepData->calPierData5G[i];
914
915
916 if (OLC_FOR_AR9280_20_LATER) {
917 u8 pcdacIdx;
918 u8 txPower;
919
920 ath9k_get_txgain_index(ah, chan,
921 (struct calDataPerFreqOpLoop *)pRawDataset,
922 pCalBChans, numPiers, &txPower, &pcdacIdx);
923 ath9k_olc_get_pdadcs(ah, pcdacIdx,
924 txPower/2, pdadcValues);
925 } else {
926 ath9k_hw_get_gain_boundaries_pdadcs(ah,
927 chan, pRawDataset,
928 pCalBChans, numPiers,
929 pdGainOverlap_t2,
930 gainBoundaries,
931 pdadcValues,
932 numXpdGain);
933 }
934
935 diff = ath9k_change_gain_boundary_setting(ah,
936 gainBoundaries,
937 numXpdGain,
938 pdGainOverlap_t2,
939 pwr_table_offset,
940 &diff);
941
942 ENABLE_REGWRITE_BUFFER(ah);
943
944 if (OLC_FOR_AR9280_20_LATER) {
945 REG_WRITE(ah,
946 AR_PHY_TPCRG5 + regChainOffset,
947 SM(0x6,
948 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
949 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
950 SM_PD_GAIN(3) | SM_PD_GAIN(4));
951 } else {
952 REG_WRITE(ah,
953 AR_PHY_TPCRG5 + regChainOffset,
954 SM(pdGainOverlap_t2,
955 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
956 SM_PDGAIN_B(0, 1) |
957 SM_PDGAIN_B(1, 2) |
958 SM_PDGAIN_B(2, 3) |
959 SM_PDGAIN_B(3, 4));
960 }
961
962 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
963 diff, pdadcValues);
964
965 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
966 for (j = 0; j < 32; j++) {
967 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
968 REG_WRITE(ah, regOffset, reg32);
969
970 ath_dbg(common, ATH_DBG_EEPROM,
971 "PDADC (%d,%4x): %4.4x %8.8x\n",
972 i, regChainOffset, regOffset,
973 reg32);
974 ath_dbg(common, ATH_DBG_EEPROM,
975 "PDADC: Chain %d | PDADC %3d "
976 "Value %3d | PDADC %3d Value %3d | "
977 "PDADC %3d Value %3d | PDADC %3d "
978 "Value %3d |\n",
979 i, 4 * j, pdadcValues[4 * j],
980 4 * j + 1, pdadcValues[4 * j + 1],
981 4 * j + 2, pdadcValues[4 * j + 2],
982 4 * j + 3, pdadcValues[4 * j + 3]);
983
984 regOffset += 4;
985 }
986 REGWRITE_BUFFER_FLUSH(ah);
987 }
988 }
989
990 #undef SM_PD_GAIN
991 #undef SM_PDGAIN_B
992 }
993
994 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
995 struct ath9k_channel *chan,
996 int16_t *ratesArray,
997 u16 cfgCtl,
998 u16 antenna_reduction,
999 u16 powerLimit)
1000 {
1001 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1002 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
1003
1004 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1005 u16 twiceMaxEdgePower = MAX_RATE_POWER;
1006 int i;
1007 struct cal_ctl_data *rep;
1008 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1009 0, { 0, 0, 0, 0}
1010 };
1011 struct cal_target_power_leg targetPowerOfdmExt = {
1012 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1013 0, { 0, 0, 0, 0 }
1014 };
1015 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1016 0, {0, 0, 0, 0}
1017 };
1018 u16 scaledPower = 0, minCtlPower;
1019 static const u16 ctlModesFor11a[] = {
1020 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1021 };
1022 static const u16 ctlModesFor11g[] = {
1023 CTL_11B, CTL_11G, CTL_2GHT20,
1024 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1025 };
1026 u16 numCtlModes;
1027 const u16 *pCtlMode;
1028 u16 ctlMode, freq;
1029 struct chan_centers centers;
1030 int tx_chainmask;
1031 u16 twiceMinEdgePower;
1032
1033 tx_chainmask = ah->txchainmask;
1034
1035 ath9k_hw_get_channel_centers(ah, chan, &centers);
1036
1037 scaledPower = powerLimit - antenna_reduction;
1038
1039 switch (ar5416_get_ntxchains(tx_chainmask)) {
1040 case 1:
1041 break;
1042 case 2:
1043 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
1044 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1045 else
1046 scaledPower = 0;
1047 break;
1048 case 3:
1049 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
1050 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1051 else
1052 scaledPower = 0;
1053 break;
1054 }
1055
1056 if (IS_CHAN_2GHZ(chan)) {
1057 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1058 SUB_NUM_CTL_MODES_AT_2G_40;
1059 pCtlMode = ctlModesFor11g;
1060
1061 ath9k_hw_get_legacy_target_powers(ah, chan,
1062 pEepData->calTargetPowerCck,
1063 AR5416_NUM_2G_CCK_TARGET_POWERS,
1064 &targetPowerCck, 4, false);
1065 ath9k_hw_get_legacy_target_powers(ah, chan,
1066 pEepData->calTargetPower2G,
1067 AR5416_NUM_2G_20_TARGET_POWERS,
1068 &targetPowerOfdm, 4, false);
1069 ath9k_hw_get_target_powers(ah, chan,
1070 pEepData->calTargetPower2GHT20,
1071 AR5416_NUM_2G_20_TARGET_POWERS,
1072 &targetPowerHt20, 8, false);
1073
1074 if (IS_CHAN_HT40(chan)) {
1075 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1076 ath9k_hw_get_target_powers(ah, chan,
1077 pEepData->calTargetPower2GHT40,
1078 AR5416_NUM_2G_40_TARGET_POWERS,
1079 &targetPowerHt40, 8, true);
1080 ath9k_hw_get_legacy_target_powers(ah, chan,
1081 pEepData->calTargetPowerCck,
1082 AR5416_NUM_2G_CCK_TARGET_POWERS,
1083 &targetPowerCckExt, 4, true);
1084 ath9k_hw_get_legacy_target_powers(ah, chan,
1085 pEepData->calTargetPower2G,
1086 AR5416_NUM_2G_20_TARGET_POWERS,
1087 &targetPowerOfdmExt, 4, true);
1088 }
1089 } else {
1090 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1091 SUB_NUM_CTL_MODES_AT_5G_40;
1092 pCtlMode = ctlModesFor11a;
1093
1094 ath9k_hw_get_legacy_target_powers(ah, chan,
1095 pEepData->calTargetPower5G,
1096 AR5416_NUM_5G_20_TARGET_POWERS,
1097 &targetPowerOfdm, 4, false);
1098 ath9k_hw_get_target_powers(ah, chan,
1099 pEepData->calTargetPower5GHT20,
1100 AR5416_NUM_5G_20_TARGET_POWERS,
1101 &targetPowerHt20, 8, false);
1102
1103 if (IS_CHAN_HT40(chan)) {
1104 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1105 ath9k_hw_get_target_powers(ah, chan,
1106 pEepData->calTargetPower5GHT40,
1107 AR5416_NUM_5G_40_TARGET_POWERS,
1108 &targetPowerHt40, 8, true);
1109 ath9k_hw_get_legacy_target_powers(ah, chan,
1110 pEepData->calTargetPower5G,
1111 AR5416_NUM_5G_20_TARGET_POWERS,
1112 &targetPowerOfdmExt, 4, true);
1113 }
1114 }
1115
1116 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1117 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1118 (pCtlMode[ctlMode] == CTL_2GHT40);
1119 if (isHt40CtlMode)
1120 freq = centers.synth_center;
1121 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1122 freq = centers.ext_center;
1123 else
1124 freq = centers.ctl_center;
1125
1126 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1127 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1128 twiceMaxEdgePower = MAX_RATE_POWER;
1129
1130 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1131 if ((((cfgCtl & ~CTL_MODE_M) |
1132 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1133 pEepData->ctlIndex[i]) ||
1134 (((cfgCtl & ~CTL_MODE_M) |
1135 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1136 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1137 rep = &(pEepData->ctlData[i]);
1138
1139 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1140 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1141 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1142
1143 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1144 twiceMaxEdgePower = min(twiceMaxEdgePower,
1145 twiceMinEdgePower);
1146 } else {
1147 twiceMaxEdgePower = twiceMinEdgePower;
1148 break;
1149 }
1150 }
1151 }
1152
1153 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1154
1155 switch (pCtlMode[ctlMode]) {
1156 case CTL_11B:
1157 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1158 targetPowerCck.tPow2x[i] =
1159 min((u16)targetPowerCck.tPow2x[i],
1160 minCtlPower);
1161 }
1162 break;
1163 case CTL_11A:
1164 case CTL_11G:
1165 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1166 targetPowerOfdm.tPow2x[i] =
1167 min((u16)targetPowerOfdm.tPow2x[i],
1168 minCtlPower);
1169 }
1170 break;
1171 case CTL_5GHT20:
1172 case CTL_2GHT20:
1173 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1174 targetPowerHt20.tPow2x[i] =
1175 min((u16)targetPowerHt20.tPow2x[i],
1176 minCtlPower);
1177 }
1178 break;
1179 case CTL_11B_EXT:
1180 targetPowerCckExt.tPow2x[0] = min((u16)
1181 targetPowerCckExt.tPow2x[0],
1182 minCtlPower);
1183 break;
1184 case CTL_11A_EXT:
1185 case CTL_11G_EXT:
1186 targetPowerOfdmExt.tPow2x[0] = min((u16)
1187 targetPowerOfdmExt.tPow2x[0],
1188 minCtlPower);
1189 break;
1190 case CTL_5GHT40:
1191 case CTL_2GHT40:
1192 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1193 targetPowerHt40.tPow2x[i] =
1194 min((u16)targetPowerHt40.tPow2x[i],
1195 minCtlPower);
1196 }
1197 break;
1198 default:
1199 break;
1200 }
1201 }
1202
1203 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1204 ratesArray[rate18mb] = ratesArray[rate24mb] =
1205 targetPowerOfdm.tPow2x[0];
1206 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1207 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1208 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1209 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1210
1211 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1212 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1213
1214 if (IS_CHAN_2GHZ(chan)) {
1215 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1216 ratesArray[rate2s] = ratesArray[rate2l] =
1217 targetPowerCck.tPow2x[1];
1218 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1219 targetPowerCck.tPow2x[2];
1220 ratesArray[rate11s] = ratesArray[rate11l] =
1221 targetPowerCck.tPow2x[3];
1222 }
1223 if (IS_CHAN_HT40(chan)) {
1224 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1225 ratesArray[rateHt40_0 + i] =
1226 targetPowerHt40.tPow2x[i];
1227 }
1228 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1229 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1230 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1231 if (IS_CHAN_2GHZ(chan)) {
1232 ratesArray[rateExtCck] =
1233 targetPowerCckExt.tPow2x[0];
1234 }
1235 }
1236 }
1237
1238 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1239 struct ath9k_channel *chan,
1240 u16 cfgCtl,
1241 u8 twiceAntennaReduction,
1242 u8 powerLimit, bool test)
1243 {
1244 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1245 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1246 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1247 struct modal_eep_header *pModal =
1248 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1249 int16_t ratesArray[Ar5416RateSize];
1250 u8 ht40PowerIncForPdadc = 2;
1251 int i, cck_ofdm_delta = 0;
1252
1253 memset(ratesArray, 0, sizeof(ratesArray));
1254
1255 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1256 AR5416_EEP_MINOR_VER_2) {
1257 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1258 }
1259
1260 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1261 &ratesArray[0], cfgCtl,
1262 twiceAntennaReduction,
1263 powerLimit);
1264
1265 ath9k_hw_set_def_power_cal_table(ah, chan);
1266
1267 regulatory->max_power_level = 0;
1268 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1269 if (ratesArray[i] > MAX_RATE_POWER)
1270 ratesArray[i] = MAX_RATE_POWER;
1271 if (ratesArray[i] > regulatory->max_power_level)
1272 regulatory->max_power_level = ratesArray[i];
1273 }
1274
1275 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1276 case 1:
1277 break;
1278 case 2:
1279 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1280 break;
1281 case 3:
1282 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1283 break;
1284 default:
1285 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1286 "Invalid chainmask configuration\n");
1287 break;
1288 }
1289
1290 if (test)
1291 return;
1292
1293 if (AR_SREV_9280_20_OR_LATER(ah)) {
1294 for (i = 0; i < Ar5416RateSize; i++) {
1295 int8_t pwr_table_offset;
1296
1297 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1298 EEP_PWR_TABLE_OFFSET);
1299 ratesArray[i] -= pwr_table_offset * 2;
1300 }
1301 }
1302
1303 ENABLE_REGWRITE_BUFFER(ah);
1304
1305 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1306 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1307 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1308 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1309 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1310 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1311 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1312 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1313 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1314 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1315
1316 if (IS_CHAN_2GHZ(chan)) {
1317 if (OLC_FOR_AR9280_20_LATER) {
1318 cck_ofdm_delta = 2;
1319 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1320 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1321 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1322 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1323 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1324 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1325 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1326 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1327 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1328 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1329 } else {
1330 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1331 ATH9K_POW_SM(ratesArray[rate2s], 24)
1332 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1333 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1334 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1335 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1336 ATH9K_POW_SM(ratesArray[rate11s], 24)
1337 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1338 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1339 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1340 }
1341 }
1342
1343 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1344 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1345 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1346 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1347 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1348 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1349 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1350 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1351 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1352 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1353
1354 if (IS_CHAN_HT40(chan)) {
1355 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1356 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1357 ht40PowerIncForPdadc, 24)
1358 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1359 ht40PowerIncForPdadc, 16)
1360 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1361 ht40PowerIncForPdadc, 8)
1362 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1363 ht40PowerIncForPdadc, 0));
1364 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1365 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1366 ht40PowerIncForPdadc, 24)
1367 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1368 ht40PowerIncForPdadc, 16)
1369 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1370 ht40PowerIncForPdadc, 8)
1371 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1372 ht40PowerIncForPdadc, 0));
1373 if (OLC_FOR_AR9280_20_LATER) {
1374 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1375 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1376 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1377 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1378 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1379 } else {
1380 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1381 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1382 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1383 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1384 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1385 }
1386 }
1387
1388 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1389 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1390 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1391
1392 REGWRITE_BUFFER_FLUSH(ah);
1393 }
1394
1395 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1396 {
1397 #define EEP_DEF_SPURCHAN \
1398 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1399 struct ath_common *common = ath9k_hw_common(ah);
1400
1401 u16 spur_val = AR_NO_SPUR;
1402
1403 ath_dbg(common, ATH_DBG_ANI,
1404 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1405 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1406
1407 switch (ah->config.spurmode) {
1408 case SPUR_DISABLE:
1409 break;
1410 case SPUR_ENABLE_IOCTL:
1411 spur_val = ah->config.spurchans[i][is2GHz];
1412 ath_dbg(common, ATH_DBG_ANI,
1413 "Getting spur val from new loc. %d\n", spur_val);
1414 break;
1415 case SPUR_ENABLE_EEPROM:
1416 spur_val = EEP_DEF_SPURCHAN;
1417 break;
1418 }
1419
1420 return spur_val;
1421
1422 #undef EEP_DEF_SPURCHAN
1423 }
1424
1425 const struct eeprom_ops eep_def_ops = {
1426 .check_eeprom = ath9k_hw_def_check_eeprom,
1427 .get_eeprom = ath9k_hw_def_get_eeprom,
1428 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1429 .dump_eeprom = ath9k_hw_def_dump_eeprom,
1430 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1431 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1432 .set_board_values = ath9k_hw_def_set_board_values,
1433 .set_addac = ath9k_hw_def_set_addac,
1434 .set_txpower = ath9k_hw_def_set_txpower,
1435 .get_spur_channel = ath9k_hw_def_get_spur_channel
1436 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree