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ath9k_hw: clean up tx power handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_9287.c
blob90d771fa2dea26b4523ac2b20c2b3df5b5d27d3a
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9002_phy.h"
20
21 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
22
23 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
24 {
25 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
26 }
27
28 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
29 {
30 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
31 }
32
33 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
34 {
35 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
36 struct ath_common *common = ath9k_hw_common(ah);
37 u16 *eep_data;
38 int addr, eep_start_loc = AR9287_EEP_START_LOC;
39 eep_data = (u16 *)eep;
40
41 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
42 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
43 eep_data)) {
44 ath_dbg(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region\n");
46 return false;
47 }
48 eep_data++;
49 }
50
51 return true;
52 }
53
54 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
55 {
56 u16 *eep_data = (u16 *)&ah->eeprom.map9287;
57
58 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
59 AR9287_HTC_EEP_START_LOC,
60 SIZE_EEPROM_AR9287);
61 return true;
62 }
63
64 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
65 {
66 struct ath_common *common = ath9k_hw_common(ah);
67
68 if (!ath9k_hw_use_flash(ah)) {
69 ath_dbg(common, ATH_DBG_EEPROM,
70 "Reading from EEPROM, not flash\n");
71 }
72
73 if (common->bus_ops->ath_bus_type == ATH_USB)
74 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
75 else
76 return __ath9k_hw_ar9287_fill_eeprom(ah);
77 }
78
79 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
80 static u32 ar9287_dump_modal_eeprom(char *buf, u32 len, u32 size,
81 struct modal_eep_ar9287_header *modal_hdr)
82 {
83 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
84 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
85 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
86 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
87 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
88 PR_EEP("Switch Settle", modal_hdr->switchSettling);
89 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
90 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
91 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
92 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
93 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
94 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
95 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
96 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
97 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
98 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
99 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
100 PR_EEP("xpdGain", modal_hdr->xpdGain);
101 PR_EEP("External PD", modal_hdr->xpd);
102 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
103 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
104 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
105 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
106 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
107 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
108 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
109 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
110 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
111 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
112 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
113 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
114 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
115 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
116 PR_EEP("AR92x7 Version", modal_hdr->version);
117 PR_EEP("DriverBias1", modal_hdr->db1);
118 PR_EEP("DriverBias2", modal_hdr->db1);
119 PR_EEP("CCK OutputBias", modal_hdr->ob_cck);
120 PR_EEP("PSK OutputBias", modal_hdr->ob_psk);
121 PR_EEP("QAM OutputBias", modal_hdr->ob_qam);
122 PR_EEP("PAL_OFF OutputBias", modal_hdr->ob_pal_off);
123
124 return len;
125 }
126
127 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
128 u8 *buf, u32 len, u32 size)
129 {
130 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
131 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
132
133 if (!dump_base_hdr) {
134 len += snprintf(buf + len, size - len,
135 "%20s :\n", "2GHz modal Header");
136 len += ar9287_dump_modal_eeprom(buf, len, size,
137 &eep->modalHeader);
138 goto out;
139 }
140
141 PR_EEP("Major Version", pBase->version >> 12);
142 PR_EEP("Minor Version", pBase->version & 0xFFF);
143 PR_EEP("Checksum", pBase->checksum);
144 PR_EEP("Length", pBase->length);
145 PR_EEP("RegDomain1", pBase->regDmn[0]);
146 PR_EEP("RegDomain2", pBase->regDmn[1]);
147 PR_EEP("TX Mask", pBase->txMask);
148 PR_EEP("RX Mask", pBase->rxMask);
149 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
150 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
151 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
152 AR5416_OPFLAGS_N_2G_HT20));
153 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
154 AR5416_OPFLAGS_N_2G_HT40));
155 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
156 AR5416_OPFLAGS_N_5G_HT20));
157 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
158 AR5416_OPFLAGS_N_5G_HT40));
159 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
160 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
161 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
162 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
163 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
164 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
165
166 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
167 pBase->macAddr);
168
169 out:
170 if (len > size)
171 len = size;
172
173 return len;
174 }
175 #else
176 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
177 u8 *buf, u32 len, u32 size)
178 {
179 return 0;
180 }
181 #endif
182
183
184 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
185 {
186 u32 sum = 0, el, integer;
187 u16 temp, word, magic, magic2, *eepdata;
188 int i, addr;
189 bool need_swap = false;
190 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
191 struct ath_common *common = ath9k_hw_common(ah);
192
193 if (!ath9k_hw_use_flash(ah)) {
194 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
195 &magic)) {
196 ath_err(common, "Reading Magic # failed\n");
197 return false;
198 }
199
200 ath_dbg(common, ATH_DBG_EEPROM,
201 "Read Magic = 0x%04X\n", magic);
202
203 if (magic != AR5416_EEPROM_MAGIC) {
204 magic2 = swab16(magic);
205
206 if (magic2 == AR5416_EEPROM_MAGIC) {
207 need_swap = true;
208 eepdata = (u16 *)(&ah->eeprom);
209
210 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
211 temp = swab16(*eepdata);
212 *eepdata = temp;
213 eepdata++;
214 }
215 } else {
216 ath_err(common,
217 "Invalid EEPROM Magic. Endianness mismatch.\n");
218 return -EINVAL;
219 }
220 }
221 }
222
223 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
224 need_swap ? "True" : "False");
225
226 if (need_swap)
227 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
228 else
229 el = ah->eeprom.map9287.baseEepHeader.length;
230
231 if (el > sizeof(struct ar9287_eeprom))
232 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
233 else
234 el = el / sizeof(u16);
235
236 eepdata = (u16 *)(&ah->eeprom);
237
238 for (i = 0; i < el; i++)
239 sum ^= *eepdata++;
240
241 if (need_swap) {
242 word = swab16(eep->baseEepHeader.length);
243 eep->baseEepHeader.length = word;
244
245 word = swab16(eep->baseEepHeader.checksum);
246 eep->baseEepHeader.checksum = word;
247
248 word = swab16(eep->baseEepHeader.version);
249 eep->baseEepHeader.version = word;
250
251 word = swab16(eep->baseEepHeader.regDmn[0]);
252 eep->baseEepHeader.regDmn[0] = word;
253
254 word = swab16(eep->baseEepHeader.regDmn[1]);
255 eep->baseEepHeader.regDmn[1] = word;
256
257 word = swab16(eep->baseEepHeader.rfSilent);
258 eep->baseEepHeader.rfSilent = word;
259
260 word = swab16(eep->baseEepHeader.blueToothOptions);
261 eep->baseEepHeader.blueToothOptions = word;
262
263 word = swab16(eep->baseEepHeader.deviceCap);
264 eep->baseEepHeader.deviceCap = word;
265
266 integer = swab32(eep->modalHeader.antCtrlCommon);
267 eep->modalHeader.antCtrlCommon = integer;
268
269 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
270 integer = swab32(eep->modalHeader.antCtrlChain[i]);
271 eep->modalHeader.antCtrlChain[i] = integer;
272 }
273
274 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
275 word = swab16(eep->modalHeader.spurChans[i].spurChan);
276 eep->modalHeader.spurChans[i].spurChan = word;
277 }
278 }
279
280 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
281 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
282 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
283 sum, ah->eep_ops->get_eeprom_ver(ah));
284 return -EINVAL;
285 }
286
287 return 0;
288 }
289
290 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
291 enum eeprom_param param)
292 {
293 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
294 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
295 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
296 u16 ver_minor;
297
298 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
299
300 switch (param) {
301 case EEP_NFTHRESH_2:
302 return pModal->noiseFloorThreshCh[0];
303 case EEP_MAC_LSW:
304 return get_unaligned_be16(pBase->macAddr);
305 case EEP_MAC_MID:
306 return get_unaligned_be16(pBase->macAddr + 2);
307 case EEP_MAC_MSW:
308 return get_unaligned_be16(pBase->macAddr + 4);
309 case EEP_REG_0:
310 return pBase->regDmn[0];
311 case EEP_REG_1:
312 return pBase->regDmn[1];
313 case EEP_OP_CAP:
314 return pBase->deviceCap;
315 case EEP_OP_MODE:
316 return pBase->opCapFlags;
317 case EEP_RF_SILENT:
318 return pBase->rfSilent;
319 case EEP_MINOR_REV:
320 return ver_minor;
321 case EEP_TX_MASK:
322 return pBase->txMask;
323 case EEP_RX_MASK:
324 return pBase->rxMask;
325 case EEP_DEV_TYPE:
326 return pBase->deviceType;
327 case EEP_OL_PWRCTRL:
328 return pBase->openLoopPwrCntl;
329 case EEP_TEMPSENSE_SLOPE:
330 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
331 return pBase->tempSensSlope;
332 else
333 return 0;
334 case EEP_TEMPSENSE_SLOPE_PAL_ON:
335 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
336 return pBase->tempSensSlopePalOn;
337 else
338 return 0;
339 case EEP_ANTENNA_GAIN_2G:
340 return max_t(u8, pModal->antennaGainCh[0],
341 pModal->antennaGainCh[1]);
342 default:
343 return 0;
344 }
345 }
346
347 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
348 struct ath9k_channel *chan,
349 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
350 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
351 {
352 u16 idxL = 0, idxR = 0, numPiers;
353 bool match;
354 struct chan_centers centers;
355
356 ath9k_hw_get_channel_centers(ah, chan, &centers);
357
358 for (numPiers = 0; numPiers < availPiers; numPiers++) {
359 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
360 break;
361 }
362
363 match = ath9k_hw_get_lower_upper_index(
364 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
365 pCalChans, numPiers, &idxL, &idxR);
366
367 if (match) {
368 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
369 } else {
370 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
371 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
372 }
373
374 }
375
376 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
377 int32_t txPower, u16 chain)
378 {
379 u32 tmpVal;
380 u32 a;
381
382 /* Enable OLPC for chain 0 */
383
384 tmpVal = REG_READ(ah, 0xa270);
385 tmpVal = tmpVal & 0xFCFFFFFF;
386 tmpVal = tmpVal | (0x3 << 24);
387 REG_WRITE(ah, 0xa270, tmpVal);
388
389 /* Enable OLPC for chain 1 */
390
391 tmpVal = REG_READ(ah, 0xb270);
392 tmpVal = tmpVal & 0xFCFFFFFF;
393 tmpVal = tmpVal | (0x3 << 24);
394 REG_WRITE(ah, 0xb270, tmpVal);
395
396 /* Write the OLPC ref power for chain 0 */
397
398 if (chain == 0) {
399 tmpVal = REG_READ(ah, 0xa398);
400 tmpVal = tmpVal & 0xff00ffff;
401 a = (txPower)&0xff;
402 tmpVal = tmpVal | (a << 16);
403 REG_WRITE(ah, 0xa398, tmpVal);
404 }
405
406 /* Write the OLPC ref power for chain 1 */
407
408 if (chain == 1) {
409 tmpVal = REG_READ(ah, 0xb398);
410 tmpVal = tmpVal & 0xff00ffff;
411 a = (txPower)&0xff;
412 tmpVal = tmpVal | (a << 16);
413 REG_WRITE(ah, 0xb398, tmpVal);
414 }
415 }
416
417 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
418 struct ath9k_channel *chan)
419 {
420 struct cal_data_per_freq_ar9287 *pRawDataset;
421 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
422 u8 *pCalBChans = NULL;
423 u16 pdGainOverlap_t2;
424 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
425 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
426 u16 numPiers = 0, i, j;
427 u16 numXpdGain, xpdMask;
428 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
429 u32 reg32, regOffset, regChainOffset, regval;
430 int16_t diff = 0;
431 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
432
433 xpdMask = pEepData->modalHeader.xpdGain;
434
435 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
436 AR9287_EEP_MINOR_VER_2)
437 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
438 else
439 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
440 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
441
442 if (IS_CHAN_2GHZ(chan)) {
443 pCalBChans = pEepData->calFreqPier2G;
444 numPiers = AR9287_NUM_2G_CAL_PIERS;
445 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
446 pRawDatasetOpenLoop =
447 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
448 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
449 }
450 }
451
452 numXpdGain = 0;
453
454 /* Calculate the value of xpdgains from the xpdGain Mask */
455 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
456 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
457 if (numXpdGain >= AR5416_NUM_PD_GAINS)
458 break;
459 xpdGainValues[numXpdGain] =
460 (u16)(AR5416_PD_GAINS_IN_MASK-i);
461 numXpdGain++;
462 }
463 }
464
465 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
466 (numXpdGain - 1) & 0x3);
467 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
468 xpdGainValues[0]);
469 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
470 xpdGainValues[1]);
471 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
472 xpdGainValues[2]);
473
474 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
475 regChainOffset = i * 0x1000;
476
477 if (pEepData->baseEepHeader.txMask & (1 << i)) {
478 pRawDatasetOpenLoop =
479 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
480
481 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
482 int8_t txPower;
483 ar9287_eeprom_get_tx_gain_index(ah, chan,
484 pRawDatasetOpenLoop,
485 pCalBChans, numPiers,
486 &txPower);
487 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
488 } else {
489 pRawDataset =
490 (struct cal_data_per_freq_ar9287 *)
491 pEepData->calPierData2G[i];
492
493 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
494 pRawDataset,
495 pCalBChans, numPiers,
496 pdGainOverlap_t2,
497 gainBoundaries,
498 pdadcValues,
499 numXpdGain);
500 }
501
502 ENABLE_REGWRITE_BUFFER(ah);
503
504 if (i == 0) {
505 if (!ath9k_hw_ar9287_get_eeprom(ah,
506 EEP_OL_PWRCTRL)) {
507
508 regval = SM(pdGainOverlap_t2,
509 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
510 | SM(gainBoundaries[0],
511 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
512 | SM(gainBoundaries[1],
513 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
514 | SM(gainBoundaries[2],
515 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
516 | SM(gainBoundaries[3],
517 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
518
519 REG_WRITE(ah,
520 AR_PHY_TPCRG5 + regChainOffset,
521 regval);
522 }
523 }
524
525 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
526 pEepData->baseEepHeader.pwrTableOffset) {
527 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
528 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
529 diff *= 2;
530
531 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
532 pdadcValues[j] = pdadcValues[j+diff];
533
534 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
535 j < AR5416_NUM_PDADC_VALUES; j++)
536 pdadcValues[j] =
537 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
538 }
539
540 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
541 regOffset = AR_PHY_BASE +
542 (672 << 2) + regChainOffset;
543
544 for (j = 0; j < 32; j++) {
545 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
546
547 REG_WRITE(ah, regOffset, reg32);
548 regOffset += 4;
549 }
550 }
551 REGWRITE_BUFFER_FLUSH(ah);
552 }
553 }
554 }
555
556 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
557 struct ath9k_channel *chan,
558 int16_t *ratesArray,
559 u16 cfgCtl,
560 u16 antenna_reduction,
561 u16 powerLimit)
562 {
563 #define CMP_CTL \
564 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
565 pEepData->ctlIndex[i])
566
567 #define CMP_NO_CTL \
568 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
569 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
570
571 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
572 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
573
574 u16 twiceMaxEdgePower = MAX_RATE_POWER;
575 int i;
576 struct cal_ctl_data_ar9287 *rep;
577 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
578 targetPowerCck = {0, {0, 0, 0, 0} };
579 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
580 targetPowerCckExt = {0, {0, 0, 0, 0} };
581 struct cal_target_power_ht targetPowerHt20,
582 targetPowerHt40 = {0, {0, 0, 0, 0} };
583 u16 scaledPower = 0, minCtlPower;
584 static const u16 ctlModesFor11g[] = {
585 CTL_11B, CTL_11G, CTL_2GHT20,
586 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
587 };
588 u16 numCtlModes = 0;
589 const u16 *pCtlMode = NULL;
590 u16 ctlMode, freq;
591 struct chan_centers centers;
592 int tx_chainmask;
593 u16 twiceMinEdgePower;
594 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
595 tx_chainmask = ah->txchainmask;
596
597 ath9k_hw_get_channel_centers(ah, chan, &centers);
598 scaledPower = powerLimit - antenna_reduction;
599
600 /*
601 * Reduce scaled Power by number of chains active
602 * to get the per chain tx power level.
603 */
604 switch (ar5416_get_ntxchains(tx_chainmask)) {
605 case 1:
606 break;
607 case 2:
608 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
609 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
610 else
611 scaledPower = 0;
612 break;
613 case 3:
614 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
615 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
616 else
617 scaledPower = 0;
618 break;
619 }
620 scaledPower = max((u16)0, scaledPower);
621
622 /*
623 * Get TX power from EEPROM.
624 */
625 if (IS_CHAN_2GHZ(chan)) {
626 /* CTL_11B, CTL_11G, CTL_2GHT20 */
627 numCtlModes =
628 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
629
630 pCtlMode = ctlModesFor11g;
631
632 ath9k_hw_get_legacy_target_powers(ah, chan,
633 pEepData->calTargetPowerCck,
634 AR9287_NUM_2G_CCK_TARGET_POWERS,
635 &targetPowerCck, 4, false);
636 ath9k_hw_get_legacy_target_powers(ah, chan,
637 pEepData->calTargetPower2G,
638 AR9287_NUM_2G_20_TARGET_POWERS,
639 &targetPowerOfdm, 4, false);
640 ath9k_hw_get_target_powers(ah, chan,
641 pEepData->calTargetPower2GHT20,
642 AR9287_NUM_2G_20_TARGET_POWERS,
643 &targetPowerHt20, 8, false);
644
645 if (IS_CHAN_HT40(chan)) {
646 /* All 2G CTLs */
647 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
648 ath9k_hw_get_target_powers(ah, chan,
649 pEepData->calTargetPower2GHT40,
650 AR9287_NUM_2G_40_TARGET_POWERS,
651 &targetPowerHt40, 8, true);
652 ath9k_hw_get_legacy_target_powers(ah, chan,
653 pEepData->calTargetPowerCck,
654 AR9287_NUM_2G_CCK_TARGET_POWERS,
655 &targetPowerCckExt, 4, true);
656 ath9k_hw_get_legacy_target_powers(ah, chan,
657 pEepData->calTargetPower2G,
658 AR9287_NUM_2G_20_TARGET_POWERS,
659 &targetPowerOfdmExt, 4, true);
660 }
661 }
662
663 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
664 bool isHt40CtlMode =
665 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
666
667 if (isHt40CtlMode)
668 freq = centers.synth_center;
669 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
670 freq = centers.ext_center;
671 else
672 freq = centers.ctl_center;
673
674 /* Walk through the CTL indices stored in EEPROM */
675 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
676 struct cal_ctl_edges *pRdEdgesPower;
677
678 /*
679 * Compare test group from regulatory channel list
680 * with test mode from pCtlMode list
681 */
682 if (CMP_CTL || CMP_NO_CTL) {
683 rep = &(pEepData->ctlData[i]);
684 pRdEdgesPower =
685 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
686
687 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
688 pRdEdgesPower,
689 IS_CHAN_2GHZ(chan),
690 AR5416_NUM_BAND_EDGES);
691
692 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
693 twiceMaxEdgePower = min(twiceMaxEdgePower,
694 twiceMinEdgePower);
695 } else {
696 twiceMaxEdgePower = twiceMinEdgePower;
697 break;
698 }
699 }
700 }
701
702 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
703
704 /* Apply ctl mode to correct target power set */
705 switch (pCtlMode[ctlMode]) {
706 case CTL_11B:
707 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
708 targetPowerCck.tPow2x[i] =
709 (u8)min((u16)targetPowerCck.tPow2x[i],
710 minCtlPower);
711 }
712 break;
713 case CTL_11A:
714 case CTL_11G:
715 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
716 targetPowerOfdm.tPow2x[i] =
717 (u8)min((u16)targetPowerOfdm.tPow2x[i],
718 minCtlPower);
719 }
720 break;
721 case CTL_5GHT20:
722 case CTL_2GHT20:
723 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
724 targetPowerHt20.tPow2x[i] =
725 (u8)min((u16)targetPowerHt20.tPow2x[i],
726 minCtlPower);
727 }
728 break;
729 case CTL_11B_EXT:
730 targetPowerCckExt.tPow2x[0] =
731 (u8)min((u16)targetPowerCckExt.tPow2x[0],
732 minCtlPower);
733 break;
734 case CTL_11A_EXT:
735 case CTL_11G_EXT:
736 targetPowerOfdmExt.tPow2x[0] =
737 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
738 minCtlPower);
739 break;
740 case CTL_5GHT40:
741 case CTL_2GHT40:
742 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
743 targetPowerHt40.tPow2x[i] =
744 (u8)min((u16)targetPowerHt40.tPow2x[i],
745 minCtlPower);
746 }
747 break;
748 default:
749 break;
750 }
751 }
752
753 /* Now set the rates array */
754
755 ratesArray[rate6mb] =
756 ratesArray[rate9mb] =
757 ratesArray[rate12mb] =
758 ratesArray[rate18mb] =
759 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
760
761 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
762 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
763 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
764 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
765
766 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
767 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
768
769 if (IS_CHAN_2GHZ(chan)) {
770 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
771 ratesArray[rate2s] =
772 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
773 ratesArray[rate5_5s] =
774 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
775 ratesArray[rate11s] =
776 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
777 }
778 if (IS_CHAN_HT40(chan)) {
779 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
780 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
781
782 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
783 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
784 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
785
786 if (IS_CHAN_2GHZ(chan))
787 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
788 }
789
790 #undef CMP_CTL
791 #undef CMP_NO_CTL
792 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
793 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
794 }
795
796 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
797 struct ath9k_channel *chan, u16 cfgCtl,
798 u8 twiceAntennaReduction,
799 u8 powerLimit, bool test)
800 {
801 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
802 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
803 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
804 int16_t ratesArray[Ar5416RateSize];
805 u8 ht40PowerIncForPdadc = 2;
806 int i;
807
808 memset(ratesArray, 0, sizeof(ratesArray));
809
810 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
811 AR9287_EEP_MINOR_VER_2)
812 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
813
814 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
815 &ratesArray[0], cfgCtl,
816 twiceAntennaReduction,
817 powerLimit);
818
819 ath9k_hw_set_ar9287_power_cal_table(ah, chan);
820
821 regulatory->max_power_level = 0;
822 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
823 if (ratesArray[i] > MAX_RATE_POWER)
824 ratesArray[i] = MAX_RATE_POWER;
825
826 if (ratesArray[i] > regulatory->max_power_level)
827 regulatory->max_power_level = ratesArray[i];
828 }
829
830 if (test)
831 return;
832
833 for (i = 0; i < Ar5416RateSize; i++)
834 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
835
836 ENABLE_REGWRITE_BUFFER(ah);
837
838 /* OFDM power per rate */
839 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
840 ATH9K_POW_SM(ratesArray[rate18mb], 24)
841 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
842 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
843 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
844
845 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
846 ATH9K_POW_SM(ratesArray[rate54mb], 24)
847 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
848 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
849 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
850
851 /* CCK power per rate */
852 if (IS_CHAN_2GHZ(chan)) {
853 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
854 ATH9K_POW_SM(ratesArray[rate2s], 24)
855 | ATH9K_POW_SM(ratesArray[rate2l], 16)
856 | ATH9K_POW_SM(ratesArray[rateXr], 8)
857 | ATH9K_POW_SM(ratesArray[rate1l], 0));
858 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
859 ATH9K_POW_SM(ratesArray[rate11s], 24)
860 | ATH9K_POW_SM(ratesArray[rate11l], 16)
861 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
862 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
863 }
864
865 /* HT20 power per rate */
866 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
867 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
868 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
869 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
870 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
871
872 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
873 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
874 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
875 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
876 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
877
878 /* HT40 power per rate */
879 if (IS_CHAN_HT40(chan)) {
880 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
881 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
882 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
883 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
884 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
885 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
886
887 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
888 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
889 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
890 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
891 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
892 } else {
893 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
894 ATH9K_POW_SM(ratesArray[rateHt40_3] +
895 ht40PowerIncForPdadc, 24)
896 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
897 ht40PowerIncForPdadc, 16)
898 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
899 ht40PowerIncForPdadc, 8)
900 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
901 ht40PowerIncForPdadc, 0));
902
903 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
904 ATH9K_POW_SM(ratesArray[rateHt40_7] +
905 ht40PowerIncForPdadc, 24)
906 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
907 ht40PowerIncForPdadc, 16)
908 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
909 ht40PowerIncForPdadc, 8)
910 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
911 ht40PowerIncForPdadc, 0));
912 }
913
914 /* Dup/Ext power per rate */
915 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
916 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
917 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
918 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
919 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
920 }
921 REGWRITE_BUFFER_FLUSH(ah);
922 }
923
924 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
925 struct ath9k_channel *chan)
926 {
927 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
928 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
929 u32 regChainOffset, regval;
930 u8 txRxAttenLocal;
931 int i;
932
933 pModal = &eep->modalHeader;
934
935 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
936
937 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
938 regChainOffset = i * 0x1000;
939
940 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
941 pModal->antCtrlChain[i]);
942
943 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
944 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
945 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
946 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
947 SM(pModal->iqCalICh[i],
948 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
949 SM(pModal->iqCalQCh[i],
950 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
951
952 txRxAttenLocal = pModal->txRxAttenCh[i];
953
954 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
955 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
956 pModal->bswMargin[i]);
957 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
958 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
959 pModal->bswAtten[i]);
960 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
961 AR9280_PHY_RXGAIN_TXRX_ATTEN,
962 txRxAttenLocal);
963 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
964 AR9280_PHY_RXGAIN_TXRX_MARGIN,
965 pModal->rxTxMarginCh[i]);
966 }
967
968
969 if (IS_CHAN_HT40(chan))
970 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
971 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
972 else
973 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
974 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
975
976 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
977 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
978
979 REG_WRITE(ah, AR_PHY_RF_CTL4,
980 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
981 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
982 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
983 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
984
985 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
986 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
987
988 REG_RMW_FIELD(ah, AR_PHY_CCA,
989 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
990 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
991 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
992
993 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
994 regval &= ~(AR9287_AN_RF2G3_DB1 |
995 AR9287_AN_RF2G3_DB2 |
996 AR9287_AN_RF2G3_OB_CCK |
997 AR9287_AN_RF2G3_OB_PSK |
998 AR9287_AN_RF2G3_OB_QAM |
999 AR9287_AN_RF2G3_OB_PAL_OFF);
1000 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1001 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1002 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1003 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1004 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1005 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1006
1007 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
1008
1009 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
1010 regval &= ~(AR9287_AN_RF2G3_DB1 |
1011 AR9287_AN_RF2G3_DB2 |
1012 AR9287_AN_RF2G3_OB_CCK |
1013 AR9287_AN_RF2G3_OB_PSK |
1014 AR9287_AN_RF2G3_OB_QAM |
1015 AR9287_AN_RF2G3_OB_PAL_OFF);
1016 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1017 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1018 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1019 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1020 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1021 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1022
1023 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
1024
1025 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1026 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1027 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1028 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1029
1030 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1031 AR9287_AN_TOP2_XPABIAS_LVL,
1032 AR9287_AN_TOP2_XPABIAS_LVL_S,
1033 pModal->xpaBiasLvl);
1034 }
1035
1036 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1037 u16 i, bool is2GHz)
1038 {
1039 #define EEP_MAP9287_SPURCHAN \
1040 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1041
1042 struct ath_common *common = ath9k_hw_common(ah);
1043 u16 spur_val = AR_NO_SPUR;
1044
1045 ath_dbg(common, ATH_DBG_ANI,
1046 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1047 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1048
1049 switch (ah->config.spurmode) {
1050 case SPUR_DISABLE:
1051 break;
1052 case SPUR_ENABLE_IOCTL:
1053 spur_val = ah->config.spurchans[i][is2GHz];
1054 ath_dbg(common, ATH_DBG_ANI,
1055 "Getting spur val from new loc. %d\n", spur_val);
1056 break;
1057 case SPUR_ENABLE_EEPROM:
1058 spur_val = EEP_MAP9287_SPURCHAN;
1059 break;
1060 }
1061
1062 return spur_val;
1063
1064 #undef EEP_MAP9287_SPURCHAN
1065 }
1066
1067 const struct eeprom_ops eep_ar9287_ops = {
1068 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1069 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1070 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1071 .dump_eeprom = ath9k_hw_ar9287_dump_eeprom,
1072 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1073 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1074 .set_board_values = ath9k_hw_ar9287_set_board_values,
1075 .set_txpower = ath9k_hw_ar9287_set_txpower,
1076 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1077 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree