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NET: bna, fix lock imbalance
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bna / bnad.c
blob8158fb93cb4c595351d007a7f2196b2659a40985
1 /*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13 /*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18 #include <linux/netdevice.h>
19 #include <linux/skbuff.h>
20 #include <linux/etherdevice.h>
21 #include <linux/in.h>
22 #include <linux/ethtool.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_ether.h>
25 #include <linux/ip.h>
26
27 #include "bnad.h"
28 #include "bna.h"
29 #include "cna.h"
30
31 DEFINE_MUTEX(bnad_fwimg_mutex);
32
33 /*
34 * Module params
35 */
36 static uint bnad_msix_disable;
37 module_param(bnad_msix_disable, uint, 0444);
38 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
39
40 static uint bnad_ioc_auto_recover = 1;
41 module_param(bnad_ioc_auto_recover, uint, 0444);
42 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
43
44 /*
45 * Global variables
46 */
47 u32 bnad_rxqs_per_cq = 2;
48
49 const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
50
51 /*
52 * Local MACROS
53 */
54 #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
55
56 #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
57
58 #define BNAD_GET_MBOX_IRQ(_bnad) \
59 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
60 ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
61 ((_bnad)->pcidev->irq))
62
63 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
64 do { \
65 (_res_info)->res_type = BNA_RES_T_MEM; \
66 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
67 (_res_info)->res_u.mem_info.num = (_num); \
68 (_res_info)->res_u.mem_info.len = \
69 sizeof(struct bnad_unmap_q) + \
70 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
71 } while (0)
72
73 /*
74 * Reinitialize completions in CQ, once Rx is taken down
75 */
76 static void
77 bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
78 {
79 struct bna_cq_entry *cmpl, *next_cmpl;
80 unsigned int wi_range, wis = 0, ccb_prod = 0;
81 int i;
82
83 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
84 wi_range);
85
86 for (i = 0; i < ccb->q_depth; i++) {
87 wis++;
88 if (likely(--wi_range))
89 next_cmpl = cmpl + 1;
90 else {
91 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
92 wis = 0;
93 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
94 next_cmpl, wi_range);
95 }
96 cmpl->valid = 0;
97 cmpl = next_cmpl;
98 }
99 }
100
101 /*
102 * Frees all pending Tx Bufs
103 * At this point no activity is expected on the Q,
104 * so DMA unmap & freeing is fine.
105 */
106 static void
107 bnad_free_all_txbufs(struct bnad *bnad,
108 struct bna_tcb *tcb)
109 {
110 u16 unmap_cons;
111 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
112 struct bnad_skb_unmap *unmap_array;
113 struct sk_buff *skb = NULL;
114 int i;
115
116 unmap_array = unmap_q->unmap_array;
117
118 unmap_cons = 0;
119 while (unmap_cons < unmap_q->q_depth) {
120 skb = unmap_array[unmap_cons].skb;
121 if (!skb) {
122 unmap_cons++;
123 continue;
124 }
125 unmap_array[unmap_cons].skb = NULL;
126
127 pci_unmap_single(bnad->pcidev,
128 pci_unmap_addr(&unmap_array[unmap_cons],
129 dma_addr), skb_headlen(skb),
130 PCI_DMA_TODEVICE);
131
132 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
133 unmap_cons++;
134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
135 pci_unmap_page(bnad->pcidev,
136 pci_unmap_addr(&unmap_array[unmap_cons],
137 dma_addr),
138 skb_shinfo(skb)->frags[i].size,
139 PCI_DMA_TODEVICE);
140 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
141 0);
142 unmap_cons++;
143 }
144 dev_kfree_skb_any(skb);
145 }
146 }
147
148 /* Data Path Handlers */
149
150 /*
151 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
152 * Can be called in a) Interrupt context
153 * b) Sending context
154 * c) Tasklet context
155 */
156 static u32
157 bnad_free_txbufs(struct bnad *bnad,
158 struct bna_tcb *tcb)
159 {
160 u32 sent_packets = 0, sent_bytes = 0;
161 u16 wis, unmap_cons, updated_hw_cons;
162 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
163 struct bnad_skb_unmap *unmap_array;
164 struct sk_buff *skb;
165 int i;
166
167 /*
168 * Just return if TX is stopped. This check is useful
169 * when bnad_free_txbufs() runs out of a tasklet scheduled
170 * before bnad_cb_tx_cleanup() cleared BNAD_RF_TX_STARTED bit
171 * but this routine runs actually after the cleanup has been
172 * executed.
173 */
174 if (!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
175 return 0;
176
177 updated_hw_cons = *(tcb->hw_consumer_index);
178
179 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
180 updated_hw_cons, tcb->q_depth);
181
182 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
183
184 unmap_array = unmap_q->unmap_array;
185 unmap_cons = unmap_q->consumer_index;
186
187 prefetch(&unmap_array[unmap_cons + 1]);
188 while (wis) {
189 skb = unmap_array[unmap_cons].skb;
190
191 unmap_array[unmap_cons].skb = NULL;
192
193 sent_packets++;
194 sent_bytes += skb->len;
195 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
196
197 pci_unmap_single(bnad->pcidev,
198 pci_unmap_addr(&unmap_array[unmap_cons],
199 dma_addr), skb_headlen(skb),
200 PCI_DMA_TODEVICE);
201 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
202 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
203
204 prefetch(&unmap_array[unmap_cons + 1]);
205 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
206 prefetch(&unmap_array[unmap_cons + 1]);
207
208 pci_unmap_page(bnad->pcidev,
209 pci_unmap_addr(&unmap_array[unmap_cons],
210 dma_addr),
211 skb_shinfo(skb)->frags[i].size,
212 PCI_DMA_TODEVICE);
213 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
214 0);
215 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
216 }
217 dev_kfree_skb_any(skb);
218 }
219
220 /* Update consumer pointers. */
221 tcb->consumer_index = updated_hw_cons;
222 unmap_q->consumer_index = unmap_cons;
223
224 tcb->txq->tx_packets += sent_packets;
225 tcb->txq->tx_bytes += sent_bytes;
226
227 return sent_packets;
228 }
229
230 /* Tx Free Tasklet function */
231 /* Frees for all the tcb's in all the Tx's */
232 /*
233 * Scheduled from sending context, so that
234 * the fat Tx lock is not held for too long
235 * in the sending context.
236 */
237 static void
238 bnad_tx_free_tasklet(unsigned long bnad_ptr)
239 {
240 struct bnad *bnad = (struct bnad *)bnad_ptr;
241 struct bna_tcb *tcb;
242 u32 acked;
243 int i, j;
244
245 for (i = 0; i < bnad->num_tx; i++) {
246 for (j = 0; j < bnad->num_txq_per_tx; j++) {
247 tcb = bnad->tx_info[i].tcb[j];
248 if (!tcb)
249 continue;
250 if (((u16) (*tcb->hw_consumer_index) !=
251 tcb->consumer_index) &&
252 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
253 &tcb->flags))) {
254 acked = bnad_free_txbufs(bnad, tcb);
255 bna_ib_ack(tcb->i_dbell, acked);
256 smp_mb__before_clear_bit();
257 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
258 }
259 }
260 }
261 }
262
263 static u32
264 bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
265 {
266 struct net_device *netdev = bnad->netdev;
267 u32 sent;
268
269 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
270 return 0;
271
272 sent = bnad_free_txbufs(bnad, tcb);
273 if (sent) {
274 if (netif_queue_stopped(netdev) &&
275 netif_carrier_ok(netdev) &&
276 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
277 BNAD_NETIF_WAKE_THRESHOLD) {
278 netif_wake_queue(netdev);
279 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
280 }
281 bna_ib_ack(tcb->i_dbell, sent);
282 } else
283 bna_ib_ack(tcb->i_dbell, 0);
284
285 smp_mb__before_clear_bit();
286 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
287
288 return sent;
289 }
290
291 /* MSIX Tx Completion Handler */
292 static irqreturn_t
293 bnad_msix_tx(int irq, void *data)
294 {
295 struct bna_tcb *tcb = (struct bna_tcb *)data;
296 struct bnad *bnad = tcb->bnad;
297
298 bnad_tx(bnad, tcb);
299
300 return IRQ_HANDLED;
301 }
302
303 static void
304 bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
305 {
306 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
307
308 rcb->producer_index = 0;
309 rcb->consumer_index = 0;
310
311 unmap_q->producer_index = 0;
312 unmap_q->consumer_index = 0;
313 }
314
315 static void
316 bnad_free_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
317 {
318 struct bnad_unmap_q *unmap_q;
319 struct sk_buff *skb;
320
321 unmap_q = rcb->unmap_q;
322 while (BNA_QE_IN_USE_CNT(unmap_q, unmap_q->q_depth)) {
323 skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
324 BUG_ON(!(skb));
325 unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
326 pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q->
327 unmap_array[unmap_q->consumer_index],
328 dma_addr), rcb->rxq->buffer_size +
329 NET_IP_ALIGN, PCI_DMA_FROMDEVICE);
330 dev_kfree_skb(skb);
331 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
332 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
333 }
334
335 bnad_reset_rcb(bnad, rcb);
336 }
337
338 static void
339 bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
340 {
341 u16 to_alloc, alloced, unmap_prod, wi_range;
342 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
343 struct bnad_skb_unmap *unmap_array;
344 struct bna_rxq_entry *rxent;
345 struct sk_buff *skb;
346 dma_addr_t dma_addr;
347
348 alloced = 0;
349 to_alloc =
350 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
351
352 unmap_array = unmap_q->unmap_array;
353 unmap_prod = unmap_q->producer_index;
354
355 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
356
357 while (to_alloc--) {
358 if (!wi_range) {
359 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
360 wi_range);
361 }
362 skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN,
363 GFP_ATOMIC);
364 if (unlikely(!skb)) {
365 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
366 goto finishing;
367 }
368 skb->dev = bnad->netdev;
369 skb_reserve(skb, NET_IP_ALIGN);
370 unmap_array[unmap_prod].skb = skb;
371 dma_addr = pci_map_single(bnad->pcidev, skb->data,
372 rcb->rxq->buffer_size, PCI_DMA_FROMDEVICE);
373 pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
374 dma_addr);
375 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
376 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
377
378 rxent++;
379 wi_range--;
380 alloced++;
381 }
382
383 finishing:
384 if (likely(alloced)) {
385 unmap_q->producer_index = unmap_prod;
386 rcb->producer_index = unmap_prod;
387 smp_mb();
388 bna_rxq_prod_indx_doorbell(rcb);
389 }
390 }
391
392 /*
393 * Locking is required in the enable path
394 * because it is called from a napi poll
395 * context, where the bna_lock is not held
396 * unlike the IRQ context.
397 */
398 static void
399 bnad_enable_txrx_irqs(struct bnad *bnad)
400 {
401 struct bna_tcb *tcb;
402 struct bna_ccb *ccb;
403 int i, j;
404 unsigned long flags;
405
406 spin_lock_irqsave(&bnad->bna_lock, flags);
407 for (i = 0; i < bnad->num_tx; i++) {
408 for (j = 0; j < bnad->num_txq_per_tx; j++) {
409 tcb = bnad->tx_info[i].tcb[j];
410 bna_ib_coalescing_timer_set(tcb->i_dbell,
411 tcb->txq->ib->ib_config.coalescing_timeo);
412 bna_ib_ack(tcb->i_dbell, 0);
413 }
414 }
415
416 for (i = 0; i < bnad->num_rx; i++) {
417 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
418 ccb = bnad->rx_info[i].rx_ctrl[j].ccb;
419 bnad_enable_rx_irq_unsafe(ccb);
420 }
421 }
422 spin_unlock_irqrestore(&bnad->bna_lock, flags);
423 }
424
425 static inline void
426 bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
427 {
428 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
429
430 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
431 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
432 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
433 bnad_alloc_n_post_rxbufs(bnad, rcb);
434 smp_mb__before_clear_bit();
435 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
436 }
437 }
438
439 static u32
440 bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
441 {
442 struct bna_cq_entry *cmpl, *next_cmpl;
443 struct bna_rcb *rcb = NULL;
444 unsigned int wi_range, packets = 0, wis = 0;
445 struct bnad_unmap_q *unmap_q;
446 struct sk_buff *skb;
447 u32 flags;
448 u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
449 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
450
451 prefetch(bnad->netdev);
452 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
453 wi_range);
454 BUG_ON(!(wi_range <= ccb->q_depth));
455 while (cmpl->valid && packets < budget) {
456 packets++;
457 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
458
459 if (qid0 == cmpl->rxq_id)
460 rcb = ccb->rcb[0];
461 else
462 rcb = ccb->rcb[1];
463
464 unmap_q = rcb->unmap_q;
465
466 skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
467 BUG_ON(!(skb));
468 unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
469 pci_unmap_single(bnad->pcidev,
470 pci_unmap_addr(&unmap_q->
471 unmap_array[unmap_q->
472 consumer_index],
473 dma_addr),
474 rcb->rxq->buffer_size,
475 PCI_DMA_FROMDEVICE);
476 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
477
478 /* Should be more efficient ? Performance ? */
479 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
480
481 wis++;
482 if (likely(--wi_range))
483 next_cmpl = cmpl + 1;
484 else {
485 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
486 wis = 0;
487 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
488 next_cmpl, wi_range);
489 BUG_ON(!(wi_range <= ccb->q_depth));
490 }
491 prefetch(next_cmpl);
492
493 flags = ntohl(cmpl->flags);
494 if (unlikely
495 (flags &
496 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
497 BNA_CQ_EF_TOO_LONG))) {
498 dev_kfree_skb_any(skb);
499 rcb->rxq->rx_packets_with_error++;
500 goto next;
501 }
502
503 skb_put(skb, ntohs(cmpl->length));
504 if (likely
505 (bnad->rx_csum &&
506 (((flags & BNA_CQ_EF_IPV4) &&
507 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
508 (flags & BNA_CQ_EF_IPV6)) &&
509 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
510 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
511 skb->ip_summed = CHECKSUM_UNNECESSARY;
512 else
513 skb_checksum_none_assert(skb);
514
515 rcb->rxq->rx_packets++;
516 rcb->rxq->rx_bytes += skb->len;
517 skb->protocol = eth_type_trans(skb, bnad->netdev);
518
519 if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) {
520 struct bnad_rx_ctrl *rx_ctrl =
521 (struct bnad_rx_ctrl *)ccb->ctrl;
522 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
523 vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp,
524 ntohs(cmpl->vlan_tag), skb);
525 else
526 vlan_hwaccel_receive_skb(skb,
527 bnad->vlan_grp,
528 ntohs(cmpl->vlan_tag));
529
530 } else { /* Not VLAN tagged/stripped */
531 struct bnad_rx_ctrl *rx_ctrl =
532 (struct bnad_rx_ctrl *)ccb->ctrl;
533 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
534 napi_gro_receive(&rx_ctrl->napi, skb);
535 else
536 netif_receive_skb(skb);
537 }
538
539 next:
540 cmpl->valid = 0;
541 cmpl = next_cmpl;
542 }
543
544 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
545
546 if (likely(ccb)) {
547 bna_ib_ack(ccb->i_dbell, packets);
548 bnad_refill_rxq(bnad, ccb->rcb[0]);
549 if (ccb->rcb[1])
550 bnad_refill_rxq(bnad, ccb->rcb[1]);
551 } else
552 bna_ib_ack(ccb->i_dbell, 0);
553
554 return packets;
555 }
556
557 static void
558 bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
559 {
560 bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
561 bna_ib_ack(ccb->i_dbell, 0);
562 }
563
564 static void
565 bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
566 {
567 spin_lock_irq(&bnad->bna_lock); /* Because of polling context */
568 bnad_enable_rx_irq_unsafe(ccb);
569 spin_unlock_irq(&bnad->bna_lock);
570 }
571
572 static void
573 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
574 {
575 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
576 if (likely(napi_schedule_prep((&rx_ctrl->napi)))) {
577 bnad_disable_rx_irq(bnad, ccb);
578 __napi_schedule((&rx_ctrl->napi));
579 }
580 BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
581 }
582
583 /* MSIX Rx Path Handler */
584 static irqreturn_t
585 bnad_msix_rx(int irq, void *data)
586 {
587 struct bna_ccb *ccb = (struct bna_ccb *)data;
588 struct bnad *bnad = ccb->bnad;
589
590 bnad_netif_rx_schedule_poll(bnad, ccb);
591
592 return IRQ_HANDLED;
593 }
594
595 /* Interrupt handlers */
596
597 /* Mbox Interrupt Handlers */
598 static irqreturn_t
599 bnad_msix_mbox_handler(int irq, void *data)
600 {
601 u32 intr_status;
602 unsigned long flags;
603 struct net_device *netdev = data;
604 struct bnad *bnad;
605
606 bnad = netdev_priv(netdev);
607
608 /* BNA_ISR_GET(bnad); Inc Ref count */
609 spin_lock_irqsave(&bnad->bna_lock, flags);
610
611 bna_intr_status_get(&bnad->bna, intr_status);
612
613 if (BNA_IS_MBOX_ERR_INTR(intr_status))
614 bna_mbox_handler(&bnad->bna, intr_status);
615
616 spin_unlock_irqrestore(&bnad->bna_lock, flags);
617
618 /* BNAD_ISR_PUT(bnad); Dec Ref count */
619 return IRQ_HANDLED;
620 }
621
622 static irqreturn_t
623 bnad_isr(int irq, void *data)
624 {
625 int i, j;
626 u32 intr_status;
627 unsigned long flags;
628 struct net_device *netdev = data;
629 struct bnad *bnad = netdev_priv(netdev);
630 struct bnad_rx_info *rx_info;
631 struct bnad_rx_ctrl *rx_ctrl;
632
633 spin_lock_irqsave(&bnad->bna_lock, flags);
634
635 bna_intr_status_get(&bnad->bna, intr_status);
636 if (!intr_status) {
637 spin_unlock_irqrestore(&bnad->bna_lock, flags);
638 return IRQ_NONE;
639 }
640
641 if (BNA_IS_MBOX_ERR_INTR(intr_status)) {
642 bna_mbox_handler(&bnad->bna, intr_status);
643 if (!BNA_IS_INTX_DATA_INTR(intr_status)) {
644 spin_unlock_irqrestore(&bnad->bna_lock, flags);
645 goto done;
646 }
647 }
648 spin_unlock_irqrestore(&bnad->bna_lock, flags);
649
650 /* Process data interrupts */
651 for (i = 0; i < bnad->num_rx; i++) {
652 rx_info = &bnad->rx_info[i];
653 if (!rx_info->rx)
654 continue;
655 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
656 rx_ctrl = &rx_info->rx_ctrl[j];
657 if (rx_ctrl->ccb)
658 bnad_netif_rx_schedule_poll(bnad,
659 rx_ctrl->ccb);
660 }
661 }
662 done:
663 return IRQ_HANDLED;
664 }
665
666 /*
667 * Called in interrupt / callback context
668 * with bna_lock held, so cfg_flags access is OK
669 */
670 static void
671 bnad_enable_mbox_irq(struct bnad *bnad)
672 {
673 int irq = BNAD_GET_MBOX_IRQ(bnad);
674
675 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
676 return;
677
678 if (test_and_clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
679 enable_irq(irq);
680 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
681 }
682
683 /*
684 * Called with bnad->bna_lock held b'cos of
685 * bnad->cfg_flags access.
686 */
687 void
688 bnad_disable_mbox_irq(struct bnad *bnad)
689 {
690 int irq = BNAD_GET_MBOX_IRQ(bnad);
691
692 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
693 return;
694
695 if (!test_and_set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
696 disable_irq_nosync(irq);
697 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
698 }
699
700 /* Control Path Handlers */
701
702 /* Callbacks */
703 void
704 bnad_cb_device_enable_mbox_intr(struct bnad *bnad)
705 {
706 bnad_enable_mbox_irq(bnad);
707 }
708
709 void
710 bnad_cb_device_disable_mbox_intr(struct bnad *bnad)
711 {
712 bnad_disable_mbox_irq(bnad);
713 }
714
715 void
716 bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status)
717 {
718 complete(&bnad->bnad_completions.ioc_comp);
719 bnad->bnad_completions.ioc_comp_status = status;
720 }
721
722 void
723 bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status)
724 {
725 complete(&bnad->bnad_completions.ioc_comp);
726 bnad->bnad_completions.ioc_comp_status = status;
727 }
728
729 static void
730 bnad_cb_port_disabled(void *arg, enum bna_cb_status status)
731 {
732 struct bnad *bnad = (struct bnad *)arg;
733
734 complete(&bnad->bnad_completions.port_comp);
735
736 netif_carrier_off(bnad->netdev);
737 }
738
739 void
740 bnad_cb_port_link_status(struct bnad *bnad,
741 enum bna_link_status link_status)
742 {
743 bool link_up = 0;
744
745 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
746
747 if (link_status == BNA_CEE_UP) {
748 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
749 BNAD_UPDATE_CTR(bnad, cee_up);
750 } else
751 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
752
753 if (link_up) {
754 if (!netif_carrier_ok(bnad->netdev)) {
755 pr_warn("bna: %s link up\n",
756 bnad->netdev->name);
757 netif_carrier_on(bnad->netdev);
758 BNAD_UPDATE_CTR(bnad, link_toggle);
759 if (test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) {
760 /* Force an immediate Transmit Schedule */
761 pr_info("bna: %s TX_STARTED\n",
762 bnad->netdev->name);
763 netif_wake_queue(bnad->netdev);
764 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
765 } else {
766 netif_stop_queue(bnad->netdev);
767 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
768 }
769 }
770 } else {
771 if (netif_carrier_ok(bnad->netdev)) {
772 pr_warn("bna: %s link down\n",
773 bnad->netdev->name);
774 netif_carrier_off(bnad->netdev);
775 BNAD_UPDATE_CTR(bnad, link_toggle);
776 }
777 }
778 }
779
780 static void
781 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx,
782 enum bna_cb_status status)
783 {
784 struct bnad *bnad = (struct bnad *)arg;
785
786 complete(&bnad->bnad_completions.tx_comp);
787 }
788
789 static void
790 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
791 {
792 struct bnad_tx_info *tx_info =
793 (struct bnad_tx_info *)tcb->txq->tx->priv;
794 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
795
796 tx_info->tcb[tcb->id] = tcb;
797 unmap_q->producer_index = 0;
798 unmap_q->consumer_index = 0;
799 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
800 }
801
802 static void
803 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
804 {
805 struct bnad_tx_info *tx_info =
806 (struct bnad_tx_info *)tcb->txq->tx->priv;
807
808 tx_info->tcb[tcb->id] = NULL;
809 }
810
811 static void
812 bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
813 {
814 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
815
816 unmap_q->producer_index = 0;
817 unmap_q->consumer_index = 0;
818 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
819 }
820
821 static void
822 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
823 {
824 struct bnad_rx_info *rx_info =
825 (struct bnad_rx_info *)ccb->cq->rx->priv;
826
827 rx_info->rx_ctrl[ccb->id].ccb = ccb;
828 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
829 }
830
831 static void
832 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
833 {
834 struct bnad_rx_info *rx_info =
835 (struct bnad_rx_info *)ccb->cq->rx->priv;
836
837 rx_info->rx_ctrl[ccb->id].ccb = NULL;
838 }
839
840 static void
841 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
842 {
843 struct bnad_tx_info *tx_info =
844 (struct bnad_tx_info *)tcb->txq->tx->priv;
845
846 if (tx_info != &bnad->tx_info[0])
847 return;
848
849 clear_bit(BNAD_RF_TX_STARTED, &bnad->run_flags);
850 netif_stop_queue(bnad->netdev);
851 pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
852 }
853
854 static void
855 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
856 {
857 if (test_and_set_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
858 return;
859
860 if (netif_carrier_ok(bnad->netdev)) {
861 pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
862 netif_wake_queue(bnad->netdev);
863 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
864 }
865 }
866
867 static void
868 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
869 {
870 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
871
872 if (!tcb || (!tcb->unmap_q))
873 return;
874
875 if (!unmap_q->unmap_array)
876 return;
877
878 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
879 return;
880
881 bnad_free_all_txbufs(bnad, tcb);
882
883 unmap_q->producer_index = 0;
884 unmap_q->consumer_index = 0;
885
886 smp_mb__before_clear_bit();
887 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
888 }
889
890 static void
891 bnad_cb_rx_cleanup(struct bnad *bnad,
892 struct bna_ccb *ccb)
893 {
894 bnad_cq_cmpl_init(bnad, ccb);
895
896 bnad_free_rxbufs(bnad, ccb->rcb[0]);
897 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
898
899 if (ccb->rcb[1]) {
900 bnad_free_rxbufs(bnad, ccb->rcb[1]);
901 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
902 }
903 }
904
905 static void
906 bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
907 {
908 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
909
910 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
911
912 /* Now allocate & post buffers for this RCB */
913 /* !!Allocation in callback context */
914 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
915 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
916 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
917 bnad_alloc_n_post_rxbufs(bnad, rcb);
918 smp_mb__before_clear_bit();
919 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
920 }
921 }
922
923 static void
924 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx,
925 enum bna_cb_status status)
926 {
927 struct bnad *bnad = (struct bnad *)arg;
928
929 complete(&bnad->bnad_completions.rx_comp);
930 }
931
932 static void
933 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx,
934 enum bna_cb_status status)
935 {
936 bnad->bnad_completions.mcast_comp_status = status;
937 complete(&bnad->bnad_completions.mcast_comp);
938 }
939
940 void
941 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
942 struct bna_stats *stats)
943 {
944 if (status == BNA_CB_SUCCESS)
945 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
946
947 if (!netif_running(bnad->netdev) ||
948 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
949 return;
950
951 mod_timer(&bnad->stats_timer,
952 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
953 }
954
955 void
956 bnad_cb_stats_clr(struct bnad *bnad)
957 {
958 }
959
960 /* Resource allocation, free functions */
961
962 static void
963 bnad_mem_free(struct bnad *bnad,
964 struct bna_mem_info *mem_info)
965 {
966 int i;
967 dma_addr_t dma_pa;
968
969 if (mem_info->mdl == NULL)
970 return;
971
972 for (i = 0; i < mem_info->num; i++) {
973 if (mem_info->mdl[i].kva != NULL) {
974 if (mem_info->mem_type == BNA_MEM_T_DMA) {
975 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
976 dma_pa);
977 pci_free_consistent(bnad->pcidev,
978 mem_info->mdl[i].len,
979 mem_info->mdl[i].kva, dma_pa);
980 } else
981 kfree(mem_info->mdl[i].kva);
982 }
983 }
984 kfree(mem_info->mdl);
985 mem_info->mdl = NULL;
986 }
987
988 static int
989 bnad_mem_alloc(struct bnad *bnad,
990 struct bna_mem_info *mem_info)
991 {
992 int i;
993 dma_addr_t dma_pa;
994
995 if ((mem_info->num == 0) || (mem_info->len == 0)) {
996 mem_info->mdl = NULL;
997 return 0;
998 }
999
1000 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1001 GFP_KERNEL);
1002 if (mem_info->mdl == NULL)
1003 return -ENOMEM;
1004
1005 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1006 for (i = 0; i < mem_info->num; i++) {
1007 mem_info->mdl[i].len = mem_info->len;
1008 mem_info->mdl[i].kva =
1009 pci_alloc_consistent(bnad->pcidev,
1010 mem_info->len, &dma_pa);
1011
1012 if (mem_info->mdl[i].kva == NULL)
1013 goto err_return;
1014
1015 BNA_SET_DMA_ADDR(dma_pa,
1016 &(mem_info->mdl[i].dma));
1017 }
1018 } else {
1019 for (i = 0; i < mem_info->num; i++) {
1020 mem_info->mdl[i].len = mem_info->len;
1021 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1022 GFP_KERNEL);
1023 if (mem_info->mdl[i].kva == NULL)
1024 goto err_return;
1025 }
1026 }
1027
1028 return 0;
1029
1030 err_return:
1031 bnad_mem_free(bnad, mem_info);
1032 return -ENOMEM;
1033 }
1034
1035 /* Free IRQ for Mailbox */
1036 static void
1037 bnad_mbox_irq_free(struct bnad *bnad,
1038 struct bna_intr_info *intr_info)
1039 {
1040 int irq;
1041 unsigned long flags;
1042
1043 if (intr_info->idl == NULL)
1044 return;
1045
1046 spin_lock_irqsave(&bnad->bna_lock, flags);
1047
1048 bnad_disable_mbox_irq(bnad);
1049
1050 irq = BNAD_GET_MBOX_IRQ(bnad);
1051 free_irq(irq, bnad->netdev);
1052
1053 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1054
1055 kfree(intr_info->idl);
1056 }
1057
1058 /*
1059 * Allocates IRQ for Mailbox, but keep it disabled
1060 * This will be enabled once we get the mbox enable callback
1061 * from bna
1062 */
1063 static int
1064 bnad_mbox_irq_alloc(struct bnad *bnad,
1065 struct bna_intr_info *intr_info)
1066 {
1067 int err;
1068 unsigned long flags;
1069 u32 irq;
1070 irq_handler_t irq_handler;
1071
1072 /* Mbox should use only 1 vector */
1073
1074 intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL);
1075 if (!intr_info->idl)
1076 return -ENOMEM;
1077
1078 spin_lock_irqsave(&bnad->bna_lock, flags);
1079 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1080 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1081 irq = bnad->msix_table[bnad->msix_num - 1].vector;
1082 flags = 0;
1083 intr_info->intr_type = BNA_INTR_T_MSIX;
1084 intr_info->idl[0].vector = bnad->msix_num - 1;
1085 } else {
1086 irq_handler = (irq_handler_t)bnad_isr;
1087 irq = bnad->pcidev->irq;
1088 flags = IRQF_SHARED;
1089 intr_info->intr_type = BNA_INTR_T_INTX;
1090 /* intr_info->idl.vector = 0 ? */
1091 }
1092 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1093
1094 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1095
1096 err = request_irq(irq, irq_handler, flags,
1097 bnad->mbox_irq_name, bnad->netdev);
1098 if (err) {
1099 kfree(intr_info->idl);
1100 intr_info->idl = NULL;
1101 return err;
1102 }
1103
1104 spin_lock_irqsave(&bnad->bna_lock, flags);
1105 bnad_disable_mbox_irq(bnad);
1106 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1107 return 0;
1108 }
1109
1110 static void
1111 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1112 {
1113 kfree(intr_info->idl);
1114 intr_info->idl = NULL;
1115 }
1116
1117 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1118 static int
1119 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1120 uint txrx_id, struct bna_intr_info *intr_info)
1121 {
1122 int i, vector_start = 0;
1123 u32 cfg_flags;
1124 unsigned long flags;
1125
1126 spin_lock_irqsave(&bnad->bna_lock, flags);
1127 cfg_flags = bnad->cfg_flags;
1128 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1129
1130 if (cfg_flags & BNAD_CF_MSIX) {
1131 intr_info->intr_type = BNA_INTR_T_MSIX;
1132 intr_info->idl = kcalloc(intr_info->num,
1133 sizeof(struct bna_intr_descr),
1134 GFP_KERNEL);
1135 if (!intr_info->idl)
1136 return -ENOMEM;
1137
1138 switch (src) {
1139 case BNAD_INTR_TX:
1140 vector_start = txrx_id;
1141 break;
1142
1143 case BNAD_INTR_RX:
1144 vector_start = bnad->num_tx * bnad->num_txq_per_tx +
1145 txrx_id;
1146 break;
1147
1148 default:
1149 BUG();
1150 }
1151
1152 for (i = 0; i < intr_info->num; i++)
1153 intr_info->idl[i].vector = vector_start + i;
1154 } else {
1155 intr_info->intr_type = BNA_INTR_T_INTX;
1156 intr_info->num = 1;
1157 intr_info->idl = kcalloc(intr_info->num,
1158 sizeof(struct bna_intr_descr),
1159 GFP_KERNEL);
1160 if (!intr_info->idl)
1161 return -ENOMEM;
1162
1163 switch (src) {
1164 case BNAD_INTR_TX:
1165 intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */
1166 break;
1167
1168 case BNAD_INTR_RX:
1169 intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */
1170 break;
1171 }
1172 }
1173 return 0;
1174 }
1175
1176 /**
1177 * NOTE: Should be called for MSIX only
1178 * Unregisters Tx MSIX vector(s) from the kernel
1179 */
1180 static void
1181 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1182 int num_txqs)
1183 {
1184 int i;
1185 int vector_num;
1186
1187 for (i = 0; i < num_txqs; i++) {
1188 if (tx_info->tcb[i] == NULL)
1189 continue;
1190
1191 vector_num = tx_info->tcb[i]->intr_vector;
1192 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1193 }
1194 }
1195
1196 /**
1197 * NOTE: Should be called for MSIX only
1198 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1199 */
1200 static int
1201 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1202 uint tx_id, int num_txqs)
1203 {
1204 int i;
1205 int err;
1206 int vector_num;
1207
1208 for (i = 0; i < num_txqs; i++) {
1209 vector_num = tx_info->tcb[i]->intr_vector;
1210 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1211 tx_id + tx_info->tcb[i]->id);
1212 err = request_irq(bnad->msix_table[vector_num].vector,
1213 (irq_handler_t)bnad_msix_tx, 0,
1214 tx_info->tcb[i]->name,
1215 tx_info->tcb[i]);
1216 if (err)
1217 goto err_return;
1218 }
1219
1220 return 0;
1221
1222 err_return:
1223 if (i > 0)
1224 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1225 return -1;
1226 }
1227
1228 /**
1229 * NOTE: Should be called for MSIX only
1230 * Unregisters Rx MSIX vector(s) from the kernel
1231 */
1232 static void
1233 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1234 int num_rxps)
1235 {
1236 int i;
1237 int vector_num;
1238
1239 for (i = 0; i < num_rxps; i++) {
1240 if (rx_info->rx_ctrl[i].ccb == NULL)
1241 continue;
1242
1243 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1244 free_irq(bnad->msix_table[vector_num].vector,
1245 rx_info->rx_ctrl[i].ccb);
1246 }
1247 }
1248
1249 /**
1250 * NOTE: Should be called for MSIX only
1251 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1252 */
1253 static int
1254 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1255 uint rx_id, int num_rxps)
1256 {
1257 int i;
1258 int err;
1259 int vector_num;
1260
1261 for (i = 0; i < num_rxps; i++) {
1262 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1263 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1264 bnad->netdev->name,
1265 rx_id + rx_info->rx_ctrl[i].ccb->id);
1266 err = request_irq(bnad->msix_table[vector_num].vector,
1267 (irq_handler_t)bnad_msix_rx, 0,
1268 rx_info->rx_ctrl[i].ccb->name,
1269 rx_info->rx_ctrl[i].ccb);
1270 if (err)
1271 goto err_return;
1272 }
1273
1274 return 0;
1275
1276 err_return:
1277 if (i > 0)
1278 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1279 return -1;
1280 }
1281
1282 /* Free Tx object Resources */
1283 static void
1284 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1285 {
1286 int i;
1287
1288 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1289 if (res_info[i].res_type == BNA_RES_T_MEM)
1290 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1291 else if (res_info[i].res_type == BNA_RES_T_INTR)
1292 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1293 }
1294 }
1295
1296 /* Allocates memory and interrupt resources for Tx object */
1297 static int
1298 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1299 uint tx_id)
1300 {
1301 int i, err = 0;
1302
1303 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1304 if (res_info[i].res_type == BNA_RES_T_MEM)
1305 err = bnad_mem_alloc(bnad,
1306 &res_info[i].res_u.mem_info);
1307 else if (res_info[i].res_type == BNA_RES_T_INTR)
1308 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1309 &res_info[i].res_u.intr_info);
1310 if (err)
1311 goto err_return;
1312 }
1313 return 0;
1314
1315 err_return:
1316 bnad_tx_res_free(bnad, res_info);
1317 return err;
1318 }
1319
1320 /* Free Rx object Resources */
1321 static void
1322 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1323 {
1324 int i;
1325
1326 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1327 if (res_info[i].res_type == BNA_RES_T_MEM)
1328 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1329 else if (res_info[i].res_type == BNA_RES_T_INTR)
1330 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1331 }
1332 }
1333
1334 /* Allocates memory and interrupt resources for Rx object */
1335 static int
1336 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1337 uint rx_id)
1338 {
1339 int i, err = 0;
1340
1341 /* All memory needs to be allocated before setup_ccbs */
1342 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1343 if (res_info[i].res_type == BNA_RES_T_MEM)
1344 err = bnad_mem_alloc(bnad,
1345 &res_info[i].res_u.mem_info);
1346 else if (res_info[i].res_type == BNA_RES_T_INTR)
1347 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1348 &res_info[i].res_u.intr_info);
1349 if (err)
1350 goto err_return;
1351 }
1352 return 0;
1353
1354 err_return:
1355 bnad_rx_res_free(bnad, res_info);
1356 return err;
1357 }
1358
1359 /* Timer callbacks */
1360 /* a) IOC timer */
1361 static void
1362 bnad_ioc_timeout(unsigned long data)
1363 {
1364 struct bnad *bnad = (struct bnad *)data;
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&bnad->bna_lock, flags);
1368 bfa_nw_ioc_timeout((void *) &bnad->bna.device.ioc);
1369 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1370 }
1371
1372 static void
1373 bnad_ioc_hb_check(unsigned long data)
1374 {
1375 struct bnad *bnad = (struct bnad *)data;
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&bnad->bna_lock, flags);
1379 bfa_nw_ioc_hb_check((void *) &bnad->bna.device.ioc);
1380 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1381 }
1382
1383 static void
1384 bnad_ioc_sem_timeout(unsigned long data)
1385 {
1386 struct bnad *bnad = (struct bnad *)data;
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&bnad->bna_lock, flags);
1390 bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
1391 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1392 }
1393
1394 /*
1395 * All timer routines use bnad->bna_lock to protect against
1396 * the following race, which may occur in case of no locking:
1397 * Time CPU m CPU n
1398 * 0 1 = test_bit
1399 * 1 clear_bit
1400 * 2 del_timer_sync
1401 * 3 mod_timer
1402 */
1403
1404 /* b) Dynamic Interrupt Moderation Timer */
1405 static void
1406 bnad_dim_timeout(unsigned long data)
1407 {
1408 struct bnad *bnad = (struct bnad *)data;
1409 struct bnad_rx_info *rx_info;
1410 struct bnad_rx_ctrl *rx_ctrl;
1411 int i, j;
1412 unsigned long flags;
1413
1414 if (!netif_carrier_ok(bnad->netdev))
1415 return;
1416
1417 spin_lock_irqsave(&bnad->bna_lock, flags);
1418 for (i = 0; i < bnad->num_rx; i++) {
1419 rx_info = &bnad->rx_info[i];
1420 if (!rx_info->rx)
1421 continue;
1422 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1423 rx_ctrl = &rx_info->rx_ctrl[j];
1424 if (!rx_ctrl->ccb)
1425 continue;
1426 bna_rx_dim_update(rx_ctrl->ccb);
1427 }
1428 }
1429
1430 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1431 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1432 mod_timer(&bnad->dim_timer,
1433 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1434 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1435 }
1436
1437 /* c) Statistics Timer */
1438 static void
1439 bnad_stats_timeout(unsigned long data)
1440 {
1441 struct bnad *bnad = (struct bnad *)data;
1442 unsigned long flags;
1443
1444 if (!netif_running(bnad->netdev) ||
1445 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1446 return;
1447
1448 spin_lock_irqsave(&bnad->bna_lock, flags);
1449 bna_stats_get(&bnad->bna);
1450 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1451 }
1452
1453 /*
1454 * Set up timer for DIM
1455 * Called with bnad->bna_lock held
1456 */
1457 void
1458 bnad_dim_timer_start(struct bnad *bnad)
1459 {
1460 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1461 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1462 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1463 (unsigned long)bnad);
1464 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1465 mod_timer(&bnad->dim_timer,
1466 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1467 }
1468 }
1469
1470 /*
1471 * Set up timer for statistics
1472 * Called with mutex_lock(&bnad->conf_mutex) held
1473 */
1474 static void
1475 bnad_stats_timer_start(struct bnad *bnad)
1476 {
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&bnad->bna_lock, flags);
1480 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1481 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1482 (unsigned long)bnad);
1483 mod_timer(&bnad->stats_timer,
1484 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1485 }
1486 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1487
1488 }
1489
1490 /*
1491 * Stops the stats timer
1492 * Called with mutex_lock(&bnad->conf_mutex) held
1493 */
1494 static void
1495 bnad_stats_timer_stop(struct bnad *bnad)
1496 {
1497 int to_del = 0;
1498 unsigned long flags;
1499
1500 spin_lock_irqsave(&bnad->bna_lock, flags);
1501 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1502 to_del = 1;
1503 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1504 if (to_del)
1505 del_timer_sync(&bnad->stats_timer);
1506 }
1507
1508 /* Utilities */
1509
1510 static void
1511 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1512 {
1513 int i = 1; /* Index 0 has broadcast address */
1514 struct netdev_hw_addr *mc_addr;
1515
1516 netdev_for_each_mc_addr(mc_addr, netdev) {
1517 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1518 ETH_ALEN);
1519 i++;
1520 }
1521 }
1522
1523 static int
1524 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1525 {
1526 struct bnad_rx_ctrl *rx_ctrl =
1527 container_of(napi, struct bnad_rx_ctrl, napi);
1528 struct bna_ccb *ccb;
1529 struct bnad *bnad;
1530 int rcvd = 0;
1531
1532 ccb = rx_ctrl->ccb;
1533
1534 bnad = ccb->bnad;
1535
1536 if (!netif_carrier_ok(bnad->netdev))
1537 goto poll_exit;
1538
1539 rcvd = bnad_poll_cq(bnad, ccb, budget);
1540 if (rcvd == budget)
1541 return rcvd;
1542
1543 poll_exit:
1544 napi_complete((napi));
1545
1546 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1547
1548 bnad_enable_rx_irq(bnad, ccb);
1549 return rcvd;
1550 }
1551
1552 static int
1553 bnad_napi_poll_txrx(struct napi_struct *napi, int budget)
1554 {
1555 struct bnad_rx_ctrl *rx_ctrl =
1556 container_of(napi, struct bnad_rx_ctrl, napi);
1557 struct bna_ccb *ccb;
1558 struct bnad *bnad;
1559 int rcvd = 0;
1560 int i, j;
1561
1562 ccb = rx_ctrl->ccb;
1563
1564 bnad = ccb->bnad;
1565
1566 if (!netif_carrier_ok(bnad->netdev))
1567 goto poll_exit;
1568
1569 /* Handle Tx Completions, if any */
1570 for (i = 0; i < bnad->num_tx; i++) {
1571 for (j = 0; j < bnad->num_txq_per_tx; j++)
1572 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
1573 }
1574
1575 /* Handle Rx Completions */
1576 rcvd = bnad_poll_cq(bnad, ccb, budget);
1577 if (rcvd == budget)
1578 return rcvd;
1579 poll_exit:
1580 napi_complete((napi));
1581
1582 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1583
1584 bnad_enable_txrx_irqs(bnad);
1585 return rcvd;
1586 }
1587
1588 static void
1589 bnad_napi_enable(struct bnad *bnad, u32 rx_id)
1590 {
1591 int (*napi_poll) (struct napi_struct *, int);
1592 struct bnad_rx_ctrl *rx_ctrl;
1593 int i;
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&bnad->bna_lock, flags);
1597 if (bnad->cfg_flags & BNAD_CF_MSIX)
1598 napi_poll = bnad_napi_poll_rx;
1599 else
1600 napi_poll = bnad_napi_poll_txrx;
1601 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1602
1603 /* Initialize & enable NAPI */
1604 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1605 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1606 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1607 napi_poll, 64);
1608 napi_enable(&rx_ctrl->napi);
1609 }
1610 }
1611
1612 static void
1613 bnad_napi_disable(struct bnad *bnad, u32 rx_id)
1614 {
1615 int i;
1616
1617 /* First disable and then clean up */
1618 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1619 napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1620 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1621 }
1622 }
1623
1624 /* Should be held with conf_lock held */
1625 void
1626 bnad_cleanup_tx(struct bnad *bnad, uint tx_id)
1627 {
1628 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1629 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1630 unsigned long flags;
1631
1632 if (!tx_info->tx)
1633 return;
1634
1635 init_completion(&bnad->bnad_completions.tx_comp);
1636 spin_lock_irqsave(&bnad->bna_lock, flags);
1637 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1638 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1639 wait_for_completion(&bnad->bnad_completions.tx_comp);
1640
1641 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1642 bnad_tx_msix_unregister(bnad, tx_info,
1643 bnad->num_txq_per_tx);
1644
1645 spin_lock_irqsave(&bnad->bna_lock, flags);
1646 bna_tx_destroy(tx_info->tx);
1647 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1648
1649 tx_info->tx = NULL;
1650
1651 if (0 == tx_id)
1652 tasklet_kill(&bnad->tx_free_tasklet);
1653
1654 bnad_tx_res_free(bnad, res_info);
1655 }
1656
1657 /* Should be held with conf_lock held */
1658 int
1659 bnad_setup_tx(struct bnad *bnad, uint tx_id)
1660 {
1661 int err;
1662 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1663 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1664 struct bna_intr_info *intr_info =
1665 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1666 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1667 struct bna_tx_event_cbfn tx_cbfn;
1668 struct bna_tx *tx;
1669 unsigned long flags;
1670
1671 /* Initialize the Tx object configuration */
1672 tx_config->num_txq = bnad->num_txq_per_tx;
1673 tx_config->txq_depth = bnad->txq_depth;
1674 tx_config->tx_type = BNA_TX_T_REGULAR;
1675
1676 /* Initialize the tx event handlers */
1677 tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
1678 tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
1679 tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
1680 tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
1681 tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
1682
1683 /* Get BNA's resource requirement for one tx object */
1684 spin_lock_irqsave(&bnad->bna_lock, flags);
1685 bna_tx_res_req(bnad->num_txq_per_tx,
1686 bnad->txq_depth, res_info);
1687 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1688
1689 /* Fill Unmap Q memory requirements */
1690 BNAD_FILL_UNMAPQ_MEM_REQ(
1691 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1692 bnad->num_txq_per_tx,
1693 BNAD_TX_UNMAPQ_DEPTH);
1694
1695 /* Allocate resources */
1696 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1697 if (err)
1698 return err;
1699
1700 /* Ask BNA to create one Tx object, supplying required resources */
1701 spin_lock_irqsave(&bnad->bna_lock, flags);
1702 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1703 tx_info);
1704 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1705 if (!tx)
1706 goto err_return;
1707 tx_info->tx = tx;
1708
1709 /* Register ISR for the Tx object */
1710 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1711 err = bnad_tx_msix_register(bnad, tx_info,
1712 tx_id, bnad->num_txq_per_tx);
1713 if (err)
1714 goto err_return;
1715 }
1716
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
1718 bna_tx_enable(tx);
1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720
1721 return 0;
1722
1723 err_return:
1724 bnad_tx_res_free(bnad, res_info);
1725 return err;
1726 }
1727
1728 /* Setup the rx config for bna_rx_create */
1729 /* bnad decides the configuration */
1730 static void
1731 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1732 {
1733 rx_config->rx_type = BNA_RX_T_REGULAR;
1734 rx_config->num_paths = bnad->num_rxp_per_rx;
1735
1736 if (bnad->num_rxp_per_rx > 1) {
1737 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1738 rx_config->rss_config.hash_type =
1739 (BFI_RSS_T_V4_TCP |
1740 BFI_RSS_T_V6_TCP |
1741 BFI_RSS_T_V4_IP |
1742 BFI_RSS_T_V6_IP);
1743 rx_config->rss_config.hash_mask =
1744 bnad->num_rxp_per_rx - 1;
1745 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1746 sizeof(rx_config->rss_config.toeplitz_hash_key));
1747 } else {
1748 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1749 memset(&rx_config->rss_config, 0,
1750 sizeof(rx_config->rss_config));
1751 }
1752 rx_config->rxp_type = BNA_RXP_SLR;
1753 rx_config->q_depth = bnad->rxq_depth;
1754
1755 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1756
1757 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1758 }
1759
1760 /* Called with mutex_lock(&bnad->conf_mutex) held */
1761 void
1762 bnad_cleanup_rx(struct bnad *bnad, uint rx_id)
1763 {
1764 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1765 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1766 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1767 unsigned long flags;
1768 int dim_timer_del = 0;
1769
1770 if (!rx_info->rx)
1771 return;
1772
1773 if (0 == rx_id) {
1774 spin_lock_irqsave(&bnad->bna_lock, flags);
1775 dim_timer_del = bnad_dim_timer_running(bnad);
1776 if (dim_timer_del)
1777 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1778 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1779 if (dim_timer_del)
1780 del_timer_sync(&bnad->dim_timer);
1781 }
1782
1783 bnad_napi_disable(bnad, rx_id);
1784
1785 init_completion(&bnad->bnad_completions.rx_comp);
1786 spin_lock_irqsave(&bnad->bna_lock, flags);
1787 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1789 wait_for_completion(&bnad->bnad_completions.rx_comp);
1790
1791 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1792 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1793
1794 spin_lock_irqsave(&bnad->bna_lock, flags);
1795 bna_rx_destroy(rx_info->rx);
1796 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1797
1798 rx_info->rx = NULL;
1799
1800 bnad_rx_res_free(bnad, res_info);
1801 }
1802
1803 /* Called with mutex_lock(&bnad->conf_mutex) held */
1804 int
1805 bnad_setup_rx(struct bnad *bnad, uint rx_id)
1806 {
1807 int err;
1808 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1809 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1810 struct bna_intr_info *intr_info =
1811 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1812 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1813 struct bna_rx_event_cbfn rx_cbfn;
1814 struct bna_rx *rx;
1815 unsigned long flags;
1816
1817 /* Initialize the Rx object configuration */
1818 bnad_init_rx_config(bnad, rx_config);
1819
1820 /* Initialize the Rx event handlers */
1821 rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
1822 rx_cbfn.rcb_destroy_cbfn = NULL;
1823 rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
1824 rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
1825 rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
1826 rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
1827
1828 /* Get BNA's resource requirement for one Rx object */
1829 spin_lock_irqsave(&bnad->bna_lock, flags);
1830 bna_rx_res_req(rx_config, res_info);
1831 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1832
1833 /* Fill Unmap Q memory requirements */
1834 BNAD_FILL_UNMAPQ_MEM_REQ(
1835 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1836 rx_config->num_paths +
1837 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1838 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1839
1840 /* Allocate resource */
1841 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1842 if (err)
1843 return err;
1844
1845 /* Ask BNA to create one Rx object, supplying required resources */
1846 spin_lock_irqsave(&bnad->bna_lock, flags);
1847 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1848 rx_info);
1849 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1850 if (!rx)
1851 goto err_return;
1852 rx_info->rx = rx;
1853
1854 /* Register ISR for the Rx object */
1855 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1856 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1857 rx_config->num_paths);
1858 if (err)
1859 goto err_return;
1860 }
1861
1862 /* Enable NAPI */
1863 bnad_napi_enable(bnad, rx_id);
1864
1865 spin_lock_irqsave(&bnad->bna_lock, flags);
1866 if (0 == rx_id) {
1867 /* Set up Dynamic Interrupt Moderation Vector */
1868 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1869 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1870
1871 /* Enable VLAN filtering only on the default Rx */
1872 bna_rx_vlanfilter_enable(rx);
1873
1874 /* Start the DIM timer */
1875 bnad_dim_timer_start(bnad);
1876 }
1877
1878 bna_rx_enable(rx);
1879 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1880
1881 return 0;
1882
1883 err_return:
1884 bnad_cleanup_rx(bnad, rx_id);
1885 return err;
1886 }
1887
1888 /* Called with conf_lock & bnad->bna_lock held */
1889 void
1890 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
1891 {
1892 struct bnad_tx_info *tx_info;
1893
1894 tx_info = &bnad->tx_info[0];
1895 if (!tx_info->tx)
1896 return;
1897
1898 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
1899 }
1900
1901 /* Called with conf_lock & bnad->bna_lock held */
1902 void
1903 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
1904 {
1905 struct bnad_rx_info *rx_info;
1906 int i;
1907
1908 for (i = 0; i < bnad->num_rx; i++) {
1909 rx_info = &bnad->rx_info[i];
1910 if (!rx_info->rx)
1911 continue;
1912 bna_rx_coalescing_timeo_set(rx_info->rx,
1913 bnad->rx_coalescing_timeo);
1914 }
1915 }
1916
1917 /*
1918 * Called with bnad->bna_lock held
1919 */
1920 static int
1921 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
1922 {
1923 int ret;
1924
1925 if (!is_valid_ether_addr(mac_addr))
1926 return -EADDRNOTAVAIL;
1927
1928 /* If datapath is down, pretend everything went through */
1929 if (!bnad->rx_info[0].rx)
1930 return 0;
1931
1932 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
1933 if (ret != BNA_CB_SUCCESS)
1934 return -EADDRNOTAVAIL;
1935
1936 return 0;
1937 }
1938
1939 /* Should be called with conf_lock held */
1940 static int
1941 bnad_enable_default_bcast(struct bnad *bnad)
1942 {
1943 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
1944 int ret;
1945 unsigned long flags;
1946
1947 init_completion(&bnad->bnad_completions.mcast_comp);
1948
1949 spin_lock_irqsave(&bnad->bna_lock, flags);
1950 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
1951 bnad_cb_rx_mcast_add);
1952 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1953
1954 if (ret == BNA_CB_SUCCESS)
1955 wait_for_completion(&bnad->bnad_completions.mcast_comp);
1956 else
1957 return -ENODEV;
1958
1959 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
1960 return -ENODEV;
1961
1962 return 0;
1963 }
1964
1965 /* Statistics utilities */
1966 void
1967 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
1968 {
1969 int i, j;
1970
1971 for (i = 0; i < bnad->num_rx; i++) {
1972 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1973 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
1974 stats->rx_packets += bnad->rx_info[i].
1975 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
1976 stats->rx_bytes += bnad->rx_info[i].
1977 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
1978 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
1979 bnad->rx_info[i].rx_ctrl[j].ccb->
1980 rcb[1]->rxq) {
1981 stats->rx_packets +=
1982 bnad->rx_info[i].rx_ctrl[j].
1983 ccb->rcb[1]->rxq->rx_packets;
1984 stats->rx_bytes +=
1985 bnad->rx_info[i].rx_ctrl[j].
1986 ccb->rcb[1]->rxq->rx_bytes;
1987 }
1988 }
1989 }
1990 }
1991 for (i = 0; i < bnad->num_tx; i++) {
1992 for (j = 0; j < bnad->num_txq_per_tx; j++) {
1993 if (bnad->tx_info[i].tcb[j]) {
1994 stats->tx_packets +=
1995 bnad->tx_info[i].tcb[j]->txq->tx_packets;
1996 stats->tx_bytes +=
1997 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
1998 }
1999 }
2000 }
2001 }
2002
2003 /*
2004 * Must be called with the bna_lock held.
2005 */
2006 void
2007 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2008 {
2009 struct bfi_ll_stats_mac *mac_stats;
2010 u64 bmap;
2011 int i;
2012
2013 mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats;
2014 stats->rx_errors =
2015 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2016 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2017 mac_stats->rx_undersize;
2018 stats->tx_errors = mac_stats->tx_fcs_error +
2019 mac_stats->tx_undersize;
2020 stats->rx_dropped = mac_stats->rx_drop;
2021 stats->tx_dropped = mac_stats->tx_drop;
2022 stats->multicast = mac_stats->rx_multicast;
2023 stats->collisions = mac_stats->tx_total_collision;
2024
2025 stats->rx_length_errors = mac_stats->rx_frame_length_error;
2026
2027 /* receive ring buffer overflow ?? */
2028
2029 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2030 stats->rx_frame_errors = mac_stats->rx_alignment_error;
2031 /* recv'r fifo overrun */
2032 bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] |
2033 ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32);
2034 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
2035 if (bmap & 1) {
2036 stats->rx_fifo_errors +=
2037 bnad->stats.bna_stats->
2038 hw_stats->rxf_stats[i].frame_drops;
2039 break;
2040 }
2041 bmap >>= 1;
2042 }
2043 }
2044
2045 static void
2046 bnad_mbox_irq_sync(struct bnad *bnad)
2047 {
2048 u32 irq;
2049 unsigned long flags;
2050
2051 spin_lock_irqsave(&bnad->bna_lock, flags);
2052 if (bnad->cfg_flags & BNAD_CF_MSIX)
2053 irq = bnad->msix_table[bnad->msix_num - 1].vector;
2054 else
2055 irq = bnad->pcidev->irq;
2056 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2057
2058 synchronize_irq(irq);
2059 }
2060
2061 /* Utility used by bnad_start_xmit, for doing TSO */
2062 static int
2063 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2064 {
2065 int err;
2066
2067 /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
2068 BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
2069 skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
2070 if (skb_header_cloned(skb)) {
2071 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2072 if (err) {
2073 BNAD_UPDATE_CTR(bnad, tso_err);
2074 return err;
2075 }
2076 }
2077
2078 /*
2079 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2080 * excluding the length field.
2081 */
2082 if (skb->protocol == htons(ETH_P_IP)) {
2083 struct iphdr *iph = ip_hdr(skb);
2084
2085 /* Do we really need these? */
2086 iph->tot_len = 0;
2087 iph->check = 0;
2088
2089 tcp_hdr(skb)->check =
2090 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2091 IPPROTO_TCP, 0);
2092 BNAD_UPDATE_CTR(bnad, tso4);
2093 } else {
2094 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2095
2096 BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
2097 ipv6h->payload_len = 0;
2098 tcp_hdr(skb)->check =
2099 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2100 IPPROTO_TCP, 0);
2101 BNAD_UPDATE_CTR(bnad, tso6);
2102 }
2103
2104 return 0;
2105 }
2106
2107 /*
2108 * Initialize Q numbers depending on Rx Paths
2109 * Called with bnad->bna_lock held, because of cfg_flags
2110 * access.
2111 */
2112 static void
2113 bnad_q_num_init(struct bnad *bnad)
2114 {
2115 int rxps;
2116
2117 rxps = min((uint)num_online_cpus(),
2118 (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX));
2119
2120 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2121 rxps = 1; /* INTx */
2122
2123 bnad->num_rx = 1;
2124 bnad->num_tx = 1;
2125 bnad->num_rxp_per_rx = rxps;
2126 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2127 }
2128
2129 /*
2130 * Adjusts the Q numbers, given a number of msix vectors
2131 * Give preference to RSS as opposed to Tx priority Queues,
2132 * in such a case, just use 1 Tx Q
2133 * Called with bnad->bna_lock held b'cos of cfg_flags access
2134 */
2135 static void
2136 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
2137 {
2138 bnad->num_txq_per_tx = 1;
2139 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2140 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2141 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2142 bnad->num_rxp_per_rx = msix_vectors -
2143 (bnad->num_tx * bnad->num_txq_per_tx) -
2144 BNAD_MAILBOX_MSIX_VECTORS;
2145 } else
2146 bnad->num_rxp_per_rx = 1;
2147 }
2148
2149 static void
2150 bnad_set_netdev_perm_addr(struct bnad *bnad)
2151 {
2152 struct net_device *netdev = bnad->netdev;
2153
2154 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
2155 if (is_zero_ether_addr(netdev->dev_addr))
2156 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
2157 }
2158
2159 /* Enable / disable device */
2160 static void
2161 bnad_device_disable(struct bnad *bnad)
2162 {
2163 unsigned long flags;
2164
2165 init_completion(&bnad->bnad_completions.ioc_comp);
2166
2167 spin_lock_irqsave(&bnad->bna_lock, flags);
2168 bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP);
2169 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2170
2171 wait_for_completion(&bnad->bnad_completions.ioc_comp);
2172
2173 }
2174
2175 static int
2176 bnad_device_enable(struct bnad *bnad)
2177 {
2178 int err = 0;
2179 unsigned long flags;
2180
2181 init_completion(&bnad->bnad_completions.ioc_comp);
2182
2183 spin_lock_irqsave(&bnad->bna_lock, flags);
2184 bna_device_enable(&bnad->bna.device);
2185 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2186
2187 wait_for_completion(&bnad->bnad_completions.ioc_comp);
2188
2189 if (bnad->bnad_completions.ioc_comp_status)
2190 err = bnad->bnad_completions.ioc_comp_status;
2191
2192 return err;
2193 }
2194
2195 /* Free BNA resources */
2196 static void
2197 bnad_res_free(struct bnad *bnad)
2198 {
2199 int i;
2200 struct bna_res_info *res_info = &bnad->res_info[0];
2201
2202 for (i = 0; i < BNA_RES_T_MAX; i++) {
2203 if (res_info[i].res_type == BNA_RES_T_MEM)
2204 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2205 else
2206 bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info);
2207 }
2208 }
2209
2210 /* Allocates memory and interrupt resources for BNA */
2211 static int
2212 bnad_res_alloc(struct bnad *bnad)
2213 {
2214 int i, err;
2215 struct bna_res_info *res_info = &bnad->res_info[0];
2216
2217 for (i = 0; i < BNA_RES_T_MAX; i++) {
2218 if (res_info[i].res_type == BNA_RES_T_MEM)
2219 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2220 else
2221 err = bnad_mbox_irq_alloc(bnad,
2222 &res_info[i].res_u.intr_info);
2223 if (err)
2224 goto err_return;
2225 }
2226 return 0;
2227
2228 err_return:
2229 bnad_res_free(bnad);
2230 return err;
2231 }
2232
2233 /* Interrupt enable / disable */
2234 static void
2235 bnad_enable_msix(struct bnad *bnad)
2236 {
2237 int i, ret;
2238 u32 tot_msix_num;
2239 unsigned long flags;
2240
2241 spin_lock_irqsave(&bnad->bna_lock, flags);
2242 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2243 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2244 return;
2245 }
2246 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2247
2248 if (bnad->msix_table)
2249 return;
2250
2251 tot_msix_num = bnad->msix_num + bnad->msix_diag_num;
2252
2253 bnad->msix_table =
2254 kcalloc(tot_msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2255
2256 if (!bnad->msix_table)
2257 goto intx_mode;
2258
2259 for (i = 0; i < tot_msix_num; i++)
2260 bnad->msix_table[i].entry = i;
2261
2262 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, tot_msix_num);
2263 if (ret > 0) {
2264 /* Not enough MSI-X vectors. */
2265
2266 spin_lock_irqsave(&bnad->bna_lock, flags);
2267 /* ret = #of vectors that we got */
2268 bnad_q_num_adjust(bnad, ret);
2269 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2270
2271 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
2272 + (bnad->num_rx
2273 * bnad->num_rxp_per_rx) +
2274 BNAD_MAILBOX_MSIX_VECTORS;
2275 tot_msix_num = bnad->msix_num + bnad->msix_diag_num;
2276
2277 /* Try once more with adjusted numbers */
2278 /* If this fails, fall back to INTx */
2279 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
2280 tot_msix_num);
2281 if (ret)
2282 goto intx_mode;
2283
2284 } else if (ret < 0)
2285 goto intx_mode;
2286 return;
2287
2288 intx_mode:
2289
2290 kfree(bnad->msix_table);
2291 bnad->msix_table = NULL;
2292 bnad->msix_num = 0;
2293 bnad->msix_diag_num = 0;
2294 spin_lock_irqsave(&bnad->bna_lock, flags);
2295 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2296 bnad_q_num_init(bnad);
2297 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2298 }
2299
2300 static void
2301 bnad_disable_msix(struct bnad *bnad)
2302 {
2303 u32 cfg_flags;
2304 unsigned long flags;
2305
2306 spin_lock_irqsave(&bnad->bna_lock, flags);
2307 cfg_flags = bnad->cfg_flags;
2308 if (bnad->cfg_flags & BNAD_CF_MSIX)
2309 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2310 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2311
2312 if (cfg_flags & BNAD_CF_MSIX) {
2313 pci_disable_msix(bnad->pcidev);
2314 kfree(bnad->msix_table);
2315 bnad->msix_table = NULL;
2316 }
2317 }
2318
2319 /* Netdev entry points */
2320 static int
2321 bnad_open(struct net_device *netdev)
2322 {
2323 int err;
2324 struct bnad *bnad = netdev_priv(netdev);
2325 struct bna_pause_config pause_config;
2326 int mtu;
2327 unsigned long flags;
2328
2329 mutex_lock(&bnad->conf_mutex);
2330
2331 /* Tx */
2332 err = bnad_setup_tx(bnad, 0);
2333 if (err)
2334 goto err_return;
2335
2336 /* Rx */
2337 err = bnad_setup_rx(bnad, 0);
2338 if (err)
2339 goto cleanup_tx;
2340
2341 /* Port */
2342 pause_config.tx_pause = 0;
2343 pause_config.rx_pause = 0;
2344
2345 mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
2346
2347 spin_lock_irqsave(&bnad->bna_lock, flags);
2348 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2349 bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
2350 bna_port_enable(&bnad->bna.port);
2351 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2352
2353 /* Enable broadcast */
2354 bnad_enable_default_bcast(bnad);
2355
2356 /* Set the UCAST address */
2357 spin_lock_irqsave(&bnad->bna_lock, flags);
2358 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2359 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2360
2361 /* Start the stats timer */
2362 bnad_stats_timer_start(bnad);
2363
2364 mutex_unlock(&bnad->conf_mutex);
2365
2366 return 0;
2367
2368 cleanup_tx:
2369 bnad_cleanup_tx(bnad, 0);
2370
2371 err_return:
2372 mutex_unlock(&bnad->conf_mutex);
2373 return err;
2374 }
2375
2376 static int
2377 bnad_stop(struct net_device *netdev)
2378 {
2379 struct bnad *bnad = netdev_priv(netdev);
2380 unsigned long flags;
2381
2382 mutex_lock(&bnad->conf_mutex);
2383
2384 /* Stop the stats timer */
2385 bnad_stats_timer_stop(bnad);
2386
2387 init_completion(&bnad->bnad_completions.port_comp);
2388
2389 spin_lock_irqsave(&bnad->bna_lock, flags);
2390 bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP,
2391 bnad_cb_port_disabled);
2392 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2393
2394 wait_for_completion(&bnad->bnad_completions.port_comp);
2395
2396 bnad_cleanup_tx(bnad, 0);
2397 bnad_cleanup_rx(bnad, 0);
2398
2399 /* Synchronize mailbox IRQ */
2400 bnad_mbox_irq_sync(bnad);
2401
2402 mutex_unlock(&bnad->conf_mutex);
2403
2404 return 0;
2405 }
2406
2407 /* TX */
2408 /*
2409 * bnad_start_xmit : Netdev entry point for Transmit
2410 * Called under lock held by net_device
2411 */
2412 static netdev_tx_t
2413 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2414 {
2415 struct bnad *bnad = netdev_priv(netdev);
2416
2417 u16 txq_prod, vlan_tag = 0;
2418 u32 unmap_prod, wis, wis_used, wi_range;
2419 u32 vectors, vect_id, i, acked;
2420 u32 tx_id;
2421 int err;
2422
2423 struct bnad_tx_info *tx_info;
2424 struct bna_tcb *tcb;
2425 struct bnad_unmap_q *unmap_q;
2426 dma_addr_t dma_addr;
2427 struct bna_txq_entry *txqent;
2428 bna_txq_wi_ctrl_flag_t flags;
2429
2430 if (unlikely
2431 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
2432 dev_kfree_skb(skb);
2433 return NETDEV_TX_OK;
2434 }
2435
2436 /*
2437 * Takes care of the Tx that is scheduled between clearing the flag
2438 * and the netif_stop_queue() call.
2439 */
2440 if (unlikely(!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))) {
2441 dev_kfree_skb(skb);
2442 return NETDEV_TX_OK;
2443 }
2444
2445 tx_id = 0;
2446
2447 tx_info = &bnad->tx_info[tx_id];
2448 tcb = tx_info->tcb[tx_id];
2449 unmap_q = tcb->unmap_q;
2450
2451 vectors = 1 + skb_shinfo(skb)->nr_frags;
2452 if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
2453 dev_kfree_skb(skb);
2454 return NETDEV_TX_OK;
2455 }
2456 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2457 acked = 0;
2458 if (unlikely
2459 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2460 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2461 if ((u16) (*tcb->hw_consumer_index) !=
2462 tcb->consumer_index &&
2463 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2464 acked = bnad_free_txbufs(bnad, tcb);
2465 bna_ib_ack(tcb->i_dbell, acked);
2466 smp_mb__before_clear_bit();
2467 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2468 } else {
2469 netif_stop_queue(netdev);
2470 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2471 }
2472
2473 smp_mb();
2474 /*
2475 * Check again to deal with race condition between
2476 * netif_stop_queue here, and netif_wake_queue in
2477 * interrupt handler which is not inside netif tx lock.
2478 */
2479 if (likely
2480 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2481 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2482 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2483 return NETDEV_TX_BUSY;
2484 } else {
2485 netif_wake_queue(netdev);
2486 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2487 }
2488 }
2489
2490 unmap_prod = unmap_q->producer_index;
2491 wis_used = 1;
2492 vect_id = 0;
2493 flags = 0;
2494
2495 txq_prod = tcb->producer_index;
2496 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2497 BUG_ON(!(wi_range <= tcb->q_depth));
2498 txqent->hdr.wi.reserved = 0;
2499 txqent->hdr.wi.num_vectors = vectors;
2500 txqent->hdr.wi.opcode =
2501 htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
2502 BNA_TXQ_WI_SEND));
2503
2504 if (bnad->vlan_grp && vlan_tx_tag_present(skb)) {
2505 vlan_tag = (u16) vlan_tx_tag_get(skb);
2506 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2507 }
2508 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2509 vlan_tag =
2510 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2511 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2512 }
2513
2514 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2515
2516 if (skb_is_gso(skb)) {
2517 err = bnad_tso_prepare(bnad, skb);
2518 if (err) {
2519 dev_kfree_skb(skb);
2520 return NETDEV_TX_OK;
2521 }
2522 txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
2523 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2524 txqent->hdr.wi.l4_hdr_size_n_offset =
2525 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2526 (tcp_hdrlen(skb) >> 2,
2527 skb_transport_offset(skb)));
2528 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2529 u8 proto = 0;
2530
2531 txqent->hdr.wi.lso_mss = 0;
2532
2533 if (skb->protocol == htons(ETH_P_IP))
2534 proto = ip_hdr(skb)->protocol;
2535 else if (skb->protocol == htons(ETH_P_IPV6)) {
2536 /* nexthdr may not be TCP immediately. */
2537 proto = ipv6_hdr(skb)->nexthdr;
2538 }
2539 if (proto == IPPROTO_TCP) {
2540 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2541 txqent->hdr.wi.l4_hdr_size_n_offset =
2542 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2543 (0, skb_transport_offset(skb)));
2544
2545 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2546
2547 BUG_ON(!(skb_headlen(skb) >=
2548 skb_transport_offset(skb) + tcp_hdrlen(skb)));
2549
2550 } else if (proto == IPPROTO_UDP) {
2551 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2552 txqent->hdr.wi.l4_hdr_size_n_offset =
2553 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2554 (0, skb_transport_offset(skb)));
2555
2556 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2557
2558 BUG_ON(!(skb_headlen(skb) >=
2559 skb_transport_offset(skb) +
2560 sizeof(struct udphdr)));
2561 } else {
2562 err = skb_checksum_help(skb);
2563 BNAD_UPDATE_CTR(bnad, csum_help);
2564 if (err) {
2565 dev_kfree_skb(skb);
2566 BNAD_UPDATE_CTR(bnad, csum_help_err);
2567 return NETDEV_TX_OK;
2568 }
2569 }
2570 } else {
2571 txqent->hdr.wi.lso_mss = 0;
2572 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2573 }
2574
2575 txqent->hdr.wi.flags = htons(flags);
2576
2577 txqent->hdr.wi.frame_length = htonl(skb->len);
2578
2579 unmap_q->unmap_array[unmap_prod].skb = skb;
2580 BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
2581 txqent->vector[vect_id].length = htons(skb_headlen(skb));
2582 dma_addr = pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb),
2583 PCI_DMA_TODEVICE);
2584 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2585 dma_addr);
2586
2587 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2588 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2589
2590 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2591 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
2592 u32 size = frag->size;
2593
2594 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2595 vect_id = 0;
2596 if (--wi_range)
2597 txqent++;
2598 else {
2599 BNA_QE_INDX_ADD(txq_prod, wis_used,
2600 tcb->q_depth);
2601 wis_used = 0;
2602 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2603 txqent, wi_range);
2604 BUG_ON(!(wi_range <= tcb->q_depth));
2605 }
2606 wis_used++;
2607 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
2608 }
2609
2610 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2611 txqent->vector[vect_id].length = htons(size);
2612 dma_addr =
2613 pci_map_page(bnad->pcidev, frag->page,
2614 frag->page_offset, size,
2615 PCI_DMA_TODEVICE);
2616 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2617 dma_addr);
2618 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2619 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2620 }
2621
2622 unmap_q->producer_index = unmap_prod;
2623 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2624 tcb->producer_index = txq_prod;
2625
2626 smp_mb();
2627 bna_txq_prod_indx_doorbell(tcb);
2628
2629 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2630 tasklet_schedule(&bnad->tx_free_tasklet);
2631
2632 return NETDEV_TX_OK;
2633 }
2634
2635 /*
2636 * Used spin_lock to synchronize reading of stats structures, which
2637 * is written by BNA under the same lock.
2638 */
2639 static struct rtnl_link_stats64 *
2640 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
2641 {
2642 struct bnad *bnad = netdev_priv(netdev);
2643 unsigned long flags;
2644
2645 spin_lock_irqsave(&bnad->bna_lock, flags);
2646
2647 bnad_netdev_qstats_fill(bnad, stats);
2648 bnad_netdev_hwstats_fill(bnad, stats);
2649
2650 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2651
2652 return stats;
2653 }
2654
2655 static void
2656 bnad_set_rx_mode(struct net_device *netdev)
2657 {
2658 struct bnad *bnad = netdev_priv(netdev);
2659 u32 new_mask, valid_mask;
2660 unsigned long flags;
2661
2662 spin_lock_irqsave(&bnad->bna_lock, flags);
2663
2664 new_mask = valid_mask = 0;
2665
2666 if (netdev->flags & IFF_PROMISC) {
2667 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2668 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2669 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2670 bnad->cfg_flags |= BNAD_CF_PROMISC;
2671 }
2672 } else {
2673 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2674 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2675 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2676 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2677 }
2678 }
2679
2680 if (netdev->flags & IFF_ALLMULTI) {
2681 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2682 new_mask |= BNA_RXMODE_ALLMULTI;
2683 valid_mask |= BNA_RXMODE_ALLMULTI;
2684 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2685 }
2686 } else {
2687 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2688 new_mask &= ~BNA_RXMODE_ALLMULTI;
2689 valid_mask |= BNA_RXMODE_ALLMULTI;
2690 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2691 }
2692 }
2693
2694 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2695
2696 if (!netdev_mc_empty(netdev)) {
2697 u8 *mcaddr_list;
2698 int mc_count = netdev_mc_count(netdev);
2699
2700 /* Index 0 holds the broadcast address */
2701 mcaddr_list =
2702 kzalloc((mc_count + 1) * ETH_ALEN,
2703 GFP_ATOMIC);
2704 if (!mcaddr_list)
2705 goto unlock;
2706
2707 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2708
2709 /* Copy rest of the MC addresses */
2710 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2711
2712 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2713 mcaddr_list, NULL);
2714
2715 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2716 kfree(mcaddr_list);
2717 }
2718 unlock:
2719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2720 }
2721
2722 /*
2723 * bna_lock is used to sync writes to netdev->addr
2724 * conf_lock cannot be used since this call may be made
2725 * in a non-blocking context.
2726 */
2727 static int
2728 bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2729 {
2730 int err;
2731 struct bnad *bnad = netdev_priv(netdev);
2732 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2733 unsigned long flags;
2734
2735 spin_lock_irqsave(&bnad->bna_lock, flags);
2736
2737 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2738
2739 if (!err)
2740 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2741
2742 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2743
2744 return err;
2745 }
2746
2747 static int
2748 bnad_change_mtu(struct net_device *netdev, int new_mtu)
2749 {
2750 int mtu, err = 0;
2751 unsigned long flags;
2752
2753 struct bnad *bnad = netdev_priv(netdev);
2754
2755 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2756 return -EINVAL;
2757
2758 mutex_lock(&bnad->conf_mutex);
2759
2760 netdev->mtu = new_mtu;
2761
2762 mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN;
2763
2764 spin_lock_irqsave(&bnad->bna_lock, flags);
2765 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2766 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2767
2768 mutex_unlock(&bnad->conf_mutex);
2769 return err;
2770 }
2771
2772 static void
2773 bnad_vlan_rx_register(struct net_device *netdev,
2774 struct vlan_group *vlan_grp)
2775 {
2776 struct bnad *bnad = netdev_priv(netdev);
2777
2778 mutex_lock(&bnad->conf_mutex);
2779 bnad->vlan_grp = vlan_grp;
2780 mutex_unlock(&bnad->conf_mutex);
2781 }
2782
2783 static void
2784 bnad_vlan_rx_add_vid(struct net_device *netdev,
2785 unsigned short vid)
2786 {
2787 struct bnad *bnad = netdev_priv(netdev);
2788 unsigned long flags;
2789
2790 if (!bnad->rx_info[0].rx)
2791 return;
2792
2793 mutex_lock(&bnad->conf_mutex);
2794
2795 spin_lock_irqsave(&bnad->bna_lock, flags);
2796 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
2797 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2798
2799 mutex_unlock(&bnad->conf_mutex);
2800 }
2801
2802 static void
2803 bnad_vlan_rx_kill_vid(struct net_device *netdev,
2804 unsigned short vid)
2805 {
2806 struct bnad *bnad = netdev_priv(netdev);
2807 unsigned long flags;
2808
2809 if (!bnad->rx_info[0].rx)
2810 return;
2811
2812 mutex_lock(&bnad->conf_mutex);
2813
2814 spin_lock_irqsave(&bnad->bna_lock, flags);
2815 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
2816 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2817
2818 mutex_unlock(&bnad->conf_mutex);
2819 }
2820
2821 #ifdef CONFIG_NET_POLL_CONTROLLER
2822 static void
2823 bnad_netpoll(struct net_device *netdev)
2824 {
2825 struct bnad *bnad = netdev_priv(netdev);
2826 struct bnad_rx_info *rx_info;
2827 struct bnad_rx_ctrl *rx_ctrl;
2828 u32 curr_mask;
2829 int i, j;
2830
2831 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2832 bna_intx_disable(&bnad->bna, curr_mask);
2833 bnad_isr(bnad->pcidev->irq, netdev);
2834 bna_intx_enable(&bnad->bna, curr_mask);
2835 } else {
2836 for (i = 0; i < bnad->num_rx; i++) {
2837 rx_info = &bnad->rx_info[i];
2838 if (!rx_info->rx)
2839 continue;
2840 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2841 rx_ctrl = &rx_info->rx_ctrl[j];
2842 if (rx_ctrl->ccb) {
2843 bnad_disable_rx_irq(bnad,
2844 rx_ctrl->ccb);
2845 bnad_netif_rx_schedule_poll(bnad,
2846 rx_ctrl->ccb);
2847 }
2848 }
2849 }
2850 }
2851 }
2852 #endif
2853
2854 static const struct net_device_ops bnad_netdev_ops = {
2855 .ndo_open = bnad_open,
2856 .ndo_stop = bnad_stop,
2857 .ndo_start_xmit = bnad_start_xmit,
2858 .ndo_get_stats64 = bnad_get_stats64,
2859 .ndo_set_rx_mode = bnad_set_rx_mode,
2860 .ndo_set_multicast_list = bnad_set_rx_mode,
2861 .ndo_validate_addr = eth_validate_addr,
2862 .ndo_set_mac_address = bnad_set_mac_address,
2863 .ndo_change_mtu = bnad_change_mtu,
2864 .ndo_vlan_rx_register = bnad_vlan_rx_register,
2865 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
2866 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
2867 #ifdef CONFIG_NET_POLL_CONTROLLER
2868 .ndo_poll_controller = bnad_netpoll
2869 #endif
2870 };
2871
2872 static void
2873 bnad_netdev_init(struct bnad *bnad, bool using_dac)
2874 {
2875 struct net_device *netdev = bnad->netdev;
2876
2877 netdev->features |= NETIF_F_IPV6_CSUM;
2878 netdev->features |= NETIF_F_TSO;
2879 netdev->features |= NETIF_F_TSO6;
2880
2881 netdev->features |= NETIF_F_GRO;
2882 pr_warn("bna: GRO enabled, using kernel stack GRO\n");
2883
2884 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2885
2886 if (using_dac)
2887 netdev->features |= NETIF_F_HIGHDMA;
2888
2889 netdev->features |=
2890 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2891 NETIF_F_HW_VLAN_FILTER;
2892
2893 netdev->vlan_features = netdev->features;
2894 netdev->mem_start = bnad->mmio_start;
2895 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
2896
2897 netdev->netdev_ops = &bnad_netdev_ops;
2898 bnad_set_ethtool_ops(netdev);
2899 }
2900
2901 /*
2902 * 1. Initialize the bnad structure
2903 * 2. Setup netdev pointer in pci_dev
2904 * 3. Initialze Tx free tasklet
2905 * 4. Initialize no. of TxQ & CQs & MSIX vectors
2906 */
2907 static int
2908 bnad_init(struct bnad *bnad,
2909 struct pci_dev *pdev, struct net_device *netdev)
2910 {
2911 unsigned long flags;
2912
2913 SET_NETDEV_DEV(netdev, &pdev->dev);
2914 pci_set_drvdata(pdev, netdev);
2915
2916 bnad->netdev = netdev;
2917 bnad->pcidev = pdev;
2918 bnad->mmio_start = pci_resource_start(pdev, 0);
2919 bnad->mmio_len = pci_resource_len(pdev, 0);
2920 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
2921 if (!bnad->bar0) {
2922 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
2923 pci_set_drvdata(pdev, NULL);
2924 return -ENOMEM;
2925 }
2926 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
2927 (unsigned long long) bnad->mmio_len);
2928
2929 spin_lock_irqsave(&bnad->bna_lock, flags);
2930 if (!bnad_msix_disable)
2931 bnad->cfg_flags = BNAD_CF_MSIX;
2932
2933 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
2934
2935 bnad_q_num_init(bnad);
2936 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2937
2938 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
2939 (bnad->num_rx * bnad->num_rxp_per_rx) +
2940 BNAD_MAILBOX_MSIX_VECTORS;
2941 bnad->msix_diag_num = 2; /* 1 for Tx, 1 for Rx */
2942
2943 bnad->txq_depth = BNAD_TXQ_DEPTH;
2944 bnad->rxq_depth = BNAD_RXQ_DEPTH;
2945 bnad->rx_csum = true;
2946
2947 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
2948 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2949
2950 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
2951 (unsigned long)bnad);
2952
2953 return 0;
2954 }
2955
2956 /*
2957 * Must be called after bnad_pci_uninit()
2958 * so that iounmap() and pci_set_drvdata(NULL)
2959 * happens only after PCI uninitialization.
2960 */
2961 static void
2962 bnad_uninit(struct bnad *bnad)
2963 {
2964 if (bnad->bar0)
2965 iounmap(bnad->bar0);
2966 pci_set_drvdata(bnad->pcidev, NULL);
2967 }
2968
2969 /*
2970 * Initialize locks
2971 a) Per device mutes used for serializing configuration
2972 changes from OS interface
2973 b) spin lock used to protect bna state machine
2974 */
2975 static void
2976 bnad_lock_init(struct bnad *bnad)
2977 {
2978 spin_lock_init(&bnad->bna_lock);
2979 mutex_init(&bnad->conf_mutex);
2980 }
2981
2982 static void
2983 bnad_lock_uninit(struct bnad *bnad)
2984 {
2985 mutex_destroy(&bnad->conf_mutex);
2986 }
2987
2988 /* PCI Initialization */
2989 static int
2990 bnad_pci_init(struct bnad *bnad,
2991 struct pci_dev *pdev, bool *using_dac)
2992 {
2993 int err;
2994
2995 err = pci_enable_device(pdev);
2996 if (err)
2997 return err;
2998 err = pci_request_regions(pdev, BNAD_NAME);
2999 if (err)
3000 goto disable_device;
3001 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
3002 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3003 *using_dac = 1;
3004 } else {
3005 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3006 if (err) {
3007 err = pci_set_consistent_dma_mask(pdev,
3008 DMA_BIT_MASK(32));
3009 if (err)
3010 goto release_regions;
3011 }
3012 *using_dac = 0;
3013 }
3014 pci_set_master(pdev);
3015 return 0;
3016
3017 release_regions:
3018 pci_release_regions(pdev);
3019 disable_device:
3020 pci_disable_device(pdev);
3021
3022 return err;
3023 }
3024
3025 static void
3026 bnad_pci_uninit(struct pci_dev *pdev)
3027 {
3028 pci_release_regions(pdev);
3029 pci_disable_device(pdev);
3030 }
3031
3032 static int __devinit
3033 bnad_pci_probe(struct pci_dev *pdev,
3034 const struct pci_device_id *pcidev_id)
3035 {
3036 bool using_dac;
3037 int err;
3038 struct bnad *bnad;
3039 struct bna *bna;
3040 struct net_device *netdev;
3041 struct bfa_pcidev pcidev_info;
3042 unsigned long flags;
3043
3044 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3045 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3046
3047 mutex_lock(&bnad_fwimg_mutex);
3048 if (!cna_get_firmware_buf(pdev)) {
3049 mutex_unlock(&bnad_fwimg_mutex);
3050 pr_warn("Failed to load Firmware Image!\n");
3051 return -ENODEV;
3052 }
3053 mutex_unlock(&bnad_fwimg_mutex);
3054
3055 /*
3056 * Allocates sizeof(struct net_device + struct bnad)
3057 * bnad = netdev->priv
3058 */
3059 netdev = alloc_etherdev(sizeof(struct bnad));
3060 if (!netdev) {
3061 dev_err(&pdev->dev, "alloc_etherdev failed\n");
3062 err = -ENOMEM;
3063 return err;
3064 }
3065 bnad = netdev_priv(netdev);
3066
3067 /*
3068 * PCI initialization
3069 * Output : using_dac = 1 for 64 bit DMA
3070 * = 0 for 32 bit DMA
3071 */
3072 err = bnad_pci_init(bnad, pdev, &using_dac);
3073 if (err)
3074 goto free_netdev;
3075
3076 bnad_lock_init(bnad);
3077 /*
3078 * Initialize bnad structure
3079 * Setup relation between pci_dev & netdev
3080 * Init Tx free tasklet
3081 */
3082 err = bnad_init(bnad, pdev, netdev);
3083 if (err)
3084 goto pci_uninit;
3085 /* Initialize netdev structure, set up ethtool ops */
3086 bnad_netdev_init(bnad, using_dac);
3087
3088 bnad_enable_msix(bnad);
3089
3090 /* Get resource requirement form bna */
3091 bna_res_req(&bnad->res_info[0]);
3092
3093 /* Allocate resources from bna */
3094 err = bnad_res_alloc(bnad);
3095 if (err)
3096 goto free_netdev;
3097
3098 bna = &bnad->bna;
3099
3100 /* Setup pcidev_info for bna_init() */
3101 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3102 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3103 pcidev_info.device_id = bnad->pcidev->device;
3104 pcidev_info.pci_bar_kva = bnad->bar0;
3105
3106 mutex_lock(&bnad->conf_mutex);
3107
3108 spin_lock_irqsave(&bnad->bna_lock, flags);
3109 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3110
3111 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3112
3113 bnad->stats.bna_stats = &bna->stats;
3114
3115 /* Set up timers */
3116 setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout,
3117 ((unsigned long)bnad));
3118 setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
3119 ((unsigned long)bnad));
3120 setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
3121 ((unsigned long)bnad));
3122
3123 /* Now start the timer before calling IOC */
3124 mod_timer(&bnad->bna.device.ioc.ioc_timer,
3125 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3126
3127 /*
3128 * Start the chip
3129 * Don't care even if err != 0, bna state machine will
3130 * deal with it
3131 */
3132 err = bnad_device_enable(bnad);
3133
3134 /* Get the burnt-in mac */
3135 spin_lock_irqsave(&bnad->bna_lock, flags);
3136 bna_port_mac_get(&bna->port, &bnad->perm_addr);
3137 bnad_set_netdev_perm_addr(bnad);
3138 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3139
3140 mutex_unlock(&bnad->conf_mutex);
3141
3142 /*
3143 * Make sure the link appears down to the stack
3144 */
3145 netif_carrier_off(netdev);
3146
3147 /* Finally, reguister with net_device layer */
3148 err = register_netdev(netdev);
3149 if (err) {
3150 pr_err("BNA : Registering with netdev failed\n");
3151 goto disable_device;
3152 }
3153
3154 return 0;
3155
3156 disable_device:
3157 mutex_lock(&bnad->conf_mutex);
3158 bnad_device_disable(bnad);
3159 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3160 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3161 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3162 spin_lock_irqsave(&bnad->bna_lock, flags);
3163 bna_uninit(bna);
3164 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3165 mutex_unlock(&bnad->conf_mutex);
3166
3167 bnad_res_free(bnad);
3168 bnad_disable_msix(bnad);
3169 pci_uninit:
3170 bnad_pci_uninit(pdev);
3171 bnad_lock_uninit(bnad);
3172 bnad_uninit(bnad);
3173 free_netdev:
3174 free_netdev(netdev);
3175 return err;
3176 }
3177
3178 static void __devexit
3179 bnad_pci_remove(struct pci_dev *pdev)
3180 {
3181 struct net_device *netdev = pci_get_drvdata(pdev);
3182 struct bnad *bnad;
3183 struct bna *bna;
3184 unsigned long flags;
3185
3186 if (!netdev)
3187 return;
3188
3189 pr_info("%s bnad_pci_remove\n", netdev->name);
3190 bnad = netdev_priv(netdev);
3191 bna = &bnad->bna;
3192
3193 unregister_netdev(netdev);
3194
3195 mutex_lock(&bnad->conf_mutex);
3196 bnad_device_disable(bnad);
3197 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3198 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3199 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3200 spin_lock_irqsave(&bnad->bna_lock, flags);
3201 bna_uninit(bna);
3202 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3203 mutex_unlock(&bnad->conf_mutex);
3204
3205 bnad_res_free(bnad);
3206 bnad_disable_msix(bnad);
3207 bnad_pci_uninit(pdev);
3208 bnad_lock_uninit(bnad);
3209 bnad_uninit(bnad);
3210 free_netdev(netdev);
3211 }
3212
3213 const struct pci_device_id bnad_pci_id_table[] = {
3214 {
3215 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3216 PCI_DEVICE_ID_BROCADE_CT),
3217 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3218 .class_mask = 0xffff00
3219 }, {0, }
3220 };
3221
3222 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3223
3224 static struct pci_driver bnad_pci_driver = {
3225 .name = BNAD_NAME,
3226 .id_table = bnad_pci_id_table,
3227 .probe = bnad_pci_probe,
3228 .remove = __devexit_p(bnad_pci_remove),
3229 };
3230
3231 static int __init
3232 bnad_module_init(void)
3233 {
3234 int err;
3235
3236 pr_info("Brocade 10G Ethernet driver\n");
3237
3238 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3239
3240 err = pci_register_driver(&bnad_pci_driver);
3241 if (err < 0) {
3242 pr_err("bna : PCI registration failed in module init "
3243 "(%d)\n", err);
3244 return err;
3245 }
3246
3247 return 0;
3248 }
3249
3250 static void __exit
3251 bnad_module_exit(void)
3252 {
3253 pci_unregister_driver(&bnad_pci_driver);
3254
3255 if (bfi_fw)
3256 release_firmware(bfi_fw);
3257 }
3258
3259 module_init(bnad_module_init);
3260 module_exit(bnad_module_exit);
3261
3262 MODULE_AUTHOR("Brocade");
3263 MODULE_LICENSE("GPL");
3264 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3265 MODULE_VERSION(BNAD_VERSION);
3266 MODULE_FIRMWARE(CNA_FW_FILE_CT);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree