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drm/i915: make sure eDP panel is turned on
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
blobe9bf5a8837f233cb862981db32d384011e17f00e
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
46
47 struct intel_dp_priv {
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 uint32_t save_DP;
52 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
53 bool has_audio;
54 int dpms_mode;
55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
58 struct intel_encoder *intel_encoder;
59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo;
61 };
62
63 static void
64 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
66
67 static void
68 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
69
70 void
71 intel_edp_link_config (struct intel_encoder *intel_encoder,
72 int *lane_num, int *link_bw)
73 {
74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
75
76 *lane_num = dp_priv->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62)
78 *link_bw = 162000;
79 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
80 *link_bw = 270000;
81 }
82
83 static int
84 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
85 {
86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
87 int max_lane_count = 4;
88
89 if (dp_priv->dpcd[0] >= 0x11) {
90 max_lane_count = dp_priv->dpcd[2] & 0x1f;
91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99 }
100
101 static int
102 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
103 {
104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
105 int max_link_bw = dp_priv->dpcd[1];
106
107 switch (max_link_bw) {
108 case DP_LINK_BW_1_62:
109 case DP_LINK_BW_2_7:
110 break;
111 default:
112 max_link_bw = DP_LINK_BW_1_62;
113 break;
114 }
115 return max_link_bw;
116 }
117
118 static int
119 intel_dp_link_clock(uint8_t link_bw)
120 {
121 if (link_bw == DP_LINK_BW_2_7)
122 return 270000;
123 else
124 return 162000;
125 }
126
127 /* I think this is a fiction */
128 static int
129 intel_dp_link_required(struct drm_device *dev,
130 struct intel_encoder *intel_encoder, int pixel_clock)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 if (IS_eDP(intel_encoder))
135 return (pixel_clock * dev_priv->edp_bpp) / 8;
136 else
137 return pixel_clock * 3;
138 }
139
140 static int
141 intel_dp_mode_valid(struct drm_connector *connector,
142 struct drm_display_mode *mode)
143 {
144 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
145 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
146 int max_lanes = intel_dp_max_lane_count(intel_encoder);
147
148 if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
149 > max_link_clock * max_lanes)
150 return MODE_CLOCK_HIGH;
151
152 if (mode->clock < 10000)
153 return MODE_CLOCK_LOW;
154
155 return MODE_OK;
156 }
157
158 static uint32_t
159 pack_aux(uint8_t *src, int src_bytes)
160 {
161 int i;
162 uint32_t v = 0;
163
164 if (src_bytes > 4)
165 src_bytes = 4;
166 for (i = 0; i < src_bytes; i++)
167 v |= ((uint32_t) src[i]) << ((3-i) * 8);
168 return v;
169 }
170
171 static void
172 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
173 {
174 int i;
175 if (dst_bytes > 4)
176 dst_bytes = 4;
177 for (i = 0; i < dst_bytes; i++)
178 dst[i] = src >> ((3-i) * 8);
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 static int
183 intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 clkcfg = I915_READ(CLKCFG);
189 switch (clkcfg & CLKCFG_FSB_MASK) {
190 case CLKCFG_FSB_400:
191 return 100;
192 case CLKCFG_FSB_533:
193 return 133;
194 case CLKCFG_FSB_667:
195 return 166;
196 case CLKCFG_FSB_800:
197 return 200;
198 case CLKCFG_FSB_1067:
199 return 266;
200 case CLKCFG_FSB_1333:
201 return 333;
202 /* these two are just a guess; one of them might be right */
203 case CLKCFG_FSB_1600:
204 case CLKCFG_FSB_1600_ALT:
205 return 400;
206 default:
207 return 133;
208 }
209 }
210
211 static int
212 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
213 uint8_t *send, int send_bytes,
214 uint8_t *recv, int recv_size)
215 {
216 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
217 uint32_t output_reg = dp_priv->output_reg;
218 struct drm_device *dev = intel_encoder->base.dev;
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 uint32_t ch_ctl = output_reg + 0x10;
221 uint32_t ch_data = ch_ctl + 4;
222 int i;
223 int recv_bytes;
224 uint32_t ctl;
225 uint32_t status;
226 uint32_t aux_clock_divider;
227 int try;
228
229 /* The clock divider is based off the hrawclk,
230 * and would like to run at 2MHz. So, take the
231 * hrawclk value and divide by 2 and use that
232 */
233 if (IS_eDP(intel_encoder))
234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
235 else if (HAS_PCH_SPLIT(dev))
236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
237 else
238 aux_clock_divider = intel_hrawclk(dev) / 2;
239
240 /* Must try at least 3 times according to DP spec */
241 for (try = 0; try < 5; try++) {
242 /* Load the send data into the aux channel data registers */
243 for (i = 0; i < send_bytes; i += 4) {
244 uint32_t d = pack_aux(send + i, send_bytes - i);
245
246 I915_WRITE(ch_data + i, d);
247 }
248
249 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
250 DP_AUX_CH_CTL_TIME_OUT_400us |
251 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
252 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
253 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
254 DP_AUX_CH_CTL_DONE |
255 DP_AUX_CH_CTL_TIME_OUT_ERROR |
256 DP_AUX_CH_CTL_RECEIVE_ERROR);
257
258 /* Send the command and wait for it to complete */
259 I915_WRITE(ch_ctl, ctl);
260 (void) I915_READ(ch_ctl);
261 for (;;) {
262 udelay(100);
263 status = I915_READ(ch_ctl);
264 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
265 break;
266 }
267
268 /* Clear done status and any errors */
269 I915_WRITE(ch_ctl, (status |
270 DP_AUX_CH_CTL_DONE |
271 DP_AUX_CH_CTL_TIME_OUT_ERROR |
272 DP_AUX_CH_CTL_RECEIVE_ERROR));
273 (void) I915_READ(ch_ctl);
274 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
275 break;
276 }
277
278 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
279 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
280 return -EBUSY;
281 }
282
283 /* Check for timeout or receive error.
284 * Timeouts occur when the sink is not connected
285 */
286 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
287 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
288 return -EIO;
289 }
290
291 /* Timeouts occur when the device isn't connected, so they're
292 * "normal" -- don't fill the kernel log with these */
293 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
294 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
295 return -ETIMEDOUT;
296 }
297
298 /* Unload any bytes sent back from the other side */
299 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
300 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
301
302 if (recv_bytes > recv_size)
303 recv_bytes = recv_size;
304
305 for (i = 0; i < recv_bytes; i += 4) {
306 uint32_t d = I915_READ(ch_data + i);
307
308 unpack_aux(d, recv + i, recv_bytes - i);
309 }
310
311 return recv_bytes;
312 }
313
314 /* Write data to the aux channel in native mode */
315 static int
316 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
317 uint16_t address, uint8_t *send, int send_bytes)
318 {
319 int ret;
320 uint8_t msg[20];
321 int msg_bytes;
322 uint8_t ack;
323
324 if (send_bytes > 16)
325 return -1;
326 msg[0] = AUX_NATIVE_WRITE << 4;
327 msg[1] = address >> 8;
328 msg[2] = address & 0xff;
329 msg[3] = send_bytes - 1;
330 memcpy(&msg[4], send, send_bytes);
331 msg_bytes = send_bytes + 4;
332 for (;;) {
333 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
334 if (ret < 0)
335 return ret;
336 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
337 break;
338 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
339 udelay(100);
340 else
341 return -EIO;
342 }
343 return send_bytes;
344 }
345
346 /* Write a single byte to the aux channel in native mode */
347 static int
348 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
349 uint16_t address, uint8_t byte)
350 {
351 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
352 }
353
354 /* read bytes from a native aux channel */
355 static int
356 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
357 uint16_t address, uint8_t *recv, int recv_bytes)
358 {
359 uint8_t msg[4];
360 int msg_bytes;
361 uint8_t reply[20];
362 int reply_bytes;
363 uint8_t ack;
364 int ret;
365
366 msg[0] = AUX_NATIVE_READ << 4;
367 msg[1] = address >> 8;
368 msg[2] = address & 0xff;
369 msg[3] = recv_bytes - 1;
370
371 msg_bytes = 4;
372 reply_bytes = recv_bytes + 1;
373
374 for (;;) {
375 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
376 reply, reply_bytes);
377 if (ret == 0)
378 return -EPROTO;
379 if (ret < 0)
380 return ret;
381 ack = reply[0];
382 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
383 memcpy(recv, reply + 1, ret - 1);
384 return ret - 1;
385 }
386 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
387 udelay(100);
388 else
389 return -EIO;
390 }
391 }
392
393 static int
394 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
395 uint8_t write_byte, uint8_t *read_byte)
396 {
397 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
398 struct intel_dp_priv *dp_priv = container_of(adapter,
399 struct intel_dp_priv,
400 adapter);
401 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
402 uint16_t address = algo_data->address;
403 uint8_t msg[5];
404 uint8_t reply[2];
405 int msg_bytes;
406 int reply_bytes;
407 int ret;
408
409 /* Set up the command byte */
410 if (mode & MODE_I2C_READ)
411 msg[0] = AUX_I2C_READ << 4;
412 else
413 msg[0] = AUX_I2C_WRITE << 4;
414
415 if (!(mode & MODE_I2C_STOP))
416 msg[0] |= AUX_I2C_MOT << 4;
417
418 msg[1] = address >> 8;
419 msg[2] = address;
420
421 switch (mode) {
422 case MODE_I2C_WRITE:
423 msg[3] = 0;
424 msg[4] = write_byte;
425 msg_bytes = 5;
426 reply_bytes = 1;
427 break;
428 case MODE_I2C_READ:
429 msg[3] = 0;
430 msg_bytes = 4;
431 reply_bytes = 2;
432 break;
433 default:
434 msg_bytes = 3;
435 reply_bytes = 1;
436 break;
437 }
438
439 for (;;) {
440 ret = intel_dp_aux_ch(intel_encoder,
441 msg, msg_bytes,
442 reply, reply_bytes);
443 if (ret < 0) {
444 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
445 return ret;
446 }
447 switch (reply[0] & AUX_I2C_REPLY_MASK) {
448 case AUX_I2C_REPLY_ACK:
449 if (mode == MODE_I2C_READ) {
450 *read_byte = reply[1];
451 }
452 return reply_bytes - 1;
453 case AUX_I2C_REPLY_NACK:
454 DRM_DEBUG_KMS("aux_ch nack\n");
455 return -EREMOTEIO;
456 case AUX_I2C_REPLY_DEFER:
457 DRM_DEBUG_KMS("aux_ch defer\n");
458 udelay(100);
459 break;
460 default:
461 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
462 return -EREMOTEIO;
463 }
464 }
465 }
466
467 static int
468 intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
469 {
470 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
471
472 DRM_DEBUG_KMS("i2c_init %s\n", name);
473 dp_priv->algo.running = false;
474 dp_priv->algo.address = 0;
475 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
476
477 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
478 dp_priv->adapter.owner = THIS_MODULE;
479 dp_priv->adapter.class = I2C_CLASS_DDC;
480 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
481 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
482 dp_priv->adapter.algo_data = &dp_priv->algo;
483 dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
484
485 return i2c_dp_aux_add_bus(&dp_priv->adapter);
486 }
487
488 static bool
489 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
490 struct drm_display_mode *adjusted_mode)
491 {
492 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
493 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
494 int lane_count, clock;
495 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
496 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
497 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
498
499 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
500 for (clock = 0; clock <= max_clock; clock++) {
501 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
502
503 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
504 <= link_avail) {
505 dp_priv->link_bw = bws[clock];
506 dp_priv->lane_count = lane_count;
507 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
508 DRM_DEBUG_KMS("Display port link bw %02x lane "
509 "count %d clock %d\n",
510 dp_priv->link_bw, dp_priv->lane_count,
511 adjusted_mode->clock);
512 return true;
513 }
514 }
515 }
516 return false;
517 }
518
519 struct intel_dp_m_n {
520 uint32_t tu;
521 uint32_t gmch_m;
522 uint32_t gmch_n;
523 uint32_t link_m;
524 uint32_t link_n;
525 };
526
527 static void
528 intel_reduce_ratio(uint32_t *num, uint32_t *den)
529 {
530 while (*num > 0xffffff || *den > 0xffffff) {
531 *num >>= 1;
532 *den >>= 1;
533 }
534 }
535
536 static void
537 intel_dp_compute_m_n(int bytes_per_pixel,
538 int nlanes,
539 int pixel_clock,
540 int link_clock,
541 struct intel_dp_m_n *m_n)
542 {
543 m_n->tu = 64;
544 m_n->gmch_m = pixel_clock * bytes_per_pixel;
545 m_n->gmch_n = link_clock * nlanes;
546 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
547 m_n->link_m = pixel_clock;
548 m_n->link_n = link_clock;
549 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
550 }
551
552 void
553 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
554 struct drm_display_mode *adjusted_mode)
555 {
556 struct drm_device *dev = crtc->dev;
557 struct drm_mode_config *mode_config = &dev->mode_config;
558 struct drm_connector *connector;
559 struct drm_i915_private *dev_priv = dev->dev_private;
560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
561 int lane_count = 4;
562 struct intel_dp_m_n m_n;
563
564 /*
565 * Find the lane count in the intel_encoder private
566 */
567 list_for_each_entry(connector, &mode_config->connector_list, head) {
568 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
569 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
570
571 if (!connector->encoder || connector->encoder->crtc != crtc)
572 continue;
573
574 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
575 lane_count = dp_priv->lane_count;
576 break;
577 }
578 }
579
580 /*
581 * Compute the GMCH and Link ratios. The '3' here is
582 * the number of bytes_per_pixel post-LUT, which we always
583 * set up for 8-bits of R/G/B, or 3 bytes total.
584 */
585 intel_dp_compute_m_n(3, lane_count,
586 mode->clock, adjusted_mode->clock, &m_n);
587
588 if (HAS_PCH_SPLIT(dev)) {
589 if (intel_crtc->pipe == 0) {
590 I915_WRITE(TRANSA_DATA_M1,
591 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
592 m_n.gmch_m);
593 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
594 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
595 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
596 } else {
597 I915_WRITE(TRANSB_DATA_M1,
598 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
599 m_n.gmch_m);
600 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
601 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
602 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
603 }
604 } else {
605 if (intel_crtc->pipe == 0) {
606 I915_WRITE(PIPEA_GMCH_DATA_M,
607 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
608 m_n.gmch_m);
609 I915_WRITE(PIPEA_GMCH_DATA_N,
610 m_n.gmch_n);
611 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
612 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
613 } else {
614 I915_WRITE(PIPEB_GMCH_DATA_M,
615 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
616 m_n.gmch_m);
617 I915_WRITE(PIPEB_GMCH_DATA_N,
618 m_n.gmch_n);
619 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
620 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
621 }
622 }
623 }
624
625 static void
626 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
627 struct drm_display_mode *adjusted_mode)
628 {
629 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
630 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
631 struct drm_crtc *crtc = intel_encoder->enc.crtc;
632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
633
634 dp_priv->DP = (DP_LINK_TRAIN_OFF |
635 DP_VOLTAGE_0_4 |
636 DP_PRE_EMPHASIS_0 |
637 DP_SYNC_VS_HIGH |
638 DP_SYNC_HS_HIGH);
639
640 switch (dp_priv->lane_count) {
641 case 1:
642 dp_priv->DP |= DP_PORT_WIDTH_1;
643 break;
644 case 2:
645 dp_priv->DP |= DP_PORT_WIDTH_2;
646 break;
647 case 4:
648 dp_priv->DP |= DP_PORT_WIDTH_4;
649 break;
650 }
651 if (dp_priv->has_audio)
652 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
653
654 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
655 dp_priv->link_configuration[0] = dp_priv->link_bw;
656 dp_priv->link_configuration[1] = dp_priv->lane_count;
657
658 /*
659 * Check for DPCD version > 1.1,
660 * enable enahanced frame stuff in that case
661 */
662 if (dp_priv->dpcd[0] >= 0x11) {
663 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
664 dp_priv->DP |= DP_ENHANCED_FRAMING;
665 }
666
667 if (intel_crtc->pipe == 1)
668 dp_priv->DP |= DP_PIPEB_SELECT;
669
670 if (IS_eDP(intel_encoder)) {
671 /* don't miss out required setting for eDP */
672 dp_priv->DP |= DP_PLL_ENABLE;
673 if (adjusted_mode->clock < 200000)
674 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
675 else
676 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
677 }
678 }
679
680 static void ironlake_edp_panel_on (struct drm_device *dev)
681 {
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
684 u32 pp, pp_status;
685
686 pp_status = I915_READ(PCH_PP_STATUS);
687 if (pp_status & PP_ON)
688 return;
689
690 pp = I915_READ(PCH_PP_CONTROL);
691 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
692 I915_WRITE(PCH_PP_CONTROL, pp);
693 do {
694 pp_status = I915_READ(PCH_PP_STATUS);
695 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
696
697 if (time_after(jiffies, timeout))
698 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
699
700 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
701 I915_WRITE(PCH_PP_CONTROL, pp);
702 }
703
704 static void ironlake_edp_panel_off (struct drm_device *dev)
705 {
706 struct drm_i915_private *dev_priv = dev->dev_private;
707 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
708 u32 pp, pp_status;
709
710 pp = I915_READ(PCH_PP_CONTROL);
711 pp &= ~POWER_TARGET_ON;
712 I915_WRITE(PCH_PP_CONTROL, pp);
713 do {
714 pp_status = I915_READ(PCH_PP_STATUS);
715 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
716
717 if (time_after(jiffies, timeout))
718 DRM_DEBUG_KMS("panel off wait timed out\n");
719
720 /* Make sure VDD is enabled so DP AUX will work */
721 pp |= EDP_FORCE_VDD;
722 I915_WRITE(PCH_PP_CONTROL, pp);
723 }
724
725 static void ironlake_edp_backlight_on (struct drm_device *dev)
726 {
727 struct drm_i915_private *dev_priv = dev->dev_private;
728 u32 pp;
729
730 DRM_DEBUG_KMS("\n");
731 pp = I915_READ(PCH_PP_CONTROL);
732 pp |= EDP_BLC_ENABLE;
733 I915_WRITE(PCH_PP_CONTROL, pp);
734 }
735
736 static void ironlake_edp_backlight_off (struct drm_device *dev)
737 {
738 struct drm_i915_private *dev_priv = dev->dev_private;
739 u32 pp;
740
741 DRM_DEBUG_KMS("\n");
742 pp = I915_READ(PCH_PP_CONTROL);
743 pp &= ~EDP_BLC_ENABLE;
744 I915_WRITE(PCH_PP_CONTROL, pp);
745 }
746
747 static void
748 intel_dp_dpms(struct drm_encoder *encoder, int mode)
749 {
750 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
751 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
752 struct drm_device *dev = intel_encoder->base.dev;
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
755
756 if (mode != DRM_MODE_DPMS_ON) {
757 if (dp_reg & DP_PORT_EN) {
758 intel_dp_link_down(intel_encoder, dp_priv->DP);
759 if (IS_eDP(intel_encoder)) {
760 ironlake_edp_backlight_off(dev);
761 ironlake_edp_backlight_off(dev);
762 }
763 }
764 } else {
765 if (!(dp_reg & DP_PORT_EN)) {
766 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
767 if (IS_eDP(intel_encoder)) {
768 ironlake_edp_panel_on(dev);
769 ironlake_edp_backlight_on(dev);
770 }
771 }
772 }
773 dp_priv->dpms_mode = mode;
774 }
775
776 /*
777 * Fetch AUX CH registers 0x202 - 0x207 which contain
778 * link status information
779 */
780 static bool
781 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
782 uint8_t link_status[DP_LINK_STATUS_SIZE])
783 {
784 int ret;
785
786 ret = intel_dp_aux_native_read(intel_encoder,
787 DP_LANE0_1_STATUS,
788 link_status, DP_LINK_STATUS_SIZE);
789 if (ret != DP_LINK_STATUS_SIZE)
790 return false;
791 return true;
792 }
793
794 static uint8_t
795 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
796 int r)
797 {
798 return link_status[r - DP_LANE0_1_STATUS];
799 }
800
801 static void
802 intel_dp_save(struct drm_connector *connector)
803 {
804 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
805 struct drm_device *dev = intel_encoder->base.dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
808
809 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
810 intel_dp_aux_native_read(intel_encoder, DP_LINK_BW_SET,
811 dp_priv->save_link_configuration,
812 sizeof (dp_priv->save_link_configuration));
813 }
814
815 static uint8_t
816 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
817 int lane)
818 {
819 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
820 int s = ((lane & 1) ?
821 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
822 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
823 uint8_t l = intel_dp_link_status(link_status, i);
824
825 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
826 }
827
828 static uint8_t
829 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
830 int lane)
831 {
832 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
833 int s = ((lane & 1) ?
834 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
835 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
836 uint8_t l = intel_dp_link_status(link_status, i);
837
838 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
839 }
840
841
842 #if 0
843 static char *voltage_names[] = {
844 "0.4V", "0.6V", "0.8V", "1.2V"
845 };
846 static char *pre_emph_names[] = {
847 "0dB", "3.5dB", "6dB", "9.5dB"
848 };
849 static char *link_train_names[] = {
850 "pattern 1", "pattern 2", "idle", "off"
851 };
852 #endif
853
854 /*
855 * These are source-specific values; current Intel hardware supports
856 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
857 */
858 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
859
860 static uint8_t
861 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
862 {
863 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
864 case DP_TRAIN_VOLTAGE_SWING_400:
865 return DP_TRAIN_PRE_EMPHASIS_6;
866 case DP_TRAIN_VOLTAGE_SWING_600:
867 return DP_TRAIN_PRE_EMPHASIS_6;
868 case DP_TRAIN_VOLTAGE_SWING_800:
869 return DP_TRAIN_PRE_EMPHASIS_3_5;
870 case DP_TRAIN_VOLTAGE_SWING_1200:
871 default:
872 return DP_TRAIN_PRE_EMPHASIS_0;
873 }
874 }
875
876 static void
877 intel_get_adjust_train(struct intel_encoder *intel_encoder,
878 uint8_t link_status[DP_LINK_STATUS_SIZE],
879 int lane_count,
880 uint8_t train_set[4])
881 {
882 uint8_t v = 0;
883 uint8_t p = 0;
884 int lane;
885
886 for (lane = 0; lane < lane_count; lane++) {
887 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
888 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
889
890 if (this_v > v)
891 v = this_v;
892 if (this_p > p)
893 p = this_p;
894 }
895
896 if (v >= I830_DP_VOLTAGE_MAX)
897 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
898
899 if (p >= intel_dp_pre_emphasis_max(v))
900 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
901
902 for (lane = 0; lane < 4; lane++)
903 train_set[lane] = v | p;
904 }
905
906 static uint32_t
907 intel_dp_signal_levels(uint8_t train_set, int lane_count)
908 {
909 uint32_t signal_levels = 0;
910
911 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
912 case DP_TRAIN_VOLTAGE_SWING_400:
913 default:
914 signal_levels |= DP_VOLTAGE_0_4;
915 break;
916 case DP_TRAIN_VOLTAGE_SWING_600:
917 signal_levels |= DP_VOLTAGE_0_6;
918 break;
919 case DP_TRAIN_VOLTAGE_SWING_800:
920 signal_levels |= DP_VOLTAGE_0_8;
921 break;
922 case DP_TRAIN_VOLTAGE_SWING_1200:
923 signal_levels |= DP_VOLTAGE_1_2;
924 break;
925 }
926 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
927 case DP_TRAIN_PRE_EMPHASIS_0:
928 default:
929 signal_levels |= DP_PRE_EMPHASIS_0;
930 break;
931 case DP_TRAIN_PRE_EMPHASIS_3_5:
932 signal_levels |= DP_PRE_EMPHASIS_3_5;
933 break;
934 case DP_TRAIN_PRE_EMPHASIS_6:
935 signal_levels |= DP_PRE_EMPHASIS_6;
936 break;
937 case DP_TRAIN_PRE_EMPHASIS_9_5:
938 signal_levels |= DP_PRE_EMPHASIS_9_5;
939 break;
940 }
941 return signal_levels;
942 }
943
944 static uint8_t
945 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
946 int lane)
947 {
948 int i = DP_LANE0_1_STATUS + (lane >> 1);
949 int s = (lane & 1) * 4;
950 uint8_t l = intel_dp_link_status(link_status, i);
951
952 return (l >> s) & 0xf;
953 }
954
955 /* Check for clock recovery is done on all channels */
956 static bool
957 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
958 {
959 int lane;
960 uint8_t lane_status;
961
962 for (lane = 0; lane < lane_count; lane++) {
963 lane_status = intel_get_lane_status(link_status, lane);
964 if ((lane_status & DP_LANE_CR_DONE) == 0)
965 return false;
966 }
967 return true;
968 }
969
970 /* Check to see if channel eq is done on all channels */
971 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
972 DP_LANE_CHANNEL_EQ_DONE|\
973 DP_LANE_SYMBOL_LOCKED)
974 static bool
975 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
976 {
977 uint8_t lane_align;
978 uint8_t lane_status;
979 int lane;
980
981 lane_align = intel_dp_link_status(link_status,
982 DP_LANE_ALIGN_STATUS_UPDATED);
983 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
984 return false;
985 for (lane = 0; lane < lane_count; lane++) {
986 lane_status = intel_get_lane_status(link_status, lane);
987 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
988 return false;
989 }
990 return true;
991 }
992
993 static bool
994 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
995 uint32_t dp_reg_value,
996 uint8_t dp_train_pat,
997 uint8_t train_set[4],
998 bool first)
999 {
1000 struct drm_device *dev = intel_encoder->base.dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1003 int ret;
1004
1005 I915_WRITE(dp_priv->output_reg, dp_reg_value);
1006 POSTING_READ(dp_priv->output_reg);
1007 if (first)
1008 intel_wait_for_vblank(dev);
1009
1010 intel_dp_aux_native_write_1(intel_encoder,
1011 DP_TRAINING_PATTERN_SET,
1012 dp_train_pat);
1013
1014 ret = intel_dp_aux_native_write(intel_encoder,
1015 DP_TRAINING_LANE0_SET, train_set, 4);
1016 if (ret != 4)
1017 return false;
1018
1019 return true;
1020 }
1021
1022 static void
1023 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1024 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1025 {
1026 struct drm_device *dev = intel_encoder->base.dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1029 uint8_t train_set[4];
1030 uint8_t link_status[DP_LINK_STATUS_SIZE];
1031 int i;
1032 uint8_t voltage;
1033 bool clock_recovery = false;
1034 bool channel_eq = false;
1035 bool first = true;
1036 int tries;
1037
1038 /* Write the link configuration data */
1039 intel_dp_aux_native_write(intel_encoder, 0x100,
1040 link_configuration, DP_LINK_CONFIGURATION_SIZE);
1041
1042 DP |= DP_PORT_EN;
1043 DP &= ~DP_LINK_TRAIN_MASK;
1044 memset(train_set, 0, 4);
1045 voltage = 0xff;
1046 tries = 0;
1047 clock_recovery = false;
1048 for (;;) {
1049 /* Use train_set[0] to set the voltage and pre emphasis values */
1050 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1051 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1052
1053 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1,
1054 DP_TRAINING_PATTERN_1, train_set, first))
1055 break;
1056 first = false;
1057 /* Set training pattern 1 */
1058
1059 udelay(100);
1060 if (!intel_dp_get_link_status(intel_encoder, link_status))
1061 break;
1062
1063 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1064 clock_recovery = true;
1065 break;
1066 }
1067
1068 /* Check to see if we've tried the max voltage */
1069 for (i = 0; i < dp_priv->lane_count; i++)
1070 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1071 break;
1072 if (i == dp_priv->lane_count)
1073 break;
1074
1075 /* Check to see if we've tried the same voltage 5 times */
1076 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1077 ++tries;
1078 if (tries == 5)
1079 break;
1080 } else
1081 tries = 0;
1082 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1083
1084 /* Compute new train_set as requested by target */
1085 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1086 }
1087
1088 /* channel equalization */
1089 tries = 0;
1090 channel_eq = false;
1091 for (;;) {
1092 /* Use train_set[0] to set the voltage and pre emphasis values */
1093 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1094 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1095
1096 /* channel eq pattern */
1097 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2,
1098 DP_TRAINING_PATTERN_2, train_set,
1099 false))
1100 break;
1101
1102 udelay(400);
1103 if (!intel_dp_get_link_status(intel_encoder, link_status))
1104 break;
1105
1106 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1107 channel_eq = true;
1108 break;
1109 }
1110
1111 /* Try 5 times */
1112 if (tries > 5)
1113 break;
1114
1115 /* Compute new train_set as requested by target */
1116 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1117 ++tries;
1118 }
1119
1120 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1121 POSTING_READ(dp_priv->output_reg);
1122 intel_dp_aux_native_write_1(intel_encoder,
1123 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1124 }
1125
1126 static void
1127 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1128 {
1129 struct drm_device *dev = intel_encoder->base.dev;
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1132
1133 DRM_DEBUG_KMS("\n");
1134
1135 if (IS_eDP(intel_encoder)) {
1136 DP &= ~DP_PLL_ENABLE;
1137 I915_WRITE(dp_priv->output_reg, DP);
1138 POSTING_READ(dp_priv->output_reg);
1139 udelay(100);
1140 }
1141
1142 DP &= ~DP_LINK_TRAIN_MASK;
1143 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1144 POSTING_READ(dp_priv->output_reg);
1145
1146 udelay(17000);
1147
1148 if (IS_eDP(intel_encoder))
1149 DP |= DP_LINK_TRAIN_OFF;
1150 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1151 POSTING_READ(dp_priv->output_reg);
1152 }
1153
1154 static void
1155 intel_dp_restore(struct drm_connector *connector)
1156 {
1157 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1158 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1159
1160 if (dp_priv->save_DP & DP_PORT_EN)
1161 intel_dp_link_train(intel_encoder, dp_priv->save_DP, dp_priv->save_link_configuration);
1162 else
1163 intel_dp_link_down(intel_encoder, dp_priv->save_DP);
1164 }
1165
1166 /*
1167 * According to DP spec
1168 * 5.1.2:
1169 * 1. Read DPCD
1170 * 2. Configure link according to Receiver Capabilities
1171 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1172 * 4. Check link status on receipt of hot-plug interrupt
1173 */
1174
1175 static void
1176 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1177 {
1178 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1179 uint8_t link_status[DP_LINK_STATUS_SIZE];
1180
1181 if (!intel_encoder->enc.crtc)
1182 return;
1183
1184 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1185 intel_dp_link_down(intel_encoder, dp_priv->DP);
1186 return;
1187 }
1188
1189 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1190 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1191 }
1192
1193 static enum drm_connector_status
1194 ironlake_dp_detect(struct drm_connector *connector)
1195 {
1196 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1197 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1198 enum drm_connector_status status;
1199
1200 status = connector_status_disconnected;
1201 if (intel_dp_aux_native_read(intel_encoder,
1202 0x000, dp_priv->dpcd,
1203 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1204 {
1205 if (dp_priv->dpcd[0] != 0)
1206 status = connector_status_connected;
1207 }
1208 return status;
1209 }
1210
1211 /**
1212 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1213 *
1214 * \return true if DP port is connected.
1215 * \return false if DP port is disconnected.
1216 */
1217 static enum drm_connector_status
1218 intel_dp_detect(struct drm_connector *connector)
1219 {
1220 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1221 struct drm_device *dev = intel_encoder->base.dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1224 uint32_t temp, bit;
1225 enum drm_connector_status status;
1226
1227 dp_priv->has_audio = false;
1228
1229 if (HAS_PCH_SPLIT(dev))
1230 return ironlake_dp_detect(connector);
1231
1232 switch (dp_priv->output_reg) {
1233 case DP_B:
1234 bit = DPB_HOTPLUG_INT_STATUS;
1235 break;
1236 case DP_C:
1237 bit = DPC_HOTPLUG_INT_STATUS;
1238 break;
1239 case DP_D:
1240 bit = DPD_HOTPLUG_INT_STATUS;
1241 break;
1242 default:
1243 return connector_status_unknown;
1244 }
1245
1246 temp = I915_READ(PORT_HOTPLUG_STAT);
1247
1248 if ((temp & bit) == 0)
1249 return connector_status_disconnected;
1250
1251 status = connector_status_disconnected;
1252 if (intel_dp_aux_native_read(intel_encoder,
1253 0x000, dp_priv->dpcd,
1254 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1255 {
1256 if (dp_priv->dpcd[0] != 0)
1257 status = connector_status_connected;
1258 }
1259 return status;
1260 }
1261
1262 static int intel_dp_get_modes(struct drm_connector *connector)
1263 {
1264 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1265 struct drm_device *dev = intel_encoder->base.dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 int ret;
1268
1269 /* We should parse the EDID data and find out if it has an audio sink
1270 */
1271
1272 ret = intel_ddc_get_modes(intel_encoder);
1273 if (ret)
1274 return ret;
1275
1276 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1277 if (IS_eDP(intel_encoder)) {
1278 if (dev_priv->panel_fixed_mode != NULL) {
1279 struct drm_display_mode *mode;
1280 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1281 drm_mode_probed_add(connector, mode);
1282 return 1;
1283 }
1284 }
1285 return 0;
1286 }
1287
1288 static void
1289 intel_dp_destroy (struct drm_connector *connector)
1290 {
1291 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1292
1293 if (intel_encoder->i2c_bus)
1294 intel_i2c_destroy(intel_encoder->i2c_bus);
1295 drm_sysfs_connector_remove(connector);
1296 drm_connector_cleanup(connector);
1297 kfree(intel_encoder);
1298 }
1299
1300 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1301 .dpms = intel_dp_dpms,
1302 .mode_fixup = intel_dp_mode_fixup,
1303 .prepare = intel_encoder_prepare,
1304 .mode_set = intel_dp_mode_set,
1305 .commit = intel_encoder_commit,
1306 };
1307
1308 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1309 .dpms = drm_helper_connector_dpms,
1310 .save = intel_dp_save,
1311 .restore = intel_dp_restore,
1312 .detect = intel_dp_detect,
1313 .fill_modes = drm_helper_probe_single_connector_modes,
1314 .destroy = intel_dp_destroy,
1315 };
1316
1317 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1318 .get_modes = intel_dp_get_modes,
1319 .mode_valid = intel_dp_mode_valid,
1320 .best_encoder = intel_best_encoder,
1321 };
1322
1323 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1324 {
1325 drm_encoder_cleanup(encoder);
1326 }
1327
1328 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1329 .destroy = intel_dp_enc_destroy,
1330 };
1331
1332 void
1333 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1334 {
1335 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1336
1337 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1338 intel_dp_check_link_status(intel_encoder);
1339 }
1340
1341 void
1342 intel_dp_init(struct drm_device *dev, int output_reg)
1343 {
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 struct drm_connector *connector;
1346 struct intel_encoder *intel_encoder;
1347 struct intel_dp_priv *dp_priv;
1348 const char *name = NULL;
1349
1350 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1351 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1352 if (!intel_encoder)
1353 return;
1354
1355 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1356
1357 connector = &intel_encoder->base;
1358 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1359 DRM_MODE_CONNECTOR_DisplayPort);
1360 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1361
1362 if (output_reg == DP_A)
1363 intel_encoder->type = INTEL_OUTPUT_EDP;
1364 else
1365 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1366
1367 if (output_reg == DP_B || output_reg == PCH_DP_B)
1368 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1369 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1370 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1371 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1372 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1373
1374 if (IS_eDP(intel_encoder))
1375 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1376
1377 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1378 connector->interlace_allowed = true;
1379 connector->doublescan_allowed = 0;
1380
1381 dp_priv->intel_encoder = intel_encoder;
1382 dp_priv->output_reg = output_reg;
1383 dp_priv->has_audio = false;
1384 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1385 intel_encoder->dev_priv = dp_priv;
1386
1387 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1388 DRM_MODE_ENCODER_TMDS);
1389 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1390
1391 drm_mode_connector_attach_encoder(&intel_encoder->base,
1392 &intel_encoder->enc);
1393 drm_sysfs_connector_add(connector);
1394
1395 /* Set up the DDC bus. */
1396 switch (output_reg) {
1397 case DP_A:
1398 name = "DPDDC-A";
1399 break;
1400 case DP_B:
1401 case PCH_DP_B:
1402 dev_priv->hotplug_supported_mask |=
1403 HDMIB_HOTPLUG_INT_STATUS;
1404 name = "DPDDC-B";
1405 break;
1406 case DP_C:
1407 case PCH_DP_C:
1408 dev_priv->hotplug_supported_mask |=
1409 HDMIC_HOTPLUG_INT_STATUS;
1410 name = "DPDDC-C";
1411 break;
1412 case DP_D:
1413 case PCH_DP_D:
1414 dev_priv->hotplug_supported_mask |=
1415 HDMID_HOTPLUG_INT_STATUS;
1416 name = "DPDDC-D";
1417 break;
1418 }
1419
1420 intel_dp_i2c_init(intel_encoder, name);
1421
1422 intel_encoder->ddc_bus = &dp_priv->adapter;
1423 intel_encoder->hot_plug = intel_dp_hot_plug;
1424
1425 if (output_reg == DP_A) {
1426 /* initialize panel mode from VBT if available for eDP */
1427 if (dev_priv->lfp_lvds_vbt_mode) {
1428 dev_priv->panel_fixed_mode =
1429 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1430 if (dev_priv->panel_fixed_mode) {
1431 dev_priv->panel_fixed_mode->type |=
1432 DRM_MODE_TYPE_PREFERRED;
1433 }
1434 }
1435 }
1436
1437 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1438 * 0xd. Failure to do so will result in spurious interrupts being
1439 * generated on the port when a cable is not attached.
1440 */
1441 if (IS_G4X(dev) && !IS_GM45(dev)) {
1442 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1443 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1444 }
1445 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree