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bnx2x: 57712 parity handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bnx2x / bnx2x.h
blobc108e4cf63338fa8983f7638bb541db4646cc13d
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/types.h>
18
19 /* compilation time flags */
20
21 /* define this to make the driver freeze on error to allow getting debug info
22 * (you will need to reboot afterwards) */
23 /* #define BNX2X_STOP_ON_ERROR */
24
25 #define DRV_MODULE_VERSION "1.62.12-0"
26 #define DRV_MODULE_RELDATE "2011/03/20"
27 #define BNX2X_BC_VER 0x040200
28
29 #define BNX2X_MULTI_QUEUE
30
31 #define BNX2X_NEW_NAPI
32
33 #if defined(CONFIG_DCB)
34 #define BCM_DCBNL
35 #endif
36 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
37 #define BCM_CNIC 1
38 #include "../cnic_if.h"
39 #endif
40
41 #ifdef BCM_CNIC
42 #define BNX2X_MIN_MSIX_VEC_CNT 3
43 #define BNX2X_MSIX_VEC_FP_START 2
44 #else
45 #define BNX2X_MIN_MSIX_VEC_CNT 2
46 #define BNX2X_MSIX_VEC_FP_START 1
47 #endif
48
49 #include <linux/mdio.h>
50
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_hsi.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_sp.h"
56 #include "bnx2x_dcb.h"
57 #include "bnx2x_stats.h"
58
59 /* error/debug prints */
60
61 #define DRV_MODULE_NAME "bnx2x"
62
63 /* for messages that are currently off */
64 #define BNX2X_MSG_OFF 0
65 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
67 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
68 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
70 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
71
72 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
73
74 /* regular debug print */
75 #define DP(__mask, __fmt, __args...) \
76 do { \
77 if (bp->msg_enable & (__mask)) \
78 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
79 __func__, __LINE__, \
80 bp->dev ? (bp->dev->name) : "?", \
81 ##__args); \
82 } while (0)
83
84 #define DP_CONT(__mask, __fmt, __args...) \
85 do { \
86 if (bp->msg_enable & (__mask)) \
87 pr_cont(__fmt, ##__args); \
88 } while (0)
89
90 /* errors debug print */
91 #define BNX2X_DBG_ERR(__fmt, __args...) \
92 do { \
93 if (netif_msg_probe(bp)) \
94 pr_err("[%s:%d(%s)]" __fmt, \
95 __func__, __LINE__, \
96 bp->dev ? (bp->dev->name) : "?", \
97 ##__args); \
98 } while (0)
99
100 /* for errors (never masked) */
101 #define BNX2X_ERR(__fmt, __args...) \
102 do { \
103 pr_err("[%s:%d(%s)]" __fmt, \
104 __func__, __LINE__, \
105 bp->dev ? (bp->dev->name) : "?", \
106 ##__args); \
107 } while (0)
108
109 #define BNX2X_ERROR(__fmt, __args...) do { \
110 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
111 } while (0)
112
113
114 /* before we have a dev->name use dev_info() */
115 #define BNX2X_DEV_INFO(__fmt, __args...) \
116 do { \
117 if (netif_msg_probe(bp)) \
118 dev_info(&bp->pdev->dev, __fmt, ##__args); \
119 } while (0)
120
121 #define BNX2X_MAC_FMT "%pM"
122 #define BNX2X_MAC_PRN_LIST(mac) (mac)
123
124
125 #ifdef BNX2X_STOP_ON_ERROR
126 #define bnx2x_panic() do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_int_disable(bp); \
130 bnx2x_panic_dump(bp); \
131 } while (0)
132 #else
133 #define bnx2x_panic() do { \
134 bp->panic = 1; \
135 BNX2X_ERR("driver assert\n"); \
136 bnx2x_panic_dump(bp); \
137 } while (0)
138 #endif
139
140 #define bnx2x_mc_addr(ha) ((ha)->addr)
141 #define bnx2x_uc_addr(ha) ((ha)->addr)
142
143 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
144 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
146
147
148 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
149
150 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
151 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
152 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
153
154 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
155 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
156 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
157
158 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
159 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
160
161 #define REG_RD_DMAE(bp, offset, valp, len32) \
162 do { \
163 bnx2x_read_dmae(bp, offset, len32);\
164 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
165 } while (0)
166
167 #define REG_WR_DMAE(bp, offset, valp, len32) \
168 do { \
169 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
170 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
171 offset, len32); \
172 } while (0)
173
174 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
175 REG_WR_DMAE(bp, offset, valp, len32)
176
177 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
178 do { \
179 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
180 bnx2x_write_big_buf_wb(bp, addr, len32); \
181 } while (0)
182
183 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
184 offsetof(struct shmem_region, field))
185 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
186 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
187
188 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
189 offsetof(struct shmem2_region, field))
190 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
191 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
192 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
193 offsetof(struct mf_cfg, field))
194 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
195 offsetof(struct mf2_cfg, field))
196
197 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
198 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
199 MF_CFG_ADDR(bp, field), (val))
200 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
201
202 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
203 (SHMEM2_RD((bp), size) > \
204 offsetof(struct shmem2_region, field)))
205
206 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
207 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
208
209 /* SP SB indices */
210
211 /* General SP events - stats query, cfc delete, etc */
212 #define HC_SP_INDEX_ETH_DEF_CONS 3
213
214 /* EQ completions */
215 #define HC_SP_INDEX_EQ_CONS 7
216
217 /* FCoE L2 connection completions */
218 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
219 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
220 /* iSCSI L2 */
221 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
222 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
223
224 /* Special clients parameters */
225
226 /* SB indices */
227 /* FCoE L2 */
228 #define BNX2X_FCOE_L2_RX_INDEX \
229 (&bp->def_status_blk->sp_sb.\
230 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
231
232 #define BNX2X_FCOE_L2_TX_INDEX \
233 (&bp->def_status_blk->sp_sb.\
234 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
235
236 /**
237 * CIDs and CLIDs:
238 * CLIDs below is a CLID for func 0, then the CLID for other
239 * functions will be calculated by the formula:
240 *
241 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
242 *
243 */
244 /* iSCSI L2 */
245 #define BNX2X_ISCSI_ETH_CL_ID_IDX 1
246 #define BNX2X_ISCSI_ETH_CID 17
247
248 /* FCoE L2 */
249 #define BNX2X_FCOE_ETH_CL_ID_IDX 2
250 #define BNX2X_FCOE_ETH_CID 18
251
252 /** Additional rings budgeting */
253 #ifdef BCM_CNIC
254 #define CNIC_CONTEXT_USE 1
255 #define FCOE_CONTEXT_USE 1
256 #else
257 #define CNIC_CONTEXT_USE 0
258 #define FCOE_CONTEXT_USE 0
259 #endif /* BCM_CNIC */
260 #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE)
261
262 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
263 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
264
265 #define SM_RX_ID 0
266 #define SM_TX_ID 1
267
268 /* fast path */
269
270 struct sw_rx_bd {
271 struct sk_buff *skb;
272 DEFINE_DMA_UNMAP_ADDR(mapping);
273 };
274
275 struct sw_tx_bd {
276 struct sk_buff *skb;
277 u16 first_bd;
278 u8 flags;
279 /* Set on the first BD descriptor when there is a split BD */
280 #define BNX2X_TSO_SPLIT_BD (1<<0)
281 };
282
283 struct sw_rx_page {
284 struct page *page;
285 DEFINE_DMA_UNMAP_ADDR(mapping);
286 };
287
288 union db_prod {
289 struct doorbell_set_prod data;
290 u32 raw;
291 };
292
293
294 /* MC hsi */
295 #define BCM_PAGE_SHIFT 12
296 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
297 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
298 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
299
300 #define PAGES_PER_SGE_SHIFT 0
301 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
302 #define SGE_PAGE_SIZE PAGE_SIZE
303 #define SGE_PAGE_SHIFT PAGE_SHIFT
304 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
305
306 /* SGE ring related macros */
307 #define NUM_RX_SGE_PAGES 2
308 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
309 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
310 /* RX_SGE_CNT is promised to be a power of 2 */
311 #define RX_SGE_MASK (RX_SGE_CNT - 1)
312 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
313 #define MAX_RX_SGE (NUM_RX_SGE - 1)
314 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
315 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
316 #define RX_SGE(x) ((x) & MAX_RX_SGE)
317
318 /* Manipulate a bit vector defined as an array of u64 */
319
320 /* Number of bits in one sge_mask array element */
321 #define BIT_VEC64_ELEM_SZ 64
322 #define BIT_VEC64_ELEM_SHIFT 6
323 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
324
325
326 #define __BIT_VEC64_SET_BIT(el, bit) \
327 do { \
328 el = ((el) | ((u64)0x1 << (bit))); \
329 } while (0)
330
331 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
332 do { \
333 el = ((el) & (~((u64)0x1 << (bit)))); \
334 } while (0)
335
336
337 #define BIT_VEC64_SET_BIT(vec64, idx) \
338 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
339 (idx) & BIT_VEC64_ELEM_MASK)
340
341 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
342 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
343 (idx) & BIT_VEC64_ELEM_MASK)
344
345 #define BIT_VEC64_TEST_BIT(vec64, idx) \
346 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
347 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
348
349 /* Creates a bitmask of all ones in less significant bits.
350 idx - index of the most significant bit in the created mask */
351 #define BIT_VEC64_ONES_MASK(idx) \
352 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
353 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
354
355 /*******************************************************/
356
357
358
359 /* Number of u64 elements in SGE mask array */
360 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
361 BIT_VEC64_ELEM_SZ)
362 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
363 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
364
365 union host_hc_status_block {
366 /* pointer to fp status block e1x */
367 struct host_hc_status_block_e1x *e1x_sb;
368 /* pointer to fp status block e2 */
369 struct host_hc_status_block_e2 *e2_sb;
370 };
371
372 struct bnx2x_agg_info {
373 /*
374 * First aggregation buffer is an skb, the following - are pages.
375 * We will preallocate the skbs for each aggregation when
376 * we open the interface and will replace the BD at the consumer
377 * with this one when we receive the TPA_START CQE in order to
378 * keep the Rx BD ring consistent.
379 */
380 struct sw_rx_bd first_buf;
381 u8 tpa_state;
382 #define BNX2X_TPA_START 1
383 #define BNX2X_TPA_STOP 2
384 #define BNX2X_TPA_ERROR 3
385 u8 placement_offset;
386 u16 parsing_flags;
387 u16 vlan_tag;
388 u16 len_on_bd;
389 };
390
391 #define Q_STATS_OFFSET32(stat_name) \
392 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
393
394 struct bnx2x_fastpath {
395 struct bnx2x *bp; /* parent */
396
397 #define BNX2X_NAPI_WEIGHT 128
398 struct napi_struct napi;
399 union host_hc_status_block status_blk;
400 /* chip independed shortcuts into sb structure */
401 __le16 *sb_index_values;
402 __le16 *sb_running_index;
403 /* chip independed shortcut into rx_prods_offset memory */
404 u32 ustorm_rx_prods_offset;
405
406 u32 rx_buf_size;
407
408 dma_addr_t status_blk_mapping;
409
410 struct sw_tx_bd *tx_buf_ring;
411
412 union eth_tx_bd_types *tx_desc_ring;
413 dma_addr_t tx_desc_mapping;
414
415 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
416 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
417
418 struct eth_rx_bd *rx_desc_ring;
419 dma_addr_t rx_desc_mapping;
420
421 union eth_rx_cqe *rx_comp_ring;
422 dma_addr_t rx_comp_mapping;
423
424 /* SGE ring */
425 struct eth_rx_sge *rx_sge_ring;
426 dma_addr_t rx_sge_mapping;
427
428 u64 sge_mask[RX_SGE_MASK_LEN];
429
430 u32 cid;
431
432 u8 index; /* number in fp array */
433 u8 cl_id; /* eth client id */
434 u8 cl_qzone_id;
435 u8 fw_sb_id; /* status block number in FW */
436 u8 igu_sb_id; /* status block number in HW */
437 union db_prod tx_db;
438
439 u16 tx_pkt_prod;
440 u16 tx_pkt_cons;
441 u16 tx_bd_prod;
442 u16 tx_bd_cons;
443 __le16 *tx_cons_sb;
444
445 __le16 fp_hc_idx;
446
447 u16 rx_bd_prod;
448 u16 rx_bd_cons;
449 u16 rx_comp_prod;
450 u16 rx_comp_cons;
451 u16 rx_sge_prod;
452 /* The last maximal completed SGE */
453 u16 last_max_sge;
454 __le16 *rx_cons_sb;
455 unsigned long tx_pkt,
456 rx_pkt,
457 rx_calls;
458
459 /* TPA related */
460 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
461 u8 disable_tpa;
462 #ifdef BNX2X_STOP_ON_ERROR
463 u64 tpa_queue_used;
464 #endif
465
466 struct tstorm_per_queue_stats old_tclient;
467 struct ustorm_per_queue_stats old_uclient;
468 struct xstorm_per_queue_stats old_xclient;
469 struct bnx2x_eth_q_stats eth_q_stats;
470
471 /* The size is calculated using the following:
472 sizeof name field from netdev structure +
473 4 ('-Xx-' string) +
474 4 (for the digits and to make it DWORD aligned) */
475 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
476 char name[FP_NAME_SIZE];
477
478 /* MACs object */
479 struct bnx2x_vlan_mac_obj mac_obj;
480
481 /* Queue State object */
482 struct bnx2x_queue_sp_obj q_obj;
483
484 };
485
486 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
487
488 /* Use 2500 as a mini-jumbo MTU for FCoE */
489 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
490
491 /* FCoE L2 `fastpath' entry is right after the eth entries */
492 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
493 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
494 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
495
496
497 #ifdef BCM_CNIC
498 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
499 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
500 #else
501 #define IS_FCOE_FP(fp) false
502 #define IS_FCOE_IDX(idx) false
503 #endif
504
505
506 /* MC hsi */
507 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
508 #define RX_COPY_THRESH 92
509
510 #define NUM_TX_RINGS 16
511 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
512 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
513 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
514 #define MAX_TX_BD (NUM_TX_BD - 1)
515 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
516 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
517 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
518 #define TX_BD(x) ((x) & MAX_TX_BD)
519 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
520
521 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
522 #define NUM_RX_RINGS 8
523 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
524 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
525 #define RX_DESC_MASK (RX_DESC_CNT - 1)
526 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
527 #define MAX_RX_BD (NUM_RX_BD - 1)
528 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
529 #define MIN_RX_AVAIL 128
530
531 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
532 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
533 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
534 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
535 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
536 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
537 MIN_RX_AVAIL))
538
539 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
540 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
541 #define RX_BD(x) ((x) & MAX_RX_BD)
542
543 /*
544 * As long as CQE is X times bigger than BD entry we have to allocate X times
545 * more pages for CQ ring in order to keep it balanced with BD ring
546 */
547 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
548 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
549 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
550 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
551 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
552 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
553 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
554 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
555 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
556 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
557
558
559 /* This is needed for determining of last_max */
560 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
561 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
562
563
564 #define BNX2X_SWCID_SHIFT 17
565 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
566
567 /* used on a CID received from the HW */
568 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
569 #define CQE_CMD(x) (le32_to_cpu(x) >> \
570 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
571
572 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
573 le32_to_cpu((bd)->addr_lo))
574 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
575
576 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
577 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
578 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
579 #error "Min DB doorbell stride is 8"
580 #endif
581 #define DPM_TRIGER_TYPE 0x40
582 #define DOORBELL(bp, cid, val) \
583 do { \
584 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
585 DPM_TRIGER_TYPE); \
586 } while (0)
587
588
589 /* TX CSUM helpers */
590 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
591 skb->csum_offset)
592 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
593 skb->csum_offset))
594
595 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
596
597 #define XMIT_PLAIN 0
598 #define XMIT_CSUM_V4 0x1
599 #define XMIT_CSUM_V6 0x2
600 #define XMIT_CSUM_TCP 0x4
601 #define XMIT_GSO_V4 0x8
602 #define XMIT_GSO_V6 0x10
603
604 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
605 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
606
607
608 /* stuff added to make the code fit 80Col */
609 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
610 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
611 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
612 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
613 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
614
615 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
616
617 #define BNX2X_IP_CSUM_ERR(cqe) \
618 (!((cqe)->fast_path_cqe.status_flags & \
619 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
620 ((cqe)->fast_path_cqe.type_error_flags & \
621 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
622
623 #define BNX2X_L4_CSUM_ERR(cqe) \
624 (!((cqe)->fast_path_cqe.status_flags & \
625 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
626 ((cqe)->fast_path_cqe.type_error_flags & \
627 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
628
629 #define BNX2X_RX_CSUM_OK(cqe) \
630 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
631
632 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
633 (((le16_to_cpu(flags) & \
634 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
635 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
636 == PRS_FLAG_OVERETH_IPV4)
637 #define BNX2X_RX_SUM_FIX(cqe) \
638 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
639
640
641 #define FP_USB_FUNC_OFF \
642 offsetof(struct cstorm_status_block_u, func)
643 #define FP_CSB_FUNC_OFF \
644 offsetof(struct cstorm_status_block_c, func)
645
646 #define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */
647 /* (HC_INDEX_U_TOE_RX_CQ_CONS) */
648 #define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */
649 /* (HC_INDEX_U_ETH_RX_CQ_CONS) */
650 #define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */
651 /* (HC_INDEX_U_ETH_RX_BD_CONS) */
652
653 #define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */
654 /* (HC_INDEX_C_TOE_TX_CQ_CONS) */
655 #define HC_INDEX_ETH_TX_CQ_CONS 5 /* Formerly Cstorm ETH CQ index */
656 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */
657
658 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_ETH_RX_CQ_CONS
659 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_ETH_RX_BD_CONS
660 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_ETH_TX_CQ_CONS
661
662 #define BNX2X_RX_SB_INDEX \
663 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
664
665 #define BNX2X_TX_SB_INDEX \
666 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
667
668 /* end of fast path */
669
670 /* common */
671
672 struct bnx2x_common {
673
674 u32 chip_id;
675 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
676 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
677
678 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
679 #define CHIP_NUM_57710 0x164e
680 #define CHIP_NUM_57711 0x164f
681 #define CHIP_NUM_57711E 0x1650
682 #define CHIP_NUM_57712 0x1662
683 #define CHIP_NUM_57712_MF 0x1663
684 #define CHIP_NUM_57713 0x1651
685 #define CHIP_NUM_57713E 0x1652
686 #define CHIP_NUM_57800 0x168a
687 #define CHIP_NUM_57800_MF 0x16a5
688 #define CHIP_NUM_57810 0x168e
689 #define CHIP_NUM_57810_MF 0x16ae
690 #define CHIP_NUM_57840 0x168d
691 #define CHIP_NUM_57840_MF 0x16ab
692 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
693 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
694 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
695 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
696 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
697 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
698 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
699 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
700 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
701 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
702 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
703 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
704 CHIP_IS_57711E(bp))
705 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
706 CHIP_IS_57712_MF(bp))
707 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
708 CHIP_IS_57800_MF(bp) || \
709 CHIP_IS_57810(bp) || \
710 CHIP_IS_57810_MF(bp) || \
711 CHIP_IS_57840(bp) || \
712 CHIP_IS_57840_MF(bp))
713 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
714 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
715 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
716
717 #define CHIP_REV_SHIFT 12
718 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
719 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
720 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
721 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
722 /* assume maximum 5 revisions */
723 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
724 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
725 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
726 !(CHIP_REV_VAL(bp) & 0x00001000))
727 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
728 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
729 (CHIP_REV_VAL(bp) & 0x00001000))
730
731 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
732 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
733
734 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
735 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
736 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
737 (CHIP_REV_SHIFT + 1)) \
738 << CHIP_REV_SHIFT)
739 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
740 CHIP_REV_SIM(bp) :\
741 CHIP_REV_VAL(bp))
742 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
743 (CHIP_REV(bp) == CHIP_REV_Bx))
744 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
745 (CHIP_REV(bp) == CHIP_REV_Ax))
746
747 int flash_size;
748 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
749 #define NVRAM_TIMEOUT_COUNT 30000
750 #define NVRAM_PAGE_SIZE 256
751
752 u32 shmem_base;
753 u32 shmem2_base;
754 u32 mf_cfg_base;
755 u32 mf2_cfg_base;
756
757 u32 hw_config;
758
759 u32 bc_ver;
760
761 u8 int_block;
762 #define INT_BLOCK_HC 0
763 #define INT_BLOCK_IGU 1
764 #define INT_BLOCK_MODE_NORMAL 0
765 #define INT_BLOCK_MODE_BW_COMP 2
766 #define CHIP_INT_MODE_IS_NBC(bp) \
767 (!CHIP_IS_E1x(bp) && \
768 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
769 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
770
771 u8 chip_port_mode;
772 #define CHIP_4_PORT_MODE 0x0
773 #define CHIP_2_PORT_MODE 0x1
774 #define CHIP_PORT_MODE_NONE 0x2
775 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
776 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
777 };
778
779 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
780 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
781 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
782
783 /* end of common */
784
785 /* port */
786
787 struct bnx2x_port {
788 u32 pmf;
789
790 u32 link_config[LINK_CONFIG_SIZE];
791
792 u32 supported[LINK_CONFIG_SIZE];
793 /* link settings - missing defines */
794 #define SUPPORTED_2500baseX_Full (1 << 15)
795
796 u32 advertising[LINK_CONFIG_SIZE];
797 /* link settings - missing defines */
798 #define ADVERTISED_2500baseX_Full (1 << 15)
799
800 u32 phy_addr;
801
802 /* used to synchronize phy accesses */
803 struct mutex phy_mutex;
804 int need_hw_lock;
805
806 u32 port_stx;
807
808 struct nig_stats old_nig_stats;
809 };
810
811 /* end of port */
812
813 #define STATS_OFFSET32(stat_name) \
814 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
815
816 /* slow path */
817
818 /* slow path work-queue */
819 extern struct workqueue_struct *bnx2x_wq;
820
821 #define BNX2X_MAX_NUM_OF_VFS 64
822 #define BNX2X_VF_ID_INVALID 0xFF
823
824 /*
825 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
826 * control by the number of fast-path status blocks supported by the
827 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
828 * status block represents an independent interrupts context that can
829 * serve a regular L2 networking queue. However special L2 queues such
830 * as the FCoE queue do not require a FP-SB and other components like
831 * the CNIC may consume FP-SB reducing the number of possible L2 queues
832 *
833 * If the maximum number of FP-SB available is X then:
834 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
835 * regular L2 queues is Y=X-1
836 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
837 * c. If the FCoE L2 queue is supported the actual number of L2 queues
838 * is Y+1
839 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
840 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
841 * FP interrupt context for the CNIC).
842 * e. The number of HW context (CID count) is always X or X+1 if FCoE
843 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
844 */
845
846 /* fast-path interrupt contexts E1x */
847 #define FP_SB_MAX_E1x 16
848 /* fast-path interrupt contexts E2 */
849 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
850
851 /*
852 * cid_cnt paramter below refers to the value returned by
853 * 'bnx2x_get_l2_cid_count()' routine
854 */
855
856 /*
857 * The number of FP context allocated by the driver == max number of regular
858 * L2 queues + 1 for the FCoE L2 queue
859 */
860 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE)
861
862 /*
863 * The number of FP-SB allocated by the driver == max number of regular L2
864 * queues + 1 for the CNIC which also consumes an FP-SB
865 */
866 #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
867 #define NUM_IGU_SB_REQUIRED(cid_cnt) \
868 (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
869
870 union cdu_context {
871 struct eth_context eth;
872 char pad[1024];
873 };
874
875 /* CDU host DB constants */
876 #define CDU_ILT_PAGE_SZ_HW 3
877 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
878 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
879
880 #ifdef BCM_CNIC
881 #define CNIC_ISCSI_CID_MAX 256
882 #define CNIC_FCOE_CID_MAX 2048
883 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
884 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
885 #endif
886
887 #define QM_ILT_PAGE_SZ_HW 0
888 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
889 #define QM_CID_ROUND 1024
890
891 #ifdef BCM_CNIC
892 /* TM (timers) host DB constants */
893 #define TM_ILT_PAGE_SZ_HW 0
894 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
895 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
896 #define TM_CONN_NUM 1024
897 #define TM_ILT_SZ (8 * TM_CONN_NUM)
898 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
899
900 /* SRC (Searcher) host DB constants */
901 #define SRC_ILT_PAGE_SZ_HW 0
902 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
903 #define SRC_HASH_BITS 10
904 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
905 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
906 #define SRC_T2_SZ SRC_ILT_SZ
907 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
908
909 #endif
910
911 #define MAX_DMAE_C 8
912
913 /* DMA memory not used in fastpath */
914 struct bnx2x_slowpath {
915 union {
916 struct mac_configuration_cmd e1x;
917 struct eth_classify_rules_ramrod_data e2;
918 } mac_rdata;
919
920
921 union {
922 struct tstorm_eth_mac_filter_config e1x;
923 struct eth_filter_rules_ramrod_data e2;
924 } rx_mode_rdata;
925
926 union {
927 struct mac_configuration_cmd e1;
928 struct eth_multicast_rules_ramrod_data e2;
929 } mcast_rdata;
930
931 struct eth_rss_update_ramrod_data rss_rdata;
932
933 /* Queue State related ramrods are always sent under rtnl_lock */
934 union {
935 struct client_init_ramrod_data init_data;
936 struct client_update_ramrod_data update_data;
937 } q_rdata;
938
939 union {
940 struct function_start_data func_start;
941 } func_rdata;
942
943 /* used by dmae command executer */
944 struct dmae_command dmae[MAX_DMAE_C];
945
946 u32 stats_comp;
947 union mac_stats mac_stats;
948 struct nig_stats nig_stats;
949 struct host_port_stats port_stats;
950 struct host_func_stats func_stats;
951 struct host_func_stats func_stats_base;
952
953 u32 wb_comp;
954 u32 wb_data[4];
955 /* pfc configuration for DCBX ramrod */
956 struct flow_control_configuration pfc_config;
957 };
958
959 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
960 #define bnx2x_sp_mapping(bp, var) \
961 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
962
963
964 /* attn group wiring */
965 #define MAX_DYNAMIC_ATTN_GRPS 8
966
967 struct attn_route {
968 u32 sig[5];
969 };
970
971 struct iro {
972 u32 base;
973 u16 m1;
974 u16 m2;
975 u16 m3;
976 u16 size;
977 };
978
979 struct hw_context {
980 union cdu_context *vcxt;
981 dma_addr_t cxt_mapping;
982 size_t size;
983 };
984
985 /* forward */
986 struct bnx2x_ilt;
987
988
989 enum bnx2x_recovery_state {
990 BNX2X_RECOVERY_DONE,
991 BNX2X_RECOVERY_INIT,
992 BNX2X_RECOVERY_WAIT,
993 BNX2X_RECOVERY_FAILED
994 };
995
996 /*
997 * Event queue (EQ or event ring) MC hsi
998 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
999 */
1000 #define NUM_EQ_PAGES 1
1001 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1002 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1003 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1004 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1005 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1006
1007 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1008 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1009 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1010
1011 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1012 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1013
1014 #define BNX2X_EQ_INDEX \
1015 (&bp->def_status_blk->sp_sb.\
1016 index_values[HC_SP_INDEX_EQ_CONS])
1017
1018 /* This is a data that will be used to create a link report message.
1019 * We will keep the data used for the last link report in order
1020 * to prevent reporting the same link parameters twice.
1021 */
1022 struct bnx2x_link_report_data {
1023 u16 line_speed; /* Effective line speed */
1024 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1025 };
1026
1027 enum {
1028 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1029 BNX2X_LINK_REPORT_LINK_DOWN,
1030 BNX2X_LINK_REPORT_RX_FC_ON,
1031 BNX2X_LINK_REPORT_TX_FC_ON,
1032 };
1033
1034 enum {
1035 BNX2X_PORT_QUERY_IDX,
1036 BNX2X_PF_QUERY_IDX,
1037 BNX2X_FIRST_QUEUE_QUERY_IDX,
1038 };
1039
1040 struct bnx2x_fw_stats_req {
1041 struct stats_query_header hdr;
1042 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1043 };
1044
1045 struct bnx2x_fw_stats_data {
1046 struct stats_counter storm_counters;
1047 struct per_port_stats port;
1048 struct per_pf_stats pf;
1049 struct per_queue_stats queue_stats[1];
1050 };
1051
1052 struct bnx2x {
1053 /* Fields used in the tx and intr/napi performance paths
1054 * are grouped together in the beginning of the structure
1055 */
1056 struct bnx2x_fastpath *fp;
1057 void __iomem *regview;
1058 void __iomem *doorbells;
1059 u16 db_size;
1060
1061 u8 pf_num; /* absolute PF number */
1062 u8 pfid; /* per-path PF number */
1063 int base_fw_ndsb; /**/
1064 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1065 #define BP_PORT(bp) (bp->pfid & 1)
1066 #define BP_FUNC(bp) (bp->pfid)
1067 #define BP_ABS_FUNC(bp) (bp->pf_num)
1068 #define BP_E1HVN(bp) (bp->pfid >> 1)
1069 #define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/
1070 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
1071 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
1072 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
1073
1074 struct net_device *dev;
1075 struct pci_dev *pdev;
1076
1077 const struct iro *iro_arr;
1078 #define IRO (bp->iro_arr)
1079
1080 enum bnx2x_recovery_state recovery_state;
1081 int is_leader;
1082 struct msix_entry *msix_table;
1083
1084 int tx_ring_size;
1085
1086 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1087 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1088 #define ETH_MIN_PACKET_SIZE 60
1089 #define ETH_MAX_PACKET_SIZE 1500
1090 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1091
1092 /* Max supported alignment is 256 (8 shift) */
1093 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1094 L1_CACHE_SHIFT : 8)
1095 /* FW use 2 Cache lines Alignment for start packet and size */
1096 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1097 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1098
1099 struct host_sp_status_block *def_status_blk;
1100 #define DEF_SB_IGU_ID 16
1101 #define DEF_SB_ID HC_SP_SB_ID
1102 __le16 def_idx;
1103 __le16 def_att_idx;
1104 u32 attn_state;
1105 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1106
1107 /* slow path ring */
1108 struct eth_spe *spq;
1109 dma_addr_t spq_mapping;
1110 u16 spq_prod_idx;
1111 struct eth_spe *spq_prod_bd;
1112 struct eth_spe *spq_last_bd;
1113 __le16 *dsb_sp_prod;
1114 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1115 /* used to synchronize spq accesses */
1116 spinlock_t spq_lock;
1117
1118 /* event queue */
1119 union event_ring_elem *eq_ring;
1120 dma_addr_t eq_mapping;
1121 u16 eq_prod;
1122 u16 eq_cons;
1123 __le16 *eq_cons_sb;
1124 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1125
1126
1127
1128 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1129 u16 stats_pending;
1130 /* Counter for completed statistics ramrods */
1131 u16 stats_comp;
1132
1133 /* End of fields used in the performance code paths */
1134
1135 int panic;
1136 int msg_enable;
1137
1138 u32 flags;
1139 #define PCIX_FLAG (1 << 0)
1140 #define PCI_32BIT_FLAG (1 << 1)
1141 #define ONE_PORT_FLAG (1 << 2)
1142 #define NO_WOL_FLAG (1 << 3)
1143 #define USING_DAC_FLAG (1 << 4)
1144 #define USING_MSIX_FLAG (1 << 5)
1145 #define USING_MSI_FLAG (1 << 6)
1146 #define DISABLE_MSI_FLAG (1 << 7)
1147 #define TPA_ENABLE_FLAG (1 << 8)
1148 #define NO_MCP_FLAG (1 << 9)
1149
1150 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1151 #define MF_FUNC_DIS (1 << 11)
1152 #define OWN_CNIC_IRQ (1 << 12)
1153 #define NO_ISCSI_OOO_FLAG (1 << 13)
1154 #define NO_ISCSI_FLAG (1 << 14)
1155 #define NO_FCOE_FLAG (1 << 15)
1156
1157 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1158 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1159 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1160
1161 int pm_cap;
1162 int pcie_cap;
1163 int mrrs;
1164
1165 struct delayed_work sp_task;
1166 struct delayed_work reset_task;
1167 struct timer_list timer;
1168 int current_interval;
1169
1170 u16 fw_seq;
1171 u16 fw_drv_pulse_wr_seq;
1172 u32 func_stx;
1173
1174 struct link_params link_params;
1175 struct link_vars link_vars;
1176 u32 link_cnt;
1177 struct bnx2x_link_report_data last_reported_link;
1178
1179 struct mdio_if_info mdio;
1180
1181 struct bnx2x_common common;
1182 struct bnx2x_port port;
1183
1184 struct cmng_struct_per_port cmng;
1185 u32 vn_weight_sum;
1186 u32 mf_config[E1HVN_MAX];
1187 u32 mf2_config[E2_FUNC_MAX];
1188 u32 path_has_ovlan; /* E3 */
1189 u16 mf_ov;
1190 u8 mf_mode;
1191 #define IS_MF(bp) (bp->mf_mode != 0)
1192 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1193 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1194
1195 u8 wol;
1196
1197 int rx_ring_size;
1198
1199 u16 tx_quick_cons_trip_int;
1200 u16 tx_quick_cons_trip;
1201 u16 tx_ticks_int;
1202 u16 tx_ticks;
1203
1204 u16 rx_quick_cons_trip_int;
1205 u16 rx_quick_cons_trip;
1206 u16 rx_ticks_int;
1207 u16 rx_ticks;
1208 /* Maximal coalescing timeout in us */
1209 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1210
1211 u32 lin_cnt;
1212
1213 u16 state;
1214 #define BNX2X_STATE_CLOSED 0
1215 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1216 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1217 #define BNX2X_STATE_OPEN 0x3000
1218 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1219 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1220
1221 #define BNX2X_STATE_DIAG 0xe000
1222 #define BNX2X_STATE_ERROR 0xf000
1223
1224 int multi_mode;
1225 int num_queues;
1226 int disable_tpa;
1227
1228 u32 rx_mode;
1229 #define BNX2X_RX_MODE_NONE 0
1230 #define BNX2X_RX_MODE_NORMAL 1
1231 #define BNX2X_RX_MODE_ALLMULTI 2
1232 #define BNX2X_RX_MODE_PROMISC 3
1233 #define BNX2X_MAX_MULTICAST 64
1234
1235 u8 igu_dsb_id;
1236 u8 igu_base_sb;
1237 u8 igu_sb_cnt;
1238 dma_addr_t def_status_blk_mapping;
1239
1240 struct bnx2x_slowpath *slowpath;
1241 dma_addr_t slowpath_mapping;
1242
1243 /* Total number of FW statistics requests */
1244 u8 fw_stats_num;
1245
1246 /*
1247 * This is a memory buffer that will contain both statistics
1248 * ramrod request and data.
1249 */
1250 void *fw_stats;
1251 dma_addr_t fw_stats_mapping;
1252
1253 /*
1254 * FW statistics request shortcut (points at the
1255 * beginning of fw_stats buffer).
1256 */
1257 struct bnx2x_fw_stats_req *fw_stats_req;
1258 dma_addr_t fw_stats_req_mapping;
1259 int fw_stats_req_sz;
1260
1261 /*
1262 * FW statistics data shortcut (points at the begining of
1263 * fw_stats buffer + fw_stats_req_sz).
1264 */
1265 struct bnx2x_fw_stats_data *fw_stats_data;
1266 dma_addr_t fw_stats_data_mapping;
1267 int fw_stats_data_sz;
1268
1269 struct hw_context context;
1270
1271 struct bnx2x_ilt *ilt;
1272 #define BP_ILT(bp) ((bp)->ilt)
1273 #define ILT_MAX_LINES 256
1274
1275 int l2_cid_count;
1276 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1277 ILT_PAGE_CIDS))
1278 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1279
1280 int qm_cid_count;
1281
1282 int dropless_fc;
1283
1284 #ifdef BCM_CNIC
1285 u32 cnic_flags;
1286 #define BNX2X_CNIC_FLAG_MAC_SET 1
1287 void *t2;
1288 dma_addr_t t2_mapping;
1289 struct cnic_ops __rcu *cnic_ops;
1290 void *cnic_data;
1291 u32 cnic_tag;
1292 struct cnic_eth_dev cnic_eth_dev;
1293 union host_hc_status_block cnic_sb;
1294 dma_addr_t cnic_sb_mapping;
1295 struct eth_spe *cnic_kwq;
1296 struct eth_spe *cnic_kwq_prod;
1297 struct eth_spe *cnic_kwq_cons;
1298 struct eth_spe *cnic_kwq_last;
1299 u16 cnic_kwq_pending;
1300 u16 cnic_spq_pending;
1301 u8 fip_mac[ETH_ALEN];
1302 struct mutex cnic_mutex;
1303 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1304
1305 /* Start index of the "special" (CNIC related) L2 cleints */
1306 u8 cnic_base_cl_id;
1307 #endif
1308
1309 int dmae_ready;
1310 /* used to synchronize dmae accesses */
1311 spinlock_t dmae_lock;
1312
1313 /* used to protect the FW mail box */
1314 struct mutex fw_mb_mutex;
1315
1316 /* used to synchronize stats collecting */
1317 int stats_state;
1318
1319 /* used for synchronization of concurrent threads statistics handling */
1320 spinlock_t stats_lock;
1321
1322 /* used by dmae command loader */
1323 struct dmae_command stats_dmae;
1324 int executer_idx;
1325
1326 u16 stats_counter;
1327 struct bnx2x_eth_stats eth_stats;
1328
1329 struct z_stream_s *strm;
1330 void *gunzip_buf;
1331 dma_addr_t gunzip_mapping;
1332 int gunzip_outlen;
1333 #define FW_BUF_SIZE 0x8000
1334 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1335 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1336 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1337
1338 struct raw_op *init_ops;
1339 /* Init blocks offsets inside init_ops */
1340 u16 *init_ops_offsets;
1341 /* Data blob - has 32 bit granularity */
1342 u32 *init_data;
1343 u32 init_mode_flags;
1344 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1345 /* Zipped PRAM blobs - raw data */
1346 const u8 *tsem_int_table_data;
1347 const u8 *tsem_pram_data;
1348 const u8 *usem_int_table_data;
1349 const u8 *usem_pram_data;
1350 const u8 *xsem_int_table_data;
1351 const u8 *xsem_pram_data;
1352 const u8 *csem_int_table_data;
1353 const u8 *csem_pram_data;
1354 #define INIT_OPS(bp) (bp->init_ops)
1355 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1356 #define INIT_DATA(bp) (bp->init_data)
1357 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1358 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1359 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1360 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1361 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1362 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1363 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1364 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1365
1366 #define PHY_FW_VER_LEN 20
1367 char fw_ver[32];
1368 const struct firmware *firmware;
1369
1370 /* LLDP params */
1371 struct bnx2x_config_lldp_params lldp_config_params;
1372
1373 /* DCB support on/off */
1374 u16 dcb_state;
1375 #define BNX2X_DCB_STATE_OFF 0
1376 #define BNX2X_DCB_STATE_ON 1
1377
1378 /* DCBX engine mode */
1379 int dcbx_enabled;
1380 #define BNX2X_DCBX_ENABLED_OFF 0
1381 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1382 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1383 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1384
1385 bool dcbx_mode_uset;
1386
1387 struct bnx2x_config_dcbx_params dcbx_config_params;
1388 struct bnx2x_dcbx_port_params dcbx_port_params;
1389 int dcb_version;
1390
1391 /* CAM credit pools */
1392 struct bnx2x_credit_pool_obj macs_pool;
1393
1394 /* RX_MODE object */
1395 struct bnx2x_rx_mode_obj rx_mode_obj;
1396
1397 /* MCAST object */
1398 struct bnx2x_mcast_obj mcast_obj;
1399
1400 /* RSS configuration object */
1401 struct bnx2x_rss_config_obj rss_conf_obj;
1402
1403 /* Function State controlling object */
1404 struct bnx2x_func_sp_obj func_obj;
1405
1406 unsigned long sp_state;
1407
1408 /* DCBX Negotation results */
1409 struct dcbx_features dcbx_local_feat;
1410 u32 dcbx_error;
1411
1412 #ifdef BCM_DCBNL
1413 struct dcbx_features dcbx_remote_feat;
1414 u32 dcbx_remote_flags;
1415 #endif
1416 u32 pending_max;
1417 };
1418
1419 /* Tx queues may be less or equal to Rx queues */
1420 extern int num_queues;
1421 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1422 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
1423
1424 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1425
1426 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1427
1428 #define RSS_IPV4_CAP_MASK \
1429 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1430
1431 #define RSS_IPV4_TCP_CAP_MASK \
1432 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1433
1434 #define RSS_IPV6_CAP_MASK \
1435 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1436
1437 #define RSS_IPV6_TCP_CAP_MASK \
1438 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1439
1440 /* func init flags */
1441 #define FUNC_FLG_RSS 0x0001
1442 #define FUNC_FLG_STATS 0x0002
1443 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1444 #define FUNC_FLG_TPA 0x0008
1445 #define FUNC_FLG_SPQ 0x0010
1446 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1447
1448
1449 struct bnx2x_func_init_params {
1450 /* dma */
1451 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1452 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1453
1454 u16 func_flgs;
1455 u16 func_id; /* abs fid */
1456 u16 pf_id;
1457 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1458 };
1459
1460 #define for_each_eth_queue(bp, var) \
1461 for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1462
1463 #define for_each_nondefault_eth_queue(bp, var) \
1464 for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1465
1466 #define for_each_queue(bp, var) \
1467 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1468 if (skip_queue(bp, var)) \
1469 continue; \
1470 else
1471
1472 #define for_each_rx_queue(bp, var) \
1473 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1474 if (skip_rx_queue(bp, var)) \
1475 continue; \
1476 else
1477
1478 #define for_each_tx_queue(bp, var) \
1479 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1480 if (skip_tx_queue(bp, var)) \
1481 continue; \
1482 else
1483
1484 #define for_each_nondefault_queue(bp, var) \
1485 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
1486 if (skip_queue(bp, var)) \
1487 continue; \
1488 else
1489
1490 /* skip rx queue
1491 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1492 */
1493 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1494
1495 /* skip tx queue
1496 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1497 */
1498 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1499
1500 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1501
1502
1503
1504
1505 /**
1506 * bnx2x_set_mac_one - configure a single MAC address
1507 *
1508 * @bp: driver handle
1509 * @mac: MAC to configure
1510 * @obj: MAC object handle
1511 * @set: if 'true' add a new MAC, otherwise - delete
1512 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1513 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1514 *
1515 * Configures one MAC according to provided parameters or continues the
1516 * execution of previously scheduled commands if RAMROD_CONT is set in
1517 * ramrod_flags.
1518 *
1519 * Returns zero if operation has successfully completed, a positive value if the
1520 * operation has been successfully scheduled and a negative - if a requested
1521 * operations has failed.
1522 */
1523 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1524 struct bnx2x_vlan_mac_obj *obj, bool set,
1525 int mac_type, unsigned long *ramrod_flags);
1526 /**
1527 * Deletes all MACs configured for the specific MAC object.
1528 *
1529 * @param bp Function driver instance
1530 * @param mac_obj MAC object to cleanup
1531 *
1532 * @return zero if all MACs were cleaned
1533 */
1534
1535 /**
1536 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1537 *
1538 * @bp: driver handle
1539 * @mac_obj: MAC object handle
1540 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1541 * @wait_for_comp: if 'true' block until completion
1542 *
1543 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1544 *
1545 * Returns zero if operation has successfully completed, a positive value if the
1546 * operation has been successfully scheduled and a negative - if a requested
1547 * operations has failed.
1548 */
1549 int bnx2x_del_all_macs(struct bnx2x *bp,
1550 struct bnx2x_vlan_mac_obj *mac_obj,
1551 int mac_type, bool wait_for_comp);
1552
1553 /* Init Function API */
1554 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1555 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1556 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1557 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1558 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1559 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1560
1561
1562 /* dmae */
1563 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1565 u32 len32);
1566 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1567 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1568 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1569 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1570 bool with_comp, u8 comp_type);
1571
1572
1573 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1574 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1575 u32 data_hi, u32 data_lo, int cmd_type);
1576 void bnx2x_update_coalesce(struct bnx2x *bp);
1577 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1578
1579 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1580 int wait)
1581 {
1582 u32 val;
1583
1584 do {
1585 val = REG_RD(bp, reg);
1586 if (val == expected)
1587 break;
1588 ms -= wait;
1589 msleep(wait);
1590
1591 } while (ms > 0);
1592
1593 return val;
1594 }
1595
1596 #define BNX2X_ILT_ZALLOC(x, y, size) \
1597 do { \
1598 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1599 if (x) \
1600 memset(x, 0, size); \
1601 } while (0)
1602
1603 #define BNX2X_ILT_FREE(x, y, size) \
1604 do { \
1605 if (x) { \
1606 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1607 x = NULL; \
1608 y = 0; \
1609 } \
1610 } while (0)
1611
1612 #define ILOG2(x) (ilog2((x)))
1613
1614 #define ILT_NUM_PAGE_ENTRIES (3072)
1615 /* In 57710/11 we use whole table since we have 8 func
1616 * In 57712 we have only 4 func, but use same size per func, then only half of
1617 * the table in use
1618 */
1619 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1620
1621 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1622 /*
1623 * the phys address is shifted right 12 bits and has an added
1624 * 1=valid bit added to the 53rd bit
1625 * then since this is a wide register(TM)
1626 * we split it into two 32 bit writes
1627 */
1628 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1629 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1630
1631 /* load/unload mode */
1632 #define LOAD_NORMAL 0
1633 #define LOAD_OPEN 1
1634 #define LOAD_DIAG 2
1635 #define UNLOAD_NORMAL 0
1636 #define UNLOAD_CLOSE 1
1637 #define UNLOAD_RECOVERY 2
1638
1639
1640 /* DMAE command defines */
1641 #define DMAE_TIMEOUT -1
1642 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1643 #define DMAE_NOT_RDY -3
1644 #define DMAE_PCI_ERR_FLAG 0x80000000
1645
1646 #define DMAE_SRC_PCI 0
1647 #define DMAE_SRC_GRC 1
1648
1649 #define DMAE_DST_NONE 0
1650 #define DMAE_DST_PCI 1
1651 #define DMAE_DST_GRC 2
1652
1653 #define DMAE_COMP_PCI 0
1654 #define DMAE_COMP_GRC 1
1655
1656 /* E2 and onward - PCI error handling in the completion */
1657
1658 #define DMAE_COMP_REGULAR 0
1659 #define DMAE_COM_SET_ERR 1
1660
1661 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1662 DMAE_COMMAND_SRC_SHIFT)
1663 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1664 DMAE_COMMAND_SRC_SHIFT)
1665
1666 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1667 DMAE_COMMAND_DST_SHIFT)
1668 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1669 DMAE_COMMAND_DST_SHIFT)
1670
1671 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1672 DMAE_COMMAND_C_DST_SHIFT)
1673 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1674 DMAE_COMMAND_C_DST_SHIFT)
1675
1676 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1677
1678 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1679 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1680 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1681 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1682
1683 #define DMAE_CMD_PORT_0 0
1684 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1685
1686 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1687 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1688 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1689
1690 #define DMAE_SRC_PF 0
1691 #define DMAE_SRC_VF 1
1692
1693 #define DMAE_DST_PF 0
1694 #define DMAE_DST_VF 1
1695
1696 #define DMAE_C_SRC 0
1697 #define DMAE_C_DST 1
1698
1699 #define DMAE_LEN32_RD_MAX 0x80
1700 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1701
1702 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1703 indicates eror */
1704
1705 #define MAX_DMAE_C_PER_PORT 8
1706 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1707 BP_E1HVN(bp))
1708 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1709 E1HVN_MAX)
1710
1711 /* PCIE link and speed */
1712 #define PCICFG_LINK_WIDTH 0x1f00000
1713 #define PCICFG_LINK_WIDTH_SHIFT 20
1714 #define PCICFG_LINK_SPEED 0xf0000
1715 #define PCICFG_LINK_SPEED_SHIFT 16
1716
1717
1718 #define BNX2X_NUM_TESTS 7
1719
1720 #define BNX2X_PHY_LOOPBACK 0
1721 #define BNX2X_MAC_LOOPBACK 1
1722 #define BNX2X_PHY_LOOPBACK_FAILED 1
1723 #define BNX2X_MAC_LOOPBACK_FAILED 2
1724 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1725 BNX2X_PHY_LOOPBACK_FAILED)
1726
1727
1728 #define STROM_ASSERT_ARRAY_SIZE 50
1729
1730
1731 /* must be used on a CID before placing it on a HW ring */
1732 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1733 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \
1734 (x))
1735
1736 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1737 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1738
1739
1740 #define BNX2X_BTR 4
1741 #define MAX_SPQ_PENDING 8
1742
1743 /* CMNG constants, as derived from system spec calculations */
1744 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1745 #define DEF_MIN_RATE 100
1746 /* resolution of the rate shaping timer - 400 usec */
1747 #define RS_PERIODIC_TIMEOUT_USEC 400
1748 /* number of bytes in single QM arbitration cycle -
1749 * coefficient for calculating the fairness timer */
1750 #define QM_ARB_BYTES 160000
1751 /* resolution of Min algorithm 1:100 */
1752 #define MIN_RES 100
1753 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1754 #define MIN_ABOVE_THRESH 32768
1755 /* Fairness algorithm integration time coefficient -
1756 * for calculating the actual Tfair */
1757 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1758 /* Memory of fairness algorithm . 2 cycles */
1759 #define FAIR_MEM 2
1760
1761
1762 #define ATTN_NIG_FOR_FUNC (1L << 8)
1763 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1764 #define GPIO_2_FUNC (1L << 10)
1765 #define GPIO_3_FUNC (1L << 11)
1766 #define GPIO_4_FUNC (1L << 12)
1767 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1768 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1769 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1770 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1771 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1772 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1773
1774 #define ATTN_HARD_WIRED_MASK 0xff00
1775 #define ATTENTION_ID 4
1776
1777
1778 /* stuff added to make the code fit 80Col */
1779
1780 #define BNX2X_PMF_LINK_ASSERT \
1781 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1782
1783 #define BNX2X_MC_ASSERT_BITS \
1784 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1785 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1786 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1787 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1788
1789 #define BNX2X_MCP_ASSERT \
1790 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1791
1792 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1793 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1794 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1795 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1796 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1797 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1798 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1799
1800 #define HW_INTERRUT_ASSERT_SET_0 \
1801 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1802 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1803 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1804 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1805 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1806 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1807 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1808 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1809 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1810 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1811 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1812 #define HW_INTERRUT_ASSERT_SET_1 \
1813 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1814 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1815 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1816 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1817 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1818 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1819 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1820 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1821 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1822 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1823 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1824 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1825 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1826 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1827 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1828 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1829 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1830 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1831 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1832 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1833 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1834 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1835 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1836 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1837 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1838 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1839 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1840 #define HW_INTERRUT_ASSERT_SET_2 \
1841 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1842 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1843 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1844 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1845 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1846 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1847 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1848 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1849 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1850 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1851 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1852 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1853 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1854
1855 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1856 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1857 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1858 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1859
1860 #define RSS_FLAGS(bp) \
1861 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1862 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1863 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1864 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1865 (bp->multi_mode << \
1866 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1867 #define MULTI_MASK 0x7f
1868
1869
1870 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
1871 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
1872 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
1873 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
1874
1875 #define DEF_USB_IGU_INDEX_OFF \
1876 offsetof(struct cstorm_def_status_block_u, igu_index)
1877 #define DEF_CSB_IGU_INDEX_OFF \
1878 offsetof(struct cstorm_def_status_block_c, igu_index)
1879 #define DEF_XSB_IGU_INDEX_OFF \
1880 offsetof(struct xstorm_def_status_block, igu_index)
1881 #define DEF_TSB_IGU_INDEX_OFF \
1882 offsetof(struct tstorm_def_status_block, igu_index)
1883
1884 #define DEF_USB_SEGMENT_OFF \
1885 offsetof(struct cstorm_def_status_block_u, segment)
1886 #define DEF_CSB_SEGMENT_OFF \
1887 offsetof(struct cstorm_def_status_block_c, segment)
1888 #define DEF_XSB_SEGMENT_OFF \
1889 offsetof(struct xstorm_def_status_block, segment)
1890 #define DEF_TSB_SEGMENT_OFF \
1891 offsetof(struct tstorm_def_status_block, segment)
1892
1893 #define BNX2X_SP_DSB_INDEX \
1894 (&bp->def_status_blk->sp_sb.\
1895 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1896
1897 #define SET_FLAG(value, mask, flag) \
1898 do {\
1899 (value) &= ~(mask);\
1900 (value) |= ((flag) << (mask##_SHIFT));\
1901 } while (0)
1902
1903 #define GET_FLAG(value, mask) \
1904 (((value) & (mask)) >> (mask##_SHIFT))
1905
1906 #define GET_FIELD(value, fname) \
1907 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1908
1909 #define CAM_IS_INVALID(x) \
1910 (GET_FLAG(x.flags, \
1911 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1912 (T_ETH_MAC_COMMAND_INVALIDATE))
1913
1914 /* Number of u32 elements in MC hash array */
1915 #define MC_HASH_SIZE 8
1916 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1917 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1918
1919
1920 #ifndef PXP2_REG_PXP2_INT_STS
1921 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1922 #endif
1923
1924 #ifndef ETH_MAX_RX_CLIENTS_E2
1925 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1926 #endif
1927
1928 #define BNX2X_VPD_LEN 128
1929 #define VENDOR_ID_LEN 4
1930
1931 /* Congestion management fairness mode */
1932 #define CMNG_FNS_NONE 0
1933 #define CMNG_FNS_MINMAX 1
1934
1935 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1936 #define HC_SEG_ACCESS_ATTN 4
1937 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1938
1939 static const u32 dmae_reg_go_c[] = {
1940 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1941 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1942 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1943 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1944 };
1945
1946 void bnx2x_set_ethtool_ops(struct net_device *netdev);
1947 #endif /* bnx2x.h */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree