arch/x86_64/kernel/i8259.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/smp_lock.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sysdev.h>
  14 #include <linux/bitops.h>
  15
  16 #include <asm/acpi.h>
  17 #include <asm/atomic.h>
  18 #include <asm/system.h>
  19 #include <asm/io.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/delay.h>
  23 #include <asm/desc.h>
  24 #include <asm/apic.h>
  25
  26 /*
  27  * Common place to define all x86 IRQ vectors
  28  *
  29  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  30  *
  31  * These macros create the low-level assembly IRQ routines that save
  32  * register context and call do_IRQ(). do_IRQ() then does all the
  33  * operations that are needed to keep the AT (or SMP IOAPIC)
  34  * interrupt-controller happy.
  35  */
  36
  37 #define BI(x,y) \
  38         BUILD_IRQ(x##y)
  39
  40 #define BUILD_16_IRQS(x) \
  41         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  42         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  43         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  44         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  45
  46 /*
  47  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  48  * (these are usually mapped to vectors 0x30-0x3f)
  49  */
  50
  51 /*
  52  * The IO-APIC gives us many more interrupt sources. Most of these
  53  * are unused but an SMP system is supposed to have enough memory ...
  54  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  55  * across the spectrum, so we really want to be prepared to get all
  56  * of these. Plus, more powerful systems might have more than 64
  57  * IO-APIC registers.
  58  *
  59  * (these are usually mapped into the 0x30-0xff vector range)
  60  */
  61                                       BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  62 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  63 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  64 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
  65
  66 #undef BUILD_16_IRQS
  67 #undef BI
  68
  69
  70 #define IRQ(x,y) \
  71         IRQ##x##y##_interrupt
  72
  73 #define IRQLIST_16(x) \
  74         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  75         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  76         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  77         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  78
  79 /* for the irq vectors */
  80 static void (*interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
  81                                           IRQLIST_16(0x2), IRQLIST_16(0x3),
  82         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
  83         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
  84         IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
  85 };
  86
  87 #undef IRQ
  88 #undef IRQLIST_16
  89
  90 /*
  91  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  92  * present in the majority of PC/AT boxes.
  93  * plus some generic x86 specific things if generic specifics makes
  94  * any sense at all.
  95  * this file should become arch/i386/kernel/irq.c when the old irq.c
  96  * moves to arch independent land
  97  */
  98
  99 static int i8259A_auto_eoi;
 100 DEFINE_SPINLOCK(i8259A_lock);
 101 static void mask_and_ack_8259A(unsigned int);
 102
 103 static struct irq_chip i8259A_chip = {
 104         .name           = "XT-PIC",
 105         .mask           = disable_8259A_irq,
 106         .disable        = disable_8259A_irq,
 107         .unmask         = enable_8259A_irq,
 108         .mask_ack       = mask_and_ack_8259A,
 109 };
 110
 111 /*
 112  * 8259A PIC functions to handle ISA devices:
 113  */
 114
 115 /*
 116  * This contains the irq mask for both 8259A irq controllers,
 117  */
 118 static unsigned int cached_irq_mask = 0xffff;
 119
 120 #define __byte(x,y)     (((unsigned char *)&(y))[x])
 121 #define cached_21       (__byte(0,cached_irq_mask))
 122 #define cached_A1       (__byte(1,cached_irq_mask))
 123
 124 /*
 125  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 126  * boards the timer interrupt is not really connected to any IO-APIC pin,
 127  * it's fed to the master 8259A's IR0 line only.
 128  *
 129  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 130  * this 'mixed mode' IRQ handling costs nothing because it's only used
 131  * at IRQ setup time.
 132  */
 133 unsigned long io_apic_irqs;
 134
 135 void disable_8259A_irq(unsigned int irq)
 136 {
 137         unsigned int mask = 1 << irq;
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&i8259A_lock, flags);
 141         cached_irq_mask |= mask;
 142         if (irq & 8)
 143                 outb(cached_A1,0xA1);
 144         else
 145                 outb(cached_21,0x21);
 146         spin_unlock_irqrestore(&i8259A_lock, flags);
 147 }
 148
 149 void enable_8259A_irq(unsigned int irq)
 150 {
 151         unsigned int mask = ~(1 << irq);
 152         unsigned long flags;
 153
 154         spin_lock_irqsave(&i8259A_lock, flags);
 155         cached_irq_mask &= mask;
 156         if (irq & 8)
 157                 outb(cached_A1,0xA1);
 158         else
 159                 outb(cached_21,0x21);
 160         spin_unlock_irqrestore(&i8259A_lock, flags);
 161 }
 162
 163 int i8259A_irq_pending(unsigned int irq)
 164 {
 165         unsigned int mask = 1<<irq;
 166         unsigned long flags;
 167         int ret;
 168
 169         spin_lock_irqsave(&i8259A_lock, flags);
 170         if (irq < 8)
 171                 ret = inb(0x20) & mask;
 172         else
 173                 ret = inb(0xA0) & (mask >> 8);
 174         spin_unlock_irqrestore(&i8259A_lock, flags);
 175
 176         return ret;
 177 }
 178
 179 void make_8259A_irq(unsigned int irq)
 180 {
 181         disable_irq_nosync(irq);
 182         io_apic_irqs &= ~(1<<irq);
 183         set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
 184                                       "XT");
 185         enable_irq(irq);
 186 }
 187
 188 /*
 189  * This function assumes to be called rarely. Switching between
 190  * 8259A registers is slow.
 191  * This has to be protected by the irq controller spinlock
 192  * before being called.
 193  */
 194 static inline int i8259A_irq_real(unsigned int irq)
 195 {
 196         int value;
 197         int irqmask = 1<<irq;
 198
 199         if (irq < 8) {
 200                 outb(0x0B,0x20);                /* ISR register */
 201                 value = inb(0x20) & irqmask;
 202                 outb(0x0A,0x20);                /* back to the IRR register */
 203                 return value;
 204         }
 205         outb(0x0B,0xA0);                /* ISR register */
 206         value = inb(0xA0) & (irqmask >> 8);
 207         outb(0x0A,0xA0);                /* back to the IRR register */
 208         return value;
 209 }
 210
 211 /*
 212  * Careful! The 8259A is a fragile beast, it pretty
 213  * much _has_ to be done exactly like this (mask it
 214  * first, _then_ send the EOI, and the order of EOI
 215  * to the two 8259s is important!
 216  */
 217 static void mask_and_ack_8259A(unsigned int irq)
 218 {
 219         unsigned int irqmask = 1 << irq;
 220         unsigned long flags;
 221
 222         spin_lock_irqsave(&i8259A_lock, flags);
 223         /*
 224          * Lightweight spurious IRQ detection. We do not want
 225          * to overdo spurious IRQ handling - it's usually a sign
 226          * of hardware problems, so we only do the checks we can
 227          * do without slowing down good hardware unnecessarily.
 228          *
 229          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 230          * usually resulting from the 8259A-1|2 PICs) occur
 231          * even if the IRQ is masked in the 8259A. Thus we
 232          * can check spurious 8259A IRQs without doing the
 233          * quite slow i8259A_irq_real() call for every IRQ.
 234          * This does not cover 100% of spurious interrupts,
 235          * but should be enough to warn the user that there
 236          * is something bad going on ...
 237          */
 238         if (cached_irq_mask & irqmask)
 239                 goto spurious_8259A_irq;
 240         cached_irq_mask |= irqmask;
 241
 242 handle_real_irq:
 243         if (irq & 8) {
 244                 inb(0xA1);              /* DUMMY - (do we need this?) */
 245                 outb(cached_A1,0xA1);
 246                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 247                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 248         } else {
 249                 inb(0x21);              /* DUMMY - (do we need this?) */
 250                 outb(cached_21,0x21);
 251                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 252         }
 253         spin_unlock_irqrestore(&i8259A_lock, flags);
 254         return;
 255
 256 spurious_8259A_irq:
 257         /*
 258          * this is the slow path - should happen rarely.
 259          */
 260         if (i8259A_irq_real(irq))
 261                 /*
 262                  * oops, the IRQ _is_ in service according to the
 263                  * 8259A - not spurious, go handle it.
 264                  */
 265                 goto handle_real_irq;
 266
 267         {
 268                 static int spurious_irq_mask;
 269                 /*
 270                  * At this point we can be sure the IRQ is spurious,
 271                  * lets ACK and report it. [once per IRQ]
 272                  */
 273                 if (!(spurious_irq_mask & irqmask)) {
 274                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 275                         spurious_irq_mask |= irqmask;
 276                 }
 277                 atomic_inc(&irq_err_count);
 278                 /*
 279                  * Theoretically we do not have to handle this IRQ,
 280                  * but in Linux this does not cause problems and is
 281                  * simpler for us.
 282                  */
 283                 goto handle_real_irq;
 284         }
 285 }
 286
 287 void init_8259A(int auto_eoi)
 288 {
 289         unsigned long flags;
 290
 291         i8259A_auto_eoi = auto_eoi;
 292
 293         spin_lock_irqsave(&i8259A_lock, flags);
 294
 295         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 296         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 297
 298         /*
 299          * outb_p - this has to work on a wide range of PC hardware.
 300          */
 301         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 302         outb_p(IRQ0_VECTOR, 0x21);      /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
 303         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 304         if (auto_eoi)
 305                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 306         else
 307                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 308
 309         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 310         outb_p(IRQ8_VECTOR, 0xA1);      /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
 311         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 312         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 313                                     is to be investigated) */
 314
 315         if (auto_eoi)
 316                 /*
 317                  * in AEOI mode we just have to mask the interrupt
 318                  * when acking.
 319                  */
 320                 i8259A_chip.mask_ack = disable_8259A_irq;
 321         else
 322                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 323
 324         udelay(100);            /* wait for 8259A to initialize */
 325
 326         outb(cached_21, 0x21);  /* restore master IRQ mask */
 327         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 328
 329         spin_unlock_irqrestore(&i8259A_lock, flags);
 330 }
 331
 332 static char irq_trigger[2];
 333 /**
 334  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 335  */
 336 static void restore_ELCR(char *trigger)
 337 {
 338         outb(trigger[0], 0x4d0);
 339         outb(trigger[1], 0x4d1);
 340 }
 341
 342 static void save_ELCR(char *trigger)
 343 {
 344         /* IRQ 0,1,2,8,13 are marked as reserved */
 345         trigger[0] = inb(0x4d0) & 0xF8;
 346         trigger[1] = inb(0x4d1) & 0xDE;
 347 }
 348
 349 static int i8259A_resume(struct sys_device *dev)
 350 {
 351         init_8259A(i8259A_auto_eoi);
 352         restore_ELCR(irq_trigger);
 353         return 0;
 354 }
 355
 356 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 357 {
 358         save_ELCR(irq_trigger);
 359         return 0;
 360 }
 361
 362 static int i8259A_shutdown(struct sys_device *dev)
 363 {
 364         /* Put the i8259A into a quiescent state that
 365          * the kernel initialization code can get it
 366          * out of.
 367          */
 368         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 369         outb(0xff, 0xA1);       /* mask all of 8259A-1 */
 370         return 0;
 371 }
 372
 373 static struct sysdev_class i8259_sysdev_class = {
 374         set_kset_name("i8259"),
 375         .suspend = i8259A_suspend,
 376         .resume = i8259A_resume,
 377         .shutdown = i8259A_shutdown,
 378 };
 379
 380 static struct sys_device device_i8259A = {
 381         .id     = 0,
 382         .cls    = &i8259_sysdev_class,
 383 };
 384
 385 static int __init i8259A_init_sysfs(void)
 386 {
 387         int error = sysdev_class_register(&i8259_sysdev_class);
 388         if (!error)
 389                 error = sysdev_register(&device_i8259A);
 390         return error;
 391 }
 392
 393 device_initcall(i8259A_init_sysfs);
 394
 395 /*
 396  * IRQ2 is cascade interrupt to second interrupt controller
 397  */
 398
 399 static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 400 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
 401         [0 ... IRQ0_VECTOR - 1] = -1,
 402         [IRQ0_VECTOR] = 0,
 403         [IRQ1_VECTOR] = 1,
 404         [IRQ2_VECTOR] = 2,
 405         [IRQ3_VECTOR] = 3,
 406         [IRQ4_VECTOR] = 4,
 407         [IRQ5_VECTOR] = 5,
 408         [IRQ6_VECTOR] = 6,
 409         [IRQ7_VECTOR] = 7,
 410         [IRQ8_VECTOR] = 8,
 411         [IRQ9_VECTOR] = 9,
 412         [IRQ10_VECTOR] = 10,
 413         [IRQ11_VECTOR] = 11,
 414         [IRQ12_VECTOR] = 12,
 415         [IRQ13_VECTOR] = 13,
 416         [IRQ14_VECTOR] = 14,
 417         [IRQ15_VECTOR] = 15,
 418         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 419 };
 420
 421 void __init init_ISA_irqs (void)
 422 {
 423         int i;
 424
 425         init_bsp_APIC();
 426         init_8259A(0);
 427
 428         for (i = 0; i < NR_IRQS; i++) {
 429                 irq_desc[i].status = IRQ_DISABLED;
 430                 irq_desc[i].action = NULL;
 431                 irq_desc[i].depth = 1;
 432
 433                 if (i < 16) {
 434                         /*
 435                          * 16 old-style INTA-cycle interrupts:
 436                          */
 437                         set_irq_chip_and_handler_name(i, &i8259A_chip,
 438                                                       handle_level_irq, "XT");
 439                 } else {
 440                         /*
 441                          * 'high' PCI IRQs filled in on demand
 442                          */
 443                         irq_desc[i].chip = &no_irq_chip;
 444                 }
 445         }
 446 }
 447
 448 void apic_timer_interrupt(void);
 449 void spurious_interrupt(void);
 450 void error_interrupt(void);
 451 void reschedule_interrupt(void);
 452 void call_function_interrupt(void);
 453 void irq_move_cleanup_interrupt(void);
 454 void invalidate_interrupt0(void);
 455 void invalidate_interrupt1(void);
 456 void invalidate_interrupt2(void);
 457 void invalidate_interrupt3(void);
 458 void invalidate_interrupt4(void);
 459 void invalidate_interrupt5(void);
 460 void invalidate_interrupt6(void);
 461 void invalidate_interrupt7(void);
 462 void thermal_interrupt(void);
 463 void threshold_interrupt(void);
 464 void i8254_timer_resume(void);
 465
 466 static void setup_timer_hardware(void)
 467 {
 468         outb_p(0x34,0x43);              /* binary, mode 2, LSB/MSB, ch 0 */
 469         udelay(10);
 470         outb_p(LATCH & 0xff , 0x40);    /* LSB */
 471         udelay(10);
 472         outb(LATCH >> 8 , 0x40);        /* MSB */
 473 }
 474
 475 static int timer_resume(struct sys_device *dev)
 476 {
 477         setup_timer_hardware();
 478         return 0;
 479 }
 480
 481 void i8254_timer_resume(void)
 482 {
 483         setup_timer_hardware();
 484 }
 485
 486 static struct sysdev_class timer_sysclass = {
 487         set_kset_name("timer_pit"),
 488         .resume         = timer_resume,
 489 };
 490
 491 static struct sys_device device_timer = {
 492         .id             = 0,
 493         .cls            = &timer_sysclass,
 494 };
 495
 496 static int __init init_timer_sysfs(void)
 497 {
 498         int error = sysdev_class_register(&timer_sysclass);
 499         if (!error)
 500                 error = sysdev_register(&device_timer);
 501         return error;
 502 }
 503
 504 device_initcall(init_timer_sysfs);
 505
 506 void __init init_IRQ(void)
 507 {
 508         int i;
 509
 510         init_ISA_irqs();
 511         /*
 512          * Cover the whole vector space, no vector can escape
 513          * us. (some of these will be overridden and become
 514          * 'special' SMP interrupts)
 515          */
 516         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 517                 int vector = FIRST_EXTERNAL_VECTOR + i;
 518                 if (vector != IA32_SYSCALL_VECTOR)
 519                         set_intr_gate(vector, interrupt[i]);
 520         }
 521
 522 #ifdef CONFIG_SMP
 523         /*
 524          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 525          * IPI, driven by wakeup.
 526          */
 527         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 528
 529         /* IPIs for invalidation */
 530         set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 531         set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 532         set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 533         set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 534         set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 535         set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 536         set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 537         set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 538
 539         /* IPI for generic function call */
 540         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 541
 542         /* Low priority IPI to cleanup after moving an irq */
 543         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 544 #endif
 545         set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 546         set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 547
 548         /* self generated IPI for local APIC timer */
 549         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 550
 551         /* IPI vectors for APIC spurious and error interrupts */
 552         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 553         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 554
 555         /*
 556          * Set the clock to HZ Hz, we already have a valid
 557          * vector now:
 558          */
 559         setup_timer_hardware();
 560
 561         if (!acpi_ioapic)
 562                 setup_irq(2, &irq2);
 563 }