2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
39 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
53 struct drm_i915_gem_pwrite
*args
,
54 struct drm_file
*file_priv
);
55 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
57 static LIST_HEAD(shrink_list
);
58 static DEFINE_SPINLOCK(shrink_list_lock
);
61 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
63 return obj_priv
->gtt_space
&&
65 obj_priv
->pin_count
== 0;
68 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
71 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
74 (start
& (PAGE_SIZE
- 1)) != 0 ||
75 (end
& (PAGE_SIZE
- 1)) != 0) {
79 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
82 dev
->gtt_total
= (uint32_t) (end
- start
);
88 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
89 struct drm_file
*file_priv
)
91 struct drm_i915_gem_init
*args
= data
;
94 mutex_lock(&dev
->struct_mutex
);
95 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
96 mutex_unlock(&dev
->struct_mutex
);
102 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
103 struct drm_file
*file_priv
)
105 struct drm_i915_gem_get_aperture
*args
= data
;
107 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
110 args
->aper_size
= dev
->gtt_total
;
111 args
->aper_available_size
= (args
->aper_size
-
112 atomic_read(&dev
->pin_memory
));
119 * Creates a new mm object and returns a handle to it.
122 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
123 struct drm_file
*file_priv
)
125 struct drm_i915_gem_create
*args
= data
;
126 struct drm_gem_object
*obj
;
130 args
->size
= roundup(args
->size
, PAGE_SIZE
);
132 /* Allocate the new object */
133 obj
= i915_gem_alloc_object(dev
, args
->size
);
137 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
139 drm_gem_object_unreference_unlocked(obj
);
143 /* Sink the floating reference from kref_init(handlecount) */
144 drm_gem_object_handle_unreference_unlocked(obj
);
146 args
->handle
= handle
;
151 fast_shmem_read(struct page
**pages
,
152 loff_t page_base
, int page_offset
,
159 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
162 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
163 kunmap_atomic(vaddr
, KM_USER0
);
171 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
173 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
174 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
176 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
177 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
181 slow_shmem_copy(struct page
*dst_page
,
183 struct page
*src_page
,
187 char *dst_vaddr
, *src_vaddr
;
189 dst_vaddr
= kmap(dst_page
);
190 src_vaddr
= kmap(src_page
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
199 slow_shmem_bit17_copy(struct page
*gpu_page
,
201 struct page
*cpu_page
,
206 char *gpu_vaddr
, *cpu_vaddr
;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page
, cpu_offset
,
212 gpu_page
, gpu_offset
, length
);
214 return slow_shmem_copy(gpu_page
, gpu_offset
,
215 cpu_page
, cpu_offset
, length
);
218 gpu_vaddr
= kmap(gpu_page
);
219 cpu_vaddr
= kmap(cpu_page
);
221 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
222 * XORing with the other bits (A9 for Y, A9 and A10 for X)
225 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
226 int this_length
= min(cacheline_end
- gpu_offset
, length
);
227 int swizzled_gpu_offset
= gpu_offset
^ 64;
230 memcpy(cpu_vaddr
+ cpu_offset
,
231 gpu_vaddr
+ swizzled_gpu_offset
,
234 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
235 cpu_vaddr
+ cpu_offset
,
238 cpu_offset
+= this_length
;
239 gpu_offset
+= this_length
;
240 length
-= this_length
;
248 * This is the fast shmem pread path, which attempts to copy_from_user directly
249 * from the backing pages of the object to the user's address space. On a
250 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
253 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
254 struct drm_i915_gem_pread
*args
,
255 struct drm_file
*file_priv
)
257 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
259 loff_t offset
, page_base
;
260 char __user
*user_data
;
261 int page_offset
, page_length
;
264 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
267 mutex_lock(&dev
->struct_mutex
);
269 ret
= i915_gem_object_get_pages(obj
, 0);
273 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
278 obj_priv
= to_intel_bo(obj
);
279 offset
= args
->offset
;
282 /* Operation in this page
284 * page_base = page offset within aperture
285 * page_offset = offset within page
286 * page_length = bytes to copy for this page
288 page_base
= (offset
& ~(PAGE_SIZE
-1));
289 page_offset
= offset
& (PAGE_SIZE
-1);
290 page_length
= remain
;
291 if ((page_offset
+ remain
) > PAGE_SIZE
)
292 page_length
= PAGE_SIZE
- page_offset
;
294 ret
= fast_shmem_read(obj_priv
->pages
,
295 page_base
, page_offset
,
296 user_data
, page_length
);
300 remain
-= page_length
;
301 user_data
+= page_length
;
302 offset
+= page_length
;
306 i915_gem_object_put_pages(obj
);
308 mutex_unlock(&dev
->struct_mutex
);
314 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
318 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
320 /* If we've insufficient memory to map in the pages, attempt
321 * to make some space by throwing out some old buffers.
323 if (ret
== -ENOMEM
) {
324 struct drm_device
*dev
= obj
->dev
;
326 ret
= i915_gem_evict_something(dev
, obj
->size
,
327 i915_gem_get_gtt_alignment(obj
));
331 ret
= i915_gem_object_get_pages(obj
, 0);
338 * This is the fallback shmem pread path, which allocates temporary storage
339 * in kernel space to copy_to_user into outside of the struct_mutex, so we
340 * can copy out of the object's backing pages while holding the struct mutex
341 * and not take page faults.
344 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
345 struct drm_i915_gem_pread
*args
,
346 struct drm_file
*file_priv
)
348 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
349 struct mm_struct
*mm
= current
->mm
;
350 struct page
**user_pages
;
352 loff_t offset
, pinned_pages
, i
;
353 loff_t first_data_page
, last_data_page
, num_pages
;
354 int shmem_page_index
, shmem_page_offset
;
355 int data_page_index
, data_page_offset
;
358 uint64_t data_ptr
= args
->data_ptr
;
359 int do_bit17_swizzling
;
363 /* Pin the user pages containing the data. We can't fault while
364 * holding the struct mutex, yet we want to hold it while
365 * dereferencing the user data.
367 first_data_page
= data_ptr
/ PAGE_SIZE
;
368 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
369 num_pages
= last_data_page
- first_data_page
+ 1;
371 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
372 if (user_pages
== NULL
)
375 down_read(&mm
->mmap_sem
);
376 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
377 num_pages
, 1, 0, user_pages
, NULL
);
378 up_read(&mm
->mmap_sem
);
379 if (pinned_pages
< num_pages
) {
381 goto fail_put_user_pages
;
384 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
386 mutex_lock(&dev
->struct_mutex
);
388 ret
= i915_gem_object_get_pages_or_evict(obj
);
392 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
397 obj_priv
= to_intel_bo(obj
);
398 offset
= args
->offset
;
401 /* Operation in this page
403 * shmem_page_index = page number within shmem file
404 * shmem_page_offset = offset within page in shmem file
405 * data_page_index = page number in get_user_pages return
406 * data_page_offset = offset with data_page_index page.
407 * page_length = bytes to copy for this page
409 shmem_page_index
= offset
/ PAGE_SIZE
;
410 shmem_page_offset
= offset
& ~PAGE_MASK
;
411 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
412 data_page_offset
= data_ptr
& ~PAGE_MASK
;
414 page_length
= remain
;
415 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
416 page_length
= PAGE_SIZE
- shmem_page_offset
;
417 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
418 page_length
= PAGE_SIZE
- data_page_offset
;
420 if (do_bit17_swizzling
) {
421 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
423 user_pages
[data_page_index
],
428 slow_shmem_copy(user_pages
[data_page_index
],
430 obj_priv
->pages
[shmem_page_index
],
435 remain
-= page_length
;
436 data_ptr
+= page_length
;
437 offset
+= page_length
;
441 i915_gem_object_put_pages(obj
);
443 mutex_unlock(&dev
->struct_mutex
);
445 for (i
= 0; i
< pinned_pages
; i
++) {
446 SetPageDirty(user_pages
[i
]);
447 page_cache_release(user_pages
[i
]);
449 drm_free_large(user_pages
);
455 * Reads data from the object referenced by handle.
457 * On error, the contents of *data are undefined.
460 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
461 struct drm_file
*file_priv
)
463 struct drm_i915_gem_pread
*args
= data
;
464 struct drm_gem_object
*obj
;
465 struct drm_i915_gem_object
*obj_priv
;
468 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
471 obj_priv
= to_intel_bo(obj
);
473 /* Bounds check source.
475 * XXX: This could use review for overflow issues...
477 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
478 args
->offset
+ args
->size
> obj
->size
) {
479 drm_gem_object_unreference_unlocked(obj
);
483 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
484 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
486 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
488 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
492 drm_gem_object_unreference_unlocked(obj
);
497 /* This is the fast write path which cannot handle
498 * page faults in the source data
502 fast_user_write(struct io_mapping
*mapping
,
503 loff_t page_base
, int page_offset
,
504 char __user
*user_data
,
508 unsigned long unwritten
;
510 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
511 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
513 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
519 /* Here's the write path which can sleep for
524 slow_kernel_write(struct io_mapping
*mapping
,
525 loff_t gtt_base
, int gtt_offset
,
526 struct page
*user_page
, int user_offset
,
529 char __iomem
*dst_vaddr
;
532 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
533 src_vaddr
= kmap(user_page
);
535 memcpy_toio(dst_vaddr
+ gtt_offset
,
536 src_vaddr
+ user_offset
,
540 io_mapping_unmap(dst_vaddr
);
544 fast_shmem_write(struct page
**pages
,
545 loff_t page_base
, int page_offset
,
550 unsigned long unwritten
;
552 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
555 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
556 kunmap_atomic(vaddr
, KM_USER0
);
564 * This is the fast pwrite path, where we copy the data directly from the
565 * user into the GTT, uncached.
568 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
569 struct drm_i915_gem_pwrite
*args
,
570 struct drm_file
*file_priv
)
572 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
575 loff_t offset
, page_base
;
576 char __user
*user_data
;
577 int page_offset
, page_length
;
580 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
582 if (!access_ok(VERIFY_READ
, user_data
, remain
))
586 mutex_lock(&dev
->struct_mutex
);
587 ret
= i915_gem_object_pin(obj
, 0);
589 mutex_unlock(&dev
->struct_mutex
);
592 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
596 obj_priv
= to_intel_bo(obj
);
597 offset
= obj_priv
->gtt_offset
+ args
->offset
;
600 /* Operation in this page
602 * page_base = page offset within aperture
603 * page_offset = offset within page
604 * page_length = bytes to copy for this page
606 page_base
= (offset
& ~(PAGE_SIZE
-1));
607 page_offset
= offset
& (PAGE_SIZE
-1);
608 page_length
= remain
;
609 if ((page_offset
+ remain
) > PAGE_SIZE
)
610 page_length
= PAGE_SIZE
- page_offset
;
612 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
613 page_offset
, user_data
, page_length
);
615 /* If we get a fault while copying data, then (presumably) our
616 * source page isn't available. Return the error and we'll
617 * retry in the slow path.
622 remain
-= page_length
;
623 user_data
+= page_length
;
624 offset
+= page_length
;
628 i915_gem_object_unpin(obj
);
629 mutex_unlock(&dev
->struct_mutex
);
635 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
636 * the memory and maps it using kmap_atomic for copying.
638 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
639 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
642 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
643 struct drm_i915_gem_pwrite
*args
,
644 struct drm_file
*file_priv
)
646 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
647 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
649 loff_t gtt_page_base
, offset
;
650 loff_t first_data_page
, last_data_page
, num_pages
;
651 loff_t pinned_pages
, i
;
652 struct page
**user_pages
;
653 struct mm_struct
*mm
= current
->mm
;
654 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
656 uint64_t data_ptr
= args
->data_ptr
;
660 /* Pin the user pages containing the data. We can't fault while
661 * holding the struct mutex, and all of the pwrite implementations
662 * want to hold it while dereferencing the user data.
664 first_data_page
= data_ptr
/ PAGE_SIZE
;
665 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
666 num_pages
= last_data_page
- first_data_page
+ 1;
668 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
669 if (user_pages
== NULL
)
672 down_read(&mm
->mmap_sem
);
673 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
674 num_pages
, 0, 0, user_pages
, NULL
);
675 up_read(&mm
->mmap_sem
);
676 if (pinned_pages
< num_pages
) {
678 goto out_unpin_pages
;
681 mutex_lock(&dev
->struct_mutex
);
682 ret
= i915_gem_object_pin(obj
, 0);
686 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
688 goto out_unpin_object
;
690 obj_priv
= to_intel_bo(obj
);
691 offset
= obj_priv
->gtt_offset
+ args
->offset
;
694 /* Operation in this page
696 * gtt_page_base = page offset within aperture
697 * gtt_page_offset = offset within page in aperture
698 * data_page_index = page number in get_user_pages return
699 * data_page_offset = offset with data_page_index page.
700 * page_length = bytes to copy for this page
702 gtt_page_base
= offset
& PAGE_MASK
;
703 gtt_page_offset
= offset
& ~PAGE_MASK
;
704 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
705 data_page_offset
= data_ptr
& ~PAGE_MASK
;
707 page_length
= remain
;
708 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
709 page_length
= PAGE_SIZE
- gtt_page_offset
;
710 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
711 page_length
= PAGE_SIZE
- data_page_offset
;
713 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
714 gtt_page_base
, gtt_page_offset
,
715 user_pages
[data_page_index
],
719 remain
-= page_length
;
720 offset
+= page_length
;
721 data_ptr
+= page_length
;
725 i915_gem_object_unpin(obj
);
727 mutex_unlock(&dev
->struct_mutex
);
729 for (i
= 0; i
< pinned_pages
; i
++)
730 page_cache_release(user_pages
[i
]);
731 drm_free_large(user_pages
);
737 * This is the fast shmem pwrite path, which attempts to directly
738 * copy_from_user into the kmapped pages backing the object.
741 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
742 struct drm_i915_gem_pwrite
*args
,
743 struct drm_file
*file_priv
)
745 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
747 loff_t offset
, page_base
;
748 char __user
*user_data
;
749 int page_offset
, page_length
;
752 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
755 mutex_lock(&dev
->struct_mutex
);
757 ret
= i915_gem_object_get_pages(obj
, 0);
761 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
765 obj_priv
= to_intel_bo(obj
);
766 offset
= args
->offset
;
770 /* Operation in this page
772 * page_base = page offset within aperture
773 * page_offset = offset within page
774 * page_length = bytes to copy for this page
776 page_base
= (offset
& ~(PAGE_SIZE
-1));
777 page_offset
= offset
& (PAGE_SIZE
-1);
778 page_length
= remain
;
779 if ((page_offset
+ remain
) > PAGE_SIZE
)
780 page_length
= PAGE_SIZE
- page_offset
;
782 ret
= fast_shmem_write(obj_priv
->pages
,
783 page_base
, page_offset
,
784 user_data
, page_length
);
788 remain
-= page_length
;
789 user_data
+= page_length
;
790 offset
+= page_length
;
794 i915_gem_object_put_pages(obj
);
796 mutex_unlock(&dev
->struct_mutex
);
802 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
803 * the memory and maps it using kmap_atomic for copying.
805 * This avoids taking mmap_sem for faulting on the user's address while the
806 * struct_mutex is held.
809 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
810 struct drm_i915_gem_pwrite
*args
,
811 struct drm_file
*file_priv
)
813 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
814 struct mm_struct
*mm
= current
->mm
;
815 struct page
**user_pages
;
817 loff_t offset
, pinned_pages
, i
;
818 loff_t first_data_page
, last_data_page
, num_pages
;
819 int shmem_page_index
, shmem_page_offset
;
820 int data_page_index
, data_page_offset
;
823 uint64_t data_ptr
= args
->data_ptr
;
824 int do_bit17_swizzling
;
828 /* Pin the user pages containing the data. We can't fault while
829 * holding the struct mutex, and all of the pwrite implementations
830 * want to hold it while dereferencing the user data.
832 first_data_page
= data_ptr
/ PAGE_SIZE
;
833 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
834 num_pages
= last_data_page
- first_data_page
+ 1;
836 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
837 if (user_pages
== NULL
)
840 down_read(&mm
->mmap_sem
);
841 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
842 num_pages
, 0, 0, user_pages
, NULL
);
843 up_read(&mm
->mmap_sem
);
844 if (pinned_pages
< num_pages
) {
846 goto fail_put_user_pages
;
849 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
851 mutex_lock(&dev
->struct_mutex
);
853 ret
= i915_gem_object_get_pages_or_evict(obj
);
857 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
861 obj_priv
= to_intel_bo(obj
);
862 offset
= args
->offset
;
866 /* Operation in this page
868 * shmem_page_index = page number within shmem file
869 * shmem_page_offset = offset within page in shmem file
870 * data_page_index = page number in get_user_pages return
871 * data_page_offset = offset with data_page_index page.
872 * page_length = bytes to copy for this page
874 shmem_page_index
= offset
/ PAGE_SIZE
;
875 shmem_page_offset
= offset
& ~PAGE_MASK
;
876 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
877 data_page_offset
= data_ptr
& ~PAGE_MASK
;
879 page_length
= remain
;
880 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
881 page_length
= PAGE_SIZE
- shmem_page_offset
;
882 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
883 page_length
= PAGE_SIZE
- data_page_offset
;
885 if (do_bit17_swizzling
) {
886 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
888 user_pages
[data_page_index
],
893 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
895 user_pages
[data_page_index
],
900 remain
-= page_length
;
901 data_ptr
+= page_length
;
902 offset
+= page_length
;
906 i915_gem_object_put_pages(obj
);
908 mutex_unlock(&dev
->struct_mutex
);
910 for (i
= 0; i
< pinned_pages
; i
++)
911 page_cache_release(user_pages
[i
]);
912 drm_free_large(user_pages
);
918 * Writes data to the object referenced by handle.
920 * On error, the contents of the buffer that were to be modified are undefined.
923 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
924 struct drm_file
*file_priv
)
926 struct drm_i915_gem_pwrite
*args
= data
;
927 struct drm_gem_object
*obj
;
928 struct drm_i915_gem_object
*obj_priv
;
931 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
934 obj_priv
= to_intel_bo(obj
);
936 /* Bounds check destination.
938 * XXX: This could use review for overflow issues...
940 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
941 args
->offset
+ args
->size
> obj
->size
) {
942 drm_gem_object_unreference_unlocked(obj
);
946 /* We can only do the GTT pwrite on untiled buffers, as otherwise
947 * it would end up going through the fenced access, and we'll get
948 * different detiling behavior between reading and writing.
949 * pread/pwrite currently are reading and writing from the CPU
950 * perspective, requiring manual detiling by the client.
952 if (obj_priv
->phys_obj
)
953 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
954 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
955 dev
->gtt_total
!= 0 &&
956 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
957 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
958 if (ret
== -EFAULT
) {
959 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
962 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
963 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
965 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
966 if (ret
== -EFAULT
) {
967 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
974 DRM_INFO("pwrite failed %d\n", ret
);
977 drm_gem_object_unreference_unlocked(obj
);
983 * Called when user space prepares to use an object with the CPU, either
984 * through the mmap ioctl's mapping or a GTT mapping.
987 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
988 struct drm_file
*file_priv
)
990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
991 struct drm_i915_gem_set_domain
*args
= data
;
992 struct drm_gem_object
*obj
;
993 struct drm_i915_gem_object
*obj_priv
;
994 uint32_t read_domains
= args
->read_domains
;
995 uint32_t write_domain
= args
->write_domain
;
998 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1001 /* Only handle setting domains to types used by the CPU. */
1002 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1005 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1008 /* Having something in the write domain implies it's in the read
1009 * domain, and only that read domain. Enforce that in the request.
1011 if (write_domain
!= 0 && read_domains
!= write_domain
)
1014 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1017 obj_priv
= to_intel_bo(obj
);
1019 mutex_lock(&dev
->struct_mutex
);
1021 intel_mark_busy(dev
, obj
);
1024 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1025 obj
, obj
->size
, read_domains
, write_domain
);
1027 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1028 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1030 /* Update the LRU on the fence for the CPU access that's
1033 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1034 struct drm_i915_fence_reg
*reg
=
1035 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1036 list_move_tail(®
->lru_list
,
1037 &dev_priv
->mm
.fence_list
);
1040 /* Silently promote "you're not bound, there was nothing to do"
1041 * to success, since the client was just asking us to
1042 * make sure everything was done.
1047 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1051 /* Maintain LRU order of "inactive" objects */
1052 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1053 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1055 drm_gem_object_unreference(obj
);
1056 mutex_unlock(&dev
->struct_mutex
);
1061 * Called when user space has done writes to this buffer
1064 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1065 struct drm_file
*file_priv
)
1067 struct drm_i915_gem_sw_finish
*args
= data
;
1068 struct drm_gem_object
*obj
;
1069 struct drm_i915_gem_object
*obj_priv
;
1072 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1075 mutex_lock(&dev
->struct_mutex
);
1076 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1078 mutex_unlock(&dev
->struct_mutex
);
1083 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1084 __func__
, args
->handle
, obj
, obj
->size
);
1086 obj_priv
= to_intel_bo(obj
);
1088 /* Pinned buffers may be scanout, so flush the cache */
1089 if (obj_priv
->pin_count
)
1090 i915_gem_object_flush_cpu_write_domain(obj
);
1092 drm_gem_object_unreference(obj
);
1093 mutex_unlock(&dev
->struct_mutex
);
1098 * Maps the contents of an object, returning the address it is mapped
1101 * While the mapping holds a reference on the contents of the object, it doesn't
1102 * imply a ref on the object itself.
1105 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file_priv
)
1108 struct drm_i915_gem_mmap
*args
= data
;
1109 struct drm_gem_object
*obj
;
1113 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1116 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1120 offset
= args
->offset
;
1122 down_write(¤t
->mm
->mmap_sem
);
1123 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1124 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1126 up_write(¤t
->mm
->mmap_sem
);
1127 drm_gem_object_unreference_unlocked(obj
);
1128 if (IS_ERR((void *)addr
))
1131 args
->addr_ptr
= (uint64_t) addr
;
1137 * i915_gem_fault - fault a page into the GTT
1138 * vma: VMA in question
1141 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1142 * from userspace. The fault handler takes care of binding the object to
1143 * the GTT (if needed), allocating and programming a fence register (again,
1144 * only if needed based on whether the old reg is still valid or the object
1145 * is tiled) and inserting a new PTE into the faulting process.
1147 * Note that the faulting process may involve evicting existing objects
1148 * from the GTT and/or fence registers to make room. So performance may
1149 * suffer if the GTT working set is large or there are few fence registers
1152 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1154 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1155 struct drm_device
*dev
= obj
->dev
;
1156 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1157 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1158 pgoff_t page_offset
;
1161 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1163 /* We don't use vmf->pgoff since that has the fake offset */
1164 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1167 /* Now bind it into the GTT if needed */
1168 mutex_lock(&dev
->struct_mutex
);
1169 if (!obj_priv
->gtt_space
) {
1170 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1174 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1179 /* Need a new fence register? */
1180 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1181 ret
= i915_gem_object_get_fence_reg(obj
);
1186 if (i915_gem_object_is_inactive(obj_priv
))
1187 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1189 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1192 /* Finally, remap it using the new GTT offset */
1193 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1195 mutex_unlock(&dev
->struct_mutex
);
1200 return VM_FAULT_NOPAGE
;
1203 return VM_FAULT_OOM
;
1205 return VM_FAULT_SIGBUS
;
1210 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1211 * @obj: obj in question
1213 * GEM memory mapping works by handing back to userspace a fake mmap offset
1214 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1215 * up the object based on the offset and sets up the various memory mapping
1218 * This routine allocates and attaches a fake offset for @obj.
1221 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1223 struct drm_device
*dev
= obj
->dev
;
1224 struct drm_gem_mm
*mm
= dev
->mm_private
;
1225 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1226 struct drm_map_list
*list
;
1227 struct drm_local_map
*map
;
1230 /* Set the object up for mmap'ing */
1231 list
= &obj
->map_list
;
1232 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1237 map
->type
= _DRM_GEM
;
1238 map
->size
= obj
->size
;
1241 /* Get a DRM GEM mmap offset allocated... */
1242 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1243 obj
->size
/ PAGE_SIZE
, 0, 0);
1244 if (!list
->file_offset_node
) {
1245 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1250 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1251 obj
->size
/ PAGE_SIZE
, 0);
1252 if (!list
->file_offset_node
) {
1257 list
->hash
.key
= list
->file_offset_node
->start
;
1258 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1259 DRM_ERROR("failed to add to map hash\n");
1264 /* By now we should be all set, any drm_mmap request on the offset
1265 * below will get to our mmap & fault handler */
1266 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1271 drm_mm_put_block(list
->file_offset_node
);
1279 * i915_gem_release_mmap - remove physical page mappings
1280 * @obj: obj in question
1282 * Preserve the reservation of the mmapping with the DRM core code, but
1283 * relinquish ownership of the pages back to the system.
1285 * It is vital that we remove the page mapping if we have mapped a tiled
1286 * object through the GTT and then lose the fence register due to
1287 * resource pressure. Similarly if the object has been moved out of the
1288 * aperture, than pages mapped into userspace must be revoked. Removing the
1289 * mapping will then trigger a page fault on the next user access, allowing
1290 * fixup by i915_gem_fault().
1293 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1295 struct drm_device
*dev
= obj
->dev
;
1296 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1298 if (dev
->dev_mapping
)
1299 unmap_mapping_range(dev
->dev_mapping
,
1300 obj_priv
->mmap_offset
, obj
->size
, 1);
1304 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1306 struct drm_device
*dev
= obj
->dev
;
1307 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1308 struct drm_gem_mm
*mm
= dev
->mm_private
;
1309 struct drm_map_list
*list
;
1311 list
= &obj
->map_list
;
1312 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1314 if (list
->file_offset_node
) {
1315 drm_mm_put_block(list
->file_offset_node
);
1316 list
->file_offset_node
= NULL
;
1324 obj_priv
->mmap_offset
= 0;
1328 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1329 * @obj: object to check
1331 * Return the required GTT alignment for an object, taking into account
1332 * potential fence register mapping if needed.
1335 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1337 struct drm_device
*dev
= obj
->dev
;
1338 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1342 * Minimum alignment is 4k (GTT page size), but might be greater
1343 * if a fence register is needed for the object.
1345 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1349 * Previous chips need to be aligned to the size of the smallest
1350 * fence register that can contain the object.
1357 for (i
= start
; i
< obj
->size
; i
<<= 1)
1364 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1366 * @data: GTT mapping ioctl data
1367 * @file_priv: GEM object info
1369 * Simply returns the fake offset to userspace so it can mmap it.
1370 * The mmap call will end up in drm_gem_mmap(), which will set things
1371 * up so we can get faults in the handler above.
1373 * The fault handler will take care of binding the object into the GTT
1374 * (since it may have been evicted to make room for something), allocating
1375 * a fence register, and mapping the appropriate aperture address into
1379 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1380 struct drm_file
*file_priv
)
1382 struct drm_i915_gem_mmap_gtt
*args
= data
;
1383 struct drm_gem_object
*obj
;
1384 struct drm_i915_gem_object
*obj_priv
;
1387 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1390 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1394 mutex_lock(&dev
->struct_mutex
);
1396 obj_priv
= to_intel_bo(obj
);
1398 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1399 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1400 drm_gem_object_unreference(obj
);
1401 mutex_unlock(&dev
->struct_mutex
);
1406 if (!obj_priv
->mmap_offset
) {
1407 ret
= i915_gem_create_mmap_offset(obj
);
1409 drm_gem_object_unreference(obj
);
1410 mutex_unlock(&dev
->struct_mutex
);
1415 args
->offset
= obj_priv
->mmap_offset
;
1418 * Pull it into the GTT so that we have a page list (makes the
1419 * initial fault faster and any subsequent flushing possible).
1421 if (!obj_priv
->agp_mem
) {
1422 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1424 drm_gem_object_unreference(obj
);
1425 mutex_unlock(&dev
->struct_mutex
);
1430 drm_gem_object_unreference(obj
);
1431 mutex_unlock(&dev
->struct_mutex
);
1437 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1439 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1440 int page_count
= obj
->size
/ PAGE_SIZE
;
1443 BUG_ON(obj_priv
->pages_refcount
== 0);
1444 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1446 if (--obj_priv
->pages_refcount
!= 0)
1449 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1450 i915_gem_object_save_bit_17_swizzle(obj
);
1452 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1453 obj_priv
->dirty
= 0;
1455 for (i
= 0; i
< page_count
; i
++) {
1456 if (obj_priv
->dirty
)
1457 set_page_dirty(obj_priv
->pages
[i
]);
1459 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1460 mark_page_accessed(obj_priv
->pages
[i
]);
1462 page_cache_release(obj_priv
->pages
[i
]);
1464 obj_priv
->dirty
= 0;
1466 drm_free_large(obj_priv
->pages
);
1467 obj_priv
->pages
= NULL
;
1471 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1472 struct intel_ring_buffer
*ring
)
1474 struct drm_device
*dev
= obj
->dev
;
1475 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1476 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1477 BUG_ON(ring
== NULL
);
1478 obj_priv
->ring
= ring
;
1480 /* Add a reference if we're newly entering the active list. */
1481 if (!obj_priv
->active
) {
1482 drm_gem_object_reference(obj
);
1483 obj_priv
->active
= 1;
1485 /* Move from whatever list we were on to the tail of execution. */
1486 spin_lock(&dev_priv
->mm
.active_list_lock
);
1487 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1488 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1489 obj_priv
->last_rendering_seqno
= seqno
;
1493 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1495 struct drm_device
*dev
= obj
->dev
;
1496 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1497 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1499 BUG_ON(!obj_priv
->active
);
1500 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1501 obj_priv
->last_rendering_seqno
= 0;
1504 /* Immediately discard the backing storage */
1506 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1508 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1509 struct inode
*inode
;
1511 /* Our goal here is to return as much of the memory as
1512 * is possible back to the system as we are called from OOM.
1513 * To do this we must instruct the shmfs to drop all of its
1514 * backing pages, *now*. Here we mirror the actions taken
1515 * when by shmem_delete_inode() to release the backing store.
1517 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1518 truncate_inode_pages(inode
->i_mapping
, 0);
1519 if (inode
->i_op
->truncate_range
)
1520 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1522 obj_priv
->madv
= __I915_MADV_PURGED
;
1526 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1528 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1532 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1534 struct drm_device
*dev
= obj
->dev
;
1535 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1536 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1538 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1539 if (obj_priv
->pin_count
!= 0)
1540 list_del_init(&obj_priv
->list
);
1542 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1544 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1546 obj_priv
->last_rendering_seqno
= 0;
1547 obj_priv
->ring
= NULL
;
1548 if (obj_priv
->active
) {
1549 obj_priv
->active
= 0;
1550 drm_gem_object_unreference(obj
);
1552 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1556 i915_gem_process_flushing_list(struct drm_device
*dev
,
1557 uint32_t flush_domains
, uint32_t seqno
,
1558 struct intel_ring_buffer
*ring
)
1560 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1561 struct drm_i915_gem_object
*obj_priv
, *next
;
1563 list_for_each_entry_safe(obj_priv
, next
,
1564 &dev_priv
->mm
.gpu_write_list
,
1566 struct drm_gem_object
*obj
= &obj_priv
->base
;
1568 if ((obj
->write_domain
& flush_domains
) ==
1569 obj
->write_domain
&&
1570 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1571 uint32_t old_write_domain
= obj
->write_domain
;
1573 obj
->write_domain
= 0;
1574 list_del_init(&obj_priv
->gpu_write_list
);
1575 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1577 /* update the fence lru list */
1578 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1579 struct drm_i915_fence_reg
*reg
=
1580 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1581 list_move_tail(®
->lru_list
,
1582 &dev_priv
->mm
.fence_list
);
1585 trace_i915_gem_object_change_domain(obj
,
1593 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1594 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1596 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1597 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1598 struct drm_i915_gem_request
*request
;
1602 if (file_priv
!= NULL
)
1603 i915_file_priv
= file_priv
->driver_priv
;
1605 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1606 if (request
== NULL
)
1609 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1611 request
->seqno
= seqno
;
1612 request
->ring
= ring
;
1613 request
->emitted_jiffies
= jiffies
;
1614 was_empty
= list_empty(&ring
->request_list
);
1615 list_add_tail(&request
->list
, &ring
->request_list
);
1617 if (i915_file_priv
) {
1618 list_add_tail(&request
->client_list
,
1619 &i915_file_priv
->mm
.request_list
);
1621 INIT_LIST_HEAD(&request
->client_list
);
1624 /* Associate any objects on the flushing list matching the write
1625 * domain we're flushing with our flush.
1627 if (flush_domains
!= 0)
1628 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1630 if (!dev_priv
->mm
.suspended
) {
1631 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1633 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1639 * Command execution barrier
1641 * Ensures that all commands in the ring are finished
1642 * before signalling the CPU
1645 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1647 uint32_t flush_domains
= 0;
1649 /* The sampler always gets flushed on i965 (sigh) */
1651 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1653 ring
->flush(dev
, ring
,
1654 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1655 return flush_domains
;
1659 * Moves buffers associated only with the given active seqno from the active
1660 * to inactive list, potentially freeing them.
1663 i915_gem_retire_request(struct drm_device
*dev
,
1664 struct drm_i915_gem_request
*request
)
1666 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1668 trace_i915_gem_request_retire(dev
, request
->seqno
);
1670 /* Move any buffers on the active list that are no longer referenced
1671 * by the ringbuffer to the flushing/inactive lists as appropriate.
1673 spin_lock(&dev_priv
->mm
.active_list_lock
);
1674 while (!list_empty(&request
->ring
->active_list
)) {
1675 struct drm_gem_object
*obj
;
1676 struct drm_i915_gem_object
*obj_priv
;
1678 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1679 struct drm_i915_gem_object
,
1681 obj
= &obj_priv
->base
;
1683 /* If the seqno being retired doesn't match the oldest in the
1684 * list, then the oldest in the list must still be newer than
1687 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1691 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1692 __func__
, request
->seqno
, obj
);
1695 if (obj
->write_domain
!= 0)
1696 i915_gem_object_move_to_flushing(obj
);
1698 /* Take a reference on the object so it won't be
1699 * freed while the spinlock is held. The list
1700 * protection for this spinlock is safe when breaking
1701 * the lock like this since the next thing we do
1702 * is just get the head of the list again.
1704 drm_gem_object_reference(obj
);
1705 i915_gem_object_move_to_inactive(obj
);
1706 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1707 drm_gem_object_unreference(obj
);
1708 spin_lock(&dev_priv
->mm
.active_list_lock
);
1712 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1716 * Returns true if seq1 is later than seq2.
1719 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1721 return (int32_t)(seq1
- seq2
) >= 0;
1725 i915_get_gem_seqno(struct drm_device
*dev
,
1726 struct intel_ring_buffer
*ring
)
1728 return ring
->get_gem_seqno(dev
, ring
);
1732 * This function clears the request list as sequence numbers are passed.
1735 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1736 struct intel_ring_buffer
*ring
)
1738 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1741 if (!ring
->status_page
.page_addr
1742 || list_empty(&ring
->request_list
))
1745 seqno
= i915_get_gem_seqno(dev
, ring
);
1747 while (!list_empty(&ring
->request_list
)) {
1748 struct drm_i915_gem_request
*request
;
1749 uint32_t retiring_seqno
;
1751 request
= list_first_entry(&ring
->request_list
,
1752 struct drm_i915_gem_request
,
1754 retiring_seqno
= request
->seqno
;
1756 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1757 atomic_read(&dev_priv
->mm
.wedged
)) {
1758 i915_gem_retire_request(dev
, request
);
1760 list_del(&request
->list
);
1761 list_del(&request
->client_list
);
1767 if (unlikely (dev_priv
->trace_irq_seqno
&&
1768 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1770 ring
->user_irq_put(dev
, ring
);
1771 dev_priv
->trace_irq_seqno
= 0;
1776 i915_gem_retire_requests(struct drm_device
*dev
)
1778 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1780 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1781 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1783 /* We must be careful that during unbind() we do not
1784 * accidentally infinitely recurse into retire requests.
1786 * retire -> free -> unbind -> wait -> retire_ring
1788 list_for_each_entry_safe(obj_priv
, tmp
,
1789 &dev_priv
->mm
.deferred_free_list
,
1791 i915_gem_free_object_tail(&obj_priv
->base
);
1794 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1796 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1800 i915_gem_retire_work_handler(struct work_struct
*work
)
1802 drm_i915_private_t
*dev_priv
;
1803 struct drm_device
*dev
;
1805 dev_priv
= container_of(work
, drm_i915_private_t
,
1806 mm
.retire_work
.work
);
1807 dev
= dev_priv
->dev
;
1809 mutex_lock(&dev
->struct_mutex
);
1810 i915_gem_retire_requests(dev
);
1812 if (!dev_priv
->mm
.suspended
&&
1813 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1815 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1816 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1817 mutex_unlock(&dev
->struct_mutex
);
1821 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1822 int interruptible
, struct intel_ring_buffer
*ring
)
1824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1830 if (atomic_read(&dev_priv
->mm
.wedged
))
1833 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1834 if (HAS_PCH_SPLIT(dev
))
1835 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1837 ier
= I915_READ(IER
);
1839 DRM_ERROR("something (likely vbetool) disabled "
1840 "interrupts, re-enabling\n");
1841 i915_driver_irq_preinstall(dev
);
1842 i915_driver_irq_postinstall(dev
);
1845 trace_i915_gem_request_wait_begin(dev
, seqno
);
1847 ring
->waiting_gem_seqno
= seqno
;
1848 ring
->user_irq_get(dev
, ring
);
1850 ret
= wait_event_interruptible(ring
->irq_queue
,
1852 ring
->get_gem_seqno(dev
, ring
), seqno
)
1853 || atomic_read(&dev_priv
->mm
.wedged
));
1855 wait_event(ring
->irq_queue
,
1857 ring
->get_gem_seqno(dev
, ring
), seqno
)
1858 || atomic_read(&dev_priv
->mm
.wedged
));
1860 ring
->user_irq_put(dev
, ring
);
1861 ring
->waiting_gem_seqno
= 0;
1863 trace_i915_gem_request_wait_end(dev
, seqno
);
1865 if (atomic_read(&dev_priv
->mm
.wedged
))
1868 if (ret
&& ret
!= -ERESTARTSYS
)
1869 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1870 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1872 /* Directly dispatch request retiring. While we have the work queue
1873 * to handle this, the waiter on a request often wants an associated
1874 * buffer to have made it to the inactive list, and we would need
1875 * a separate wait queue to handle that.
1878 i915_gem_retire_requests_ring(dev
, ring
);
1884 * Waits for a sequence number to be signaled, and cleans up the
1885 * request and object lists appropriately for that event.
1888 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1889 struct intel_ring_buffer
*ring
)
1891 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1895 i915_gem_flush(struct drm_device
*dev
,
1896 uint32_t invalidate_domains
,
1897 uint32_t flush_domains
)
1899 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1900 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1901 drm_agp_chipset_flush(dev
);
1902 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1907 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1913 * Ensures that all rendering to the object has completed and the object is
1914 * safe to unbind from the GTT or access from the CPU.
1917 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1919 struct drm_device
*dev
= obj
->dev
;
1920 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1923 /* This function only exists to support waiting for existing rendering,
1924 * not for emitting required flushes.
1926 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1928 /* If there is rendering queued on the buffer being evicted, wait for
1931 if (obj_priv
->active
) {
1933 DRM_INFO("%s: object %p wait for seqno %08x\n",
1934 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1936 ret
= i915_wait_request(dev
,
1937 obj_priv
->last_rendering_seqno
, obj_priv
->ring
);
1946 * Unbinds an object from the GTT aperture.
1949 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1951 struct drm_device
*dev
= obj
->dev
;
1952 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1953 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1957 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1958 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1960 if (obj_priv
->gtt_space
== NULL
)
1963 if (obj_priv
->pin_count
!= 0) {
1964 DRM_ERROR("Attempting to unbind pinned buffer\n");
1968 /* blow away mappings if mapped through GTT */
1969 i915_gem_release_mmap(obj
);
1971 /* Move the object to the CPU domain to ensure that
1972 * any possible CPU writes while it's not in the GTT
1973 * are flushed when we go to remap it. This will
1974 * also ensure that all pending GPU writes are finished
1977 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1978 if (ret
== -ERESTARTSYS
)
1980 /* Continue on if we fail due to EIO, the GPU is hung so we
1981 * should be safe and we need to cleanup or else we might
1982 * cause memory corruption through use-after-free.
1985 /* release the fence reg _after_ flushing */
1986 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1987 i915_gem_clear_fence_reg(obj
);
1989 if (obj_priv
->agp_mem
!= NULL
) {
1990 drm_unbind_agp(obj_priv
->agp_mem
);
1991 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1992 obj_priv
->agp_mem
= NULL
;
1995 i915_gem_object_put_pages(obj
);
1996 BUG_ON(obj_priv
->pages_refcount
);
1998 if (obj_priv
->gtt_space
) {
1999 atomic_dec(&dev
->gtt_count
);
2000 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2002 drm_mm_put_block(obj_priv
->gtt_space
);
2003 obj_priv
->gtt_space
= NULL
;
2006 /* Remove ourselves from the LRU list if present. */
2007 spin_lock(&dev_priv
->mm
.active_list_lock
);
2008 if (!list_empty(&obj_priv
->list
))
2009 list_del_init(&obj_priv
->list
);
2010 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2012 if (i915_gem_object_is_purgeable(obj_priv
))
2013 i915_gem_object_truncate(obj
);
2015 trace_i915_gem_object_unbind(obj
);
2021 i915_gpu_idle(struct drm_device
*dev
)
2023 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2025 uint32_t seqno1
, seqno2
;
2028 spin_lock(&dev_priv
->mm
.active_list_lock
);
2029 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2030 list_empty(&dev_priv
->render_ring
.active_list
) &&
2032 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2033 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2038 /* Flush everything onto the inactive list. */
2039 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2040 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2041 &dev_priv
->render_ring
);
2044 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2047 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2048 &dev_priv
->bsd_ring
);
2052 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2062 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2065 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2067 struct address_space
*mapping
;
2068 struct inode
*inode
;
2071 BUG_ON(obj_priv
->pages_refcount
2072 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2074 if (obj_priv
->pages_refcount
++ != 0)
2077 /* Get the list of pages out of our struct file. They'll be pinned
2078 * at this point until we release them.
2080 page_count
= obj
->size
/ PAGE_SIZE
;
2081 BUG_ON(obj_priv
->pages
!= NULL
);
2082 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2083 if (obj_priv
->pages
== NULL
) {
2084 obj_priv
->pages_refcount
--;
2088 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2089 mapping
= inode
->i_mapping
;
2090 for (i
= 0; i
< page_count
; i
++) {
2091 page
= read_cache_page_gfp(mapping
, i
,
2099 obj_priv
->pages
[i
] = page
;
2102 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2103 i915_gem_object_do_bit_17_swizzle(obj
);
2109 page_cache_release(obj_priv
->pages
[i
]);
2111 drm_free_large(obj_priv
->pages
);
2112 obj_priv
->pages
= NULL
;
2113 obj_priv
->pages_refcount
--;
2114 return PTR_ERR(page
);
2117 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2119 struct drm_gem_object
*obj
= reg
->obj
;
2120 struct drm_device
*dev
= obj
->dev
;
2121 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2122 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2123 int regnum
= obj_priv
->fence_reg
;
2126 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2128 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2129 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2130 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2132 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2133 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2134 val
|= I965_FENCE_REG_VALID
;
2136 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2139 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2141 struct drm_gem_object
*obj
= reg
->obj
;
2142 struct drm_device
*dev
= obj
->dev
;
2143 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2144 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2145 int regnum
= obj_priv
->fence_reg
;
2148 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2150 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2151 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2152 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2153 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2154 val
|= I965_FENCE_REG_VALID
;
2156 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2159 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2161 struct drm_gem_object
*obj
= reg
->obj
;
2162 struct drm_device
*dev
= obj
->dev
;
2163 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2164 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2165 int regnum
= obj_priv
->fence_reg
;
2167 uint32_t fence_reg
, val
;
2170 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2171 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2172 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2173 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2177 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2178 HAS_128_BYTE_Y_TILING(dev
))
2183 /* Note: pitch better be a power of two tile widths */
2184 pitch_val
= obj_priv
->stride
/ tile_width
;
2185 pitch_val
= ffs(pitch_val
) - 1;
2187 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2188 HAS_128_BYTE_Y_TILING(dev
))
2189 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2191 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2193 val
= obj_priv
->gtt_offset
;
2194 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2195 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2196 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2197 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2198 val
|= I830_FENCE_REG_VALID
;
2201 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2203 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2204 I915_WRITE(fence_reg
, val
);
2207 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2209 struct drm_gem_object
*obj
= reg
->obj
;
2210 struct drm_device
*dev
= obj
->dev
;
2211 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2212 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2213 int regnum
= obj_priv
->fence_reg
;
2216 uint32_t fence_size_bits
;
2218 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2219 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2220 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2221 __func__
, obj_priv
->gtt_offset
);
2225 pitch_val
= obj_priv
->stride
/ 128;
2226 pitch_val
= ffs(pitch_val
) - 1;
2227 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2229 val
= obj_priv
->gtt_offset
;
2230 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2231 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2232 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2233 WARN_ON(fence_size_bits
& ~0x00000f00);
2234 val
|= fence_size_bits
;
2235 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2236 val
|= I830_FENCE_REG_VALID
;
2238 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2241 static int i915_find_fence_reg(struct drm_device
*dev
)
2243 struct drm_i915_fence_reg
*reg
= NULL
;
2244 struct drm_i915_gem_object
*obj_priv
= NULL
;
2245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2246 struct drm_gem_object
*obj
= NULL
;
2249 /* First try to find a free reg */
2251 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2252 reg
= &dev_priv
->fence_regs
[i
];
2256 obj_priv
= to_intel_bo(reg
->obj
);
2257 if (!obj_priv
->pin_count
)
2264 /* None available, try to steal one or wait for a user to finish */
2265 i
= I915_FENCE_REG_NONE
;
2266 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2269 obj_priv
= to_intel_bo(obj
);
2271 if (obj_priv
->pin_count
)
2275 i
= obj_priv
->fence_reg
;
2279 BUG_ON(i
== I915_FENCE_REG_NONE
);
2281 /* We only have a reference on obj from the active list. put_fence_reg
2282 * might drop that one, causing a use-after-free in it. So hold a
2283 * private reference to obj like the other callers of put_fence_reg
2284 * (set_tiling ioctl) do. */
2285 drm_gem_object_reference(obj
);
2286 ret
= i915_gem_object_put_fence_reg(obj
);
2287 drm_gem_object_unreference(obj
);
2295 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2296 * @obj: object to map through a fence reg
2298 * When mapping objects through the GTT, userspace wants to be able to write
2299 * to them without having to worry about swizzling if the object is tiled.
2301 * This function walks the fence regs looking for a free one for @obj,
2302 * stealing one if it can't find any.
2304 * It then sets up the reg based on the object's properties: address, pitch
2305 * and tiling format.
2308 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2310 struct drm_device
*dev
= obj
->dev
;
2311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2312 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2313 struct drm_i915_fence_reg
*reg
= NULL
;
2316 /* Just update our place in the LRU if our fence is getting used. */
2317 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2318 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2319 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2323 switch (obj_priv
->tiling_mode
) {
2324 case I915_TILING_NONE
:
2325 WARN(1, "allocating a fence for non-tiled object?\n");
2328 if (!obj_priv
->stride
)
2330 WARN((obj_priv
->stride
& (512 - 1)),
2331 "object 0x%08x is X tiled but has non-512B pitch\n",
2332 obj_priv
->gtt_offset
);
2335 if (!obj_priv
->stride
)
2337 WARN((obj_priv
->stride
& (128 - 1)),
2338 "object 0x%08x is Y tiled but has non-128B pitch\n",
2339 obj_priv
->gtt_offset
);
2343 ret
= i915_find_fence_reg(dev
);
2347 obj_priv
->fence_reg
= ret
;
2348 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2349 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2354 sandybridge_write_fence_reg(reg
);
2355 else if (IS_I965G(dev
))
2356 i965_write_fence_reg(reg
);
2357 else if (IS_I9XX(dev
))
2358 i915_write_fence_reg(reg
);
2360 i830_write_fence_reg(reg
);
2362 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2363 obj_priv
->tiling_mode
);
2369 * i915_gem_clear_fence_reg - clear out fence register info
2370 * @obj: object to clear
2372 * Zeroes out the fence register itself and clears out the associated
2373 * data structures in dev_priv and obj_priv.
2376 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2378 struct drm_device
*dev
= obj
->dev
;
2379 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2380 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2381 struct drm_i915_fence_reg
*reg
=
2382 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2385 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2386 (obj_priv
->fence_reg
* 8), 0);
2387 } else if (IS_I965G(dev
)) {
2388 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2392 if (obj_priv
->fence_reg
< 8)
2393 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2395 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2398 I915_WRITE(fence_reg
, 0);
2402 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2403 list_del_init(®
->lru_list
);
2407 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2408 * to the buffer to finish, and then resets the fence register.
2409 * @obj: tiled object holding a fence register.
2411 * Zeroes out the fence register itself and clears out the associated
2412 * data structures in dev_priv and obj_priv.
2415 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2417 struct drm_device
*dev
= obj
->dev
;
2418 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2420 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2423 /* If we've changed tiling, GTT-mappings of the object
2424 * need to re-fault to ensure that the correct fence register
2425 * setup is in place.
2427 i915_gem_release_mmap(obj
);
2429 /* On the i915, GPU access to tiled buffers is via a fence,
2430 * therefore we must wait for any outstanding access to complete
2431 * before clearing the fence.
2433 if (!IS_I965G(dev
)) {
2436 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2440 ret
= i915_gem_object_wait_rendering(obj
);
2445 i915_gem_object_flush_gtt_write_domain(obj
);
2446 i915_gem_clear_fence_reg (obj
);
2452 * Finds free space in the GTT aperture and binds the object there.
2455 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2457 struct drm_device
*dev
= obj
->dev
;
2458 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2459 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2460 struct drm_mm_node
*free_space
;
2461 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2464 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2465 DRM_ERROR("Attempting to bind a purgeable object\n");
2470 alignment
= i915_gem_get_gtt_alignment(obj
);
2471 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2472 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2476 /* If the object is bigger than the entire aperture, reject it early
2477 * before evicting everything in a vain attempt to find space.
2479 if (obj
->size
> dev
->gtt_total
) {
2480 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2485 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2486 obj
->size
, alignment
, 0);
2487 if (free_space
!= NULL
) {
2488 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2490 if (obj_priv
->gtt_space
!= NULL
)
2491 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2493 if (obj_priv
->gtt_space
== NULL
) {
2494 /* If the gtt is empty and we're still having trouble
2495 * fitting our object in, we're out of memory.
2498 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2500 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2508 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2509 obj
->size
, obj_priv
->gtt_offset
);
2511 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2513 drm_mm_put_block(obj_priv
->gtt_space
);
2514 obj_priv
->gtt_space
= NULL
;
2516 if (ret
== -ENOMEM
) {
2517 /* first try to clear up some space from the GTT */
2518 ret
= i915_gem_evict_something(dev
, obj
->size
,
2521 /* now try to shrink everyone else */
2536 /* Create an AGP memory structure pointing at our pages, and bind it
2539 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2541 obj
->size
>> PAGE_SHIFT
,
2542 obj_priv
->gtt_offset
,
2543 obj_priv
->agp_type
);
2544 if (obj_priv
->agp_mem
== NULL
) {
2545 i915_gem_object_put_pages(obj
);
2546 drm_mm_put_block(obj_priv
->gtt_space
);
2547 obj_priv
->gtt_space
= NULL
;
2549 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2555 atomic_inc(&dev
->gtt_count
);
2556 atomic_add(obj
->size
, &dev
->gtt_memory
);
2558 /* keep track of bounds object by adding it to the inactive list */
2559 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2561 /* Assert that the object is not currently in any GPU domain. As it
2562 * wasn't in the GTT, there shouldn't be any way it could have been in
2565 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2566 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2568 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2574 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2576 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2578 /* If we don't have a page list set up, then we're not pinned
2579 * to GPU, and we can ignore the cache flush because it'll happen
2580 * again at bind time.
2582 if (obj_priv
->pages
== NULL
)
2585 trace_i915_gem_object_clflush(obj
);
2587 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2590 /** Flushes any GPU write domain for the object if it's dirty. */
2592 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2594 struct drm_device
*dev
= obj
->dev
;
2595 uint32_t old_write_domain
;
2596 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2598 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2601 /* Queue the GPU write cache flushing we need. */
2602 old_write_domain
= obj
->write_domain
;
2603 i915_gem_flush(dev
, 0, obj
->write_domain
);
2604 if (i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
) == 0)
2607 trace_i915_gem_object_change_domain(obj
,
2613 /** Flushes the GTT write domain for the object if it's dirty. */
2615 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2617 uint32_t old_write_domain
;
2619 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2622 /* No actual flushing is required for the GTT write domain. Writes
2623 * to it immediately go to main memory as far as we know, so there's
2624 * no chipset flush. It also doesn't land in render cache.
2626 old_write_domain
= obj
->write_domain
;
2627 obj
->write_domain
= 0;
2629 trace_i915_gem_object_change_domain(obj
,
2634 /** Flushes the CPU write domain for the object if it's dirty. */
2636 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2638 struct drm_device
*dev
= obj
->dev
;
2639 uint32_t old_write_domain
;
2641 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2644 i915_gem_clflush_object(obj
);
2645 drm_agp_chipset_flush(dev
);
2646 old_write_domain
= obj
->write_domain
;
2647 obj
->write_domain
= 0;
2649 trace_i915_gem_object_change_domain(obj
,
2655 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2659 switch (obj
->write_domain
) {
2660 case I915_GEM_DOMAIN_GTT
:
2661 i915_gem_object_flush_gtt_write_domain(obj
);
2663 case I915_GEM_DOMAIN_CPU
:
2664 i915_gem_object_flush_cpu_write_domain(obj
);
2667 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2675 * Moves a single object to the GTT read, and possibly write domain.
2677 * This function returns when the move is complete, including waiting on
2681 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2683 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2684 uint32_t old_write_domain
, old_read_domains
;
2687 /* Not valid to be called on unbound objects. */
2688 if (obj_priv
->gtt_space
== NULL
)
2691 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2695 /* Wait on any GPU rendering and flushing to occur. */
2696 ret
= i915_gem_object_wait_rendering(obj
);
2700 old_write_domain
= obj
->write_domain
;
2701 old_read_domains
= obj
->read_domains
;
2703 /* If we're writing through the GTT domain, then CPU and GPU caches
2704 * will need to be invalidated at next use.
2707 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2709 i915_gem_object_flush_cpu_write_domain(obj
);
2711 /* It should now be out of any other write domains, and we can update
2712 * the domain values for our changes.
2714 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2715 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2717 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2718 obj_priv
->dirty
= 1;
2721 trace_i915_gem_object_change_domain(obj
,
2729 * Prepare buffer for display plane. Use uninterruptible for possible flush
2730 * wait, as in modesetting process we're not supposed to be interrupted.
2733 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2735 struct drm_device
*dev
= obj
->dev
;
2736 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2737 uint32_t old_write_domain
, old_read_domains
;
2740 /* Not valid to be called on unbound objects. */
2741 if (obj_priv
->gtt_space
== NULL
)
2744 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2748 /* Wait on any GPU rendering and flushing to occur. */
2749 if (obj_priv
->active
) {
2751 DRM_INFO("%s: object %p wait for seqno %08x\n",
2752 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2754 ret
= i915_do_wait_request(dev
,
2755 obj_priv
->last_rendering_seqno
,
2762 i915_gem_object_flush_cpu_write_domain(obj
);
2764 old_write_domain
= obj
->write_domain
;
2765 old_read_domains
= obj
->read_domains
;
2767 /* It should now be out of any other write domains, and we can update
2768 * the domain values for our changes.
2770 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2771 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2772 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2773 obj_priv
->dirty
= 1;
2775 trace_i915_gem_object_change_domain(obj
,
2783 * Moves a single object to the CPU read, and possibly write domain.
2785 * This function returns when the move is complete, including waiting on
2789 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2791 uint32_t old_write_domain
, old_read_domains
;
2794 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2798 /* Wait on any GPU rendering and flushing to occur. */
2799 ret
= i915_gem_object_wait_rendering(obj
);
2803 i915_gem_object_flush_gtt_write_domain(obj
);
2805 /* If we have a partially-valid cache of the object in the CPU,
2806 * finish invalidating it and free the per-page flags.
2808 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2810 old_write_domain
= obj
->write_domain
;
2811 old_read_domains
= obj
->read_domains
;
2813 /* Flush the CPU cache if it's still invalid. */
2814 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2815 i915_gem_clflush_object(obj
);
2817 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2820 /* It should now be out of any other write domains, and we can update
2821 * the domain values for our changes.
2823 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2825 /* If we're writing through the CPU, then the GPU read domains will
2826 * need to be invalidated at next use.
2829 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2830 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2833 trace_i915_gem_object_change_domain(obj
,
2841 * Set the next domain for the specified object. This
2842 * may not actually perform the necessary flushing/invaliding though,
2843 * as that may want to be batched with other set_domain operations
2845 * This is (we hope) the only really tricky part of gem. The goal
2846 * is fairly simple -- track which caches hold bits of the object
2847 * and make sure they remain coherent. A few concrete examples may
2848 * help to explain how it works. For shorthand, we use the notation
2849 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2850 * a pair of read and write domain masks.
2852 * Case 1: the batch buffer
2858 * 5. Unmapped from GTT
2861 * Let's take these a step at a time
2864 * Pages allocated from the kernel may still have
2865 * cache contents, so we set them to (CPU, CPU) always.
2866 * 2. Written by CPU (using pwrite)
2867 * The pwrite function calls set_domain (CPU, CPU) and
2868 * this function does nothing (as nothing changes)
2870 * This function asserts that the object is not
2871 * currently in any GPU-based read or write domains
2873 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2874 * As write_domain is zero, this function adds in the
2875 * current read domains (CPU+COMMAND, 0).
2876 * flush_domains is set to CPU.
2877 * invalidate_domains is set to COMMAND
2878 * clflush is run to get data out of the CPU caches
2879 * then i915_dev_set_domain calls i915_gem_flush to
2880 * emit an MI_FLUSH and drm_agp_chipset_flush
2881 * 5. Unmapped from GTT
2882 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2883 * flush_domains and invalidate_domains end up both zero
2884 * so no flushing/invalidating happens
2888 * Case 2: The shared render buffer
2892 * 3. Read/written by GPU
2893 * 4. set_domain to (CPU,CPU)
2894 * 5. Read/written by CPU
2895 * 6. Read/written by GPU
2898 * Same as last example, (CPU, CPU)
2900 * Nothing changes (assertions find that it is not in the GPU)
2901 * 3. Read/written by GPU
2902 * execbuffer calls set_domain (RENDER, RENDER)
2903 * flush_domains gets CPU
2904 * invalidate_domains gets GPU
2906 * MI_FLUSH and drm_agp_chipset_flush
2907 * 4. set_domain (CPU, CPU)
2908 * flush_domains gets GPU
2909 * invalidate_domains gets CPU
2910 * wait_rendering (obj) to make sure all drawing is complete.
2911 * This will include an MI_FLUSH to get the data from GPU
2913 * clflush (obj) to invalidate the CPU cache
2914 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2915 * 5. Read/written by CPU
2916 * cache lines are loaded and dirtied
2917 * 6. Read written by GPU
2918 * Same as last GPU access
2920 * Case 3: The constant buffer
2925 * 4. Updated (written) by CPU again
2934 * flush_domains = CPU
2935 * invalidate_domains = RENDER
2938 * drm_agp_chipset_flush
2939 * 4. Updated (written) by CPU again
2941 * flush_domains = 0 (no previous write domain)
2942 * invalidate_domains = 0 (no new read domains)
2945 * flush_domains = CPU
2946 * invalidate_domains = RENDER
2949 * drm_agp_chipset_flush
2952 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2954 struct drm_device
*dev
= obj
->dev
;
2955 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2956 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2957 uint32_t invalidate_domains
= 0;
2958 uint32_t flush_domains
= 0;
2959 uint32_t old_read_domains
;
2961 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2962 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2964 intel_mark_busy(dev
, obj
);
2967 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2969 obj
->read_domains
, obj
->pending_read_domains
,
2970 obj
->write_domain
, obj
->pending_write_domain
);
2973 * If the object isn't moving to a new write domain,
2974 * let the object stay in multiple read domains
2976 if (obj
->pending_write_domain
== 0)
2977 obj
->pending_read_domains
|= obj
->read_domains
;
2979 obj_priv
->dirty
= 1;
2982 * Flush the current write domain if
2983 * the new read domains don't match. Invalidate
2984 * any read domains which differ from the old
2987 if (obj
->write_domain
&&
2988 obj
->write_domain
!= obj
->pending_read_domains
) {
2989 flush_domains
|= obj
->write_domain
;
2990 invalidate_domains
|=
2991 obj
->pending_read_domains
& ~obj
->write_domain
;
2994 * Invalidate any read caches which may have
2995 * stale data. That is, any new read domains.
2997 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2998 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3000 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3001 __func__
, flush_domains
, invalidate_domains
);
3003 i915_gem_clflush_object(obj
);
3006 old_read_domains
= obj
->read_domains
;
3008 /* The actual obj->write_domain will be updated with
3009 * pending_write_domain after we emit the accumulated flush for all
3010 * of our domain changes in execbuffers (which clears objects'
3011 * write_domains). So if we have a current write domain that we
3012 * aren't changing, set pending_write_domain to that.
3014 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3015 obj
->pending_write_domain
= obj
->write_domain
;
3016 obj
->read_domains
= obj
->pending_read_domains
;
3018 if (flush_domains
& I915_GEM_GPU_DOMAINS
) {
3019 if (obj_priv
->ring
== &dev_priv
->render_ring
)
3020 dev_priv
->flush_rings
|= FLUSH_RENDER_RING
;
3021 else if (obj_priv
->ring
== &dev_priv
->bsd_ring
)
3022 dev_priv
->flush_rings
|= FLUSH_BSD_RING
;
3025 dev
->invalidate_domains
|= invalidate_domains
;
3026 dev
->flush_domains
|= flush_domains
;
3028 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3030 obj
->read_domains
, obj
->write_domain
,
3031 dev
->invalidate_domains
, dev
->flush_domains
);
3034 trace_i915_gem_object_change_domain(obj
,
3040 * Moves the object from a partially CPU read to a full one.
3042 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3043 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3046 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3048 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3050 if (!obj_priv
->page_cpu_valid
)
3053 /* If we're partially in the CPU read domain, finish moving it in.
3055 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3058 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3059 if (obj_priv
->page_cpu_valid
[i
])
3061 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3065 /* Free the page_cpu_valid mappings which are now stale, whether
3066 * or not we've got I915_GEM_DOMAIN_CPU.
3068 kfree(obj_priv
->page_cpu_valid
);
3069 obj_priv
->page_cpu_valid
= NULL
;
3073 * Set the CPU read domain on a range of the object.
3075 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3076 * not entirely valid. The page_cpu_valid member of the object flags which
3077 * pages have been flushed, and will be respected by
3078 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3079 * of the whole object.
3081 * This function returns when the move is complete, including waiting on
3085 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3086 uint64_t offset
, uint64_t size
)
3088 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3089 uint32_t old_read_domains
;
3092 if (offset
== 0 && size
== obj
->size
)
3093 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3095 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3099 /* Wait on any GPU rendering and flushing to occur. */
3100 ret
= i915_gem_object_wait_rendering(obj
);
3103 i915_gem_object_flush_gtt_write_domain(obj
);
3105 /* If we're already fully in the CPU read domain, we're done. */
3106 if (obj_priv
->page_cpu_valid
== NULL
&&
3107 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3110 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3111 * newly adding I915_GEM_DOMAIN_CPU
3113 if (obj_priv
->page_cpu_valid
== NULL
) {
3114 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3116 if (obj_priv
->page_cpu_valid
== NULL
)
3118 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3119 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3121 /* Flush the cache on any pages that are still invalid from the CPU's
3124 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3126 if (obj_priv
->page_cpu_valid
[i
])
3129 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3131 obj_priv
->page_cpu_valid
[i
] = 1;
3134 /* It should now be out of any other write domains, and we can update
3135 * the domain values for our changes.
3137 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3139 old_read_domains
= obj
->read_domains
;
3140 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3142 trace_i915_gem_object_change_domain(obj
,
3150 * Pin an object to the GTT and evaluate the relocations landing in it.
3153 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3154 struct drm_file
*file_priv
,
3155 struct drm_i915_gem_exec_object2
*entry
,
3156 struct drm_i915_gem_relocation_entry
*relocs
)
3158 struct drm_device
*dev
= obj
->dev
;
3159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3160 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3162 void __iomem
*reloc_page
;
3165 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3166 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3168 /* Check fence reg constraints and rebind if necessary */
3170 !i915_gem_object_fence_offset_ok(obj
,
3171 obj_priv
->tiling_mode
)) {
3172 ret
= i915_gem_object_unbind(obj
);
3177 /* Choose the GTT offset for our buffer and put it there. */
3178 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3183 * Pre-965 chips need a fence register set up in order to
3184 * properly handle blits to/from tiled surfaces.
3187 ret
= i915_gem_object_get_fence_reg(obj
);
3189 i915_gem_object_unpin(obj
);
3194 entry
->offset
= obj_priv
->gtt_offset
;
3196 /* Apply the relocations, using the GTT aperture to avoid cache
3197 * flushing requirements.
3199 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3200 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3201 struct drm_gem_object
*target_obj
;
3202 struct drm_i915_gem_object
*target_obj_priv
;
3203 uint32_t reloc_val
, reloc_offset
;
3204 uint32_t __iomem
*reloc_entry
;
3206 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3207 reloc
->target_handle
);
3208 if (target_obj
== NULL
) {
3209 i915_gem_object_unpin(obj
);
3212 target_obj_priv
= to_intel_bo(target_obj
);
3215 DRM_INFO("%s: obj %p offset %08x target %d "
3216 "read %08x write %08x gtt %08x "
3217 "presumed %08x delta %08x\n",
3220 (int) reloc
->offset
,
3221 (int) reloc
->target_handle
,
3222 (int) reloc
->read_domains
,
3223 (int) reloc
->write_domain
,
3224 (int) target_obj_priv
->gtt_offset
,
3225 (int) reloc
->presumed_offset
,
3229 /* The target buffer should have appeared before us in the
3230 * exec_object list, so it should have a GTT space bound by now.
3232 if (target_obj_priv
->gtt_space
== NULL
) {
3233 DRM_ERROR("No GTT space found for object %d\n",
3234 reloc
->target_handle
);
3235 drm_gem_object_unreference(target_obj
);
3236 i915_gem_object_unpin(obj
);
3240 /* Validate that the target is in a valid r/w GPU domain */
3241 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3242 DRM_ERROR("reloc with multiple write domains: "
3243 "obj %p target %d offset %d "
3244 "read %08x write %08x",
3245 obj
, reloc
->target_handle
,
3246 (int) reloc
->offset
,
3247 reloc
->read_domains
,
3248 reloc
->write_domain
);
3251 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3252 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3253 DRM_ERROR("reloc with read/write CPU domains: "
3254 "obj %p target %d offset %d "
3255 "read %08x write %08x",
3256 obj
, reloc
->target_handle
,
3257 (int) reloc
->offset
,
3258 reloc
->read_domains
,
3259 reloc
->write_domain
);
3260 drm_gem_object_unreference(target_obj
);
3261 i915_gem_object_unpin(obj
);
3264 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3265 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3266 DRM_ERROR("Write domain conflict: "
3267 "obj %p target %d offset %d "
3268 "new %08x old %08x\n",
3269 obj
, reloc
->target_handle
,
3270 (int) reloc
->offset
,
3271 reloc
->write_domain
,
3272 target_obj
->pending_write_domain
);
3273 drm_gem_object_unreference(target_obj
);
3274 i915_gem_object_unpin(obj
);
3278 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3279 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3281 /* If the relocation already has the right value in it, no
3282 * more work needs to be done.
3284 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3285 drm_gem_object_unreference(target_obj
);
3289 /* Check that the relocation address is valid... */
3290 if (reloc
->offset
> obj
->size
- 4) {
3291 DRM_ERROR("Relocation beyond object bounds: "
3292 "obj %p target %d offset %d size %d.\n",
3293 obj
, reloc
->target_handle
,
3294 (int) reloc
->offset
, (int) obj
->size
);
3295 drm_gem_object_unreference(target_obj
);
3296 i915_gem_object_unpin(obj
);
3299 if (reloc
->offset
& 3) {
3300 DRM_ERROR("Relocation not 4-byte aligned: "
3301 "obj %p target %d offset %d.\n",
3302 obj
, reloc
->target_handle
,
3303 (int) reloc
->offset
);
3304 drm_gem_object_unreference(target_obj
);
3305 i915_gem_object_unpin(obj
);
3309 /* and points to somewhere within the target object. */
3310 if (reloc
->delta
>= target_obj
->size
) {
3311 DRM_ERROR("Relocation beyond target object bounds: "
3312 "obj %p target %d delta %d size %d.\n",
3313 obj
, reloc
->target_handle
,
3314 (int) reloc
->delta
, (int) target_obj
->size
);
3315 drm_gem_object_unreference(target_obj
);
3316 i915_gem_object_unpin(obj
);
3320 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3322 drm_gem_object_unreference(target_obj
);
3323 i915_gem_object_unpin(obj
);
3327 /* Map the page containing the relocation we're going to
3330 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3331 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3335 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3336 (reloc_offset
& (PAGE_SIZE
- 1)));
3337 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3340 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3341 obj
, (unsigned int) reloc
->offset
,
3342 readl(reloc_entry
), reloc_val
);
3344 writel(reloc_val
, reloc_entry
);
3345 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3347 /* The updated presumed offset for this entry will be
3348 * copied back out to the user.
3350 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3352 drm_gem_object_unreference(target_obj
);
3357 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3362 /* Throttle our rendering by waiting until the ring has completed our requests
3363 * emitted over 20 msec ago.
3365 * Note that if we were to use the current jiffies each time around the loop,
3366 * we wouldn't escape the function with any frames outstanding if the time to
3367 * render a frame was over 20ms.
3369 * This should get us reasonable parallelism between CPU and GPU but also
3370 * relatively low latency when blocking on a particular request to finish.
3373 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3375 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3377 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3379 mutex_lock(&dev
->struct_mutex
);
3380 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3381 struct drm_i915_gem_request
*request
;
3383 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3384 struct drm_i915_gem_request
,
3387 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3390 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3394 mutex_unlock(&dev
->struct_mutex
);
3400 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3401 uint32_t buffer_count
,
3402 struct drm_i915_gem_relocation_entry
**relocs
)
3404 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3408 for (i
= 0; i
< buffer_count
; i
++) {
3409 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3411 reloc_count
+= exec_list
[i
].relocation_count
;
3414 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3415 if (*relocs
== NULL
) {
3416 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3420 for (i
= 0; i
< buffer_count
; i
++) {
3421 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3423 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3425 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3427 exec_list
[i
].relocation_count
*
3430 drm_free_large(*relocs
);
3435 reloc_index
+= exec_list
[i
].relocation_count
;
3442 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3443 uint32_t buffer_count
,
3444 struct drm_i915_gem_relocation_entry
*relocs
)
3446 uint32_t reloc_count
= 0, i
;
3452 for (i
= 0; i
< buffer_count
; i
++) {
3453 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3456 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3458 unwritten
= copy_to_user(user_relocs
,
3459 &relocs
[reloc_count
],
3460 exec_list
[i
].relocation_count
*
3468 reloc_count
+= exec_list
[i
].relocation_count
;
3472 drm_free_large(relocs
);
3478 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3479 uint64_t exec_offset
)
3481 uint32_t exec_start
, exec_len
;
3483 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3484 exec_len
= (uint32_t) exec
->batch_len
;
3486 if ((exec_start
| exec_len
) & 0x7)
3496 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3497 struct drm_gem_object
**object_list
,
3500 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3501 struct drm_i915_gem_object
*obj_priv
;
3506 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3507 &wait
, TASK_INTERRUPTIBLE
);
3508 for (i
= 0; i
< count
; i
++) {
3509 obj_priv
= to_intel_bo(object_list
[i
]);
3510 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3516 if (!signal_pending(current
)) {
3517 mutex_unlock(&dev
->struct_mutex
);
3519 mutex_lock(&dev
->struct_mutex
);
3525 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3532 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3533 struct drm_file
*file_priv
,
3534 struct drm_i915_gem_execbuffer2
*args
,
3535 struct drm_i915_gem_exec_object2
*exec_list
)
3537 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3538 struct drm_gem_object
**object_list
= NULL
;
3539 struct drm_gem_object
*batch_obj
;
3540 struct drm_i915_gem_object
*obj_priv
;
3541 struct drm_clip_rect
*cliprects
= NULL
;
3542 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3543 int ret
= 0, ret2
, i
, pinned
= 0;
3544 uint64_t exec_offset
;
3545 uint32_t seqno
, flush_domains
, reloc_index
;
3546 int pin_tries
, flips
;
3548 struct intel_ring_buffer
*ring
= NULL
;
3551 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3552 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3554 if (args
->flags
& I915_EXEC_BSD
) {
3555 if (!HAS_BSD(dev
)) {
3556 DRM_ERROR("execbuf with wrong flag\n");
3559 ring
= &dev_priv
->bsd_ring
;
3561 ring
= &dev_priv
->render_ring
;
3564 if (args
->buffer_count
< 1) {
3565 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3568 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3569 if (object_list
== NULL
) {
3570 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3571 args
->buffer_count
);
3576 if (args
->num_cliprects
!= 0) {
3577 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3579 if (cliprects
== NULL
) {
3584 ret
= copy_from_user(cliprects
,
3585 (struct drm_clip_rect __user
*)
3586 (uintptr_t) args
->cliprects_ptr
,
3587 sizeof(*cliprects
) * args
->num_cliprects
);
3589 DRM_ERROR("copy %d cliprects failed: %d\n",
3590 args
->num_cliprects
, ret
);
3596 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3601 mutex_lock(&dev
->struct_mutex
);
3603 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3605 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3606 mutex_unlock(&dev
->struct_mutex
);
3611 if (dev_priv
->mm
.suspended
) {
3612 mutex_unlock(&dev
->struct_mutex
);
3617 /* Look up object handles */
3619 for (i
= 0; i
< args
->buffer_count
; i
++) {
3620 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3621 exec_list
[i
].handle
);
3622 if (object_list
[i
] == NULL
) {
3623 DRM_ERROR("Invalid object handle %d at index %d\n",
3624 exec_list
[i
].handle
, i
);
3625 /* prevent error path from reading uninitialized data */
3626 args
->buffer_count
= i
+ 1;
3631 obj_priv
= to_intel_bo(object_list
[i
]);
3632 if (obj_priv
->in_execbuffer
) {
3633 DRM_ERROR("Object %p appears more than once in object list\n",
3635 /* prevent error path from reading uninitialized data */
3636 args
->buffer_count
= i
+ 1;
3640 obj_priv
->in_execbuffer
= true;
3641 flips
+= atomic_read(&obj_priv
->pending_flip
);
3645 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3646 args
->buffer_count
);
3651 /* Pin and relocate */
3652 for (pin_tries
= 0; ; pin_tries
++) {
3656 for (i
= 0; i
< args
->buffer_count
; i
++) {
3657 object_list
[i
]->pending_read_domains
= 0;
3658 object_list
[i
]->pending_write_domain
= 0;
3659 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3662 &relocs
[reloc_index
]);
3666 reloc_index
+= exec_list
[i
].relocation_count
;
3672 /* error other than GTT full, or we've already tried again */
3673 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3674 if (ret
!= -ERESTARTSYS
) {
3675 unsigned long long total_size
= 0;
3677 for (i
= 0; i
< args
->buffer_count
; i
++) {
3678 obj_priv
= to_intel_bo(object_list
[i
]);
3680 total_size
+= object_list
[i
]->size
;
3682 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3683 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3685 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3686 pinned
+1, args
->buffer_count
,
3687 total_size
, num_fences
,
3689 DRM_ERROR("%d objects [%d pinned], "
3690 "%d object bytes [%d pinned], "
3691 "%d/%d gtt bytes\n",
3692 atomic_read(&dev
->object_count
),
3693 atomic_read(&dev
->pin_count
),
3694 atomic_read(&dev
->object_memory
),
3695 atomic_read(&dev
->pin_memory
),
3696 atomic_read(&dev
->gtt_memory
),
3702 /* unpin all of our buffers */
3703 for (i
= 0; i
< pinned
; i
++)
3704 i915_gem_object_unpin(object_list
[i
]);
3707 /* evict everyone we can from the aperture */
3708 ret
= i915_gem_evict_everything(dev
);
3709 if (ret
&& ret
!= -ENOSPC
)
3713 /* Set the pending read domains for the batch buffer to COMMAND */
3714 batch_obj
= object_list
[args
->buffer_count
-1];
3715 if (batch_obj
->pending_write_domain
) {
3716 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3720 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3722 /* Sanity check the batch buffer, prior to moving objects */
3723 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3724 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3726 DRM_ERROR("execbuf with invalid offset/length\n");
3730 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3732 /* Zero the global flush/invalidate flags. These
3733 * will be modified as new domains are computed
3736 dev
->invalidate_domains
= 0;
3737 dev
->flush_domains
= 0;
3738 dev_priv
->flush_rings
= 0;
3740 for (i
= 0; i
< args
->buffer_count
; i
++) {
3741 struct drm_gem_object
*obj
= object_list
[i
];
3743 /* Compute new gpu domains and update invalidate/flush */
3744 i915_gem_object_set_to_gpu_domain(obj
);
3747 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3749 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3751 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3753 dev
->invalidate_domains
,
3754 dev
->flush_domains
);
3757 dev
->invalidate_domains
,
3758 dev
->flush_domains
);
3759 if (dev_priv
->flush_rings
& FLUSH_RENDER_RING
)
3760 (void)i915_add_request(dev
, file_priv
,
3762 &dev_priv
->render_ring
);
3763 if (dev_priv
->flush_rings
& FLUSH_BSD_RING
)
3764 (void)i915_add_request(dev
, file_priv
,
3766 &dev_priv
->bsd_ring
);
3769 for (i
= 0; i
< args
->buffer_count
; i
++) {
3770 struct drm_gem_object
*obj
= object_list
[i
];
3771 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3772 uint32_t old_write_domain
= obj
->write_domain
;
3774 obj
->write_domain
= obj
->pending_write_domain
;
3775 if (obj
->write_domain
)
3776 list_move_tail(&obj_priv
->gpu_write_list
,
3777 &dev_priv
->mm
.gpu_write_list
);
3779 list_del_init(&obj_priv
->gpu_write_list
);
3781 trace_i915_gem_object_change_domain(obj
,
3786 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3789 for (i
= 0; i
< args
->buffer_count
; i
++) {
3790 i915_gem_object_check_coherency(object_list
[i
],
3791 exec_list
[i
].handle
);
3796 i915_gem_dump_object(batch_obj
,
3802 /* Exec the batchbuffer */
3803 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3804 cliprects
, exec_offset
);
3806 DRM_ERROR("dispatch failed %d\n", ret
);
3811 * Ensure that the commands in the batch buffer are
3812 * finished before the interrupt fires
3814 flush_domains
= i915_retire_commands(dev
, ring
);
3816 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3819 * Get a seqno representing the execution of the current buffer,
3820 * which we can wait on. We would like to mitigate these interrupts,
3821 * likely by only creating seqnos occasionally (so that we have
3822 * *some* interrupts representing completion of buffers that we can
3823 * wait on when trying to clear up gtt space).
3825 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3827 for (i
= 0; i
< args
->buffer_count
; i
++) {
3828 struct drm_gem_object
*obj
= object_list
[i
];
3829 obj_priv
= to_intel_bo(obj
);
3831 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3833 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3837 i915_dump_lru(dev
, __func__
);
3840 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3843 for (i
= 0; i
< pinned
; i
++)
3844 i915_gem_object_unpin(object_list
[i
]);
3846 for (i
= 0; i
< args
->buffer_count
; i
++) {
3847 if (object_list
[i
]) {
3848 obj_priv
= to_intel_bo(object_list
[i
]);
3849 obj_priv
->in_execbuffer
= false;
3851 drm_gem_object_unreference(object_list
[i
]);
3854 mutex_unlock(&dev
->struct_mutex
);
3857 /* Copy the updated relocations out regardless of current error
3858 * state. Failure to update the relocs would mean that the next
3859 * time userland calls execbuf, it would do so with presumed offset
3860 * state that didn't match the actual object state.
3862 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3865 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3871 drm_free_large(object_list
);
3878 * Legacy execbuffer just creates an exec2 list from the original exec object
3879 * list array and passes it to the real function.
3882 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3883 struct drm_file
*file_priv
)
3885 struct drm_i915_gem_execbuffer
*args
= data
;
3886 struct drm_i915_gem_execbuffer2 exec2
;
3887 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3888 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3892 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3893 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3896 if (args
->buffer_count
< 1) {
3897 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3901 /* Copy in the exec list from userland */
3902 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3903 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3904 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3905 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3906 args
->buffer_count
);
3907 drm_free_large(exec_list
);
3908 drm_free_large(exec2_list
);
3911 ret
= copy_from_user(exec_list
,
3912 (struct drm_i915_relocation_entry __user
*)
3913 (uintptr_t) args
->buffers_ptr
,
3914 sizeof(*exec_list
) * args
->buffer_count
);
3916 DRM_ERROR("copy %d exec entries failed %d\n",
3917 args
->buffer_count
, ret
);
3918 drm_free_large(exec_list
);
3919 drm_free_large(exec2_list
);
3923 for (i
= 0; i
< args
->buffer_count
; i
++) {
3924 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3925 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3926 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3927 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3928 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3930 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3932 exec2_list
[i
].flags
= 0;
3935 exec2
.buffers_ptr
= args
->buffers_ptr
;
3936 exec2
.buffer_count
= args
->buffer_count
;
3937 exec2
.batch_start_offset
= args
->batch_start_offset
;
3938 exec2
.batch_len
= args
->batch_len
;
3939 exec2
.DR1
= args
->DR1
;
3940 exec2
.DR4
= args
->DR4
;
3941 exec2
.num_cliprects
= args
->num_cliprects
;
3942 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3943 exec2
.flags
= I915_EXEC_RENDER
;
3945 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3947 /* Copy the new buffer offsets back to the user's exec list. */
3948 for (i
= 0; i
< args
->buffer_count
; i
++)
3949 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3950 /* ... and back out to userspace */
3951 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3952 (uintptr_t) args
->buffers_ptr
,
3954 sizeof(*exec_list
) * args
->buffer_count
);
3957 DRM_ERROR("failed to copy %d exec entries "
3958 "back to user (%d)\n",
3959 args
->buffer_count
, ret
);
3963 drm_free_large(exec_list
);
3964 drm_free_large(exec2_list
);
3969 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3970 struct drm_file
*file_priv
)
3972 struct drm_i915_gem_execbuffer2
*args
= data
;
3973 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3977 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3978 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3981 if (args
->buffer_count
< 1) {
3982 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3986 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3987 if (exec2_list
== NULL
) {
3988 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3989 args
->buffer_count
);
3992 ret
= copy_from_user(exec2_list
,
3993 (struct drm_i915_relocation_entry __user
*)
3994 (uintptr_t) args
->buffers_ptr
,
3995 sizeof(*exec2_list
) * args
->buffer_count
);
3997 DRM_ERROR("copy %d exec entries failed %d\n",
3998 args
->buffer_count
, ret
);
3999 drm_free_large(exec2_list
);
4003 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4005 /* Copy the new buffer offsets back to the user's exec list. */
4006 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4007 (uintptr_t) args
->buffers_ptr
,
4009 sizeof(*exec2_list
) * args
->buffer_count
);
4012 DRM_ERROR("failed to copy %d exec entries "
4013 "back to user (%d)\n",
4014 args
->buffer_count
, ret
);
4018 drm_free_large(exec2_list
);
4023 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4025 struct drm_device
*dev
= obj
->dev
;
4026 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4029 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4031 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4033 if (obj_priv
->gtt_space
!= NULL
) {
4035 alignment
= i915_gem_get_gtt_alignment(obj
);
4036 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4037 WARN(obj_priv
->pin_count
,
4038 "bo is already pinned with incorrect alignment:"
4039 " offset=%x, req.alignment=%x\n",
4040 obj_priv
->gtt_offset
, alignment
);
4041 ret
= i915_gem_object_unbind(obj
);
4047 if (obj_priv
->gtt_space
== NULL
) {
4048 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4053 obj_priv
->pin_count
++;
4055 /* If the object is not active and not pending a flush,
4056 * remove it from the inactive list
4058 if (obj_priv
->pin_count
== 1) {
4059 atomic_inc(&dev
->pin_count
);
4060 atomic_add(obj
->size
, &dev
->pin_memory
);
4061 if (!obj_priv
->active
&&
4062 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4063 list_del_init(&obj_priv
->list
);
4065 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4071 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4073 struct drm_device
*dev
= obj
->dev
;
4074 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4075 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4077 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4078 obj_priv
->pin_count
--;
4079 BUG_ON(obj_priv
->pin_count
< 0);
4080 BUG_ON(obj_priv
->gtt_space
== NULL
);
4082 /* If the object is no longer pinned, and is
4083 * neither active nor being flushed, then stick it on
4086 if (obj_priv
->pin_count
== 0) {
4087 if (!obj_priv
->active
&&
4088 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4089 list_move_tail(&obj_priv
->list
,
4090 &dev_priv
->mm
.inactive_list
);
4091 atomic_dec(&dev
->pin_count
);
4092 atomic_sub(obj
->size
, &dev
->pin_memory
);
4094 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4098 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4099 struct drm_file
*file_priv
)
4101 struct drm_i915_gem_pin
*args
= data
;
4102 struct drm_gem_object
*obj
;
4103 struct drm_i915_gem_object
*obj_priv
;
4106 mutex_lock(&dev
->struct_mutex
);
4108 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4110 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4112 mutex_unlock(&dev
->struct_mutex
);
4115 obj_priv
= to_intel_bo(obj
);
4117 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4118 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4119 drm_gem_object_unreference(obj
);
4120 mutex_unlock(&dev
->struct_mutex
);
4124 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4125 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4127 drm_gem_object_unreference(obj
);
4128 mutex_unlock(&dev
->struct_mutex
);
4132 obj_priv
->user_pin_count
++;
4133 obj_priv
->pin_filp
= file_priv
;
4134 if (obj_priv
->user_pin_count
== 1) {
4135 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4137 drm_gem_object_unreference(obj
);
4138 mutex_unlock(&dev
->struct_mutex
);
4143 /* XXX - flush the CPU caches for pinned objects
4144 * as the X server doesn't manage domains yet
4146 i915_gem_object_flush_cpu_write_domain(obj
);
4147 args
->offset
= obj_priv
->gtt_offset
;
4148 drm_gem_object_unreference(obj
);
4149 mutex_unlock(&dev
->struct_mutex
);
4155 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4156 struct drm_file
*file_priv
)
4158 struct drm_i915_gem_pin
*args
= data
;
4159 struct drm_gem_object
*obj
;
4160 struct drm_i915_gem_object
*obj_priv
;
4162 mutex_lock(&dev
->struct_mutex
);
4164 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4166 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4168 mutex_unlock(&dev
->struct_mutex
);
4172 obj_priv
= to_intel_bo(obj
);
4173 if (obj_priv
->pin_filp
!= file_priv
) {
4174 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4176 drm_gem_object_unreference(obj
);
4177 mutex_unlock(&dev
->struct_mutex
);
4180 obj_priv
->user_pin_count
--;
4181 if (obj_priv
->user_pin_count
== 0) {
4182 obj_priv
->pin_filp
= NULL
;
4183 i915_gem_object_unpin(obj
);
4186 drm_gem_object_unreference(obj
);
4187 mutex_unlock(&dev
->struct_mutex
);
4192 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4193 struct drm_file
*file_priv
)
4195 struct drm_i915_gem_busy
*args
= data
;
4196 struct drm_gem_object
*obj
;
4197 struct drm_i915_gem_object
*obj_priv
;
4199 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4201 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4206 mutex_lock(&dev
->struct_mutex
);
4208 /* Count all active objects as busy, even if they are currently not used
4209 * by the gpu. Users of this interface expect objects to eventually
4210 * become non-busy without any further actions, therefore emit any
4211 * necessary flushes here.
4213 obj_priv
= to_intel_bo(obj
);
4214 args
->busy
= obj_priv
->active
;
4216 /* Unconditionally flush objects, even when the gpu still uses this
4217 * object. Userspace calling this function indicates that it wants to
4218 * use this buffer rather sooner than later, so issuing the required
4219 * flush earlier is beneficial.
4221 if (obj
->write_domain
) {
4222 i915_gem_flush(dev
, 0, obj
->write_domain
);
4223 (void)i915_add_request(dev
, file_priv
, obj
->write_domain
, obj_priv
->ring
);
4226 /* Update the active list for the hardware's current position.
4227 * Otherwise this only updates on a delayed timer or when irqs
4228 * are actually unmasked, and our working set ends up being
4229 * larger than required.
4231 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4233 args
->busy
= obj_priv
->active
;
4236 drm_gem_object_unreference(obj
);
4237 mutex_unlock(&dev
->struct_mutex
);
4242 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4243 struct drm_file
*file_priv
)
4245 return i915_gem_ring_throttle(dev
, file_priv
);
4249 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4250 struct drm_file
*file_priv
)
4252 struct drm_i915_gem_madvise
*args
= data
;
4253 struct drm_gem_object
*obj
;
4254 struct drm_i915_gem_object
*obj_priv
;
4256 switch (args
->madv
) {
4257 case I915_MADV_DONTNEED
:
4258 case I915_MADV_WILLNEED
:
4264 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4266 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4271 mutex_lock(&dev
->struct_mutex
);
4272 obj_priv
= to_intel_bo(obj
);
4274 if (obj_priv
->pin_count
) {
4275 drm_gem_object_unreference(obj
);
4276 mutex_unlock(&dev
->struct_mutex
);
4278 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4282 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4283 obj_priv
->madv
= args
->madv
;
4285 /* if the object is no longer bound, discard its backing storage */
4286 if (i915_gem_object_is_purgeable(obj_priv
) &&
4287 obj_priv
->gtt_space
== NULL
)
4288 i915_gem_object_truncate(obj
);
4290 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4292 drm_gem_object_unreference(obj
);
4293 mutex_unlock(&dev
->struct_mutex
);
4298 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4301 struct drm_i915_gem_object
*obj
;
4303 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4307 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4312 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4313 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4315 obj
->agp_type
= AGP_USER_MEMORY
;
4316 obj
->base
.driver_private
= NULL
;
4317 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4318 INIT_LIST_HEAD(&obj
->list
);
4319 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4320 obj
->madv
= I915_MADV_WILLNEED
;
4322 trace_i915_gem_object_create(&obj
->base
);
4327 int i915_gem_init_object(struct drm_gem_object
*obj
)
4334 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4336 struct drm_device
*dev
= obj
->dev
;
4337 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4338 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4341 ret
= i915_gem_object_unbind(obj
);
4342 if (ret
== -ERESTARTSYS
) {
4343 list_move(&obj_priv
->list
,
4344 &dev_priv
->mm
.deferred_free_list
);
4348 if (obj_priv
->mmap_offset
)
4349 i915_gem_free_mmap_offset(obj
);
4351 drm_gem_object_release(obj
);
4353 kfree(obj_priv
->page_cpu_valid
);
4354 kfree(obj_priv
->bit_17
);
4358 void i915_gem_free_object(struct drm_gem_object
*obj
)
4360 struct drm_device
*dev
= obj
->dev
;
4361 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4363 trace_i915_gem_object_destroy(obj
);
4365 while (obj_priv
->pin_count
> 0)
4366 i915_gem_object_unpin(obj
);
4368 if (obj_priv
->phys_obj
)
4369 i915_gem_detach_phys_object(dev
, obj
);
4371 i915_gem_free_object_tail(obj
);
4375 i915_gem_idle(struct drm_device
*dev
)
4377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4380 mutex_lock(&dev
->struct_mutex
);
4382 if (dev_priv
->mm
.suspended
||
4383 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4385 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4386 mutex_unlock(&dev
->struct_mutex
);
4390 ret
= i915_gpu_idle(dev
);
4392 mutex_unlock(&dev
->struct_mutex
);
4396 /* Under UMS, be paranoid and evict. */
4397 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4398 ret
= i915_gem_evict_inactive(dev
);
4400 mutex_unlock(&dev
->struct_mutex
);
4405 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4406 * We need to replace this with a semaphore, or something.
4407 * And not confound mm.suspended!
4409 dev_priv
->mm
.suspended
= 1;
4410 del_timer(&dev_priv
->hangcheck_timer
);
4412 i915_kernel_lost_context(dev
);
4413 i915_gem_cleanup_ringbuffer(dev
);
4415 mutex_unlock(&dev
->struct_mutex
);
4417 /* Cancel the retire work handler, which should be idle now. */
4418 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4424 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4425 * over cache flushing.
4428 i915_gem_init_pipe_control(struct drm_device
*dev
)
4430 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4431 struct drm_gem_object
*obj
;
4432 struct drm_i915_gem_object
*obj_priv
;
4435 obj
= i915_gem_alloc_object(dev
, 4096);
4437 DRM_ERROR("Failed to allocate seqno page\n");
4441 obj_priv
= to_intel_bo(obj
);
4442 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4444 ret
= i915_gem_object_pin(obj
, 4096);
4448 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4449 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4450 if (dev_priv
->seqno_page
== NULL
)
4453 dev_priv
->seqno_obj
= obj
;
4454 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4459 i915_gem_object_unpin(obj
);
4461 drm_gem_object_unreference(obj
);
4468 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4470 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4471 struct drm_gem_object
*obj
;
4472 struct drm_i915_gem_object
*obj_priv
;
4474 obj
= dev_priv
->seqno_obj
;
4475 obj_priv
= to_intel_bo(obj
);
4476 kunmap(obj_priv
->pages
[0]);
4477 i915_gem_object_unpin(obj
);
4478 drm_gem_object_unreference(obj
);
4479 dev_priv
->seqno_obj
= NULL
;
4481 dev_priv
->seqno_page
= NULL
;
4485 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4487 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4490 dev_priv
->render_ring
= render_ring
;
4492 if (!I915_NEED_GFX_HWS(dev
)) {
4493 dev_priv
->render_ring
.status_page
.page_addr
4494 = dev_priv
->status_page_dmah
->vaddr
;
4495 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4499 if (HAS_PIPE_CONTROL(dev
)) {
4500 ret
= i915_gem_init_pipe_control(dev
);
4505 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4507 goto cleanup_pipe_control
;
4510 dev_priv
->bsd_ring
= bsd_ring
;
4511 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4513 goto cleanup_render_ring
;
4516 dev_priv
->next_seqno
= 1;
4520 cleanup_render_ring
:
4521 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4522 cleanup_pipe_control
:
4523 if (HAS_PIPE_CONTROL(dev
))
4524 i915_gem_cleanup_pipe_control(dev
);
4529 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4531 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4533 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4535 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4536 if (HAS_PIPE_CONTROL(dev
))
4537 i915_gem_cleanup_pipe_control(dev
);
4541 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4542 struct drm_file
*file_priv
)
4544 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4547 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4550 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4551 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4552 atomic_set(&dev_priv
->mm
.wedged
, 0);
4555 mutex_lock(&dev
->struct_mutex
);
4556 dev_priv
->mm
.suspended
= 0;
4558 ret
= i915_gem_init_ringbuffer(dev
);
4560 mutex_unlock(&dev
->struct_mutex
);
4564 spin_lock(&dev_priv
->mm
.active_list_lock
);
4565 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4566 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4567 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4569 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4570 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4571 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4572 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4573 mutex_unlock(&dev
->struct_mutex
);
4575 ret
= drm_irq_install(dev
);
4577 goto cleanup_ringbuffer
;
4582 mutex_lock(&dev
->struct_mutex
);
4583 i915_gem_cleanup_ringbuffer(dev
);
4584 dev_priv
->mm
.suspended
= 1;
4585 mutex_unlock(&dev
->struct_mutex
);
4591 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4592 struct drm_file
*file_priv
)
4594 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4597 drm_irq_uninstall(dev
);
4598 return i915_gem_idle(dev
);
4602 i915_gem_lastclose(struct drm_device
*dev
)
4606 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4609 ret
= i915_gem_idle(dev
);
4611 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4615 i915_gem_load(struct drm_device
*dev
)
4618 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4620 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4621 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4622 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4623 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4624 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4625 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4626 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4627 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4629 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4630 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4632 for (i
= 0; i
< 16; i
++)
4633 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4634 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4635 i915_gem_retire_work_handler
);
4636 spin_lock(&shrink_list_lock
);
4637 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4638 spin_unlock(&shrink_list_lock
);
4640 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4642 u32 tmp
= I915_READ(MI_ARB_STATE
);
4643 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4644 /* arb state is a masked write, so set bit + bit in mask */
4645 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4646 I915_WRITE(MI_ARB_STATE
, tmp
);
4650 /* Old X drivers will take 0-2 for front, back, depth buffers */
4651 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4652 dev_priv
->fence_reg_start
= 3;
4654 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4655 dev_priv
->num_fence_regs
= 16;
4657 dev_priv
->num_fence_regs
= 8;
4659 /* Initialize fence registers to zero */
4660 if (IS_I965G(dev
)) {
4661 for (i
= 0; i
< 16; i
++)
4662 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4664 for (i
= 0; i
< 8; i
++)
4665 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4666 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4667 for (i
= 0; i
< 8; i
++)
4668 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4670 i915_gem_detect_bit_6_swizzle(dev
);
4671 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4675 * Create a physically contiguous memory object for this object
4676 * e.g. for cursor + overlay regs
4678 int i915_gem_init_phys_object(struct drm_device
*dev
,
4679 int id
, int size
, int align
)
4681 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4682 struct drm_i915_gem_phys_object
*phys_obj
;
4685 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4688 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4694 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4695 if (!phys_obj
->handle
) {
4700 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4703 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4711 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4713 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4714 struct drm_i915_gem_phys_object
*phys_obj
;
4716 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4719 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4720 if (phys_obj
->cur_obj
) {
4721 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4725 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4727 drm_pci_free(dev
, phys_obj
->handle
);
4729 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4732 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4736 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4737 i915_gem_free_phys_object(dev
, i
);
4740 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4741 struct drm_gem_object
*obj
)
4743 struct drm_i915_gem_object
*obj_priv
;
4748 obj_priv
= to_intel_bo(obj
);
4749 if (!obj_priv
->phys_obj
)
4752 ret
= i915_gem_object_get_pages(obj
, 0);
4756 page_count
= obj
->size
/ PAGE_SIZE
;
4758 for (i
= 0; i
< page_count
; i
++) {
4759 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4760 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4762 memcpy(dst
, src
, PAGE_SIZE
);
4763 kunmap_atomic(dst
, KM_USER0
);
4765 drm_clflush_pages(obj_priv
->pages
, page_count
);
4766 drm_agp_chipset_flush(dev
);
4768 i915_gem_object_put_pages(obj
);
4770 obj_priv
->phys_obj
->cur_obj
= NULL
;
4771 obj_priv
->phys_obj
= NULL
;
4775 i915_gem_attach_phys_object(struct drm_device
*dev
,
4776 struct drm_gem_object
*obj
,
4780 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4781 struct drm_i915_gem_object
*obj_priv
;
4786 if (id
> I915_MAX_PHYS_OBJECT
)
4789 obj_priv
= to_intel_bo(obj
);
4791 if (obj_priv
->phys_obj
) {
4792 if (obj_priv
->phys_obj
->id
== id
)
4794 i915_gem_detach_phys_object(dev
, obj
);
4797 /* create a new object */
4798 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4799 ret
= i915_gem_init_phys_object(dev
, id
,
4802 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4807 /* bind to the object */
4808 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4809 obj_priv
->phys_obj
->cur_obj
= obj
;
4811 ret
= i915_gem_object_get_pages(obj
, 0);
4813 DRM_ERROR("failed to get page list\n");
4817 page_count
= obj
->size
/ PAGE_SIZE
;
4819 for (i
= 0; i
< page_count
; i
++) {
4820 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4821 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4823 memcpy(dst
, src
, PAGE_SIZE
);
4824 kunmap_atomic(src
, KM_USER0
);
4827 i915_gem_object_put_pages(obj
);
4835 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4836 struct drm_i915_gem_pwrite
*args
,
4837 struct drm_file
*file_priv
)
4839 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4842 char __user
*user_data
;
4844 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4845 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4847 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4848 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4852 drm_agp_chipset_flush(dev
);
4856 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4858 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4860 /* Clean up our request list when the client is going away, so that
4861 * later retire_requests won't dereference our soon-to-be-gone
4864 mutex_lock(&dev
->struct_mutex
);
4865 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4866 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4867 mutex_unlock(&dev
->struct_mutex
);
4871 i915_gpu_is_active(struct drm_device
*dev
)
4873 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4876 spin_lock(&dev_priv
->mm
.active_list_lock
);
4877 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4878 list_empty(&dev_priv
->render_ring
.active_list
);
4880 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4881 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4883 return !lists_empty
;
4887 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4889 drm_i915_private_t
*dev_priv
, *next_dev
;
4890 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4892 int would_deadlock
= 1;
4894 /* "fast-path" to count number of available objects */
4895 if (nr_to_scan
== 0) {
4896 spin_lock(&shrink_list_lock
);
4897 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4898 struct drm_device
*dev
= dev_priv
->dev
;
4900 if (mutex_trylock(&dev
->struct_mutex
)) {
4901 list_for_each_entry(obj_priv
,
4902 &dev_priv
->mm
.inactive_list
,
4905 mutex_unlock(&dev
->struct_mutex
);
4908 spin_unlock(&shrink_list_lock
);
4910 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4913 spin_lock(&shrink_list_lock
);
4916 /* first scan for clean buffers */
4917 list_for_each_entry_safe(dev_priv
, next_dev
,
4918 &shrink_list
, mm
.shrink_list
) {
4919 struct drm_device
*dev
= dev_priv
->dev
;
4921 if (! mutex_trylock(&dev
->struct_mutex
))
4924 spin_unlock(&shrink_list_lock
);
4925 i915_gem_retire_requests(dev
);
4927 list_for_each_entry_safe(obj_priv
, next_obj
,
4928 &dev_priv
->mm
.inactive_list
,
4930 if (i915_gem_object_is_purgeable(obj_priv
)) {
4931 i915_gem_object_unbind(&obj_priv
->base
);
4932 if (--nr_to_scan
<= 0)
4937 spin_lock(&shrink_list_lock
);
4938 mutex_unlock(&dev
->struct_mutex
);
4942 if (nr_to_scan
<= 0)
4946 /* second pass, evict/count anything still on the inactive list */
4947 list_for_each_entry_safe(dev_priv
, next_dev
,
4948 &shrink_list
, mm
.shrink_list
) {
4949 struct drm_device
*dev
= dev_priv
->dev
;
4951 if (! mutex_trylock(&dev
->struct_mutex
))
4954 spin_unlock(&shrink_list_lock
);
4956 list_for_each_entry_safe(obj_priv
, next_obj
,
4957 &dev_priv
->mm
.inactive_list
,
4959 if (nr_to_scan
> 0) {
4960 i915_gem_object_unbind(&obj_priv
->base
);
4966 spin_lock(&shrink_list_lock
);
4967 mutex_unlock(&dev
->struct_mutex
);
4976 * We are desperate for pages, so as a last resort, wait
4977 * for the GPU to finish and discard whatever we can.
4978 * This has a dramatic impact to reduce the number of
4979 * OOM-killer events whilst running the GPU aggressively.
4981 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4982 struct drm_device
*dev
= dev_priv
->dev
;
4984 if (!mutex_trylock(&dev
->struct_mutex
))
4987 spin_unlock(&shrink_list_lock
);
4989 if (i915_gpu_is_active(dev
)) {
4994 spin_lock(&shrink_list_lock
);
4995 mutex_unlock(&dev
->struct_mutex
);
5002 spin_unlock(&shrink_list_lock
);
5007 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5012 static struct shrinker shrinker
= {
5013 .shrink
= i915_gem_shrink
,
5014 .seeks
= DEFAULT_SEEKS
,
5018 i915_gem_shrinker_init(void)
5020 register_shrinker(&shrinker
);
5024 i915_gem_shrinker_exit(void)
5026 unregister_shrinker(&shrinker
);