?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ASoC: Add WM8915 CODEC driver
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / codecs / wm8915.c
blob3adad2872c7e6b8841220ff25d302207dab6264d
1 /*
2 * wm8915.c - WM8915 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/delay.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <trace/events/asoc.h>
34
35 #include <sound/wm8915.h>
36 #include "wm8915.h"
37
38 #define WM8915_AIFS 2
39
40 #define HPOUT1L 1
41 #define HPOUT1R 2
42 #define HPOUT2L 4
43 #define HPOUT2R 8
44
45 #define WM8915_NUM_SUPPLIES 6
46 static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
47 "DCVDD",
48 "DBVDD",
49 "AVDD1",
50 "AVDD2",
51 "CPVDD",
52 "MICVDD",
53 };
54
55 struct wm8915_priv {
56 struct snd_soc_codec *codec;
57
58 int ldo1ena;
59
60 int sysclk;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
76
77 struct wm8915_pdata pdata;
78
79 int rx_rate[WM8915_AIFS];
80
81 /* Platform dependant ReTune mobile configuration */
82 int num_retune_mobile_texts;
83 const char **retune_mobile_texts;
84 int retune_mobile_cfg[2];
85 struct soc_enum retune_mobile_enum;
86
87 struct snd_soc_jack *jack;
88 bool detecting;
89 bool jack_mic;
90 wm8915_polarity_fn polarity_cb;
91
92 #ifdef CONFIG_GPIOLIB
93 struct gpio_chip gpio_chip;
94 #endif
95 };
96
97 /* We can't use the same notifier block for more than one supply and
98 * there's no way I can see to get from a callback to the caller
99 * except container_of().
100 */
101 #define WM8915_REGULATOR_EVENT(n) \
102 static int wm8915_regulator_event_##n(struct notifier_block *nb, \
103 unsigned long event, void *data) \
104 { \
105 struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
106 disable_nb[n]); \
107 if (event & REGULATOR_EVENT_DISABLE) { \
108 wm8915->codec->cache_sync = 1; \
109 } \
110 return 0; \
111 }
112
113 WM8915_REGULATOR_EVENT(0)
114 WM8915_REGULATOR_EVENT(1)
115 WM8915_REGULATOR_EVENT(2)
116 WM8915_REGULATOR_EVENT(3)
117 WM8915_REGULATOR_EVENT(4)
118 WM8915_REGULATOR_EVENT(5)
119
120 static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
121 [WM8915_SOFTWARE_RESET] = 0x8915,
122 [WM8915_POWER_MANAGEMENT_7] = 0x10,
123 [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
124 [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
125 [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
126 [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
127 [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
128 [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
129 [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
130 [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
131 [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
132 [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
133 [WM8915_MICBIAS_1] = 0x39,
134 [WM8915_MICBIAS_2] = 0x39,
135 [WM8915_LDO_1] = 0x3,
136 [WM8915_LDO_2] = 0x13,
137 [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
138 [WM8915_HEADPHONE_DETECT_1] = 0x20,
139 [WM8915_MIC_DETECT_1] = 0x7600,
140 [WM8915_MIC_DETECT_2] = 0xbf,
141 [WM8915_CHARGE_PUMP_1] = 0x1f25,
142 [WM8915_CHARGE_PUMP_2] = 0xab19,
143 [WM8915_DC_SERVO_5] = 0x2a2a,
144 [WM8915_CONTROL_INTERFACE_1] = 0x8004,
145 [WM8915_CLOCKING_1] = 0x10,
146 [WM8915_AIF_RATE] = 0x83,
147 [WM8915_FLL_CONTROL_4] = 0x5dc0,
148 [WM8915_FLL_CONTROL_5] = 0xc84,
149 [WM8915_FLL_EFS_2] = 0x2,
150 [WM8915_AIF1_TX_LRCLK_1] = 0x80,
151 [WM8915_AIF1_TX_LRCLK_2] = 0x8,
152 [WM8915_AIF1_RX_LRCLK_1] = 0x80,
153 [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
154 [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
155 [WM8915_AIF1TX_TEST] = 0x7,
156 [WM8915_AIF2_TX_LRCLK_1] = 0x80,
157 [WM8915_AIF2_TX_LRCLK_2] = 0x8,
158 [WM8915_AIF2_RX_LRCLK_1] = 0x80,
159 [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
160 [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
161 [WM8915_AIF2TX_TEST] = 0x1,
162 [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
163 [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
164 [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
165 [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
166 [WM8915_DSP1_TX_FILTERS] = 0x2000,
167 [WM8915_DSP1_RX_FILTERS_1] = 0x200,
168 [WM8915_DSP1_RX_FILTERS_2] = 0x10,
169 [WM8915_DSP1_DRC_1] = 0x98,
170 [WM8915_DSP1_DRC_2] = 0x845,
171 [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
172 [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
173 [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
174 [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
175 [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
176 [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
177 [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
178 [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
179 [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
180 [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
181 [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
182 [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
183 [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
184 [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
185 [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
186 [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
187 [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
188 [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
189 [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
190 [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
191 [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
192 [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
193 [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
194 [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
195 [WM8915_DSP2_TX_FILTERS] = 0x2000,
196 [WM8915_DSP2_RX_FILTERS_1] = 0x200,
197 [WM8915_DSP2_RX_FILTERS_2] = 0x10,
198 [WM8915_DSP2_DRC_1] = 0x98,
199 [WM8915_DSP2_DRC_2] = 0x845,
200 [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
201 [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
202 [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
203 [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
204 [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
205 [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
206 [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
207 [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
208 [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
209 [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
210 [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
211 [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
212 [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
213 [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
214 [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
215 [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
216 [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
217 [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
218 [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
219 [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
220 [WM8915_OVERSAMPLING] = 0xd,
221 [WM8915_SIDETONE] = 0x1040,
222 [WM8915_GPIO_1] = 0xa101,
223 [WM8915_GPIO_2] = 0xa101,
224 [WM8915_GPIO_3] = 0xa101,
225 [WM8915_GPIO_4] = 0xa101,
226 [WM8915_GPIO_5] = 0xa101,
227 [WM8915_PULL_CONTROL_2] = 0x140,
228 [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
229 [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
230 [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
231 [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
232 [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
233 [WM8915_WRITE_SEQUENCER_0] = 0x1,
234 [WM8915_WRITE_SEQUENCER_1] = 0x1,
235 [WM8915_WRITE_SEQUENCER_3] = 0x6,
236 [WM8915_WRITE_SEQUENCER_4] = 0x40,
237 [WM8915_WRITE_SEQUENCER_5] = 0x1,
238 [WM8915_WRITE_SEQUENCER_6] = 0xf,
239 [WM8915_WRITE_SEQUENCER_7] = 0x6,
240 [WM8915_WRITE_SEQUENCER_8] = 0x1,
241 [WM8915_WRITE_SEQUENCER_9] = 0x3,
242 [WM8915_WRITE_SEQUENCER_10] = 0x104,
243 [WM8915_WRITE_SEQUENCER_12] = 0x60,
244 [WM8915_WRITE_SEQUENCER_13] = 0x11,
245 [WM8915_WRITE_SEQUENCER_14] = 0x401,
246 [WM8915_WRITE_SEQUENCER_16] = 0x50,
247 [WM8915_WRITE_SEQUENCER_17] = 0x3,
248 [WM8915_WRITE_SEQUENCER_18] = 0x100,
249 [WM8915_WRITE_SEQUENCER_20] = 0x51,
250 [WM8915_WRITE_SEQUENCER_21] = 0x3,
251 [WM8915_WRITE_SEQUENCER_22] = 0x104,
252 [WM8915_WRITE_SEQUENCER_23] = 0xa,
253 [WM8915_WRITE_SEQUENCER_24] = 0x60,
254 [WM8915_WRITE_SEQUENCER_25] = 0x3b,
255 [WM8915_WRITE_SEQUENCER_26] = 0x502,
256 [WM8915_WRITE_SEQUENCER_27] = 0x100,
257 [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
258 [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
259 [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
260 [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
261 [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
262 [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
263 [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
264 [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
265 [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
266 [WM8915_WRITE_SEQUENCER_64] = 0x1,
267 [WM8915_WRITE_SEQUENCER_65] = 0x1,
268 [WM8915_WRITE_SEQUENCER_67] = 0x6,
269 [WM8915_WRITE_SEQUENCER_68] = 0x40,
270 [WM8915_WRITE_SEQUENCER_69] = 0x1,
271 [WM8915_WRITE_SEQUENCER_70] = 0xf,
272 [WM8915_WRITE_SEQUENCER_71] = 0x6,
273 [WM8915_WRITE_SEQUENCER_72] = 0x1,
274 [WM8915_WRITE_SEQUENCER_73] = 0x3,
275 [WM8915_WRITE_SEQUENCER_74] = 0x104,
276 [WM8915_WRITE_SEQUENCER_76] = 0x60,
277 [WM8915_WRITE_SEQUENCER_77] = 0x11,
278 [WM8915_WRITE_SEQUENCER_78] = 0x401,
279 [WM8915_WRITE_SEQUENCER_80] = 0x50,
280 [WM8915_WRITE_SEQUENCER_81] = 0x3,
281 [WM8915_WRITE_SEQUENCER_82] = 0x100,
282 [WM8915_WRITE_SEQUENCER_84] = 0x60,
283 [WM8915_WRITE_SEQUENCER_85] = 0x3b,
284 [WM8915_WRITE_SEQUENCER_86] = 0x502,
285 [WM8915_WRITE_SEQUENCER_87] = 0x100,
286 [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
287 [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
288 [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
289 [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
290 [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
291 [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
292 [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
293 [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
294 [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
295 [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
296 [WM8915_WRITE_SEQUENCER_128] = 0x1,
297 [WM8915_WRITE_SEQUENCER_129] = 0x1,
298 [WM8915_WRITE_SEQUENCER_131] = 0x6,
299 [WM8915_WRITE_SEQUENCER_132] = 0x40,
300 [WM8915_WRITE_SEQUENCER_133] = 0x1,
301 [WM8915_WRITE_SEQUENCER_134] = 0xf,
302 [WM8915_WRITE_SEQUENCER_135] = 0x6,
303 [WM8915_WRITE_SEQUENCER_136] = 0x1,
304 [WM8915_WRITE_SEQUENCER_137] = 0x3,
305 [WM8915_WRITE_SEQUENCER_138] = 0x106,
306 [WM8915_WRITE_SEQUENCER_140] = 0x61,
307 [WM8915_WRITE_SEQUENCER_141] = 0x11,
308 [WM8915_WRITE_SEQUENCER_142] = 0x401,
309 [WM8915_WRITE_SEQUENCER_144] = 0x50,
310 [WM8915_WRITE_SEQUENCER_145] = 0x3,
311 [WM8915_WRITE_SEQUENCER_146] = 0x102,
312 [WM8915_WRITE_SEQUENCER_148] = 0x51,
313 [WM8915_WRITE_SEQUENCER_149] = 0x3,
314 [WM8915_WRITE_SEQUENCER_150] = 0x106,
315 [WM8915_WRITE_SEQUENCER_151] = 0xa,
316 [WM8915_WRITE_SEQUENCER_152] = 0x61,
317 [WM8915_WRITE_SEQUENCER_153] = 0x3b,
318 [WM8915_WRITE_SEQUENCER_154] = 0x502,
319 [WM8915_WRITE_SEQUENCER_155] = 0x100,
320 [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
321 [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
322 [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
323 [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
324 [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
325 [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
326 [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
327 [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
328 [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
329 [WM8915_WRITE_SEQUENCER_192] = 0x1,
330 [WM8915_WRITE_SEQUENCER_193] = 0x1,
331 [WM8915_WRITE_SEQUENCER_195] = 0x6,
332 [WM8915_WRITE_SEQUENCER_196] = 0x40,
333 [WM8915_WRITE_SEQUENCER_197] = 0x1,
334 [WM8915_WRITE_SEQUENCER_198] = 0xf,
335 [WM8915_WRITE_SEQUENCER_199] = 0x6,
336 [WM8915_WRITE_SEQUENCER_200] = 0x1,
337 [WM8915_WRITE_SEQUENCER_201] = 0x3,
338 [WM8915_WRITE_SEQUENCER_202] = 0x106,
339 [WM8915_WRITE_SEQUENCER_204] = 0x61,
340 [WM8915_WRITE_SEQUENCER_205] = 0x11,
341 [WM8915_WRITE_SEQUENCER_206] = 0x401,
342 [WM8915_WRITE_SEQUENCER_208] = 0x50,
343 [WM8915_WRITE_SEQUENCER_209] = 0x3,
344 [WM8915_WRITE_SEQUENCER_210] = 0x102,
345 [WM8915_WRITE_SEQUENCER_212] = 0x61,
346 [WM8915_WRITE_SEQUENCER_213] = 0x3b,
347 [WM8915_WRITE_SEQUENCER_214] = 0x502,
348 [WM8915_WRITE_SEQUENCER_215] = 0x100,
349 [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
350 [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
351 [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
352 [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
353 [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
354 [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
355 [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
356 [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
357 [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
358 [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
359 [WM8915_WRITE_SEQUENCER_256] = 0x60,
360 [WM8915_WRITE_SEQUENCER_258] = 0x601,
361 [WM8915_WRITE_SEQUENCER_260] = 0x50,
362 [WM8915_WRITE_SEQUENCER_262] = 0x100,
363 [WM8915_WRITE_SEQUENCER_264] = 0x1,
364 [WM8915_WRITE_SEQUENCER_266] = 0x104,
365 [WM8915_WRITE_SEQUENCER_267] = 0x100,
366 [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
367 [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
368 [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
369 [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
370 [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
371 [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
372 [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
373 [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
374 [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
375 [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
376 [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
377 [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
378 [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
379 [WM8915_WRITE_SEQUENCER_320] = 0x61,
380 [WM8915_WRITE_SEQUENCER_322] = 0x601,
381 [WM8915_WRITE_SEQUENCER_324] = 0x50,
382 [WM8915_WRITE_SEQUENCER_326] = 0x102,
383 [WM8915_WRITE_SEQUENCER_328] = 0x1,
384 [WM8915_WRITE_SEQUENCER_330] = 0x106,
385 [WM8915_WRITE_SEQUENCER_331] = 0x100,
386 [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
387 [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
388 [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
389 [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
390 [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
391 [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
392 [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
393 [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
394 [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
395 [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
396 [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
397 [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
398 [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
399 [WM8915_WRITE_SEQUENCER_384] = 0x60,
400 [WM8915_WRITE_SEQUENCER_386] = 0x601,
401 [WM8915_WRITE_SEQUENCER_388] = 0x61,
402 [WM8915_WRITE_SEQUENCER_390] = 0x601,
403 [WM8915_WRITE_SEQUENCER_392] = 0x50,
404 [WM8915_WRITE_SEQUENCER_394] = 0x300,
405 [WM8915_WRITE_SEQUENCER_396] = 0x1,
406 [WM8915_WRITE_SEQUENCER_398] = 0x304,
407 [WM8915_WRITE_SEQUENCER_400] = 0x40,
408 [WM8915_WRITE_SEQUENCER_402] = 0xf,
409 [WM8915_WRITE_SEQUENCER_404] = 0x1,
410 [WM8915_WRITE_SEQUENCER_407] = 0x100,
411 };
412
413 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
414 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
415 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
416 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
417 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
418 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
419 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
420
421 static const char *sidetone_hpf_text[] = {
422 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
423 };
424
425 static const struct soc_enum sidetone_hpf =
426 SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
427
428 static const char *hpf_mode_text[] = {
429 "HiFi", "Custom", "Voice"
430 };
431
432 static const struct soc_enum dsp1tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
434
435 static const struct soc_enum dsp2tx_hpf_mode =
436 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
437
438 static const char *hpf_cutoff_text[] = {
439 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
440 };
441
442 static const struct soc_enum dsp1tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445 static const struct soc_enum dsp2tx_hpf_cutoff =
446 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
447
448 static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
449 {
450 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
451 struct wm8915_pdata *pdata = &wm8915->pdata;
452 int base, best, best_val, save, i, cfg, iface;
453
454 if (!wm8915->num_retune_mobile_texts)
455 return;
456
457 switch (block) {
458 case 0:
459 base = WM8915_DSP1_RX_EQ_GAINS_1;
460 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
461 WM8915_DSP1RX_SRC)
462 iface = 1;
463 else
464 iface = 0;
465 break;
466 case 1:
467 base = WM8915_DSP1_RX_EQ_GAINS_2;
468 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
469 WM8915_DSP2RX_SRC)
470 iface = 1;
471 else
472 iface = 0;
473 break;
474 default:
475 return;
476 }
477
478 /* Find the version of the currently selected configuration
479 * with the nearest sample rate. */
480 cfg = wm8915->retune_mobile_cfg[block];
481 best = 0;
482 best_val = INT_MAX;
483 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
484 if (strcmp(pdata->retune_mobile_cfgs[i].name,
485 wm8915->retune_mobile_texts[cfg]) == 0 &&
486 abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8915->rx_rate[iface]) < best_val) {
488 best = i;
489 best_val = abs(pdata->retune_mobile_cfgs[i].rate
490 - wm8915->rx_rate[iface]);
491 }
492 }
493
494 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
495 block,
496 pdata->retune_mobile_cfgs[best].name,
497 pdata->retune_mobile_cfgs[best].rate,
498 wm8915->rx_rate[iface]);
499
500 /* The EQ will be disabled while reconfiguring it, remember the
501 * current configuration.
502 */
503 save = snd_soc_read(codec, base);
504 save &= WM8915_DSP1RX_EQ_ENA;
505
506 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
507 snd_soc_update_bits(codec, base + i, 0xffff,
508 pdata->retune_mobile_cfgs[best].regs[i]);
509
510 snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
511 }
512
513 /* Icky as hell but saves code duplication */
514 static int wm8915_get_retune_mobile_block(const char *name)
515 {
516 if (strcmp(name, "DSP1 EQ Mode") == 0)
517 return 0;
518 if (strcmp(name, "DSP2 EQ Mode") == 0)
519 return 1;
520 return -EINVAL;
521 }
522
523 static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol)
525 {
526 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
527 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
528 struct wm8915_pdata *pdata = &wm8915->pdata;
529 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
530 int value = ucontrol->value.integer.value[0];
531
532 if (block < 0)
533 return block;
534
535 if (value >= pdata->num_retune_mobile_cfgs)
536 return -EINVAL;
537
538 wm8915->retune_mobile_cfg[block] = value;
539
540 wm8915_set_retune_mobile(codec, block);
541
542 return 0;
543 }
544
545 static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
546 struct snd_ctl_elem_value *ucontrol)
547 {
548 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
549 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
550 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
551
552 ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
553
554 return 0;
555 }
556
557 static const struct snd_kcontrol_new wm8915_snd_controls[] = {
558 SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
559 WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
560 SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
561 WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
562
563 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
564 0, 5, 24, 0, sidetone_tlv),
565 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
566 0, 5, 24, 0, sidetone_tlv),
567 SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
568 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
569 SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
570
571 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
572 WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
573 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
574 WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
575
576 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
577 13, 1, 0),
578 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
579 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
580 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
581
582 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
583 13, 1, 0),
584 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
585 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
586 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
587
588 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
589 WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
590 SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
591
592 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
593 WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
594 SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
595
596 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
597 WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
598 SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
599 WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
600
601 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
602 WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
603 SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
604 WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
605
606 SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
607 SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
608 SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
609 SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
610
611 SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
612 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
613
614 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
615 8, 0, out_digital_tlv),
616 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
617 8, 0, out_digital_tlv),
618
619 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
620 WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
621 SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME,
622 WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
623
624 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
625 WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
626 SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME,
627 WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
628
629 SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
630 spk_tlv),
631 SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
632 WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
633 SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
634 WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
635
636 SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
637 SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
638 };
639
640 static const struct snd_kcontrol_new wm8915_eq_controls[] = {
641 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
642 eq_tlv),
643 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
644 eq_tlv),
645 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
646 eq_tlv),
647 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
648 eq_tlv),
649 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
650 eq_tlv),
651
652 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
653 eq_tlv),
654 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
655 eq_tlv),
656 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
657 eq_tlv),
658 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
659 eq_tlv),
660 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
661 eq_tlv),
662 };
663
664 static int cp_event(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
666 {
667 switch (event) {
668 case SND_SOC_DAPM_POST_PMU:
669 msleep(5);
670 break;
671 default:
672 BUG();
673 return -EINVAL;
674 }
675
676 return 0;
677 }
678
679 static int rmv_short_event(struct snd_soc_dapm_widget *w,
680 struct snd_kcontrol *kcontrol, int event)
681 {
682 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
683
684 /* Record which outputs we enabled */
685 switch (event) {
686 case SND_SOC_DAPM_PRE_PMD:
687 wm8915->hpout_pending &= ~w->shift;
688 break;
689 case SND_SOC_DAPM_PRE_PMU:
690 wm8915->hpout_pending |= w->shift;
691 break;
692 default:
693 BUG();
694 return -EINVAL;
695 }
696
697 return 0;
698 }
699
700 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
701 {
702 struct i2c_client *i2c = to_i2c_client(codec->dev);
703 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
704 int i, ret;
705 unsigned long timeout = 200;
706
707 snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
708
709 /* Use the interrupt if possible */
710 do {
711 if (i2c->irq) {
712 timeout = wait_for_completion_timeout(&wm8915->dcs_done,
713 msecs_to_jiffies(200));
714 if (timeout == 0)
715 dev_err(codec->dev, "DC servo timed out\n");
716
717 } else {
718 msleep(1);
719 if (--i) {
720 timeout = 0;
721 break;
722 }
723 }
724
725 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
726 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
727 } while (ret & mask);
728
729 if (timeout == 0)
730 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
731 else
732 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
733 }
734
735 static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
736 enum snd_soc_dapm_type event, int subseq)
737 {
738 struct snd_soc_codec *codec = container_of(dapm,
739 struct snd_soc_codec, dapm);
740 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
741 u16 val, mask;
742
743 /* Complete any pending DC servo starts */
744 if (wm8915->dcs_pending) {
745 dev_dbg(codec->dev, "Starting DC servo for %x\n",
746 wm8915->dcs_pending);
747
748 /* Trigger a startup sequence */
749 wait_for_dc_servo(codec, wm8915->dcs_pending
750 << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
751
752 wm8915->dcs_pending = 0;
753 }
754
755 if (wm8915->hpout_pending != wm8915->hpout_ena) {
756 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
757 wm8915->hpout_ena, wm8915->hpout_pending);
758
759 val = 0;
760 mask = 0;
761 if (wm8915->hpout_pending & HPOUT1L) {
762 val |= WM8915_HPOUT1L_RMV_SHORT;
763 mask |= WM8915_HPOUT1L_RMV_SHORT;
764 } else {
765 mask |= WM8915_HPOUT1L_RMV_SHORT |
766 WM8915_HPOUT1L_OUTP |
767 WM8915_HPOUT1L_DLY;
768 }
769
770 if (wm8915->hpout_pending & HPOUT1R) {
771 val |= WM8915_HPOUT1R_RMV_SHORT;
772 mask |= WM8915_HPOUT1R_RMV_SHORT;
773 } else {
774 mask |= WM8915_HPOUT1R_RMV_SHORT |
775 WM8915_HPOUT1R_OUTP |
776 WM8915_HPOUT1R_DLY;
777 }
778
779 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
780
781 val = 0;
782 mask = 0;
783 if (wm8915->hpout_pending & HPOUT2L) {
784 val |= WM8915_HPOUT2L_RMV_SHORT;
785 mask |= WM8915_HPOUT2L_RMV_SHORT;
786 } else {
787 mask |= WM8915_HPOUT2L_RMV_SHORT |
788 WM8915_HPOUT2L_OUTP |
789 WM8915_HPOUT2L_DLY;
790 }
791
792 if (wm8915->hpout_pending & HPOUT2R) {
793 val |= WM8915_HPOUT2R_RMV_SHORT;
794 mask |= WM8915_HPOUT2R_RMV_SHORT;
795 } else {
796 mask |= WM8915_HPOUT2R_RMV_SHORT |
797 WM8915_HPOUT2R_OUTP |
798 WM8915_HPOUT2R_DLY;
799 }
800
801 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
802
803 wm8915->hpout_ena = wm8915->hpout_pending;
804 }
805 }
806
807 static int dcs_start(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809 {
810 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
811
812 switch (event) {
813 case SND_SOC_DAPM_POST_PMU:
814 wm8915->dcs_pending |= 1 << w->shift;
815 break;
816 default:
817 BUG();
818 return -EINVAL;
819 }
820
821 return 0;
822 }
823
824 static const char *sidetone_text[] = {
825 "IN1", "IN2",
826 };
827
828 static const struct soc_enum left_sidetone_enum =
829 SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
830
831 static const struct snd_kcontrol_new left_sidetone =
832 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
833
834 static const struct soc_enum right_sidetone_enum =
835 SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
836
837 static const struct snd_kcontrol_new right_sidetone =
838 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
839
840 static const char *spk_text[] = {
841 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
842 };
843
844 static const struct soc_enum spkl_enum =
845 SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
846
847 static const struct snd_kcontrol_new spkl_mux =
848 SOC_DAPM_ENUM("SPKL", spkl_enum);
849
850 static const struct soc_enum spkr_enum =
851 SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
852
853 static const struct snd_kcontrol_new spkr_mux =
854 SOC_DAPM_ENUM("SPKR", spkr_enum);
855
856 static const char *dsp1rx_text[] = {
857 "AIF1", "AIF2"
858 };
859
860 static const struct soc_enum dsp1rx_enum =
861 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
862
863 static const struct snd_kcontrol_new dsp1rx =
864 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
865
866 static const char *dsp2rx_text[] = {
867 "AIF2", "AIF1"
868 };
869
870 static const struct soc_enum dsp2rx_enum =
871 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
872
873 static const struct snd_kcontrol_new dsp2rx =
874 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
875
876 static const char *aif2tx_text[] = {
877 "DSP2", "DSP1", "AIF1"
878 };
879
880 static const struct soc_enum aif2tx_enum =
881 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
882
883 static const struct snd_kcontrol_new aif2tx =
884 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
885
886 static const char *inmux_text[] = {
887 "ADC", "DMIC1", "DMIC2"
888 };
889
890 static const struct soc_enum in1_enum =
891 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
892
893 static const struct snd_kcontrol_new in1_mux =
894 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
895
896 static const struct soc_enum in2_enum =
897 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
898
899 static const struct snd_kcontrol_new in2_mux =
900 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
901
902 static const struct snd_kcontrol_new dac2r_mix[] = {
903 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
904 5, 1, 0),
905 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
906 4, 1, 0),
907 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
908 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
909 };
910
911 static const struct snd_kcontrol_new dac2l_mix[] = {
912 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
913 5, 1, 0),
914 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
915 4, 1, 0),
916 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
917 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
918 };
919
920 static const struct snd_kcontrol_new dac1r_mix[] = {
921 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
922 5, 1, 0),
923 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
924 4, 1, 0),
925 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
926 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
927 };
928
929 static const struct snd_kcontrol_new dac1l_mix[] = {
930 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
931 5, 1, 0),
932 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
933 4, 1, 0),
934 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
935 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
936 };
937
938 static const struct snd_kcontrol_new dsp1txl[] = {
939 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
940 1, 1, 0),
941 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
942 0, 1, 0),
943 };
944
945 static const struct snd_kcontrol_new dsp1txr[] = {
946 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
947 1, 1, 0),
948 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
949 0, 1, 0),
950 };
951
952 static const struct snd_kcontrol_new dsp2txl[] = {
953 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
954 1, 1, 0),
955 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
956 0, 1, 0),
957 };
958
959 static const struct snd_kcontrol_new dsp2txr[] = {
960 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
961 1, 1, 0),
962 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
963 0, 1, 0),
964 };
965
966
967 static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
968 SND_SOC_DAPM_INPUT("IN1LN"),
969 SND_SOC_DAPM_INPUT("IN1LP"),
970 SND_SOC_DAPM_INPUT("IN1RN"),
971 SND_SOC_DAPM_INPUT("IN1RP"),
972
973 SND_SOC_DAPM_INPUT("IN2LN"),
974 SND_SOC_DAPM_INPUT("IN2LP"),
975 SND_SOC_DAPM_INPUT("IN2RN"),
976 SND_SOC_DAPM_INPUT("IN2RP"),
977
978 SND_SOC_DAPM_INPUT("DMIC1DAT"),
979 SND_SOC_DAPM_INPUT("DMIC2DAT"),
980
981 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
982 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
983 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
984 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
985 SND_SOC_DAPM_POST_PMU),
986
987 SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
988 SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
989 SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
990
991 SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
992 SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
993
994 SND_SOC_DAPM_PGA("ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
995
996 SND_SOC_DAPM_MUX("IN1 Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
997 SND_SOC_DAPM_MUX("IN2 Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
998
999 SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
1002 SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1003
1004 /* FIXME - these need to be concentrator widgets */
1005 SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1006 SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1007
1008 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1009 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1010 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1011 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1012
1013 SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1014 SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1015
1016 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1017 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1018
1019 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1020 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1021 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1022 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1023
1024 SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1025 dsp2txl, ARRAY_SIZE(dsp2txl)),
1026 SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1027 dsp2txr, ARRAY_SIZE(dsp2txr)),
1028 SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1029 dsp1txl, ARRAY_SIZE(dsp1txl)),
1030 SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1031 dsp1txr, ARRAY_SIZE(dsp1txr)),
1032
1033 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1034 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1035 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1036 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1037 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1038 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1039 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1040 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1041
1042 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1043 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1044 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1045 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1046
1047 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1048 WM8915_POWER_MANAGEMENT_4, 9, 0),
1049 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1050 WM8915_POWER_MANAGEMENT_4, 8, 0),
1051
1052 SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1053 WM8915_POWER_MANAGEMENT_6, 9, 0),
1054 SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1055 WM8915_POWER_MANAGEMENT_6, 8, 0),
1056
1057 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1058 WM8915_POWER_MANAGEMENT_4, 5, 0),
1059 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1060 WM8915_POWER_MANAGEMENT_4, 4, 0),
1061 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1062 WM8915_POWER_MANAGEMENT_4, 3, 0),
1063 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1064 WM8915_POWER_MANAGEMENT_4, 2, 0),
1065 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1066 WM8915_POWER_MANAGEMENT_4, 1, 0),
1067 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1068 WM8915_POWER_MANAGEMENT_4, 0, 0),
1069
1070 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1071 WM8915_POWER_MANAGEMENT_6, 5, 0),
1072 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1073 WM8915_POWER_MANAGEMENT_6, 4, 0),
1074 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1075 WM8915_POWER_MANAGEMENT_6, 3, 0),
1076 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1077 WM8915_POWER_MANAGEMENT_6, 2, 0),
1078 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1079 WM8915_POWER_MANAGEMENT_6, 1, 0),
1080 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1081 WM8915_POWER_MANAGEMENT_6, 0, 0),
1082
1083 /* We route as stereo pairs so define some dummy widgets to squash
1084 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1085 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1086 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1087 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1088 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1089 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1090
1091 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1092 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1093 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1094
1095 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1096 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1097 SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1098 SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1099
1100 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1101 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1102 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1103 SND_SOC_DAPM_POST_PMU),
1104 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1105 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1106 rmv_short_event,
1107 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1108
1109 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1110 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1111 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1112 SND_SOC_DAPM_POST_PMU),
1113 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1114 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1115 rmv_short_event,
1116 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1117
1118 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1119 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1120 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1121 SND_SOC_DAPM_POST_PMU),
1122 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1123 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1124 rmv_short_event,
1125 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1126
1127 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1128 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1129 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1130 SND_SOC_DAPM_POST_PMU),
1131 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1132 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1133 rmv_short_event,
1134 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1135
1136 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1137 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1138 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1139 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1140 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1141 };
1142
1143 static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1144 { "AIFCLK", NULL, "SYSCLK" },
1145 { "SYSDSPCLK", NULL, "SYSCLK" },
1146 { "Charge Pump", NULL, "SYSCLK" },
1147
1148 { "MICB1", NULL, "LDO2" },
1149 { "MICB2", NULL, "LDO2" },
1150
1151 { "IN1L PGA", NULL, "IN2LN" },
1152 { "IN1L PGA", NULL, "IN2LP" },
1153 { "IN1L PGA", NULL, "IN1LN" },
1154 { "IN1L PGA", NULL, "IN1LP" },
1155
1156 { "IN1R PGA", NULL, "IN2RN" },
1157 { "IN1R PGA", NULL, "IN2RP" },
1158 { "IN1R PGA", NULL, "IN1RN" },
1159 { "IN1R PGA", NULL, "IN1RP" },
1160
1161 { "ADCL", NULL, "IN1L PGA" },
1162
1163 { "ADCR", NULL, "IN1R PGA" },
1164
1165 { "DMIC1L", NULL, "DMIC1DAT" },
1166 { "DMIC1R", NULL, "DMIC1DAT" },
1167 { "DMIC2L", NULL, "DMIC2DAT" },
1168 { "DMIC2R", NULL, "DMIC2DAT" },
1169
1170 { "DMIC2L", NULL, "DMIC2" },
1171 { "DMIC2R", NULL, "DMIC2" },
1172 { "DMIC1L", NULL, "DMIC1" },
1173 { "DMIC1R", NULL, "DMIC1" },
1174
1175 { "ADC", NULL, "ADCL" },
1176 { "ADC", NULL, "ADCR" },
1177
1178 { "IN1 Mux", "ADC", "ADC" },
1179 { "IN1 Mux", "DMIC1", "DMIC1" },
1180 { "IN1 Mux", "DMIC2", "DMIC2" },
1181
1182 { "IN2 Mux", "ADC", "ADC" },
1183 { "IN2 Mux", "DMIC1", "DMIC1" },
1184 { "IN2 Mux", "DMIC2", "DMIC2" },
1185
1186 { "Left Sidetone", "IN1", "IN1 Mux" },
1187 { "Left Sidetone", "IN2", "IN2 Mux" },
1188
1189 { "Right Sidetone", "IN1", "IN1 Mux" },
1190 { "Right Sidetone", "IN2", "IN2 Mux" },
1191
1192 { "DSP1TXL", "IN1 Switch", "IN1 Mux" },
1193 { "DSP1TXR", "IN1 Switch", "IN1 Mux" },
1194
1195 { "DSP2TXL", "IN1 Switch", "IN2 Mux" },
1196 { "DSP2TXR", "IN1 Switch", "IN2 Mux" },
1197
1198 { "AIF1TX0", NULL, "DSP1TXL" },
1199 { "AIF1TX1", NULL, "DSP1TXR" },
1200 { "AIF1TX2", NULL, "DSP2TXL" },
1201 { "AIF1TX3", NULL, "DSP2TXR" },
1202 { "AIF1TX4", NULL, "AIF2RX0" },
1203 { "AIF1TX5", NULL, "AIF2RX1" },
1204
1205 { "AIF1RX0", NULL, "AIFCLK" },
1206 { "AIF1RX1", NULL, "AIFCLK" },
1207 { "AIF1RX2", NULL, "AIFCLK" },
1208 { "AIF1RX3", NULL, "AIFCLK" },
1209 { "AIF1RX4", NULL, "AIFCLK" },
1210 { "AIF1RX5", NULL, "AIFCLK" },
1211
1212 { "AIF2RX0", NULL, "AIFCLK" },
1213 { "AIF2RX1", NULL, "AIFCLK" },
1214
1215 { "DSP1RXL", NULL, "SYSDSPCLK" },
1216 { "DSP1RXR", NULL, "SYSDSPCLK" },
1217 { "DSP2RXL", NULL, "SYSDSPCLK" },
1218 { "DSP2RXR", NULL, "SYSDSPCLK" },
1219 { "DSP1TXL", NULL, "SYSDSPCLK" },
1220 { "DSP1TXR", NULL, "SYSDSPCLK" },
1221 { "DSP2TXL", NULL, "SYSDSPCLK" },
1222 { "DSP2TXR", NULL, "SYSDSPCLK" },
1223
1224 { "AIF1RXA", NULL, "AIF1RX0" },
1225 { "AIF1RXA", NULL, "AIF1RX1" },
1226 { "AIF1RXB", NULL, "AIF1RX2" },
1227 { "AIF1RXB", NULL, "AIF1RX3" },
1228 { "AIF1RXC", NULL, "AIF1RX4" },
1229 { "AIF1RXC", NULL, "AIF1RX5" },
1230
1231 { "AIF2RX", NULL, "AIF2RX0" },
1232 { "AIF2RX", NULL, "AIF2RX1" },
1233
1234 { "AIF2TX", "DSP2", "DSP2TX" },
1235 { "AIF2TX", "DSP1", "DSP1RX" },
1236 { "AIF2TX", "AIF1", "AIF1RXC" },
1237
1238 { "DSP1RXL", NULL, "DSP1RX" },
1239 { "DSP1RXR", NULL, "DSP1RX" },
1240 { "DSP2RXL", NULL, "DSP2RX" },
1241 { "DSP2RXR", NULL, "DSP2RX" },
1242
1243 { "DSP2TX", NULL, "DSP2TXL" },
1244 { "DSP2TX", NULL, "DSP2TXR" },
1245
1246 { "DSP1RX", "AIF1", "AIF1RXA" },
1247 { "DSP1RX", "AIF2", "AIF2RX" },
1248
1249 { "DSP2RX", "AIF1", "AIF1RXB" },
1250 { "DSP2RX", "AIF2", "AIF2RX" },
1251
1252 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1253 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1254 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1255 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1256
1257 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1258 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1259 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1260 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1261
1262 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1263 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1264 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1265 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1266
1267 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1268 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1269 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1270 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1271
1272 { "DAC1L", NULL, "DAC1L Mixer" },
1273 { "DAC1R", NULL, "DAC1R Mixer" },
1274 { "DAC2L", NULL, "DAC2L Mixer" },
1275 { "DAC2R", NULL, "DAC2R Mixer" },
1276
1277 { "HPOUT2L PGA", NULL, "Charge Pump" },
1278 { "HPOUT2L PGA", NULL, "DAC2L" },
1279 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1280 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1281 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1282 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1283
1284 { "HPOUT2R PGA", NULL, "Charge Pump" },
1285 { "HPOUT2R PGA", NULL, "DAC2R" },
1286 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1287 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1288 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1289 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1290
1291 { "HPOUT1L PGA", NULL, "Charge Pump" },
1292 { "HPOUT1L PGA", NULL, "DAC1L" },
1293 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1294 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1295 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1296 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1297
1298 { "HPOUT1R PGA", NULL, "Charge Pump" },
1299 { "HPOUT1R PGA", NULL, "DAC1R" },
1300 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1301 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1302 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1303 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1304
1305 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1306 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1307 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1308 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1309
1310 { "SPKL", "DAC1L", "DAC1L" },
1311 { "SPKL", "DAC1R", "DAC1R" },
1312 { "SPKL", "DAC2L", "DAC2L" },
1313 { "SPKL", "DAC2R", "DAC2R" },
1314
1315 { "SPKR", "DAC1L", "DAC1L" },
1316 { "SPKR", "DAC1R", "DAC1R" },
1317 { "SPKR", "DAC2L", "DAC2L" },
1318 { "SPKR", "DAC2R", "DAC2R" },
1319
1320 { "SPKL PGA", NULL, "SPKL" },
1321 { "SPKR PGA", NULL, "SPKR" },
1322
1323 { "SPKDAT", NULL, "SPKL PGA" },
1324 { "SPKDAT", NULL, "SPKR PGA" },
1325 };
1326
1327 static int wm8915_readable_register(struct snd_soc_codec *codec,
1328 unsigned int reg)
1329 {
1330 /* Due to the sparseness of the register map the compiler
1331 * output from an explicit switch statement ends up being much
1332 * more efficient than a table.
1333 */
1334 switch (reg) {
1335 case WM8915_SOFTWARE_RESET:
1336 case WM8915_POWER_MANAGEMENT_1:
1337 case WM8915_POWER_MANAGEMENT_2:
1338 case WM8915_POWER_MANAGEMENT_3:
1339 case WM8915_POWER_MANAGEMENT_4:
1340 case WM8915_POWER_MANAGEMENT_5:
1341 case WM8915_POWER_MANAGEMENT_6:
1342 case WM8915_POWER_MANAGEMENT_7:
1343 case WM8915_POWER_MANAGEMENT_8:
1344 case WM8915_LEFT_LINE_INPUT_VOLUME:
1345 case WM8915_RIGHT_LINE_INPUT_VOLUME:
1346 case WM8915_LINE_INPUT_CONTROL:
1347 case WM8915_DAC1_HPOUT1_VOLUME:
1348 case WM8915_DAC2_HPOUT2_VOLUME:
1349 case WM8915_DAC1_LEFT_VOLUME:
1350 case WM8915_DAC1_RIGHT_VOLUME:
1351 case WM8915_DAC2_LEFT_VOLUME:
1352 case WM8915_DAC2_RIGHT_VOLUME:
1353 case WM8915_OUTPUT1_LEFT_VOLUME:
1354 case WM8915_OUTPUT1_RIGHT_VOLUME:
1355 case WM8915_OUTPUT2_LEFT_VOLUME:
1356 case WM8915_OUTPUT2_RIGHT_VOLUME:
1357 case WM8915_MICBIAS_1:
1358 case WM8915_MICBIAS_2:
1359 case WM8915_LDO_1:
1360 case WM8915_LDO_2:
1361 case WM8915_ACCESSORY_DETECT_MODE_1:
1362 case WM8915_ACCESSORY_DETECT_MODE_2:
1363 case WM8915_HEADPHONE_DETECT_1:
1364 case WM8915_HEADPHONE_DETECT_2:
1365 case WM8915_MIC_DETECT_1:
1366 case WM8915_MIC_DETECT_2:
1367 case WM8915_MIC_DETECT_3:
1368 case WM8915_CHARGE_PUMP_1:
1369 case WM8915_CHARGE_PUMP_2:
1370 case WM8915_DC_SERVO_1:
1371 case WM8915_DC_SERVO_2:
1372 case WM8915_DC_SERVO_3:
1373 case WM8915_DC_SERVO_5:
1374 case WM8915_DC_SERVO_6:
1375 case WM8915_DC_SERVO_7:
1376 case WM8915_DC_SERVO_READBACK_0:
1377 case WM8915_ANALOGUE_HP_1:
1378 case WM8915_ANALOGUE_HP_2:
1379 case WM8915_CHIP_REVISION:
1380 case WM8915_CONTROL_INTERFACE_1:
1381 case WM8915_WRITE_SEQUENCER_CTRL_1:
1382 case WM8915_WRITE_SEQUENCER_CTRL_2:
1383 case WM8915_AIF_CLOCKING_1:
1384 case WM8915_AIF_CLOCKING_2:
1385 case WM8915_CLOCKING_1:
1386 case WM8915_CLOCKING_2:
1387 case WM8915_AIF_RATE:
1388 case WM8915_FLL_CONTROL_1:
1389 case WM8915_FLL_CONTROL_2:
1390 case WM8915_FLL_CONTROL_3:
1391 case WM8915_FLL_CONTROL_4:
1392 case WM8915_FLL_CONTROL_5:
1393 case WM8915_FLL_CONTROL_6:
1394 case WM8915_FLL_EFS_1:
1395 case WM8915_FLL_EFS_2:
1396 case WM8915_AIF1_CONTROL:
1397 case WM8915_AIF1_BCLK:
1398 case WM8915_AIF1_TX_LRCLK_1:
1399 case WM8915_AIF1_TX_LRCLK_2:
1400 case WM8915_AIF1_RX_LRCLK_1:
1401 case WM8915_AIF1_RX_LRCLK_2:
1402 case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1403 case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1404 case WM8915_AIF1RX_DATA_CONFIGURATION:
1405 case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1406 case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1407 case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1408 case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1409 case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1410 case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1411 case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1412 case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1413 case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1414 case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1415 case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1416 case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1417 case WM8915_AIF1RX_MONO_CONFIGURATION:
1418 case WM8915_AIF1TX_TEST:
1419 case WM8915_AIF2_CONTROL:
1420 case WM8915_AIF2_BCLK:
1421 case WM8915_AIF2_TX_LRCLK_1:
1422 case WM8915_AIF2_TX_LRCLK_2:
1423 case WM8915_AIF2_RX_LRCLK_1:
1424 case WM8915_AIF2_RX_LRCLK_2:
1425 case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1426 case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1427 case WM8915_AIF2RX_DATA_CONFIGURATION:
1428 case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1429 case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1430 case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1431 case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1432 case WM8915_AIF2RX_MONO_CONFIGURATION:
1433 case WM8915_AIF2TX_TEST:
1434 case WM8915_DSP1_TX_LEFT_VOLUME:
1435 case WM8915_DSP1_TX_RIGHT_VOLUME:
1436 case WM8915_DSP1_RX_LEFT_VOLUME:
1437 case WM8915_DSP1_RX_RIGHT_VOLUME:
1438 case WM8915_DSP1_TX_FILTERS:
1439 case WM8915_DSP1_RX_FILTERS_1:
1440 case WM8915_DSP1_RX_FILTERS_2:
1441 case WM8915_DSP1_DRC_1:
1442 case WM8915_DSP1_DRC_2:
1443 case WM8915_DSP1_DRC_3:
1444 case WM8915_DSP1_DRC_4:
1445 case WM8915_DSP1_DRC_5:
1446 case WM8915_DSP1_RX_EQ_GAINS_1:
1447 case WM8915_DSP1_RX_EQ_GAINS_2:
1448 case WM8915_DSP1_RX_EQ_BAND_1_A:
1449 case WM8915_DSP1_RX_EQ_BAND_1_B:
1450 case WM8915_DSP1_RX_EQ_BAND_1_PG:
1451 case WM8915_DSP1_RX_EQ_BAND_2_A:
1452 case WM8915_DSP1_RX_EQ_BAND_2_B:
1453 case WM8915_DSP1_RX_EQ_BAND_2_C:
1454 case WM8915_DSP1_RX_EQ_BAND_2_PG:
1455 case WM8915_DSP1_RX_EQ_BAND_3_A:
1456 case WM8915_DSP1_RX_EQ_BAND_3_B:
1457 case WM8915_DSP1_RX_EQ_BAND_3_C:
1458 case WM8915_DSP1_RX_EQ_BAND_3_PG:
1459 case WM8915_DSP1_RX_EQ_BAND_4_A:
1460 case WM8915_DSP1_RX_EQ_BAND_4_B:
1461 case WM8915_DSP1_RX_EQ_BAND_4_C:
1462 case WM8915_DSP1_RX_EQ_BAND_4_PG:
1463 case WM8915_DSP1_RX_EQ_BAND_5_A:
1464 case WM8915_DSP1_RX_EQ_BAND_5_B:
1465 case WM8915_DSP1_RX_EQ_BAND_5_PG:
1466 case WM8915_DSP2_TX_LEFT_VOLUME:
1467 case WM8915_DSP2_TX_RIGHT_VOLUME:
1468 case WM8915_DSP2_RX_LEFT_VOLUME:
1469 case WM8915_DSP2_RX_RIGHT_VOLUME:
1470 case WM8915_DSP2_TX_FILTERS:
1471 case WM8915_DSP2_RX_FILTERS_1:
1472 case WM8915_DSP2_RX_FILTERS_2:
1473 case WM8915_DSP2_DRC_1:
1474 case WM8915_DSP2_DRC_2:
1475 case WM8915_DSP2_DRC_3:
1476 case WM8915_DSP2_DRC_4:
1477 case WM8915_DSP2_DRC_5:
1478 case WM8915_DSP2_RX_EQ_GAINS_1:
1479 case WM8915_DSP2_RX_EQ_GAINS_2:
1480 case WM8915_DSP2_RX_EQ_BAND_1_A:
1481 case WM8915_DSP2_RX_EQ_BAND_1_B:
1482 case WM8915_DSP2_RX_EQ_BAND_1_PG:
1483 case WM8915_DSP2_RX_EQ_BAND_2_A:
1484 case WM8915_DSP2_RX_EQ_BAND_2_B:
1485 case WM8915_DSP2_RX_EQ_BAND_2_C:
1486 case WM8915_DSP2_RX_EQ_BAND_2_PG:
1487 case WM8915_DSP2_RX_EQ_BAND_3_A:
1488 case WM8915_DSP2_RX_EQ_BAND_3_B:
1489 case WM8915_DSP2_RX_EQ_BAND_3_C:
1490 case WM8915_DSP2_RX_EQ_BAND_3_PG:
1491 case WM8915_DSP2_RX_EQ_BAND_4_A:
1492 case WM8915_DSP2_RX_EQ_BAND_4_B:
1493 case WM8915_DSP2_RX_EQ_BAND_4_C:
1494 case WM8915_DSP2_RX_EQ_BAND_4_PG:
1495 case WM8915_DSP2_RX_EQ_BAND_5_A:
1496 case WM8915_DSP2_RX_EQ_BAND_5_B:
1497 case WM8915_DSP2_RX_EQ_BAND_5_PG:
1498 case WM8915_DAC1_MIXER_VOLUMES:
1499 case WM8915_DAC1_LEFT_MIXER_ROUTING:
1500 case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1501 case WM8915_DAC2_MIXER_VOLUMES:
1502 case WM8915_DAC2_LEFT_MIXER_ROUTING:
1503 case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1504 case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1505 case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1506 case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1507 case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1508 case WM8915_DSP_TX_MIXER_SELECT:
1509 case WM8915_DAC_SOFTMUTE:
1510 case WM8915_OVERSAMPLING:
1511 case WM8915_SIDETONE:
1512 case WM8915_GPIO_1:
1513 case WM8915_GPIO_2:
1514 case WM8915_GPIO_3:
1515 case WM8915_GPIO_4:
1516 case WM8915_GPIO_5:
1517 case WM8915_PULL_CONTROL_1:
1518 case WM8915_PULL_CONTROL_2:
1519 case WM8915_INTERRUPT_STATUS_1:
1520 case WM8915_INTERRUPT_STATUS_2:
1521 case WM8915_INTERRUPT_RAW_STATUS_2:
1522 case WM8915_INTERRUPT_STATUS_1_MASK:
1523 case WM8915_INTERRUPT_STATUS_2_MASK:
1524 case WM8915_INTERRUPT_CONTROL:
1525 case WM8915_LEFT_PDM_SPEAKER:
1526 case WM8915_RIGHT_PDM_SPEAKER:
1527 case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1528 case WM8915_PDM_SPEAKER_VOLUME:
1529 return 1;
1530 default:
1531 return 0;
1532 }
1533 }
1534
1535 static int wm8915_volatile_register(struct snd_soc_codec *codec,
1536 unsigned int reg)
1537 {
1538 switch (reg) {
1539 case WM8915_SOFTWARE_RESET:
1540 case WM8915_CHIP_REVISION:
1541 case WM8915_LDO_1:
1542 case WM8915_LDO_2:
1543 case WM8915_INTERRUPT_STATUS_1:
1544 case WM8915_INTERRUPT_STATUS_2:
1545 case WM8915_INTERRUPT_RAW_STATUS_2:
1546 case WM8915_DC_SERVO_READBACK_0:
1547 case WM8915_DC_SERVO_2:
1548 case WM8915_DC_SERVO_6:
1549 case WM8915_DC_SERVO_7:
1550 case WM8915_FLL_CONTROL_6:
1551 case WM8915_MIC_DETECT_3:
1552 case WM8915_HEADPHONE_DETECT_1:
1553 case WM8915_HEADPHONE_DETECT_2:
1554 return 1;
1555 default:
1556 return 0;
1557 }
1558 }
1559
1560 static int wm8915_reset(struct snd_soc_codec *codec)
1561 {
1562 return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1563 }
1564
1565 static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1566 enum snd_soc_bias_level level)
1567 {
1568 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1569 int ret;
1570
1571 switch (level) {
1572 case SND_SOC_BIAS_ON:
1573 break;
1574
1575 case SND_SOC_BIAS_PREPARE:
1576 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1577 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1578 WM8915_BG_ENA, WM8915_BG_ENA);
1579 msleep(2);
1580 }
1581 break;
1582
1583 case SND_SOC_BIAS_STANDBY:
1584 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1585 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1586 wm8915->supplies);
1587 if (ret != 0) {
1588 dev_err(codec->dev,
1589 "Failed to enable supplies: %d\n",
1590 ret);
1591 return ret;
1592 }
1593
1594 if (wm8915->pdata.ldo_ena >= 0) {
1595 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1596 1);
1597 msleep(5);
1598 }
1599
1600 codec->cache_only = false;
1601 snd_soc_cache_sync(codec);
1602 }
1603
1604 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1605 WM8915_BG_ENA, 0);
1606 break;
1607
1608 case SND_SOC_BIAS_OFF:
1609 codec->cache_only = true;
1610 if (wm8915->pdata.ldo_ena >= 0)
1611 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1612 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1613 wm8915->supplies);
1614 break;
1615 }
1616
1617 codec->dapm.bias_level = level;
1618
1619 return 0;
1620 }
1621
1622 static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1623 {
1624 struct snd_soc_codec *codec = dai->codec;
1625 int aifctrl = 0;
1626 int bclk = 0;
1627 int lrclk_tx = 0;
1628 int lrclk_rx = 0;
1629 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1630
1631 switch (dai->id) {
1632 case 0:
1633 aifctrl_reg = WM8915_AIF1_CONTROL;
1634 bclk_reg = WM8915_AIF1_BCLK;
1635 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1636 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1637 break;
1638 case 1:
1639 aifctrl_reg = WM8915_AIF2_CONTROL;
1640 bclk_reg = WM8915_AIF2_BCLK;
1641 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1642 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1643 break;
1644 default:
1645 BUG();
1646 return -EINVAL;
1647 }
1648
1649 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1650 case SND_SOC_DAIFMT_NB_NF:
1651 break;
1652 case SND_SOC_DAIFMT_IB_NF:
1653 bclk |= WM8915_AIF1_BCLK_INV;
1654 break;
1655 case SND_SOC_DAIFMT_NB_IF:
1656 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1657 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1658 break;
1659 case SND_SOC_DAIFMT_IB_IF:
1660 bclk |= WM8915_AIF1_BCLK_INV;
1661 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1662 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1663 break;
1664 }
1665
1666 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1667 case SND_SOC_DAIFMT_CBS_CFS:
1668 break;
1669 case SND_SOC_DAIFMT_CBS_CFM:
1670 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1671 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1672 break;
1673 case SND_SOC_DAIFMT_CBM_CFS:
1674 bclk |= WM8915_AIF1_BCLK_MSTR;
1675 break;
1676 case SND_SOC_DAIFMT_CBM_CFM:
1677 bclk |= WM8915_AIF1_BCLK_MSTR;
1678 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1679 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1680 break;
1681 default:
1682 return -EINVAL;
1683 }
1684
1685 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1686 case SND_SOC_DAIFMT_DSP_A:
1687 break;
1688 case SND_SOC_DAIFMT_DSP_B:
1689 aifctrl |= 1;
1690 break;
1691 case SND_SOC_DAIFMT_I2S:
1692 aifctrl |= 2;
1693 break;
1694 case SND_SOC_DAIFMT_LEFT_J:
1695 aifctrl |= 3;
1696 break;
1697 default:
1698 return -EINVAL;
1699 }
1700
1701 snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1702 snd_soc_update_bits(codec, bclk_reg,
1703 WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1704 bclk);
1705 snd_soc_update_bits(codec, lrclk_tx_reg,
1706 WM8915_AIF1TX_LRCLK_INV |
1707 WM8915_AIF1TX_LRCLK_MSTR,
1708 lrclk_tx);
1709 snd_soc_update_bits(codec, lrclk_rx_reg,
1710 WM8915_AIF1RX_LRCLK_INV |
1711 WM8915_AIF1RX_LRCLK_MSTR,
1712 lrclk_rx);
1713
1714 return 0;
1715 }
1716
1717 static const int bclk_divs[] = {
1718 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1719 };
1720
1721 static const int dsp_divs[] = {
1722 48000, 32000, 16000, 8000
1723 };
1724
1725 static int wm8915_hw_params(struct snd_pcm_substream *substream,
1726 struct snd_pcm_hw_params *params,
1727 struct snd_soc_dai *dai)
1728 {
1729 struct snd_soc_codec *codec = dai->codec;
1730 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1731 int bits, i, bclk_rate, best, cur_val;
1732 int aifdata = 0;
1733 int bclk = 0;
1734 int lrclk = 0;
1735 int dsp = 0;
1736 int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
1737
1738 if (!wm8915->sysclk) {
1739 dev_err(codec->dev, "SYSCLK not configured\n");
1740 return -EINVAL;
1741 }
1742
1743 switch (dai->id) {
1744 case 0:
1745 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1746 (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1747 aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1748 lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1749 } else {
1750 aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1751 lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1752 }
1753 bclk_reg = WM8915_AIF1_BCLK;
1754 dsp_shift = 0;
1755 break;
1756 case 1:
1757 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1758 (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1759 aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1760 lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1761 } else {
1762 aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1763 lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1764 }
1765 bclk_reg = WM8915_AIF2_BCLK;
1766 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1767 break;
1768 default:
1769 BUG();
1770 return -EINVAL;
1771 }
1772
1773 bclk_rate = snd_soc_params_to_bclk(params);
1774 if (bclk_rate < 0) {
1775 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1776 return bclk_rate;
1777 }
1778
1779 /* Needs looking at for TDM */
1780 bits = snd_pcm_format_width(params_format(params));
1781 if (bits < 0)
1782 return bits;
1783 aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1784
1785 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1786 if (dsp_divs[i] == params_rate(params))
1787 break;
1788 }
1789 if (i == ARRAY_SIZE(dsp_divs)) {
1790 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1791 params_rate(params));
1792 return -EINVAL;
1793 }
1794 dsp |= i << dsp_shift;
1795
1796 /* Pick a divisor for BCLK as close as we can get to ideal */
1797 best = 0;
1798 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1799 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1800 if (cur_val < 0) /* BCLK table is sorted */
1801 break;
1802 best = i;
1803 }
1804 bclk_rate = wm8915->sysclk / bclk_divs[best];
1805 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1806 bclk_divs[best], bclk_rate);
1807 bclk |= best;
1808
1809 lrclk = bclk_rate / params_rate(params);
1810 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1811 lrclk, bclk_rate / lrclk);
1812
1813 snd_soc_update_bits(codec, aifdata_reg,
1814 WM8915_AIF1TX_WL_MASK |
1815 WM8915_AIF1TX_SLOT_LEN_MASK,
1816 aifdata);
1817 snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
1818 snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1819 lrclk);
1820 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1821 WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1822
1823 wm8915->rx_rate[dai->id] = params_rate(params);
1824
1825 return 0;
1826 }
1827
1828 static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1829 int clk_id, unsigned int freq, int dir)
1830 {
1831 struct snd_soc_codec *codec = dai->codec;
1832 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1833 int lfclk = 0;
1834 int src;
1835 int old;
1836
1837 /* Disable SYSCLK while we reconfigure */
1838 old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1);
1839 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1840 WM8915_SYSCLK_ENA, 0);
1841
1842 switch (clk_id) {
1843 case WM8915_SYSCLK_MCLK1:
1844 wm8915->sysclk = freq;
1845 src = 0;
1846 break;
1847 case WM8915_SYSCLK_MCLK2:
1848 wm8915->sysclk = freq;
1849 src = 1;
1850 break;
1851 case WM8915_SYSCLK_FLL:
1852 wm8915->sysclk = freq;
1853 src = 2;
1854 break;
1855 default:
1856 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1857 return -EINVAL;
1858 }
1859
1860 switch (wm8915->sysclk) {
1861 case 6144000:
1862 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1863 WM8915_SYSCLK_RATE, 0);
1864 break;
1865 case 12288000:
1866 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1867 WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1868 break;
1869 case 32000:
1870 case 32768:
1871 lfclk = WM8915_LFCLK_ENA;
1872 break;
1873 default:
1874 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1875 wm8915->sysclk);
1876 return -EINVAL;
1877 }
1878
1879 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1880 WM8915_SYSCLK_SRC_MASK,
1881 src << WM8915_SYSCLK_SRC_SHIFT);
1882 snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1883 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1884 WM8915_SYSCLK_ENA, old);
1885
1886 return 0;
1887 }
1888
1889 struct _fll_div {
1890 u16 fll_fratio;
1891 u16 fll_outdiv;
1892 u16 fll_refclk_div;
1893 u16 fll_loop_gain;
1894 u16 fll_ref_freq;
1895 u16 n;
1896 u16 theta;
1897 u16 lambda;
1898 };
1899
1900 static struct {
1901 unsigned int min;
1902 unsigned int max;
1903 u16 fll_fratio;
1904 int ratio;
1905 } fll_fratios[] = {
1906 { 0, 64000, 4, 16 },
1907 { 64000, 128000, 3, 8 },
1908 { 128000, 256000, 2, 4 },
1909 { 256000, 1000000, 1, 2 },
1910 { 1000000, 13500000, 0, 1 },
1911 };
1912
1913 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1914 unsigned int Fout)
1915 {
1916 unsigned int target;
1917 unsigned int div;
1918 unsigned int fratio, gcd_fll;
1919 int i;
1920
1921 /* Fref must be <=13.5MHz */
1922 div = 1;
1923 fll_div->fll_refclk_div = 0;
1924 while ((Fref / div) > 13500000) {
1925 div *= 2;
1926 fll_div->fll_refclk_div++;
1927
1928 if (div > 8) {
1929 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1930 Fref);
1931 return -EINVAL;
1932 }
1933 }
1934
1935 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1936
1937 /* Apply the division for our remaining calculations */
1938 Fref /= div;
1939
1940 if (Fref >= 3000000)
1941 fll_div->fll_loop_gain = 5;
1942 else
1943 fll_div->fll_loop_gain = 0;
1944
1945 if (Fref >= 48000)
1946 fll_div->fll_ref_freq = 0;
1947 else
1948 fll_div->fll_ref_freq = 1;
1949
1950 /* Fvco should be 90-100MHz; don't check the upper bound */
1951 div = 2;
1952 while (Fout * div < 90000000) {
1953 div++;
1954 if (div > 64) {
1955 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1956 Fout);
1957 return -EINVAL;
1958 }
1959 }
1960 target = Fout * div;
1961 fll_div->fll_outdiv = div - 1;
1962
1963 pr_debug("FLL Fvco=%dHz\n", target);
1964
1965 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1966 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1967 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1968 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1969 fratio = fll_fratios[i].ratio;
1970 break;
1971 }
1972 }
1973 if (i == ARRAY_SIZE(fll_fratios)) {
1974 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1975 return -EINVAL;
1976 }
1977
1978 fll_div->n = target / (fratio * Fref);
1979
1980 if (target % Fref == 0) {
1981 fll_div->theta = 0;
1982 fll_div->lambda = 0;
1983 } else {
1984 gcd_fll = gcd(target, fratio * Fref);
1985
1986 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1987 / gcd_fll;
1988 fll_div->lambda = (fratio * Fref) / gcd_fll;
1989 }
1990
1991 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1992 fll_div->n, fll_div->theta, fll_div->lambda);
1993 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1994 fll_div->fll_fratio, fll_div->fll_outdiv,
1995 fll_div->fll_refclk_div);
1996
1997 return 0;
1998 }
1999
2000 static int wm8915_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
2001 unsigned int Fref, unsigned int Fout)
2002 {
2003 struct snd_soc_codec *codec = dai->codec;
2004 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2005 struct _fll_div fll_div;
2006 unsigned long timeout;
2007 int ret, reg;
2008
2009 /* Any change? */
2010 if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2011 Fout == wm8915->fll_fout)
2012 return 0;
2013
2014 if (Fout == 0) {
2015 dev_dbg(codec->dev, "FLL disabled\n");
2016
2017 wm8915->fll_fref = 0;
2018 wm8915->fll_fout = 0;
2019
2020 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2021 WM8915_FLL_ENA, 0);
2022
2023 return 0;
2024 }
2025
2026 ret = fll_factors(&fll_div, Fref, Fout);
2027 if (ret != 0)
2028 return ret;
2029
2030 switch (source) {
2031 case WM8915_FLL_MCLK1:
2032 reg = 0;
2033 break;
2034 case WM8915_FLL_MCLK2:
2035 reg = 1;
2036 case WM8915_FLL_DACLRCLK1:
2037 reg = 2;
2038 break;
2039 case WM8915_FLL_BCLK1:
2040 reg = 3;
2041 break;
2042 default:
2043 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2044 return -EINVAL;
2045 }
2046
2047 reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2048 reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2049
2050 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2051 WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2052 WM8915_FLL_REFCLK_SRC_MASK, reg);
2053
2054 reg = 0;
2055 if (fll_div.theta || fll_div.lambda)
2056 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2057 else
2058 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2059 snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2060
2061 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2062 WM8915_FLL_OUTDIV_MASK |
2063 WM8915_FLL_FRATIO_MASK,
2064 (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2065 (fll_div.fll_fratio));
2066
2067 snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2068
2069 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2070 WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2071 (fll_div.n << WM8915_FLL_N_SHIFT) |
2072 fll_div.fll_loop_gain);
2073
2074 snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2075
2076 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2077 WM8915_FLL_ENA, WM8915_FLL_ENA);
2078
2079 /* The FLL supports live reconfiguration - kick that in case we were
2080 * already enabled.
2081 */
2082 snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2083
2084 /* Wait for the FLL to lock, using the interrupt if possible */
2085 if (Fref > 1000000)
2086 timeout = usecs_to_jiffies(300);
2087 else
2088 timeout = msecs_to_jiffies(2);
2089
2090 wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2091
2092 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2093
2094 wm8915->fll_fref = Fref;
2095 wm8915->fll_fout = Fout;
2096 wm8915->fll_src = source;
2097
2098 return 0;
2099 }
2100
2101 #ifdef CONFIG_GPIOLIB
2102 static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2103 {
2104 return container_of(chip, struct wm8915_priv, gpio_chip);
2105 }
2106
2107 static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2108 {
2109 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2110 struct snd_soc_codec *codec = wm8915->codec;
2111
2112 snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2113 WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2114 }
2115
2116 static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2117 unsigned offset, int value)
2118 {
2119 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2120 struct snd_soc_codec *codec = wm8915->codec;
2121 int val;
2122
2123 val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2124
2125 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2126 WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2127 WM8915_GP1_LVL, val);
2128 }
2129
2130 static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2131 {
2132 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2133 struct snd_soc_codec *codec = wm8915->codec;
2134 int ret;
2135
2136 ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2137 if (ret < 0)
2138 return ret;
2139
2140 return (ret & WM8915_GP1_LVL) != 0;
2141 }
2142
2143 static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2144 {
2145 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2146 struct snd_soc_codec *codec = wm8915->codec;
2147
2148 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2149 WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2150 (1 << WM8915_GP1_FN_SHIFT) |
2151 (1 << WM8915_GP1_DIR_SHIFT));
2152 }
2153
2154 static struct gpio_chip wm8915_template_chip = {
2155 .label = "wm8915",
2156 .owner = THIS_MODULE,
2157 .direction_output = wm8915_gpio_direction_out,
2158 .set = wm8915_gpio_set,
2159 .direction_input = wm8915_gpio_direction_in,
2160 .get = wm8915_gpio_get,
2161 .can_sleep = 1,
2162 };
2163
2164 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2165 {
2166 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2167 int ret;
2168
2169 wm8915->gpio_chip = wm8915_template_chip;
2170 wm8915->gpio_chip.ngpio = 5;
2171 wm8915->gpio_chip.dev = codec->dev;
2172
2173 if (wm8915->pdata.gpio_base)
2174 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2175 else
2176 wm8915->gpio_chip.base = -1;
2177
2178 ret = gpiochip_add(&wm8915->gpio_chip);
2179 if (ret != 0)
2180 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2181 }
2182
2183 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2184 {
2185 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2186 int ret;
2187
2188 ret = gpiochip_remove(&wm8915->gpio_chip);
2189 if (ret != 0)
2190 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2191 }
2192 #else
2193 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2194 {
2195 }
2196
2197 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2198 {
2199 }
2200 #endif
2201
2202 /**
2203 * wm8915_detect - Enable default WM8915 jack detection
2204 *
2205 * The WM8915 has advanced accessory detection support for headsets.
2206 * This function provides a default implementation which integrates
2207 * the majority of this functionality with minimal user configuration.
2208 *
2209 * This will detect headset, headphone and short circuit button and
2210 * will also detect inverted microphone ground connections and update
2211 * the polarity of the connections.
2212 */
2213 int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2214 wm8915_polarity_fn polarity_cb)
2215 {
2216 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2217
2218 wm8915->jack = jack;
2219 wm8915->detecting = true;
2220 wm8915->polarity_cb = polarity_cb;
2221
2222 if (wm8915->polarity_cb)
2223 wm8915->polarity_cb(codec, 0);
2224
2225 /* Clear discarge to avoid noise during detection */
2226 snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2227 WM8915_MICB1_DISCH, 0);
2228 snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2229 WM8915_MICB2_DISCH, 0);
2230
2231 /* LDO2 powers the microphones, SYSCLK clocks detection */
2232 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2233 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2234
2235 /* We start off just enabling microphone detection - even a
2236 * plain headphone will trigger detection.
2237 */
2238 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2239 WM8915_MICD_ENA, WM8915_MICD_ENA);
2240
2241 /* Slowest detection rate, gives debounce for initial detection */
2242 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2243 WM8915_MICD_RATE_MASK,
2244 WM8915_MICD_RATE_MASK);
2245
2246 /* Enable interrupts and we're off */
2247 snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2248 WM8915_IM_MICD_EINT, 0);
2249
2250 return 0;
2251 }
2252 EXPORT_SYMBOL_GPL(wm8915_detect);
2253
2254 static void wm8915_micd(struct snd_soc_codec *codec)
2255 {
2256 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2257 int val, reg;
2258
2259 val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2260
2261 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2262
2263 if (!(val & WM8915_MICD_VALID)) {
2264 dev_warn(codec->dev, "Microphone detection state invalid\n");
2265 return;
2266 }
2267
2268 /* No accessory, reset everything and report removal */
2269 if (!(val & WM8915_MICD_STS)) {
2270 dev_dbg(codec->dev, "Jack removal detected\n");
2271 wm8915->jack_mic = false;
2272 wm8915->detecting = true;
2273 snd_soc_jack_report(wm8915->jack, 0,
2274 SND_JACK_HEADSET | SND_JACK_BTN_0);
2275 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2276 WM8915_MICD_RATE_MASK,
2277 WM8915_MICD_RATE_MASK);
2278 return;
2279 }
2280
2281 /* If the measurement is very high we've got a microphone but
2282 * do a little debounce to account for mechanical issues.
2283 */
2284 if (val & 0x400) {
2285 dev_dbg(codec->dev, "Microphone detected\n");
2286 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2287 SND_JACK_HEADSET | SND_JACK_BTN_0);
2288 wm8915->jack_mic = true;
2289 wm8915->detecting = false;
2290 }
2291
2292 /* If we detected a lower impedence during initial startup
2293 * then we probably have the wrong polarity, flip it. Don't
2294 * do this for the lowest impedences to speed up detection of
2295 * plain headphones.
2296 */
2297 if (wm8915->detecting && (val & 0x3f0)) {
2298 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2299 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2300 WM8915_MICD_BIAS_SRC;
2301 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2302 WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2303 WM8915_MICD_BIAS_SRC, reg);
2304
2305 if (wm8915->polarity_cb)
2306 wm8915->polarity_cb(codec,
2307 (reg & WM8915_MICD_SRC) != 0);
2308
2309 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2310 (reg & WM8915_MICD_SRC) != 0);
2311
2312 return;
2313 }
2314
2315 /* Don't distinguish between buttons, just report any low
2316 * impedence as BTN_0.
2317 */
2318 if (val & 0x3fc) {
2319 if (wm8915->jack_mic) {
2320 dev_dbg(codec->dev, "Mic button detected\n");
2321 snd_soc_jack_report(wm8915->jack,
2322 SND_JACK_HEADSET | SND_JACK_BTN_0,
2323 SND_JACK_HEADSET | SND_JACK_BTN_0);
2324 } else {
2325 dev_dbg(codec->dev, "Headphone detected\n");
2326 snd_soc_jack_report(wm8915->jack,
2327 SND_JACK_HEADPHONE,
2328 SND_JACK_HEADSET |
2329 SND_JACK_BTN_0);
2330 wm8915->detecting = false;
2331 }
2332 }
2333
2334 /* Increase poll rate to give better responsiveness for buttons */
2335 if (!wm8915->detecting)
2336 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2337 WM8915_MICD_RATE_MASK,
2338 5 << WM8915_MICD_RATE_SHIFT);
2339 }
2340
2341 static irqreturn_t wm8915_irq(int irq, void *data)
2342 {
2343 struct snd_soc_codec *codec = data;
2344 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2345 int irq_val;
2346
2347 irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2348 if (irq_val < 0) {
2349 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2350 irq_val);
2351 return IRQ_NONE;
2352 }
2353 irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2354
2355 if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2356 dev_dbg(codec->dev, "DC servo IRQ\n");
2357 complete(&wm8915->dcs_done);
2358 }
2359
2360 if (irq_val & WM8915_FIFOS_ERR_EINT)
2361 dev_err(codec->dev, "Digital core FIFO error\n");
2362
2363 if (irq_val & WM8915_FLL_LOCK_EINT) {
2364 dev_dbg(codec->dev, "FLL locked\n");
2365 complete(&wm8915->fll_lock);
2366 }
2367
2368 if (irq_val & WM8915_MICD_EINT)
2369 wm8915_micd(codec);
2370
2371 if (irq_val) {
2372 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2373
2374 return IRQ_HANDLED;
2375 } else {
2376 return IRQ_NONE;
2377 }
2378 }
2379
2380 static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2381 {
2382 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2383 struct wm8915_pdata *pdata = &wm8915->pdata;
2384
2385 struct snd_kcontrol_new controls[] = {
2386 SOC_ENUM_EXT("DSP1 EQ Mode",
2387 wm8915->retune_mobile_enum,
2388 wm8915_get_retune_mobile_enum,
2389 wm8915_put_retune_mobile_enum),
2390 SOC_ENUM_EXT("DSP2 EQ Mode",
2391 wm8915->retune_mobile_enum,
2392 wm8915_get_retune_mobile_enum,
2393 wm8915_put_retune_mobile_enum),
2394 };
2395 int ret, i, j;
2396 const char **t;
2397
2398 /* We need an array of texts for the enum API but the number
2399 * of texts is likely to be less than the number of
2400 * configurations due to the sample rate dependency of the
2401 * configurations. */
2402 wm8915->num_retune_mobile_texts = 0;
2403 wm8915->retune_mobile_texts = NULL;
2404 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2405 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2406 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2407 wm8915->retune_mobile_texts[j]) == 0)
2408 break;
2409 }
2410
2411 if (j != wm8915->num_retune_mobile_texts)
2412 continue;
2413
2414 /* Expand the array... */
2415 t = krealloc(wm8915->retune_mobile_texts,
2416 sizeof(char *) *
2417 (wm8915->num_retune_mobile_texts + 1),
2418 GFP_KERNEL);
2419 if (t == NULL)
2420 continue;
2421
2422 /* ...store the new entry... */
2423 t[wm8915->num_retune_mobile_texts] =
2424 pdata->retune_mobile_cfgs[i].name;
2425
2426 /* ...and remember the new version. */
2427 wm8915->num_retune_mobile_texts++;
2428 wm8915->retune_mobile_texts = t;
2429 }
2430
2431 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2432 wm8915->num_retune_mobile_texts);
2433
2434 wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2435 wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2436
2437 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2438 if (ret != 0)
2439 dev_err(codec->dev,
2440 "Failed to add ReTune Mobile controls: %d\n", ret);
2441 }
2442
2443 static int wm8915_probe(struct snd_soc_codec *codec)
2444 {
2445 int ret;
2446 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2447 struct i2c_client *i2c = to_i2c_client(codec->dev);
2448 struct snd_soc_dapm_context *dapm = &codec->dapm;
2449 int i, irq_flags;
2450
2451 wm8915->codec = codec;
2452
2453 init_completion(&wm8915->dcs_done);
2454 init_completion(&wm8915->fll_lock);
2455
2456 dapm->idle_bias_off = true;
2457 dapm->bias_level = SND_SOC_BIAS_OFF;
2458
2459 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2460 if (ret != 0) {
2461 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2462 goto err;
2463 }
2464
2465 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2466 wm8915->supplies[i].supply = wm8915_supply_names[i];
2467
2468 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2469 wm8915->supplies);
2470 if (ret != 0) {
2471 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2472 goto err;
2473 }
2474
2475 wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2476 wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2477 wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2478 wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2479 wm8915->disable_nb[4].notifier_call = wm8915_regulator_event_4;
2480 wm8915->disable_nb[5].notifier_call = wm8915_regulator_event_5;
2481
2482 /* This should really be moved into the regulator core */
2483 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2484 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2485 &wm8915->disable_nb[i]);
2486 if (ret != 0) {
2487 dev_err(codec->dev,
2488 "Failed to register regulator notifier: %d\n",
2489 ret);
2490 }
2491 }
2492
2493 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2494 wm8915->supplies);
2495 if (ret != 0) {
2496 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2497 goto err_get;
2498 }
2499
2500 if (wm8915->pdata.ldo_ena >= 0) {
2501 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2502 msleep(5);
2503 }
2504
2505 ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2506 if (ret < 0) {
2507 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2508 goto err_enable;
2509 }
2510 if (ret != 0x8915) {
2511 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2512 ret = -EINVAL;
2513 goto err_enable;
2514 }
2515
2516 ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2517 if (ret < 0) {
2518 dev_err(codec->dev, "Failed to read device revision: %d\n",
2519 ret);
2520 goto err_enable;
2521 }
2522
2523 dev_info(codec->dev, "revision %c\n",
2524 (ret & WM8915_CHIP_REV_MASK) + 'A');
2525
2526 if (wm8915->pdata.ldo_ena >= 0) {
2527 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2528 } else {
2529 ret = wm8915_reset(codec);
2530 if (ret < 0) {
2531 dev_err(codec->dev, "Failed to issue reset\n");
2532 goto err_enable;
2533 }
2534 }
2535
2536 codec->cache_only = true;
2537
2538 /* Apply platform data settings */
2539 snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2540 WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2541 wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2542 wm8915->pdata.inr_mode);
2543
2544 for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2545 if (!wm8915->pdata.gpio_default[i])
2546 continue;
2547
2548 snd_soc_write(codec, WM8915_GPIO_1 + i,
2549 wm8915->pdata.gpio_default[i] & 0xffff);
2550 }
2551
2552 if (wm8915->pdata.spkmute_seq)
2553 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2554 WM8915_SPK_MUTE_ENDIAN |
2555 WM8915_SPK_MUTE_SEQ1_MASK,
2556 wm8915->pdata.spkmute_seq);
2557
2558 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2559 WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2560 WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2561
2562 /* Latch volume update bits */
2563 snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2564 WM8915_IN1_VU, WM8915_IN1_VU);
2565 snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2566 WM8915_IN1_VU, WM8915_IN1_VU);
2567
2568 snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2569 WM8915_DAC1_VU, WM8915_DAC1_VU);
2570 snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2571 WM8915_DAC1_VU, WM8915_DAC1_VU);
2572 snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2573 WM8915_DAC2_VU, WM8915_DAC2_VU);
2574 snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2575 WM8915_DAC2_VU, WM8915_DAC2_VU);
2576
2577 snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2578 WM8915_DAC1_VU, WM8915_DAC1_VU);
2579 snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2580 WM8915_DAC1_VU, WM8915_DAC1_VU);
2581 snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2582 WM8915_DAC2_VU, WM8915_DAC2_VU);
2583 snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2584 WM8915_DAC2_VU, WM8915_DAC2_VU);
2585
2586 snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2587 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2588 snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2589 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2590 snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2591 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2592 snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2593 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2594
2595 snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2596 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2597 snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2598 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2599 snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2600 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2601 snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2602 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2603
2604 /* No support currently for the underclocked TDM modes and
2605 * pick a default TDM layout with each channel pair working with
2606 * slots 0 and 1. */
2607 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2608 WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2609 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2610 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2611 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2612 WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2613 WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2614 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2615 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2616 WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2617 WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2618 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2619 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2620 WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2621 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2622 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2623 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2624 WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2625 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2626 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2627 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2628 WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2629 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2630 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2631
2632 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2633 WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2634 WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2635 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2636 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2637 WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2638 WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2639 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2640
2641 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2642 WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2643 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2644 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2645 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2646 WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2647 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2648 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2649 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2650 WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2651 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2652 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2653 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2654 WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2655 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2656 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2657 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2658 WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2659 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2660 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2661 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2662 WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2663 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2664 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2665
2666 snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2667 WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2668 WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2669 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2670 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2671 WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2672 WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2673 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2674
2675 if (wm8915->pdata.num_retune_mobile_cfgs)
2676 wm8915_retune_mobile_pdata(codec);
2677 else
2678 snd_soc_add_controls(codec, wm8915_eq_controls,
2679 ARRAY_SIZE(wm8915_eq_controls));
2680
2681 /* If the TX LRCLK pins are not in LRCLK mode configure the
2682 * AIFs to source their clocks from the RX LRCLKs.
2683 */
2684 if ((snd_soc_read(codec, WM8915_GPIO_1)))
2685 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2686 WM8915_AIF1TX_LRCLK_MODE,
2687 WM8915_AIF1TX_LRCLK_MODE);
2688
2689 if ((snd_soc_read(codec, WM8915_GPIO_2)))
2690 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2691 WM8915_AIF2TX_LRCLK_MODE,
2692 WM8915_AIF2TX_LRCLK_MODE);
2693
2694 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2695
2696 wm8915_init_gpio(codec);
2697
2698 if (i2c->irq) {
2699 if (wm8915->pdata.irq_flags)
2700 irq_flags = wm8915->pdata.irq_flags;
2701 else
2702 irq_flags = IRQF_TRIGGER_LOW;
2703
2704 irq_flags |= IRQF_ONESHOT;
2705
2706 ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2707 irq_flags, "wm8915", codec);
2708 if (ret == 0) {
2709 /* Unmask the interrupt */
2710 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2711 WM8915_IM_IRQ, 0);
2712
2713 /* Enable error reporting and DC servo status */
2714 snd_soc_update_bits(codec,
2715 WM8915_INTERRUPT_STATUS_2_MASK,
2716 WM8915_IM_DCS_DONE_23_EINT |
2717 WM8915_IM_DCS_DONE_01_EINT |
2718 WM8915_IM_FLL_LOCK_EINT |
2719 WM8915_IM_FIFOS_ERR_EINT,
2720 0);
2721 } else {
2722 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2723 ret);
2724 }
2725 }
2726
2727 return 0;
2728
2729 err_enable:
2730 if (wm8915->pdata.ldo_ena >= 0)
2731 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2732
2733 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2734 err_get:
2735 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2736 err:
2737 return ret;
2738 }
2739
2740 static int wm8915_remove(struct snd_soc_codec *codec)
2741 {
2742 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2743 struct i2c_client *i2c = to_i2c_client(codec->dev);
2744 int i;
2745
2746 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2747 WM8915_IM_IRQ, WM8915_IM_IRQ);
2748
2749 if (i2c->irq)
2750 free_irq(i2c->irq, codec);
2751
2752 wm8915_free_gpio(codec);
2753
2754 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2755 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2756 &wm8915->disable_nb[i]);
2757 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2758
2759 return 0;
2760 }
2761
2762 static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2763 .probe = wm8915_probe,
2764 .remove = wm8915_remove,
2765 .set_bias_level = wm8915_set_bias_level,
2766 .seq_notifier = wm8915_seq_notifier,
2767 .reg_cache_size = WM8915_MAX_REGISTER + 1,
2768 .reg_word_size = sizeof(u16),
2769 .reg_cache_default = wm8915_reg,
2770 .volatile_register = wm8915_volatile_register,
2771 .readable_register = wm8915_readable_register,
2772 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2773 .controls = wm8915_snd_controls,
2774 .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2775 .dapm_widgets = wm8915_dapm_widgets,
2776 .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2777 .dapm_routes = wm8915_dapm_routes,
2778 .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
2779 };
2780
2781 #define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2782 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2783 #define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2784 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2785 SNDRV_PCM_FMTBIT_S32_LE)
2786
2787 static struct snd_soc_dai_ops wm8915_dai_ops = {
2788 .set_fmt = wm8915_set_fmt,
2789 .hw_params = wm8915_hw_params,
2790 .set_sysclk = wm8915_set_sysclk,
2791 .set_pll = wm8915_set_fll,
2792 };
2793
2794 static struct snd_soc_dai_driver wm8915_dai[] = {
2795 {
2796 .name = "wm8915-aif1",
2797 .playback = {
2798 .stream_name = "AIF1 Playback",
2799 .channels_min = 1,
2800 .channels_max = 6,
2801 .rates = WM8915_RATES,
2802 .formats = WM8915_FORMATS,
2803 },
2804 .capture = {
2805 .stream_name = "AIF1 Capture",
2806 .channels_min = 1,
2807 .channels_max = 6,
2808 .rates = WM8915_RATES,
2809 .formats = WM8915_FORMATS,
2810 },
2811 .ops = &wm8915_dai_ops,
2812 },
2813 {
2814 .name = "wm8915-aif2",
2815 .playback = {
2816 .stream_name = "AIF2 Playback",
2817 .channels_min = 1,
2818 .channels_max = 2,
2819 .rates = WM8915_RATES,
2820 .formats = WM8915_FORMATS,
2821 },
2822 .capture = {
2823 .stream_name = "AIF2 Capture",
2824 .channels_min = 1,
2825 .channels_max = 2,
2826 .rates = WM8915_RATES,
2827 .formats = WM8915_FORMATS,
2828 },
2829 .ops = &wm8915_dai_ops,
2830 },
2831 };
2832
2833 static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2834 const struct i2c_device_id *id)
2835 {
2836 struct wm8915_priv *wm8915;
2837 int ret;
2838
2839 wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2840 if (wm8915 == NULL)
2841 return -ENOMEM;
2842
2843 i2c_set_clientdata(i2c, wm8915);
2844
2845 if (dev_get_platdata(&i2c->dev))
2846 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2847 sizeof(wm8915->pdata));
2848
2849 if (wm8915->pdata.ldo_ena > 0) {
2850 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2851 GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2852 if (ret < 0) {
2853 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2854 wm8915->pdata.ldo_ena, ret);
2855 goto err;
2856 }
2857 }
2858
2859 ret = snd_soc_register_codec(&i2c->dev,
2860 &soc_codec_dev_wm8915, wm8915_dai,
2861 ARRAY_SIZE(wm8915_dai));
2862 if (ret < 0)
2863 goto err_gpio;
2864
2865 return ret;
2866
2867 err_gpio:
2868 if (wm8915->pdata.ldo_ena > 0)
2869 gpio_free(wm8915->pdata.ldo_ena);
2870 err:
2871 kfree(wm8915);
2872
2873 return ret;
2874 }
2875
2876 static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2877 {
2878 struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2879
2880 snd_soc_unregister_codec(&client->dev);
2881 if (wm8915->pdata.ldo_ena > 0)
2882 gpio_free(wm8915->pdata.ldo_ena);
2883 kfree(i2c_get_clientdata(client));
2884 return 0;
2885 }
2886
2887 static const struct i2c_device_id wm8915_i2c_id[] = {
2888 { "wm8915", 0 },
2889 { }
2890 };
2891 MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2892
2893 static struct i2c_driver wm8915_i2c_driver = {
2894 .driver = {
2895 .name = "wm8915",
2896 .owner = THIS_MODULE,
2897 },
2898 .probe = wm8915_i2c_probe,
2899 .remove = __devexit_p(wm8915_i2c_remove),
2900 .id_table = wm8915_i2c_id,
2901 };
2902
2903 static int __init wm8915_modinit(void)
2904 {
2905 int ret;
2906
2907 ret = i2c_add_driver(&wm8915_i2c_driver);
2908 if (ret != 0) {
2909 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2910 ret);
2911 }
2912
2913 return ret;
2914 }
2915 module_init(wm8915_modinit);
2916
2917 static void __exit wm8915_exit(void)
2918 {
2919 i2c_del_driver(&wm8915_i2c_driver);
2920 }
2921 module_exit(wm8915_exit);
2922
2923 MODULE_DESCRIPTION("ASoC WM8915 driver");
2924 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2925 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree