2 * Freescale MPC85xx Memory Controller kenel module
4 * Author: Dave Jiang <djiang@mvista.com>
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/ctype.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/edac.h>
19 #include <linux/smp.h>
20 #include <linux/gfp.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_device.h>
24 #include "edac_module.h"
25 #include "edac_core.h"
26 #include "mpc85xx_edac.h"
28 static int edac_dev_idx
;
30 static int edac_pci_idx
;
32 static int edac_mc_idx
;
34 static u32 orig_ddr_err_disable
;
35 static u32 orig_ddr_err_sbe
;
41 static u32 orig_pci_err_cap_dr
;
42 static u32 orig_pci_err_en
;
45 static u32 orig_l2_err_disable
;
47 static u32 orig_hid1
[2];
50 /************************ MC SYSFS parts ***********************************/
52 static ssize_t
mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info
*mci
,
55 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
56 return sprintf(data
, "0x%08x",
57 in_be32(pdata
->mc_vbase
+
58 MPC85XX_MC_DATA_ERR_INJECT_HI
));
61 static ssize_t
mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info
*mci
,
64 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
65 return sprintf(data
, "0x%08x",
66 in_be32(pdata
->mc_vbase
+
67 MPC85XX_MC_DATA_ERR_INJECT_LO
));
70 static ssize_t
mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info
*mci
, char *data
)
72 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
73 return sprintf(data
, "0x%08x",
74 in_be32(pdata
->mc_vbase
+ MPC85XX_MC_ECC_ERR_INJECT
));
77 static ssize_t
mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info
*mci
,
78 const char *data
, size_t count
)
80 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
82 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_DATA_ERR_INJECT_HI
,
83 simple_strtoul(data
, NULL
, 0));
89 static ssize_t
mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info
*mci
,
90 const char *data
, size_t count
)
92 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
94 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_DATA_ERR_INJECT_LO
,
95 simple_strtoul(data
, NULL
, 0));
101 static ssize_t
mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info
*mci
,
102 const char *data
, size_t count
)
104 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
105 if (isdigit(*data
)) {
106 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ECC_ERR_INJECT
,
107 simple_strtoul(data
, NULL
, 0));
113 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes
[] = {
116 .name
= "inject_data_hi",
117 .mode
= (S_IRUGO
| S_IWUSR
)
119 .show
= mpc85xx_mc_inject_data_hi_show
,
120 .store
= mpc85xx_mc_inject_data_hi_store
},
123 .name
= "inject_data_lo",
124 .mode
= (S_IRUGO
| S_IWUSR
)
126 .show
= mpc85xx_mc_inject_data_lo_show
,
127 .store
= mpc85xx_mc_inject_data_lo_store
},
130 .name
= "inject_ctrl",
131 .mode
= (S_IRUGO
| S_IWUSR
)
133 .show
= mpc85xx_mc_inject_ctrl_show
,
134 .store
= mpc85xx_mc_inject_ctrl_store
},
138 .attr
= {.name
= NULL
}
142 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info
*mci
)
144 mci
->mc_driver_sysfs_attributes
= mpc85xx_mc_sysfs_attributes
;
147 /**************************** PCI Err device ***************************/
150 static void mpc85xx_pci_check(struct edac_pci_ctl_info
*pci
)
152 struct mpc85xx_pci_pdata
*pdata
= pci
->pvt_info
;
155 err_detect
= in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DR
);
157 /* master aborts can happen during PCI config cycles */
158 if (!(err_detect
& ~(PCI_EDE_MULTI_ERR
| PCI_EDE_MST_ABRT
))) {
159 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DR
, err_detect
);
163 printk(KERN_ERR
"PCI error(s) detected\n");
164 printk(KERN_ERR
"PCI/X ERR_DR register: %#08x\n", err_detect
);
166 printk(KERN_ERR
"PCI/X ERR_ATTRIB register: %#08x\n",
167 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_ATTRIB
));
168 printk(KERN_ERR
"PCI/X ERR_ADDR register: %#08x\n",
169 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_ADDR
));
170 printk(KERN_ERR
"PCI/X ERR_EXT_ADDR register: %#08x\n",
171 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_EXT_ADDR
));
172 printk(KERN_ERR
"PCI/X ERR_DL register: %#08x\n",
173 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DL
));
174 printk(KERN_ERR
"PCI/X ERR_DH register: %#08x\n",
175 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DH
));
177 /* clear error bits */
178 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DR
, err_detect
);
180 if (err_detect
& PCI_EDE_PERR_MASK
)
181 edac_pci_handle_pe(pci
, pci
->ctl_name
);
183 if ((err_detect
& ~PCI_EDE_MULTI_ERR
) & ~PCI_EDE_PERR_MASK
)
184 edac_pci_handle_npe(pci
, pci
->ctl_name
);
187 static irqreturn_t
mpc85xx_pci_isr(int irq
, void *dev_id
)
189 struct edac_pci_ctl_info
*pci
= dev_id
;
190 struct mpc85xx_pci_pdata
*pdata
= pci
->pvt_info
;
193 err_detect
= in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DR
);
198 mpc85xx_pci_check(pci
);
203 static int __devinit
mpc85xx_pci_err_probe(struct of_device
*op
,
204 const struct of_device_id
*match
)
206 struct edac_pci_ctl_info
*pci
;
207 struct mpc85xx_pci_pdata
*pdata
;
211 if (!devres_open_group(&op
->dev
, mpc85xx_pci_err_probe
, GFP_KERNEL
))
214 pci
= edac_pci_alloc_ctl_info(sizeof(*pdata
), "mpc85xx_pci_err");
218 pdata
= pci
->pvt_info
;
219 pdata
->name
= "mpc85xx_pci_err";
221 dev_set_drvdata(&op
->dev
, pci
);
223 pci
->mod_name
= EDAC_MOD_STR
;
224 pci
->ctl_name
= pdata
->name
;
225 pci
->dev_name
= dev_name(&op
->dev
);
227 if (edac_op_state
== EDAC_OPSTATE_POLL
)
228 pci
->edac_check
= mpc85xx_pci_check
;
230 pdata
->edac_idx
= edac_pci_idx
++;
232 res
= of_address_to_resource(op
->dev
.of_node
, 0, &r
);
234 printk(KERN_ERR
"%s: Unable to get resource for "
235 "PCI err regs\n", __func__
);
239 /* we only need the error registers */
242 if (!devm_request_mem_region(&op
->dev
, r
.start
, resource_size(&r
),
244 printk(KERN_ERR
"%s: Error while requesting mem region\n",
250 pdata
->pci_vbase
= devm_ioremap(&op
->dev
, r
.start
, resource_size(&r
));
251 if (!pdata
->pci_vbase
) {
252 printk(KERN_ERR
"%s: Unable to setup PCI err regs\n", __func__
);
257 orig_pci_err_cap_dr
=
258 in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_CAP_DR
);
260 /* PCI master abort is expected during config cycles */
261 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_CAP_DR
, 0x40);
263 orig_pci_err_en
= in_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_EN
);
265 /* disable master abort reporting */
266 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_EN
, ~0x40);
268 /* clear error bits */
269 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_DR
, ~0);
271 if (edac_pci_add_device(pci
, pdata
->edac_idx
) > 0) {
272 debugf3("%s(): failed edac_pci_add_device()\n", __func__
);
276 if (edac_op_state
== EDAC_OPSTATE_INT
) {
277 pdata
->irq
= irq_of_parse_and_map(op
->dev
.of_node
, 0);
278 res
= devm_request_irq(&op
->dev
, pdata
->irq
,
279 mpc85xx_pci_isr
, IRQF_DISABLED
,
280 "[EDAC] PCI err", pci
);
283 "%s: Unable to requiest irq %d for "
284 "MPC85xx PCI err\n", __func__
, pdata
->irq
);
285 irq_dispose_mapping(pdata
->irq
);
290 printk(KERN_INFO EDAC_MOD_STR
" acquired irq %d for PCI Err\n",
294 devres_remove_group(&op
->dev
, mpc85xx_pci_err_probe
);
295 debugf3("%s(): success\n", __func__
);
296 printk(KERN_INFO EDAC_MOD_STR
" PCI err registered\n");
301 edac_pci_del_device(&op
->dev
);
303 edac_pci_free_ctl_info(pci
);
304 devres_release_group(&op
->dev
, mpc85xx_pci_err_probe
);
308 static int mpc85xx_pci_err_remove(struct of_device
*op
)
310 struct edac_pci_ctl_info
*pci
= dev_get_drvdata(&op
->dev
);
311 struct mpc85xx_pci_pdata
*pdata
= pci
->pvt_info
;
313 debugf0("%s()\n", __func__
);
315 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_CAP_DR
,
316 orig_pci_err_cap_dr
);
318 out_be32(pdata
->pci_vbase
+ MPC85XX_PCI_ERR_EN
, orig_pci_err_en
);
320 edac_pci_del_device(pci
->dev
);
322 if (edac_op_state
== EDAC_OPSTATE_INT
)
323 irq_dispose_mapping(pdata
->irq
);
325 edac_pci_free_ctl_info(pci
);
330 static struct of_device_id mpc85xx_pci_err_of_match
[] = {
332 .compatible
= "fsl,mpc8540-pcix",
335 .compatible
= "fsl,mpc8540-pci",
339 MODULE_DEVICE_TABLE(of
, mpc85xx_pci_err_of_match
);
341 static struct of_platform_driver mpc85xx_pci_err_driver
= {
342 .probe
= mpc85xx_pci_err_probe
,
343 .remove
= __devexit_p(mpc85xx_pci_err_remove
),
345 .name
= "mpc85xx_pci_err",
346 .owner
= THIS_MODULE
,
347 .of_match_table
= mpc85xx_pci_err_of_match
,
351 #endif /* CONFIG_PCI */
353 /**************************** L2 Err device ***************************/
355 /************************ L2 SYSFS parts ***********************************/
357 static ssize_t
mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
358 *edac_dev
, char *data
)
360 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
361 return sprintf(data
, "0x%08x",
362 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJHI
));
365 static ssize_t
mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
366 *edac_dev
, char *data
)
368 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
369 return sprintf(data
, "0x%08x",
370 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJLO
));
373 static ssize_t
mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
374 *edac_dev
, char *data
)
376 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
377 return sprintf(data
, "0x%08x",
378 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJCTL
));
381 static ssize_t
mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
382 *edac_dev
, const char *data
,
385 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
386 if (isdigit(*data
)) {
387 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJHI
,
388 simple_strtoul(data
, NULL
, 0));
394 static ssize_t
mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
395 *edac_dev
, const char *data
,
398 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
399 if (isdigit(*data
)) {
400 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJLO
,
401 simple_strtoul(data
, NULL
, 0));
407 static ssize_t
mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
408 *edac_dev
, const char *data
,
411 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
412 if (isdigit(*data
)) {
413 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINJCTL
,
414 simple_strtoul(data
, NULL
, 0));
420 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes
[] = {
423 .name
= "inject_data_hi",
424 .mode
= (S_IRUGO
| S_IWUSR
)
426 .show
= mpc85xx_l2_inject_data_hi_show
,
427 .store
= mpc85xx_l2_inject_data_hi_store
},
430 .name
= "inject_data_lo",
431 .mode
= (S_IRUGO
| S_IWUSR
)
433 .show
= mpc85xx_l2_inject_data_lo_show
,
434 .store
= mpc85xx_l2_inject_data_lo_store
},
437 .name
= "inject_ctrl",
438 .mode
= (S_IRUGO
| S_IWUSR
)
440 .show
= mpc85xx_l2_inject_ctrl_show
,
441 .store
= mpc85xx_l2_inject_ctrl_store
},
445 .attr
= {.name
= NULL
}
449 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
452 edac_dev
->sysfs_attributes
= mpc85xx_l2_sysfs_attributes
;
455 /***************************** L2 ops ***********************************/
457 static void mpc85xx_l2_check(struct edac_device_ctl_info
*edac_dev
)
459 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
462 err_detect
= in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDET
);
464 if (!(err_detect
& L2_EDE_MASK
))
467 printk(KERN_ERR
"ECC Error in CPU L2 cache\n");
468 printk(KERN_ERR
"L2 Error Detect Register: 0x%08x\n", err_detect
);
469 printk(KERN_ERR
"L2 Error Capture Data High Register: 0x%08x\n",
470 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_CAPTDATAHI
));
471 printk(KERN_ERR
"L2 Error Capture Data Lo Register: 0x%08x\n",
472 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_CAPTDATALO
));
473 printk(KERN_ERR
"L2 Error Syndrome Register: 0x%08x\n",
474 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_CAPTECC
));
475 printk(KERN_ERR
"L2 Error Attributes Capture Register: 0x%08x\n",
476 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRATTR
));
477 printk(KERN_ERR
"L2 Error Address Capture Register: 0x%08x\n",
478 in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRADDR
));
480 /* clear error detect register */
481 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDET
, err_detect
);
483 if (err_detect
& L2_EDE_CE_MASK
)
484 edac_device_handle_ce(edac_dev
, 0, 0, edac_dev
->ctl_name
);
486 if (err_detect
& L2_EDE_UE_MASK
)
487 edac_device_handle_ue(edac_dev
, 0, 0, edac_dev
->ctl_name
);
490 static irqreturn_t
mpc85xx_l2_isr(int irq
, void *dev_id
)
492 struct edac_device_ctl_info
*edac_dev
= dev_id
;
493 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
496 err_detect
= in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDET
);
498 if (!(err_detect
& L2_EDE_MASK
))
501 mpc85xx_l2_check(edac_dev
);
506 static int __devinit
mpc85xx_l2_err_probe(struct of_device
*op
,
507 const struct of_device_id
*match
)
509 struct edac_device_ctl_info
*edac_dev
;
510 struct mpc85xx_l2_pdata
*pdata
;
514 if (!devres_open_group(&op
->dev
, mpc85xx_l2_err_probe
, GFP_KERNEL
))
517 edac_dev
= edac_device_alloc_ctl_info(sizeof(*pdata
),
518 "cpu", 1, "L", 1, 2, NULL
, 0,
521 devres_release_group(&op
->dev
, mpc85xx_l2_err_probe
);
525 pdata
= edac_dev
->pvt_info
;
526 pdata
->name
= "mpc85xx_l2_err";
528 edac_dev
->dev
= &op
->dev
;
529 dev_set_drvdata(edac_dev
->dev
, edac_dev
);
530 edac_dev
->ctl_name
= pdata
->name
;
531 edac_dev
->dev_name
= pdata
->name
;
533 res
= of_address_to_resource(op
->dev
.of_node
, 0, &r
);
535 printk(KERN_ERR
"%s: Unable to get resource for "
536 "L2 err regs\n", __func__
);
540 /* we only need the error registers */
543 if (!devm_request_mem_region(&op
->dev
, r
.start
,
544 r
.end
- r
.start
+ 1, pdata
->name
)) {
545 printk(KERN_ERR
"%s: Error while requesting mem region\n",
551 pdata
->l2_vbase
= devm_ioremap(&op
->dev
, r
.start
, r
.end
- r
.start
+ 1);
552 if (!pdata
->l2_vbase
) {
553 printk(KERN_ERR
"%s: Unable to setup L2 err regs\n", __func__
);
558 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDET
, ~0);
560 orig_l2_err_disable
= in_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDIS
);
562 /* clear the err_dis */
563 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDIS
, 0);
565 edac_dev
->mod_name
= EDAC_MOD_STR
;
567 if (edac_op_state
== EDAC_OPSTATE_POLL
)
568 edac_dev
->edac_check
= mpc85xx_l2_check
;
570 mpc85xx_set_l2_sysfs_attributes(edac_dev
);
572 pdata
->edac_idx
= edac_dev_idx
++;
574 if (edac_device_add_device(edac_dev
) > 0) {
575 debugf3("%s(): failed edac_device_add_device()\n", __func__
);
579 if (edac_op_state
== EDAC_OPSTATE_INT
) {
580 pdata
->irq
= irq_of_parse_and_map(op
->dev
.of_node
, 0);
581 res
= devm_request_irq(&op
->dev
, pdata
->irq
,
582 mpc85xx_l2_isr
, IRQF_DISABLED
,
583 "[EDAC] L2 err", edac_dev
);
586 "%s: Unable to requiest irq %d for "
587 "MPC85xx L2 err\n", __func__
, pdata
->irq
);
588 irq_dispose_mapping(pdata
->irq
);
593 printk(KERN_INFO EDAC_MOD_STR
" acquired irq %d for L2 Err\n",
596 edac_dev
->op_state
= OP_RUNNING_INTERRUPT
;
598 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINTEN
, L2_EIE_MASK
);
601 devres_remove_group(&op
->dev
, mpc85xx_l2_err_probe
);
603 debugf3("%s(): success\n", __func__
);
604 printk(KERN_INFO EDAC_MOD_STR
" L2 err registered\n");
609 edac_device_del_device(&op
->dev
);
611 devres_release_group(&op
->dev
, mpc85xx_l2_err_probe
);
612 edac_device_free_ctl_info(edac_dev
);
616 static int mpc85xx_l2_err_remove(struct of_device
*op
)
618 struct edac_device_ctl_info
*edac_dev
= dev_get_drvdata(&op
->dev
);
619 struct mpc85xx_l2_pdata
*pdata
= edac_dev
->pvt_info
;
621 debugf0("%s()\n", __func__
);
623 if (edac_op_state
== EDAC_OPSTATE_INT
) {
624 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRINTEN
, 0);
625 irq_dispose_mapping(pdata
->irq
);
628 out_be32(pdata
->l2_vbase
+ MPC85XX_L2_ERRDIS
, orig_l2_err_disable
);
629 edac_device_del_device(&op
->dev
);
630 edac_device_free_ctl_info(edac_dev
);
634 static struct of_device_id mpc85xx_l2_err_of_match
[] = {
635 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
636 { .compatible
= "fsl,8540-l2-cache-controller", },
637 { .compatible
= "fsl,8541-l2-cache-controller", },
638 { .compatible
= "fsl,8544-l2-cache-controller", },
639 { .compatible
= "fsl,8548-l2-cache-controller", },
640 { .compatible
= "fsl,8555-l2-cache-controller", },
641 { .compatible
= "fsl,8568-l2-cache-controller", },
642 { .compatible
= "fsl,mpc8536-l2-cache-controller", },
643 { .compatible
= "fsl,mpc8540-l2-cache-controller", },
644 { .compatible
= "fsl,mpc8541-l2-cache-controller", },
645 { .compatible
= "fsl,mpc8544-l2-cache-controller", },
646 { .compatible
= "fsl,mpc8548-l2-cache-controller", },
647 { .compatible
= "fsl,mpc8555-l2-cache-controller", },
648 { .compatible
= "fsl,mpc8560-l2-cache-controller", },
649 { .compatible
= "fsl,mpc8568-l2-cache-controller", },
650 { .compatible
= "fsl,mpc8572-l2-cache-controller", },
651 { .compatible
= "fsl,p2020-l2-cache-controller", },
654 MODULE_DEVICE_TABLE(of
, mpc85xx_l2_err_of_match
);
656 static struct of_platform_driver mpc85xx_l2_err_driver
= {
657 .probe
= mpc85xx_l2_err_probe
,
658 .remove
= mpc85xx_l2_err_remove
,
660 .name
= "mpc85xx_l2_err",
661 .owner
= THIS_MODULE
,
662 .of_match_table
= mpc85xx_l2_err_of_match
,
666 /**************************** MC Err device ***************************/
669 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
670 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
671 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
672 * below correspond to Freescale's manuals.
674 static unsigned int ecc_table
[16] = {
677 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
678 0x00ff00ff, 0x00fff0ff,
679 0x0f0f0f0f, 0x0f0fff00,
680 0x11113333, 0x7777000f,
681 0x22224444, 0x8888222f,
682 0x44448888, 0xffff4441,
683 0x8888ffff, 0x11118882,
684 0xffff1111, 0x22221114, /* Syndrome bit 0 */
688 * Calculate the correct ECC value for a 64-bit value specified by high:low
690 static u8
calculate_ecc(u32 high
, u32 low
)
699 for (i
= 0; i
< 8; i
++) {
700 mask_high
= ecc_table
[i
* 2];
701 mask_low
= ecc_table
[i
* 2 + 1];
704 for (j
= 0; j
< 32; j
++) {
705 if ((mask_high
>> j
) & 1)
706 bit_cnt
^= (high
>> j
) & 1;
707 if ((mask_low
>> j
) & 1)
708 bit_cnt
^= (low
>> j
) & 1;
718 * Create the syndrome code which is generated if the data line specified by
719 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
720 * User's Manual and 9-61 in the MPC8572 User's Manual.
722 static u8
syndrome_from_bit(unsigned int bit
) {
727 * Cycle through the upper or lower 32-bit portion of each value in
728 * ecc_table depending on if 'bit' is in the upper or lower half of
731 for (i
= bit
< 32; i
< 16; i
+= 2)
732 syndrome
|= ((ecc_table
[i
] >> (bit
% 32)) & 1) << (i
/ 2);
738 * Decode data and ecc syndrome to determine what went wrong
739 * Note: This can only decode single-bit errors
741 static void sbe_ecc_decode(u32 cap_high
, u32 cap_low
, u32 cap_ecc
,
742 int *bad_data_bit
, int *bad_ecc_bit
)
751 * Calculate the ECC of the captured data and XOR it with the captured
752 * ECC to find an ECC syndrome value we can search for
754 syndrome
= calculate_ecc(cap_high
, cap_low
) ^ cap_ecc
;
756 /* Check if a data line is stuck... */
757 for (i
= 0; i
< 64; i
++) {
758 if (syndrome
== syndrome_from_bit(i
)) {
764 /* If data is correct, check ECC bits for errors... */
765 for (i
= 0; i
< 8; i
++) {
766 if ((syndrome
>> i
) & 0x1) {
773 static void mpc85xx_mc_check(struct mem_ctl_info
*mci
)
775 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
776 struct csrow_info
*csrow
;
788 err_detect
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DETECT
);
792 mpc85xx_mc_printk(mci
, KERN_ERR
, "Err Detect Register: %#8.8x\n",
795 /* no more processing if not ECC bit errors */
796 if (!(err_detect
& (DDR_EDE_SBE
| DDR_EDE_MBE
))) {
797 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DETECT
, err_detect
);
801 syndrome
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_CAPTURE_ECC
);
803 /* Mask off appropriate bits of syndrome based on bus width */
804 bus_width
= (in_be32(pdata
->mc_vbase
+ MPC85XX_MC_DDR_SDRAM_CFG
) &
805 DSC_DBW_MASK
) ? 32 : 64;
811 err_addr
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_CAPTURE_ADDRESS
);
812 pfn
= err_addr
>> PAGE_SHIFT
;
814 for (row_index
= 0; row_index
< mci
->nr_csrows
; row_index
++) {
815 csrow
= &mci
->csrows
[row_index
];
816 if ((pfn
>= csrow
->first_page
) && (pfn
<= csrow
->last_page
))
820 cap_high
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_CAPTURE_DATA_HI
);
821 cap_low
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_CAPTURE_DATA_LO
);
824 * Analyze single-bit errors on 64-bit wide buses
825 * TODO: Add support for 32-bit wide buses
827 if ((err_detect
& DDR_EDE_SBE
) && (bus_width
== 64)) {
828 sbe_ecc_decode(cap_high
, cap_low
, syndrome
,
829 &bad_data_bit
, &bad_ecc_bit
);
831 if (bad_data_bit
!= -1)
832 mpc85xx_mc_printk(mci
, KERN_ERR
,
833 "Faulty Data bit: %d\n", bad_data_bit
);
834 if (bad_ecc_bit
!= -1)
835 mpc85xx_mc_printk(mci
, KERN_ERR
,
836 "Faulty ECC bit: %d\n", bad_ecc_bit
);
838 mpc85xx_mc_printk(mci
, KERN_ERR
,
839 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
840 cap_high
^ (1 << (bad_data_bit
- 32)),
841 cap_low
^ (1 << bad_data_bit
),
842 syndrome
^ (1 << bad_ecc_bit
));
845 mpc85xx_mc_printk(mci
, KERN_ERR
,
846 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
847 cap_high
, cap_low
, syndrome
);
848 mpc85xx_mc_printk(mci
, KERN_ERR
, "Err addr: %#8.8x\n", err_addr
);
849 mpc85xx_mc_printk(mci
, KERN_ERR
, "PFN: %#8.8x\n", pfn
);
851 /* we are out of range */
852 if (row_index
== mci
->nr_csrows
)
853 mpc85xx_mc_printk(mci
, KERN_ERR
, "PFN out of range!\n");
855 if (err_detect
& DDR_EDE_SBE
)
856 edac_mc_handle_ce(mci
, pfn
, err_addr
& PAGE_MASK
,
857 syndrome
, row_index
, 0, mci
->ctl_name
);
859 if (err_detect
& DDR_EDE_MBE
)
860 edac_mc_handle_ue(mci
, pfn
, err_addr
& PAGE_MASK
,
861 row_index
, mci
->ctl_name
);
863 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DETECT
, err_detect
);
866 static irqreturn_t
mpc85xx_mc_isr(int irq
, void *dev_id
)
868 struct mem_ctl_info
*mci
= dev_id
;
869 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
872 err_detect
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DETECT
);
876 mpc85xx_mc_check(mci
);
881 static void __devinit
mpc85xx_init_csrows(struct mem_ctl_info
*mci
)
883 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
884 struct csrow_info
*csrow
;
891 sdram_ctl
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_DDR_SDRAM_CFG
);
893 sdtype
= sdram_ctl
& DSC_SDTYPE_MASK
;
894 if (sdram_ctl
& DSC_RD_EN
) {
899 case DSC_SDTYPE_DDR2
:
902 case DSC_SDTYPE_DDR3
:
914 case DSC_SDTYPE_DDR2
:
917 case DSC_SDTYPE_DDR3
:
926 for (index
= 0; index
< mci
->nr_csrows
; index
++) {
930 csrow
= &mci
->csrows
[index
];
931 cs_bnds
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_CS_BNDS_0
+
932 (index
* MPC85XX_MC_CS_BNDS_OFS
));
934 start
= (cs_bnds
& 0xffff0000) >> 16;
935 end
= (cs_bnds
& 0x0000ffff);
938 continue; /* not populated */
940 start
<<= (24 - PAGE_SHIFT
);
941 end
<<= (24 - PAGE_SHIFT
);
942 end
|= (1 << (24 - PAGE_SHIFT
)) - 1;
944 csrow
->first_page
= start
;
945 csrow
->last_page
= end
;
946 csrow
->nr_pages
= end
+ 1 - start
;
948 csrow
->mtype
= mtype
;
949 csrow
->dtype
= DEV_UNKNOWN
;
950 if (sdram_ctl
& DSC_X32_EN
)
951 csrow
->dtype
= DEV_X32
;
952 csrow
->edac_mode
= EDAC_SECDED
;
956 static int __devinit
mpc85xx_mc_err_probe(struct of_device
*op
,
957 const struct of_device_id
*match
)
959 struct mem_ctl_info
*mci
;
960 struct mpc85xx_mc_pdata
*pdata
;
965 if (!devres_open_group(&op
->dev
, mpc85xx_mc_err_probe
, GFP_KERNEL
))
968 mci
= edac_mc_alloc(sizeof(*pdata
), 4, 1, edac_mc_idx
);
970 devres_release_group(&op
->dev
, mpc85xx_mc_err_probe
);
974 pdata
= mci
->pvt_info
;
975 pdata
->name
= "mpc85xx_mc_err";
978 pdata
->edac_idx
= edac_mc_idx
++;
979 dev_set_drvdata(mci
->dev
, mci
);
980 mci
->ctl_name
= pdata
->name
;
981 mci
->dev_name
= pdata
->name
;
983 res
= of_address_to_resource(op
->dev
.of_node
, 0, &r
);
985 printk(KERN_ERR
"%s: Unable to get resource for MC err regs\n",
990 if (!devm_request_mem_region(&op
->dev
, r
.start
,
991 r
.end
- r
.start
+ 1, pdata
->name
)) {
992 printk(KERN_ERR
"%s: Error while requesting mem region\n",
998 pdata
->mc_vbase
= devm_ioremap(&op
->dev
, r
.start
, r
.end
- r
.start
+ 1);
999 if (!pdata
->mc_vbase
) {
1000 printk(KERN_ERR
"%s: Unable to setup MC err regs\n", __func__
);
1005 sdram_ctl
= in_be32(pdata
->mc_vbase
+ MPC85XX_MC_DDR_SDRAM_CFG
);
1006 if (!(sdram_ctl
& DSC_ECC_EN
)) {
1008 printk(KERN_WARNING
"%s: No ECC DIMMs discovered\n", __func__
);
1013 debugf3("%s(): init mci\n", __func__
);
1014 mci
->mtype_cap
= MEM_FLAG_RDDR
| MEM_FLAG_RDDR2
|
1015 MEM_FLAG_DDR
| MEM_FLAG_DDR2
;
1016 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
1017 mci
->edac_cap
= EDAC_FLAG_SECDED
;
1018 mci
->mod_name
= EDAC_MOD_STR
;
1019 mci
->mod_ver
= MPC85XX_REVISION
;
1021 if (edac_op_state
== EDAC_OPSTATE_POLL
)
1022 mci
->edac_check
= mpc85xx_mc_check
;
1024 mci
->ctl_page_to_phys
= NULL
;
1026 mci
->scrub_mode
= SCRUB_SW_SRC
;
1028 mpc85xx_set_mc_sysfs_attributes(mci
);
1030 mpc85xx_init_csrows(mci
);
1032 /* store the original error disable bits */
1033 orig_ddr_err_disable
=
1034 in_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DISABLE
);
1035 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DISABLE
, 0);
1037 /* clear all error bits */
1038 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DETECT
, ~0);
1040 if (edac_mc_add_mc(mci
)) {
1041 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
1045 if (edac_op_state
== EDAC_OPSTATE_INT
) {
1046 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_INT_EN
,
1047 DDR_EIE_MBEE
| DDR_EIE_SBEE
);
1049 /* store the original error management threshold */
1050 orig_ddr_err_sbe
= in_be32(pdata
->mc_vbase
+
1051 MPC85XX_MC_ERR_SBE
) & 0xff0000;
1053 /* set threshold to 1 error per interrupt */
1054 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_SBE
, 0x10000);
1056 /* register interrupts */
1057 pdata
->irq
= irq_of_parse_and_map(op
->dev
.of_node
, 0);
1058 res
= devm_request_irq(&op
->dev
, pdata
->irq
,
1060 IRQF_DISABLED
| IRQF_SHARED
,
1061 "[EDAC] MC err", mci
);
1063 printk(KERN_ERR
"%s: Unable to request irq %d for "
1064 "MPC85xx DRAM ERR\n", __func__
, pdata
->irq
);
1065 irq_dispose_mapping(pdata
->irq
);
1070 printk(KERN_INFO EDAC_MOD_STR
" acquired irq %d for MC\n",
1074 devres_remove_group(&op
->dev
, mpc85xx_mc_err_probe
);
1075 debugf3("%s(): success\n", __func__
);
1076 printk(KERN_INFO EDAC_MOD_STR
" MC err registered\n");
1081 edac_mc_del_mc(&op
->dev
);
1083 devres_release_group(&op
->dev
, mpc85xx_mc_err_probe
);
1088 static int mpc85xx_mc_err_remove(struct of_device
*op
)
1090 struct mem_ctl_info
*mci
= dev_get_drvdata(&op
->dev
);
1091 struct mpc85xx_mc_pdata
*pdata
= mci
->pvt_info
;
1093 debugf0("%s()\n", __func__
);
1095 if (edac_op_state
== EDAC_OPSTATE_INT
) {
1096 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_INT_EN
, 0);
1097 irq_dispose_mapping(pdata
->irq
);
1100 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_DISABLE
,
1101 orig_ddr_err_disable
);
1102 out_be32(pdata
->mc_vbase
+ MPC85XX_MC_ERR_SBE
, orig_ddr_err_sbe
);
1104 edac_mc_del_mc(&op
->dev
);
1109 static struct of_device_id mpc85xx_mc_err_of_match
[] = {
1110 /* deprecate the fsl,85.. forms in the future, 2.6.30? */
1111 { .compatible
= "fsl,8540-memory-controller", },
1112 { .compatible
= "fsl,8541-memory-controller", },
1113 { .compatible
= "fsl,8544-memory-controller", },
1114 { .compatible
= "fsl,8548-memory-controller", },
1115 { .compatible
= "fsl,8555-memory-controller", },
1116 { .compatible
= "fsl,8568-memory-controller", },
1117 { .compatible
= "fsl,mpc8536-memory-controller", },
1118 { .compatible
= "fsl,mpc8540-memory-controller", },
1119 { .compatible
= "fsl,mpc8541-memory-controller", },
1120 { .compatible
= "fsl,mpc8544-memory-controller", },
1121 { .compatible
= "fsl,mpc8548-memory-controller", },
1122 { .compatible
= "fsl,mpc8555-memory-controller", },
1123 { .compatible
= "fsl,mpc8560-memory-controller", },
1124 { .compatible
= "fsl,mpc8568-memory-controller", },
1125 { .compatible
= "fsl,mpc8569-memory-controller", },
1126 { .compatible
= "fsl,mpc8572-memory-controller", },
1127 { .compatible
= "fsl,mpc8349-memory-controller", },
1128 { .compatible
= "fsl,p2020-memory-controller", },
1131 MODULE_DEVICE_TABLE(of
, mpc85xx_mc_err_of_match
);
1133 static struct of_platform_driver mpc85xx_mc_err_driver
= {
1134 .probe
= mpc85xx_mc_err_probe
,
1135 .remove
= mpc85xx_mc_err_remove
,
1137 .name
= "mpc85xx_mc_err",
1138 .owner
= THIS_MODULE
,
1139 .of_match_table
= mpc85xx_mc_err_of_match
,
1143 #ifdef CONFIG_MPC85xx
1144 static void __init
mpc85xx_mc_clear_rfxe(void *data
)
1146 orig_hid1
[smp_processor_id()] = mfspr(SPRN_HID1
);
1147 mtspr(SPRN_HID1
, (orig_hid1
[smp_processor_id()] & ~0x20000));
1151 static int __init
mpc85xx_mc_init(void)
1155 printk(KERN_INFO
"Freescale(R) MPC85xx EDAC driver, "
1156 "(C) 2006 Montavista Software\n");
1158 /* make sure error reporting method is sane */
1159 switch (edac_op_state
) {
1160 case EDAC_OPSTATE_POLL
:
1161 case EDAC_OPSTATE_INT
:
1164 edac_op_state
= EDAC_OPSTATE_INT
;
1168 res
= of_register_platform_driver(&mpc85xx_mc_err_driver
);
1170 printk(KERN_WARNING EDAC_MOD_STR
"MC fails to register\n");
1172 res
= of_register_platform_driver(&mpc85xx_l2_err_driver
);
1174 printk(KERN_WARNING EDAC_MOD_STR
"L2 fails to register\n");
1177 res
= of_register_platform_driver(&mpc85xx_pci_err_driver
);
1179 printk(KERN_WARNING EDAC_MOD_STR
"PCI fails to register\n");
1182 #ifdef CONFIG_MPC85xx
1184 * need to clear HID1[RFXE] to disable machine check int
1185 * so we can catch it
1187 if (edac_op_state
== EDAC_OPSTATE_INT
)
1188 on_each_cpu(mpc85xx_mc_clear_rfxe
, NULL
, 0);
1194 module_init(mpc85xx_mc_init
);
1196 #ifdef CONFIG_MPC85xx
1197 static void __exit
mpc85xx_mc_restore_hid1(void *data
)
1199 mtspr(SPRN_HID1
, orig_hid1
[smp_processor_id()]);
1203 static void __exit
mpc85xx_mc_exit(void)
1205 #ifdef CONFIG_MPC85xx
1206 on_each_cpu(mpc85xx_mc_restore_hid1
, NULL
, 0);
1209 of_unregister_platform_driver(&mpc85xx_pci_err_driver
);
1211 of_unregister_platform_driver(&mpc85xx_l2_err_driver
);
1212 of_unregister_platform_driver(&mpc85xx_mc_err_driver
);
1215 module_exit(mpc85xx_mc_exit
);
1217 MODULE_LICENSE("GPL");
1218 MODULE_AUTHOR("Montavista Software, Inc.");
1219 module_param(edac_op_state
, int, 0444);
1220 MODULE_PARM_DESC(edac_op_state
,
1221 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");