drivers/net/gianfar.h

   1 /*
   2  * drivers/net/gianfar.h
   3  *
   4  * Gianfar Ethernet Driver
   5  * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  *
  11  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  *  Still left to do:
  19  *      -Add support for module parameters
  20  *      -Add patch for ethtool phys id
  21  */
  22 #ifndef __GIANFAR_H
  23 #define __GIANFAR_H
  24
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/string.h>
  28 #include <linux/errno.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/mm.h>
  38 #include <linux/mii.h>
  39 #include <linux/phy.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/uaccess.h>
  44 #include <linux/module.h>
  45 #include <linux/crc32.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/ethtool.h>
  48 #include <linux/fsl_devices.h>
  49 #include "gianfar_mii.h"
  50
  51 /* The maximum number of packets to be handled in one call of gfar_poll */
  52 #define GFAR_DEV_WEIGHT 64
  53
  54 /* Length for FCB */
  55 #define GMAC_FCB_LEN 8
  56
  57 /* Default padding amount */
  58 #define DEFAULT_PADDING 2
  59
  60 /* Number of bytes to align the rx bufs to */
  61 #define RXBUF_ALIGNMENT 64
  62
  63 /* The number of bytes which composes a unit for the purpose of
  64  * allocating data buffers.  ie-for any given MTU, the data buffer
  65  * will be the next highest multiple of 512 bytes. */
  66 #define INCREMENTAL_BUFFER_SIZE 512
  67
  68
  69 #define MAC_ADDR_LEN 6
  70
  71 #define PHY_INIT_TIMEOUT 100000
  72 #define GFAR_PHY_CHANGE_TIME 2
  73
  74 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
  75 #define DRV_NAME "gfar-enet"
  76 extern const char gfar_driver_name[];
  77 extern const char gfar_driver_version[];
  78
  79 /* These need to be powers of 2 for this driver */
  80 #define DEFAULT_TX_RING_SIZE    256
  81 #define DEFAULT_RX_RING_SIZE    256
  82
  83 #define GFAR_RX_MAX_RING_SIZE   256
  84 #define GFAR_TX_MAX_RING_SIZE   256
  85
  86 #define GFAR_MAX_FIFO_THRESHOLD 511
  87 #define GFAR_MAX_FIFO_STARVE    511
  88 #define GFAR_MAX_FIFO_STARVE_OFF 511
  89
  90 #define DEFAULT_RX_BUFFER_SIZE  1536
  91 #define TX_RING_MOD_MASK(size) (size-1)
  92 #define RX_RING_MOD_MASK(size) (size-1)
  93 #define JUMBO_BUFFER_SIZE 9728
  94 #define JUMBO_FRAME_SIZE 9600
  95
  96 #define DEFAULT_FIFO_TX_THR 0x100
  97 #define DEFAULT_FIFO_TX_STARVE 0x40
  98 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
  99 #define DEFAULT_BD_STASH 1
 100 #define DEFAULT_STASH_LENGTH    96
 101 #define DEFAULT_STASH_INDEX     0
 102
 103 /* The number of Exact Match registers */
 104 #define GFAR_EM_NUM     15
 105
 106 /* Latency of interface clock in nanoseconds */
 107 /* Interface clock latency , in this case, means the
 108  * time described by a value of 1 in the interrupt
 109  * coalescing registers' time fields.  Since those fields
 110  * refer to the time it takes for 64 clocks to pass, the
 111  * latencies are as such:
 112  * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 113  * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 114  * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 115  */
 116 #define GFAR_GBIT_TIME  512
 117 #define GFAR_100_TIME   2560
 118 #define GFAR_10_TIME    25600
 119
 120 #define DEFAULT_TX_COALESCE 1
 121 #define DEFAULT_TXCOUNT 16
 122 #define DEFAULT_TXTIME  21
 123
 124 #define DEFAULT_RXTIME  21
 125
 126 #define DEFAULT_RX_COALESCE 0
 127 #define DEFAULT_RXCOUNT 0
 128
 129 #define MIIMCFG_INIT_VALUE      0x00000007
 130 #define MIIMCFG_RESET           0x80000000
 131 #define MIIMIND_BUSY            0x00000001
 132
 133 /* TBI register addresses */
 134 #define MII_TBICON              0x11
 135
 136 /* TBICON register bit fields */
 137 #define TBICON_CLK_SELECT       0x0020
 138
 139 /* MAC register bits */
 140 #define MACCFG1_SOFT_RESET      0x80000000
 141 #define MACCFG1_RESET_RX_MC     0x00080000
 142 #define MACCFG1_RESET_TX_MC     0x00040000
 143 #define MACCFG1_RESET_RX_FUN    0x00020000
 144 #define MACCFG1_RESET_TX_FUN    0x00010000
 145 #define MACCFG1_LOOPBACK        0x00000100
 146 #define MACCFG1_RX_FLOW         0x00000020
 147 #define MACCFG1_TX_FLOW         0x00000010
 148 #define MACCFG1_SYNCD_RX_EN     0x00000008
 149 #define MACCFG1_RX_EN           0x00000004
 150 #define MACCFG1_SYNCD_TX_EN     0x00000002
 151 #define MACCFG1_TX_EN           0x00000001
 152
 153 #define MACCFG2_INIT_SETTINGS   0x00007205
 154 #define MACCFG2_FULL_DUPLEX     0x00000001
 155 #define MACCFG2_IF              0x00000300
 156 #define MACCFG2_MII             0x00000100
 157 #define MACCFG2_GMII            0x00000200
 158 #define MACCFG2_HUGEFRAME       0x00000020
 159 #define MACCFG2_LENGTHCHECK     0x00000010
 160 #define MACCFG2_MPEN            0x00000008
 161
 162 #define ECNTRL_INIT_SETTINGS    0x00001000
 163 #define ECNTRL_TBI_MODE         0x00000020
 164 #define ECNTRL_REDUCED_MODE     0x00000010
 165 #define ECNTRL_R100             0x00000008
 166 #define ECNTRL_REDUCED_MII_MODE 0x00000004
 167 #define ECNTRL_SGMII_MODE       0x00000002
 168
 169 #define MRBLR_INIT_SETTINGS     DEFAULT_RX_BUFFER_SIZE
 170
 171 #define MINFLR_INIT_SETTINGS    0x00000040
 172
 173 /* Init to do tx snooping for buffers and descriptors */
 174 #define DMACTRL_INIT_SETTINGS   0x000000c3
 175 #define DMACTRL_GRS             0x00000010
 176 #define DMACTRL_GTS             0x00000008
 177
 178 #define TSTAT_CLEAR_THALT       0x80000000
 179
 180 /* Interrupt coalescing macros */
 181 #define IC_ICEN                 0x80000000
 182 #define IC_ICFT_MASK            0x1fe00000
 183 #define IC_ICFT_SHIFT           21
 184 #define mk_ic_icft(x)           \
 185         (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
 186 #define IC_ICTT_MASK            0x0000ffff
 187 #define mk_ic_ictt(x)           (x&IC_ICTT_MASK)
 188
 189 #define mk_ic_value(count, time) (IC_ICEN | \
 190                                 mk_ic_icft(count) | \
 191                                 mk_ic_ictt(time))
 192
 193 #define RCTRL_PAL_MASK          0x001f0000
 194 #define RCTRL_VLEX              0x00002000
 195 #define RCTRL_FILREN            0x00001000
 196 #define RCTRL_GHTX              0x00000400
 197 #define RCTRL_IPCSEN            0x00000200
 198 #define RCTRL_TUCSEN            0x00000100
 199 #define RCTRL_PRSDEP_MASK       0x000000c0
 200 #define RCTRL_PRSDEP_INIT       0x000000c0
 201 #define RCTRL_PROM              0x00000008
 202 #define RCTRL_EMEN              0x00000002
 203 #define RCTRL_CHECKSUMMING      (RCTRL_IPCSEN \
 204                 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
 205 #define RCTRL_EXTHASH           (RCTRL_GHTX)
 206 #define RCTRL_VLAN              (RCTRL_PRSDEP_INIT)
 207 #define RCTRL_PADDING(x)        ((x << 16) & RCTRL_PAL_MASK)
 208
 209
 210 #define RSTAT_CLEAR_RHALT       0x00800000
 211
 212 #define TCTRL_IPCSEN            0x00004000
 213 #define TCTRL_TUCSEN            0x00002000
 214 #define TCTRL_VLINS             0x00001000
 215 #define TCTRL_INIT_CSUM         (TCTRL_TUCSEN | TCTRL_IPCSEN)
 216
 217 #define IEVENT_INIT_CLEAR       0xffffffff
 218 #define IEVENT_BABR             0x80000000
 219 #define IEVENT_RXC              0x40000000
 220 #define IEVENT_BSY              0x20000000
 221 #define IEVENT_EBERR            0x10000000
 222 #define IEVENT_MSRO             0x04000000
 223 #define IEVENT_GTSC             0x02000000
 224 #define IEVENT_BABT             0x01000000
 225 #define IEVENT_TXC              0x00800000
 226 #define IEVENT_TXE              0x00400000
 227 #define IEVENT_TXB              0x00200000
 228 #define IEVENT_TXF              0x00100000
 229 #define IEVENT_LC               0x00040000
 230 #define IEVENT_CRL              0x00020000
 231 #define IEVENT_XFUN             0x00010000
 232 #define IEVENT_RXB0             0x00008000
 233 #define IEVENT_MAG              0x00000800
 234 #define IEVENT_GRSC             0x00000100
 235 #define IEVENT_RXF0             0x00000080
 236 #define IEVENT_FIR              0x00000008
 237 #define IEVENT_FIQ              0x00000004
 238 #define IEVENT_DPE              0x00000002
 239 #define IEVENT_PERR             0x00000001
 240 #define IEVENT_RX_MASK          (IEVENT_RXB0 | IEVENT_RXF0)
 241 #define IEVENT_TX_MASK          (IEVENT_TXB | IEVENT_TXF)
 242 #define IEVENT_RTX_MASK         (IEVENT_RX_MASK | IEVENT_TX_MASK)
 243 #define IEVENT_ERR_MASK         \
 244 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
 245  IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
 246  | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
 247  | IEVENT_MAG)
 248
 249 #define IMASK_INIT_CLEAR        0x00000000
 250 #define IMASK_BABR              0x80000000
 251 #define IMASK_RXC               0x40000000
 252 #define IMASK_BSY               0x20000000
 253 #define IMASK_EBERR             0x10000000
 254 #define IMASK_MSRO              0x04000000
 255 #define IMASK_GRSC              0x02000000
 256 #define IMASK_BABT              0x01000000
 257 #define IMASK_TXC               0x00800000
 258 #define IMASK_TXEEN             0x00400000
 259 #define IMASK_TXBEN             0x00200000
 260 #define IMASK_TXFEN             0x00100000
 261 #define IMASK_LC                0x00040000
 262 #define IMASK_CRL               0x00020000
 263 #define IMASK_XFUN              0x00010000
 264 #define IMASK_RXB0              0x00008000
 265 #define IMASK_MAG               0x00000800
 266 #define IMASK_GTSC              0x00000100
 267 #define IMASK_RXFEN0            0x00000080
 268 #define IMASK_FIR               0x00000008
 269 #define IMASK_FIQ               0x00000004
 270 #define IMASK_DPE               0x00000002
 271 #define IMASK_PERR              0x00000001
 272 #define IMASK_DEFAULT  (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
 273                 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
 274                 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
 275                 | IMASK_PERR)
 276 #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
 277                            & IMASK_DEFAULT)
 278
 279 /* Fifo management */
 280 #define FIFO_TX_THR_MASK        0x01ff
 281 #define FIFO_TX_STARVE_MASK     0x01ff
 282 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
 283
 284 /* Attribute fields */
 285
 286 /* This enables rx snooping for buffers and descriptors */
 287 #define ATTR_BDSTASH            0x00000800
 288
 289 #define ATTR_BUFSTASH           0x00004000
 290
 291 #define ATTR_SNOOPING           0x000000c0
 292 #define ATTR_INIT_SETTINGS      ATTR_SNOOPING
 293
 294 #define ATTRELI_INIT_SETTINGS   0x0
 295 #define ATTRELI_EL_MASK         0x3fff0000
 296 #define ATTRELI_EL(x) (x << 16)
 297 #define ATTRELI_EI_MASK         0x00003fff
 298 #define ATTRELI_EI(x) (x)
 299
 300
 301 /* TxBD status field bits */
 302 #define TXBD_READY              0x8000
 303 #define TXBD_PADCRC             0x4000
 304 #define TXBD_WRAP               0x2000
 305 #define TXBD_INTERRUPT          0x1000
 306 #define TXBD_LAST               0x0800
 307 #define TXBD_CRC                0x0400
 308 #define TXBD_DEF                0x0200
 309 #define TXBD_HUGEFRAME          0x0080
 310 #define TXBD_LATECOLLISION      0x0080
 311 #define TXBD_RETRYLIMIT         0x0040
 312 #define TXBD_RETRYCOUNTMASK     0x003c
 313 #define TXBD_UNDERRUN           0x0002
 314 #define TXBD_TOE                0x0002
 315
 316 /* Tx FCB param bits */
 317 #define TXFCB_VLN               0x80
 318 #define TXFCB_IP                0x40
 319 #define TXFCB_IP6               0x20
 320 #define TXFCB_TUP               0x10
 321 #define TXFCB_UDP               0x08
 322 #define TXFCB_CIP               0x04
 323 #define TXFCB_CTU               0x02
 324 #define TXFCB_NPH               0x01
 325 #define TXFCB_DEFAULT           (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
 326
 327 /* RxBD status field bits */
 328 #define RXBD_EMPTY              0x8000
 329 #define RXBD_RO1                0x4000
 330 #define RXBD_WRAP               0x2000
 331 #define RXBD_INTERRUPT          0x1000
 332 #define RXBD_LAST               0x0800
 333 #define RXBD_FIRST              0x0400
 334 #define RXBD_MISS               0x0100
 335 #define RXBD_BROADCAST          0x0080
 336 #define RXBD_MULTICAST          0x0040
 337 #define RXBD_LARGE              0x0020
 338 #define RXBD_NONOCTET           0x0010
 339 #define RXBD_SHORT              0x0008
 340 #define RXBD_CRCERR             0x0004
 341 #define RXBD_OVERRUN            0x0002
 342 #define RXBD_TRUNCATED          0x0001
 343 #define RXBD_STATS              0x01ff
 344 #define RXBD_ERR                (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET        \
 345                                 | RXBD_CRCERR | RXBD_OVERRUN                    \
 346                                 | RXBD_TRUNCATED)
 347
 348 /* Rx FCB status field bits */
 349 #define RXFCB_VLN               0x8000
 350 #define RXFCB_IP                0x4000
 351 #define RXFCB_IP6               0x2000
 352 #define RXFCB_TUP               0x1000
 353 #define RXFCB_CIP               0x0800
 354 #define RXFCB_CTU               0x0400
 355 #define RXFCB_EIP               0x0200
 356 #define RXFCB_ETU               0x0100
 357 #define RXFCB_CSUM_MASK         0x0f00
 358 #define RXFCB_PERR_MASK         0x000c
 359 #define RXFCB_PERR_BADL3        0x0008
 360
 361 struct txbd8
 362 {
 363         u16     status; /* Status Fields */
 364         u16     length; /* Buffer length */
 365         u32     bufPtr; /* Buffer Pointer */
 366 };
 367
 368 struct txfcb {
 369         u8      flags;
 370         u8      reserved;
 371         u8      l4os;   /* Level 4 Header Offset */
 372         u8      l3os;   /* Level 3 Header Offset */
 373         u16     phcs;   /* Pseudo-header Checksum */
 374         u16     vlctl;  /* VLAN control word */
 375 };
 376
 377 struct rxbd8
 378 {
 379         u16     status; /* Status Fields */
 380         u16     length; /* Buffer Length */
 381         u32     bufPtr; /* Buffer Pointer */
 382 };
 383
 384 struct rxfcb {
 385         u16     flags;
 386         u8      rq;     /* Receive Queue index */
 387         u8      pro;    /* Layer 4 Protocol */
 388         u16     reserved;
 389         u16     vlctl;  /* VLAN control word */
 390 };
 391
 392 struct rmon_mib
 393 {
 394         u32     tr64;   /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
 395         u32     tr127;  /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
 396         u32     tr255;  /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
 397         u32     tr511;  /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
 398         u32     tr1k;   /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
 399         u32     trmax;  /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
 400         u32     trmgv;  /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 401         u32     rbyt;   /* 0x.69c - Receive Byte Counter */
 402         u32     rpkt;   /* 0x.6a0 - Receive Packet Counter */
 403         u32     rfcs;   /* 0x.6a4 - Receive FCS Error Counter */
 404         u32     rmca;   /* 0x.6a8 - Receive Multicast Packet Counter */
 405         u32     rbca;   /* 0x.6ac - Receive Broadcast Packet Counter */
 406         u32     rxcf;   /* 0x.6b0 - Receive Control Frame Packet Counter */
 407         u32     rxpf;   /* 0x.6b4 - Receive Pause Frame Packet Counter */
 408         u32     rxuo;   /* 0x.6b8 - Receive Unknown OP Code Counter */
 409         u32     raln;   /* 0x.6bc - Receive Alignment Error Counter */
 410         u32     rflr;   /* 0x.6c0 - Receive Frame Length Error Counter */
 411         u32     rcde;   /* 0x.6c4 - Receive Code Error Counter */
 412         u32     rcse;   /* 0x.6c8 - Receive Carrier Sense Error Counter */
 413         u32     rund;   /* 0x.6cc - Receive Undersize Packet Counter */
 414         u32     rovr;   /* 0x.6d0 - Receive Oversize Packet Counter */
 415         u32     rfrg;   /* 0x.6d4 - Receive Fragments Counter */
 416         u32     rjbr;   /* 0x.6d8 - Receive Jabber Counter */
 417         u32     rdrp;   /* 0x.6dc - Receive Drop Counter */
 418         u32     tbyt;   /* 0x.6e0 - Transmit Byte Counter Counter */
 419         u32     tpkt;   /* 0x.6e4 - Transmit Packet Counter */
 420         u32     tmca;   /* 0x.6e8 - Transmit Multicast Packet Counter */
 421         u32     tbca;   /* 0x.6ec - Transmit Broadcast Packet Counter */
 422         u32     txpf;   /* 0x.6f0 - Transmit Pause Control Frame Counter */
 423         u32     tdfr;   /* 0x.6f4 - Transmit Deferral Packet Counter */
 424         u32     tedf;   /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
 425         u32     tscl;   /* 0x.6fc - Transmit Single Collision Packet Counter */
 426         u32     tmcl;   /* 0x.700 - Transmit Multiple Collision Packet Counter */
 427         u32     tlcl;   /* 0x.704 - Transmit Late Collision Packet Counter */
 428         u32     txcl;   /* 0x.708 - Transmit Excessive Collision Packet Counter */
 429         u32     tncl;   /* 0x.70c - Transmit Total Collision Counter */
 430         u8      res1[4];
 431         u32     tdrp;   /* 0x.714 - Transmit Drop Frame Counter */
 432         u32     tjbr;   /* 0x.718 - Transmit Jabber Frame Counter */
 433         u32     tfcs;   /* 0x.71c - Transmit FCS Error Counter */
 434         u32     txcf;   /* 0x.720 - Transmit Control Frame Counter */
 435         u32     tovr;   /* 0x.724 - Transmit Oversize Frame Counter */
 436         u32     tund;   /* 0x.728 - Transmit Undersize Frame Counter */
 437         u32     tfrg;   /* 0x.72c - Transmit Fragments Frame Counter */
 438         u32     car1;   /* 0x.730 - Carry Register One */
 439         u32     car2;   /* 0x.734 - Carry Register Two */
 440         u32     cam1;   /* 0x.738 - Carry Mask Register One */
 441         u32     cam2;   /* 0x.73c - Carry Mask Register Two */
 442 };
 443
 444 struct gfar_extra_stats {
 445         u64 kernel_dropped;
 446         u64 rx_large;
 447         u64 rx_short;
 448         u64 rx_nonoctet;
 449         u64 rx_crcerr;
 450         u64 rx_overrun;
 451         u64 rx_bsy;
 452         u64 rx_babr;
 453         u64 rx_trunc;
 454         u64 eberr;
 455         u64 tx_babt;
 456         u64 tx_underrun;
 457         u64 rx_skbmissing;
 458         u64 tx_timeout;
 459 };
 460
 461 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
 462 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
 463
 464 /* Number of stats in the stats structure (ignore car and cam regs)*/
 465 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
 466
 467 #define GFAR_INFOSTR_LEN 32
 468
 469 struct gfar_stats {
 470         u64 extra[GFAR_EXTRA_STATS_LEN];
 471         u64 rmon[GFAR_RMON_LEN];
 472 };
 473
 474
 475 struct gfar {
 476         u32     tsec_id;        /* 0x.000 - Controller ID register */
 477         u8      res1[12];
 478         u32     ievent;         /* 0x.010 - Interrupt Event Register */
 479         u32     imask;          /* 0x.014 - Interrupt Mask Register */
 480         u32     edis;           /* 0x.018 - Error Disabled Register */
 481         u8      res2[4];
 482         u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
 483         u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
 484         u32     ptv;            /* 0x.028 - Pause Time Value Register */
 485         u32     dmactrl;        /* 0x.02c - DMA Control Register */
 486         u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
 487         u8      res3[88];
 488         u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
 489         u8      res4[8];
 490         u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
 491         u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
 492         u8      res5[4];
 493         u32     fifo_rx_pause;  /* 0x.0a4 - FIFO receive pause threshold register */
 494         u32     fifo_rx_alarm;  /* 0x.0a8 - FIFO receive alarm threshold register */
 495         u8      res6[84];
 496         u32     tctrl;          /* 0x.100 - Transmit Control Register */
 497         u32     tstat;          /* 0x.104 - Transmit Status Register */
 498         u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
 499         u32     tbdlen;         /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
 500         u32     txic;           /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
 501         u32     tqueue;         /* 0x.114 - Transmit queue control register */
 502         u8      res7[40];
 503         u32     tr03wt;         /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
 504         u32     tr47wt;         /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
 505         u8      res8[52];
 506         u32     tbdbph;         /* 0x.17c - Tx data buffer pointer high */
 507         u8      res9a[4];
 508         u32     tbptr0;         /* 0x.184 - TxBD Pointer for ring 0 */
 509         u8      res9b[4];
 510         u32     tbptr1;         /* 0x.18c - TxBD Pointer for ring 1 */
 511         u8      res9c[4];
 512         u32     tbptr2;         /* 0x.194 - TxBD Pointer for ring 2 */
 513         u8      res9d[4];
 514         u32     tbptr3;         /* 0x.19c - TxBD Pointer for ring 3 */
 515         u8      res9e[4];
 516         u32     tbptr4;         /* 0x.1a4 - TxBD Pointer for ring 4 */
 517         u8      res9f[4];
 518         u32     tbptr5;         /* 0x.1ac - TxBD Pointer for ring 5 */
 519         u8      res9g[4];
 520         u32     tbptr6;         /* 0x.1b4 - TxBD Pointer for ring 6 */
 521         u8      res9h[4];
 522         u32     tbptr7;         /* 0x.1bc - TxBD Pointer for ring 7 */
 523         u8      res9[64];
 524         u32     tbaseh;         /* 0x.200 - TxBD base address high */
 525         u32     tbase0;         /* 0x.204 - TxBD Base Address of ring 0 */
 526         u8      res10a[4];
 527         u32     tbase1;         /* 0x.20c - TxBD Base Address of ring 1 */
 528         u8      res10b[4];
 529         u32     tbase2;         /* 0x.214 - TxBD Base Address of ring 2 */
 530         u8      res10c[4];
 531         u32     tbase3;         /* 0x.21c - TxBD Base Address of ring 3 */
 532         u8      res10d[4];
 533         u32     tbase4;         /* 0x.224 - TxBD Base Address of ring 4 */
 534         u8      res10e[4];
 535         u32     tbase5;         /* 0x.22c - TxBD Base Address of ring 5 */
 536         u8      res10f[4];
 537         u32     tbase6;         /* 0x.234 - TxBD Base Address of ring 6 */
 538         u8      res10g[4];
 539         u32     tbase7;         /* 0x.23c - TxBD Base Address of ring 7 */
 540         u8      res10[192];
 541         u32     rctrl;          /* 0x.300 - Receive Control Register */
 542         u32     rstat;          /* 0x.304 - Receive Status Register */
 543         u8      res12[8];
 544         u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
 545         u32     rqueue;         /* 0x.314 - Receive queue control register */
 546         u8      res13[24];
 547         u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
 548         u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
 549         u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
 550         u32     rqfpr;          /* 0x.33c - Receive queue filing table property register */
 551         u32     mrblr;          /* 0x.340 - Maximum Receive Buffer Length Register */
 552         u8      res14[56];
 553         u32     rbdbph;         /* 0x.37c - Rx data buffer pointer high */
 554         u8      res15a[4];
 555         u32     rbptr0;         /* 0x.384 - RxBD pointer for ring 0 */
 556         u8      res15b[4];
 557         u32     rbptr1;         /* 0x.38c - RxBD pointer for ring 1 */
 558         u8      res15c[4];
 559         u32     rbptr2;         /* 0x.394 - RxBD pointer for ring 2 */
 560         u8      res15d[4];
 561         u32     rbptr3;         /* 0x.39c - RxBD pointer for ring 3 */
 562         u8      res15e[4];
 563         u32     rbptr4;         /* 0x.3a4 - RxBD pointer for ring 4 */
 564         u8      res15f[4];
 565         u32     rbptr5;         /* 0x.3ac - RxBD pointer for ring 5 */
 566         u8      res15g[4];
 567         u32     rbptr6;         /* 0x.3b4 - RxBD pointer for ring 6 */
 568         u8      res15h[4];
 569         u32     rbptr7;         /* 0x.3bc - RxBD pointer for ring 7 */
 570         u8      res16[64];
 571         u32     rbaseh;         /* 0x.400 - RxBD base address high */
 572         u32     rbase0;         /* 0x.404 - RxBD base address of ring 0 */
 573         u8      res17a[4];
 574         u32     rbase1;         /* 0x.40c - RxBD base address of ring 1 */
 575         u8      res17b[4];
 576         u32     rbase2;         /* 0x.414 - RxBD base address of ring 2 */
 577         u8      res17c[4];
 578         u32     rbase3;         /* 0x.41c - RxBD base address of ring 3 */
 579         u8      res17d[4];
 580         u32     rbase4;         /* 0x.424 - RxBD base address of ring 4 */
 581         u8      res17e[4];
 582         u32     rbase5;         /* 0x.42c - RxBD base address of ring 5 */
 583         u8      res17f[4];
 584         u32     rbase6;         /* 0x.434 - RxBD base address of ring 6 */
 585         u8      res17g[4];
 586         u32     rbase7;         /* 0x.43c - RxBD base address of ring 7 */
 587         u8      res17[192];
 588         u32     maccfg1;        /* 0x.500 - MAC Configuration 1 Register */
 589         u32     maccfg2;        /* 0x.504 - MAC Configuration 2 Register */
 590         u32     ipgifg;         /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
 591         u32     hafdup;         /* 0x.50c - Half Duplex Register */
 592         u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
 593         u8      res18[12];
 594         u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
 595         u8      res19[4];
 596         u32     ifstat;         /* 0x.53c - Interface Status Register */
 597         u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
 598         u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
 599         u32     mac01addr1;     /* 0x.548 - MAC exact match address 1, part 1 */
 600         u32     mac01addr2;     /* 0x.54c - MAC exact match address 1, part 2 */
 601         u32     mac02addr1;     /* 0x.550 - MAC exact match address 2, part 1 */
 602         u32     mac02addr2;     /* 0x.554 - MAC exact match address 2, part 2 */
 603         u32     mac03addr1;     /* 0x.558 - MAC exact match address 3, part 1 */
 604         u32     mac03addr2;     /* 0x.55c - MAC exact match address 3, part 2 */
 605         u32     mac04addr1;     /* 0x.560 - MAC exact match address 4, part 1 */
 606         u32     mac04addr2;     /* 0x.564 - MAC exact match address 4, part 2 */
 607         u32     mac05addr1;     /* 0x.568 - MAC exact match address 5, part 1 */
 608         u32     mac05addr2;     /* 0x.56c - MAC exact match address 5, part 2 */
 609         u32     mac06addr1;     /* 0x.570 - MAC exact match address 6, part 1 */
 610         u32     mac06addr2;     /* 0x.574 - MAC exact match address 6, part 2 */
 611         u32     mac07addr1;     /* 0x.578 - MAC exact match address 7, part 1 */
 612         u32     mac07addr2;     /* 0x.57c - MAC exact match address 7, part 2 */
 613         u32     mac08addr1;     /* 0x.580 - MAC exact match address 8, part 1 */
 614         u32     mac08addr2;     /* 0x.584 - MAC exact match address 8, part 2 */
 615         u32     mac09addr1;     /* 0x.588 - MAC exact match address 9, part 1 */
 616         u32     mac09addr2;     /* 0x.58c - MAC exact match address 9, part 2 */
 617         u32     mac10addr1;     /* 0x.590 - MAC exact match address 10, part 1*/
 618         u32     mac10addr2;     /* 0x.594 - MAC exact match address 10, part 2*/
 619         u32     mac11addr1;     /* 0x.598 - MAC exact match address 11, part 1*/
 620         u32     mac11addr2;     /* 0x.59c - MAC exact match address 11, part 2*/
 621         u32     mac12addr1;     /* 0x.5a0 - MAC exact match address 12, part 1*/
 622         u32     mac12addr2;     /* 0x.5a4 - MAC exact match address 12, part 2*/
 623         u32     mac13addr1;     /* 0x.5a8 - MAC exact match address 13, part 1*/
 624         u32     mac13addr2;     /* 0x.5ac - MAC exact match address 13, part 2*/
 625         u32     mac14addr1;     /* 0x.5b0 - MAC exact match address 14, part 1*/
 626         u32     mac14addr2;     /* 0x.5b4 - MAC exact match address 14, part 2*/
 627         u32     mac15addr1;     /* 0x.5b8 - MAC exact match address 15, part 1*/
 628         u32     mac15addr2;     /* 0x.5bc - MAC exact match address 15, part 2*/
 629         u8      res20[192];
 630         struct rmon_mib rmon;   /* 0x.680-0x.73c */
 631         u32     rrej;           /* 0x.740 - Receive filer rejected packet counter */
 632         u8      res21[188];
 633         u32     igaddr0;        /* 0x.800 - Indivdual/Group address register 0*/
 634         u32     igaddr1;        /* 0x.804 - Indivdual/Group address register 1*/
 635         u32     igaddr2;        /* 0x.808 - Indivdual/Group address register 2*/
 636         u32     igaddr3;        /* 0x.80c - Indivdual/Group address register 3*/
 637         u32     igaddr4;        /* 0x.810 - Indivdual/Group address register 4*/
 638         u32     igaddr5;        /* 0x.814 - Indivdual/Group address register 5*/
 639         u32     igaddr6;        /* 0x.818 - Indivdual/Group address register 6*/
 640         u32     igaddr7;        /* 0x.81c - Indivdual/Group address register 7*/
 641         u8      res22[96];
 642         u32     gaddr0;         /* 0x.880 - Group address register 0 */
 643         u32     gaddr1;         /* 0x.884 - Group address register 1 */
 644         u32     gaddr2;         /* 0x.888 - Group address register 2 */
 645         u32     gaddr3;         /* 0x.88c - Group address register 3 */
 646         u32     gaddr4;         /* 0x.890 - Group address register 4 */
 647         u32     gaddr5;         /* 0x.894 - Group address register 5 */
 648         u32     gaddr6;         /* 0x.898 - Group address register 6 */
 649         u32     gaddr7;         /* 0x.89c - Group address register 7 */
 650         u8      res23a[352];
 651         u32     fifocfg;        /* 0x.a00 - FIFO interface config register */
 652         u8      res23b[252];
 653         u8      res23c[248];
 654         u32     attr;           /* 0x.bf8 - Attributes Register */
 655         u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
 656         u8      res24[1024];
 657
 658 };
 659
 660 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
 661  * (Ok, that's not so true anymore, but there is a family resemblence)
 662  * The GFAR buffer descriptors track the ring buffers.  The rx_bd_base
 663  * and tx_bd_base always point to the currently available buffer.
 664  * The dirty_tx tracks the current buffer that is being sent by the
 665  * controller.  The cur_tx and dirty_tx are equal under both completely
 666  * empty and completely full conditions.  The empty/ready indicator in
 667  * the buffer descriptor determines the actual condition.
 668  */
 669 struct gfar_private {
 670         /* Fields controlled by TX lock */
 671         spinlock_t txlock;
 672
 673         /* Pointer to the array of skbuffs */
 674         struct sk_buff ** tx_skbuff;
 675
 676         /* next free skb in the array */
 677         u16 skb_curtx;
 678
 679         /* First skb in line to be transmitted */
 680         u16 skb_dirtytx;
 681
 682         /* Configuration info for the coalescing features */
 683         unsigned char txcoalescing;
 684         unsigned short txcount;
 685         unsigned short txtime;
 686
 687         /* Buffer descriptor pointers */
 688         struct txbd8 *tx_bd_base;       /* First tx buffer descriptor */
 689         struct txbd8 *cur_tx;           /* Next free ring entry */
 690         struct txbd8 *dirty_tx;         /* First buffer in line
 691                                            to be transmitted */
 692         unsigned int tx_ring_size;
 693
 694         /* RX Locked fields */
 695         spinlock_t rxlock;
 696
 697         struct net_device *dev;
 698         struct napi_struct napi;
 699
 700         /* skb array and index */
 701         struct sk_buff ** rx_skbuff;
 702         u16 skb_currx;
 703
 704         /* RX Coalescing values */
 705         unsigned char rxcoalescing;
 706         unsigned short rxcount;
 707         unsigned short rxtime;
 708
 709         struct rxbd8 *rx_bd_base;       /* First Rx buffers */
 710         struct rxbd8 *cur_rx;           /* Next free rx ring entry */
 711
 712         /* RX parameters */
 713         unsigned int rx_ring_size;
 714         unsigned int rx_buffer_size;
 715         unsigned int rx_stash_size;
 716         unsigned int rx_stash_index;
 717
 718         struct vlan_group *vlgrp;
 719
 720         /* Unprotected fields */
 721         /* Pointer to the GFAR memory mapped Registers */
 722         struct gfar __iomem *regs;
 723
 724         /* Hash registers and their width */
 725         u32 __iomem *hash_regs[16];
 726         int hash_width;
 727
 728         /* global parameters */
 729         unsigned int fifo_threshold;
 730         unsigned int fifo_starve;
 731         unsigned int fifo_starve_off;
 732
 733         /* Bitfield update lock */
 734         spinlock_t bflock;
 735
 736         unsigned char vlan_enable:1,
 737                 rx_csum_enable:1,
 738                 extended_hash:1,
 739                 bd_stash_en:1,
 740                 wol_en:1; /* Wake-on-LAN enabled */
 741         unsigned short padding;
 742
 743         unsigned int interruptTransmit;
 744         unsigned int interruptReceive;
 745         unsigned int interruptError;
 746
 747         /* info structure initialized by platform code */
 748         struct gianfar_platform_data *einfo;
 749
 750         /* PHY stuff */
 751         struct phy_device *phydev;
 752         struct mii_bus *mii_bus;
 753         int oldspeed;
 754         int oldduplex;
 755         int oldlink;
 756
 757         uint32_t msg_enable;
 758
 759         struct work_struct reset_task;
 760         /* Network Statistics */
 761         struct gfar_extra_stats extra_stats;
 762 };
 763
 764 static inline u32 gfar_read(volatile unsigned __iomem *addr)
 765 {
 766         u32 val;
 767         val = in_be32(addr);
 768         return val;
 769 }
 770
 771 static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
 772 {
 773         out_be32(addr, val);
 774 }
 775
 776 extern irqreturn_t gfar_receive(int irq, void *dev_id);
 777 extern int startup_gfar(struct net_device *dev);
 778 extern void stop_gfar(struct net_device *dev);
 779 extern void gfar_halt(struct net_device *dev);
 780 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
 781                 int enable, u32 regnum, u32 read);
 782 void gfar_init_sysfs(struct net_device *dev);
 783 int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
 784                           int regnum, u16 value);
 785 int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
 786
 787 #endif /* __GIANFAR_H */