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ALSA: virtuoso: fix silent analog output on Xonar Essence ST Deluxe
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / cnic.c
blob11a92afdf982ef62be6a6097a88f768e9b3d599e
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/prefetch.h>
31 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
32 #define BCM_VLAN 1
33 #endif
34 #include <net/ip.h>
35 #include <net/tcp.h>
36 #include <net/route.h>
37 #include <net/ipv6.h>
38 #include <net/ip6_route.h>
39 #include <net/ip6_checksum.h>
40 #include <scsi/iscsi_if.h>
41
42 #include "cnic_if.h"
43 #include "bnx2.h"
44 #include "bnx2x/bnx2x_reg.h"
45 #include "bnx2x/bnx2x_fw_defs.h"
46 #include "bnx2x/bnx2x_hsi.h"
47 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
48 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
49 #include "cnic.h"
50 #include "cnic_defs.h"
51
52 #define DRV_MODULE_NAME "cnic"
53
54 static char version[] __devinitdata =
55 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
56
57 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
58 "Chen (zongxi@broadcom.com");
59 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
60 MODULE_LICENSE("GPL");
61 MODULE_VERSION(CNIC_MODULE_VERSION);
62
63 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
64 static LIST_HEAD(cnic_dev_list);
65 static LIST_HEAD(cnic_udev_list);
66 static DEFINE_RWLOCK(cnic_dev_lock);
67 static DEFINE_MUTEX(cnic_lock);
68
69 static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
70
71 /* helper function, assuming cnic_lock is held */
72 static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
73 {
74 return rcu_dereference_protected(cnic_ulp_tbl[type],
75 lockdep_is_held(&cnic_lock));
76 }
77
78 static int cnic_service_bnx2(void *, void *);
79 static int cnic_service_bnx2x(void *, void *);
80 static int cnic_ctl(void *, struct cnic_ctl_info *);
81
82 static struct cnic_ops cnic_bnx2_ops = {
83 .cnic_owner = THIS_MODULE,
84 .cnic_handler = cnic_service_bnx2,
85 .cnic_ctl = cnic_ctl,
86 };
87
88 static struct cnic_ops cnic_bnx2x_ops = {
89 .cnic_owner = THIS_MODULE,
90 .cnic_handler = cnic_service_bnx2x,
91 .cnic_ctl = cnic_ctl,
92 };
93
94 static struct workqueue_struct *cnic_wq;
95
96 static void cnic_shutdown_rings(struct cnic_dev *);
97 static void cnic_init_rings(struct cnic_dev *);
98 static int cnic_cm_set_pg(struct cnic_sock *);
99
100 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
101 {
102 struct cnic_uio_dev *udev = uinfo->priv;
103 struct cnic_dev *dev;
104
105 if (!capable(CAP_NET_ADMIN))
106 return -EPERM;
107
108 if (udev->uio_dev != -1)
109 return -EBUSY;
110
111 rtnl_lock();
112 dev = udev->dev;
113
114 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
115 rtnl_unlock();
116 return -ENODEV;
117 }
118
119 udev->uio_dev = iminor(inode);
120
121 cnic_shutdown_rings(dev);
122 cnic_init_rings(dev);
123 rtnl_unlock();
124
125 return 0;
126 }
127
128 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
129 {
130 struct cnic_uio_dev *udev = uinfo->priv;
131
132 udev->uio_dev = -1;
133 return 0;
134 }
135
136 static inline void cnic_hold(struct cnic_dev *dev)
137 {
138 atomic_inc(&dev->ref_count);
139 }
140
141 static inline void cnic_put(struct cnic_dev *dev)
142 {
143 atomic_dec(&dev->ref_count);
144 }
145
146 static inline void csk_hold(struct cnic_sock *csk)
147 {
148 atomic_inc(&csk->ref_count);
149 }
150
151 static inline void csk_put(struct cnic_sock *csk)
152 {
153 atomic_dec(&csk->ref_count);
154 }
155
156 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
157 {
158 struct cnic_dev *cdev;
159
160 read_lock(&cnic_dev_lock);
161 list_for_each_entry(cdev, &cnic_dev_list, list) {
162 if (netdev == cdev->netdev) {
163 cnic_hold(cdev);
164 read_unlock(&cnic_dev_lock);
165 return cdev;
166 }
167 }
168 read_unlock(&cnic_dev_lock);
169 return NULL;
170 }
171
172 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
173 {
174 atomic_inc(&ulp_ops->ref_count);
175 }
176
177 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
178 {
179 atomic_dec(&ulp_ops->ref_count);
180 }
181
182 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
183 {
184 struct cnic_local *cp = dev->cnic_priv;
185 struct cnic_eth_dev *ethdev = cp->ethdev;
186 struct drv_ctl_info info;
187 struct drv_ctl_io *io = &info.data.io;
188
189 info.cmd = DRV_CTL_CTX_WR_CMD;
190 io->cid_addr = cid_addr;
191 io->offset = off;
192 io->data = val;
193 ethdev->drv_ctl(dev->netdev, &info);
194 }
195
196 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
197 {
198 struct cnic_local *cp = dev->cnic_priv;
199 struct cnic_eth_dev *ethdev = cp->ethdev;
200 struct drv_ctl_info info;
201 struct drv_ctl_io *io = &info.data.io;
202
203 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
204 io->offset = off;
205 io->dma_addr = addr;
206 ethdev->drv_ctl(dev->netdev, &info);
207 }
208
209 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
210 {
211 struct cnic_local *cp = dev->cnic_priv;
212 struct cnic_eth_dev *ethdev = cp->ethdev;
213 struct drv_ctl_info info;
214 struct drv_ctl_l2_ring *ring = &info.data.ring;
215
216 if (start)
217 info.cmd = DRV_CTL_START_L2_CMD;
218 else
219 info.cmd = DRV_CTL_STOP_L2_CMD;
220
221 ring->cid = cid;
222 ring->client_id = cl_id;
223 ethdev->drv_ctl(dev->netdev, &info);
224 }
225
226 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
227 {
228 struct cnic_local *cp = dev->cnic_priv;
229 struct cnic_eth_dev *ethdev = cp->ethdev;
230 struct drv_ctl_info info;
231 struct drv_ctl_io *io = &info.data.io;
232
233 info.cmd = DRV_CTL_IO_WR_CMD;
234 io->offset = off;
235 io->data = val;
236 ethdev->drv_ctl(dev->netdev, &info);
237 }
238
239 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
240 {
241 struct cnic_local *cp = dev->cnic_priv;
242 struct cnic_eth_dev *ethdev = cp->ethdev;
243 struct drv_ctl_info info;
244 struct drv_ctl_io *io = &info.data.io;
245
246 info.cmd = DRV_CTL_IO_RD_CMD;
247 io->offset = off;
248 ethdev->drv_ctl(dev->netdev, &info);
249 return io->data;
250 }
251
252 static int cnic_in_use(struct cnic_sock *csk)
253 {
254 return test_bit(SK_F_INUSE, &csk->flags);
255 }
256
257 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
258 {
259 struct cnic_local *cp = dev->cnic_priv;
260 struct cnic_eth_dev *ethdev = cp->ethdev;
261 struct drv_ctl_info info;
262
263 info.cmd = cmd;
264 info.data.credit.credit_count = count;
265 ethdev->drv_ctl(dev->netdev, &info);
266 }
267
268 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
269 {
270 u32 i;
271
272 for (i = 0; i < cp->max_cid_space; i++) {
273 if (cp->ctx_tbl[i].cid == cid) {
274 *l5_cid = i;
275 return 0;
276 }
277 }
278 return -EINVAL;
279 }
280
281 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
282 struct cnic_sock *csk)
283 {
284 struct iscsi_path path_req;
285 char *buf = NULL;
286 u16 len = 0;
287 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
288 struct cnic_ulp_ops *ulp_ops;
289 struct cnic_uio_dev *udev = cp->udev;
290 int rc = 0, retry = 0;
291
292 if (!udev || udev->uio_dev == -1)
293 return -ENODEV;
294
295 if (csk) {
296 len = sizeof(path_req);
297 buf = (char *) &path_req;
298 memset(&path_req, 0, len);
299
300 msg_type = ISCSI_KEVENT_PATH_REQ;
301 path_req.handle = (u64) csk->l5_cid;
302 if (test_bit(SK_F_IPV6, &csk->flags)) {
303 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
304 sizeof(struct in6_addr));
305 path_req.ip_addr_len = 16;
306 } else {
307 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
308 sizeof(struct in_addr));
309 path_req.ip_addr_len = 4;
310 }
311 path_req.vlan_id = csk->vlan_id;
312 path_req.pmtu = csk->mtu;
313 }
314
315 while (retry < 3) {
316 rc = 0;
317 rcu_read_lock();
318 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
319 if (ulp_ops)
320 rc = ulp_ops->iscsi_nl_send_msg(
321 cp->ulp_handle[CNIC_ULP_ISCSI],
322 msg_type, buf, len);
323 rcu_read_unlock();
324 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
325 break;
326
327 msleep(100);
328 retry++;
329 }
330 return 0;
331 }
332
333 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
334
335 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
336 char *buf, u16 len)
337 {
338 int rc = -EINVAL;
339
340 switch (msg_type) {
341 case ISCSI_UEVENT_PATH_UPDATE: {
342 struct cnic_local *cp;
343 u32 l5_cid;
344 struct cnic_sock *csk;
345 struct iscsi_path *path_resp;
346
347 if (len < sizeof(*path_resp))
348 break;
349
350 path_resp = (struct iscsi_path *) buf;
351 cp = dev->cnic_priv;
352 l5_cid = (u32) path_resp->handle;
353 if (l5_cid >= MAX_CM_SK_TBL_SZ)
354 break;
355
356 rcu_read_lock();
357 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
358 rc = -ENODEV;
359 rcu_read_unlock();
360 break;
361 }
362 csk = &cp->csk_tbl[l5_cid];
363 csk_hold(csk);
364 if (cnic_in_use(csk) &&
365 test_bit(SK_F_CONNECT_START, &csk->flags)) {
366
367 memcpy(csk->ha, path_resp->mac_addr, 6);
368 if (test_bit(SK_F_IPV6, &csk->flags))
369 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
370 sizeof(struct in6_addr));
371 else
372 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
373 sizeof(struct in_addr));
374
375 if (is_valid_ether_addr(csk->ha)) {
376 cnic_cm_set_pg(csk);
377 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
378 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
379
380 cnic_cm_upcall(cp, csk,
381 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
382 clear_bit(SK_F_CONNECT_START, &csk->flags);
383 }
384 }
385 csk_put(csk);
386 rcu_read_unlock();
387 rc = 0;
388 }
389 }
390
391 return rc;
392 }
393
394 static int cnic_offld_prep(struct cnic_sock *csk)
395 {
396 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
397 return 0;
398
399 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
400 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
401 return 0;
402 }
403
404 return 1;
405 }
406
407 static int cnic_close_prep(struct cnic_sock *csk)
408 {
409 clear_bit(SK_F_CONNECT_START, &csk->flags);
410 smp_mb__after_clear_bit();
411
412 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
413 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
414 msleep(1);
415
416 return 1;
417 }
418 return 0;
419 }
420
421 static int cnic_abort_prep(struct cnic_sock *csk)
422 {
423 clear_bit(SK_F_CONNECT_START, &csk->flags);
424 smp_mb__after_clear_bit();
425
426 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
427 msleep(1);
428
429 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
430 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
431 return 1;
432 }
433
434 return 0;
435 }
436
437 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
438 {
439 struct cnic_dev *dev;
440
441 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
442 pr_err("%s: Bad type %d\n", __func__, ulp_type);
443 return -EINVAL;
444 }
445 mutex_lock(&cnic_lock);
446 if (cnic_ulp_tbl_prot(ulp_type)) {
447 pr_err("%s: Type %d has already been registered\n",
448 __func__, ulp_type);
449 mutex_unlock(&cnic_lock);
450 return -EBUSY;
451 }
452
453 read_lock(&cnic_dev_lock);
454 list_for_each_entry(dev, &cnic_dev_list, list) {
455 struct cnic_local *cp = dev->cnic_priv;
456
457 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
458 }
459 read_unlock(&cnic_dev_lock);
460
461 atomic_set(&ulp_ops->ref_count, 0);
462 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
463 mutex_unlock(&cnic_lock);
464
465 /* Prevent race conditions with netdev_event */
466 rtnl_lock();
467 list_for_each_entry(dev, &cnic_dev_list, list) {
468 struct cnic_local *cp = dev->cnic_priv;
469
470 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
471 ulp_ops->cnic_init(dev);
472 }
473 rtnl_unlock();
474
475 return 0;
476 }
477
478 int cnic_unregister_driver(int ulp_type)
479 {
480 struct cnic_dev *dev;
481 struct cnic_ulp_ops *ulp_ops;
482 int i = 0;
483
484 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
485 pr_err("%s: Bad type %d\n", __func__, ulp_type);
486 return -EINVAL;
487 }
488 mutex_lock(&cnic_lock);
489 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
490 if (!ulp_ops) {
491 pr_err("%s: Type %d has not been registered\n",
492 __func__, ulp_type);
493 goto out_unlock;
494 }
495 read_lock(&cnic_dev_lock);
496 list_for_each_entry(dev, &cnic_dev_list, list) {
497 struct cnic_local *cp = dev->cnic_priv;
498
499 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
500 pr_err("%s: Type %d still has devices registered\n",
501 __func__, ulp_type);
502 read_unlock(&cnic_dev_lock);
503 goto out_unlock;
504 }
505 }
506 read_unlock(&cnic_dev_lock);
507
508 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
509
510 mutex_unlock(&cnic_lock);
511 synchronize_rcu();
512 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
513 msleep(100);
514 i++;
515 }
516
517 if (atomic_read(&ulp_ops->ref_count) != 0)
518 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
519 return 0;
520
521 out_unlock:
522 mutex_unlock(&cnic_lock);
523 return -EINVAL;
524 }
525
526 static int cnic_start_hw(struct cnic_dev *);
527 static void cnic_stop_hw(struct cnic_dev *);
528
529 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
530 void *ulp_ctx)
531 {
532 struct cnic_local *cp = dev->cnic_priv;
533 struct cnic_ulp_ops *ulp_ops;
534
535 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
536 pr_err("%s: Bad type %d\n", __func__, ulp_type);
537 return -EINVAL;
538 }
539 mutex_lock(&cnic_lock);
540 if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
541 pr_err("%s: Driver with type %d has not been registered\n",
542 __func__, ulp_type);
543 mutex_unlock(&cnic_lock);
544 return -EAGAIN;
545 }
546 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
547 pr_err("%s: Type %d has already been registered to this device\n",
548 __func__, ulp_type);
549 mutex_unlock(&cnic_lock);
550 return -EBUSY;
551 }
552
553 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
554 cp->ulp_handle[ulp_type] = ulp_ctx;
555 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
556 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
557 cnic_hold(dev);
558
559 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
560 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
561 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
562
563 mutex_unlock(&cnic_lock);
564
565 return 0;
566
567 }
568 EXPORT_SYMBOL(cnic_register_driver);
569
570 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
571 {
572 struct cnic_local *cp = dev->cnic_priv;
573 int i = 0;
574
575 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
576 pr_err("%s: Bad type %d\n", __func__, ulp_type);
577 return -EINVAL;
578 }
579 mutex_lock(&cnic_lock);
580 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
581 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
582 cnic_put(dev);
583 } else {
584 pr_err("%s: device not registered to this ulp type %d\n",
585 __func__, ulp_type);
586 mutex_unlock(&cnic_lock);
587 return -EINVAL;
588 }
589 mutex_unlock(&cnic_lock);
590
591 if (ulp_type == CNIC_ULP_ISCSI)
592 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
593
594 synchronize_rcu();
595
596 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
597 i < 20) {
598 msleep(100);
599 i++;
600 }
601 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
602 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
603
604 return 0;
605 }
606 EXPORT_SYMBOL(cnic_unregister_driver);
607
608 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
609 {
610 id_tbl->start = start_id;
611 id_tbl->max = size;
612 id_tbl->next = 0;
613 spin_lock_init(&id_tbl->lock);
614 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
615 if (!id_tbl->table)
616 return -ENOMEM;
617
618 return 0;
619 }
620
621 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
622 {
623 kfree(id_tbl->table);
624 id_tbl->table = NULL;
625 }
626
627 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
628 {
629 int ret = -1;
630
631 id -= id_tbl->start;
632 if (id >= id_tbl->max)
633 return ret;
634
635 spin_lock(&id_tbl->lock);
636 if (!test_bit(id, id_tbl->table)) {
637 set_bit(id, id_tbl->table);
638 ret = 0;
639 }
640 spin_unlock(&id_tbl->lock);
641 return ret;
642 }
643
644 /* Returns -1 if not successful */
645 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
646 {
647 u32 id;
648
649 spin_lock(&id_tbl->lock);
650 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
651 if (id >= id_tbl->max) {
652 id = -1;
653 if (id_tbl->next != 0) {
654 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
655 if (id >= id_tbl->next)
656 id = -1;
657 }
658 }
659
660 if (id < id_tbl->max) {
661 set_bit(id, id_tbl->table);
662 id_tbl->next = (id + 1) & (id_tbl->max - 1);
663 id += id_tbl->start;
664 }
665
666 spin_unlock(&id_tbl->lock);
667
668 return id;
669 }
670
671 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
672 {
673 if (id == -1)
674 return;
675
676 id -= id_tbl->start;
677 if (id >= id_tbl->max)
678 return;
679
680 clear_bit(id, id_tbl->table);
681 }
682
683 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
684 {
685 int i;
686
687 if (!dma->pg_arr)
688 return;
689
690 for (i = 0; i < dma->num_pages; i++) {
691 if (dma->pg_arr[i]) {
692 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
693 dma->pg_arr[i], dma->pg_map_arr[i]);
694 dma->pg_arr[i] = NULL;
695 }
696 }
697 if (dma->pgtbl) {
698 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
699 dma->pgtbl, dma->pgtbl_map);
700 dma->pgtbl = NULL;
701 }
702 kfree(dma->pg_arr);
703 dma->pg_arr = NULL;
704 dma->num_pages = 0;
705 }
706
707 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
708 {
709 int i;
710 __le32 *page_table = (__le32 *) dma->pgtbl;
711
712 for (i = 0; i < dma->num_pages; i++) {
713 /* Each entry needs to be in big endian format. */
714 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
715 page_table++;
716 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
717 page_table++;
718 }
719 }
720
721 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
722 {
723 int i;
724 __le32 *page_table = (__le32 *) dma->pgtbl;
725
726 for (i = 0; i < dma->num_pages; i++) {
727 /* Each entry needs to be in little endian format. */
728 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
729 page_table++;
730 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
731 page_table++;
732 }
733 }
734
735 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
736 int pages, int use_pg_tbl)
737 {
738 int i, size;
739 struct cnic_local *cp = dev->cnic_priv;
740
741 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
742 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
743 if (dma->pg_arr == NULL)
744 return -ENOMEM;
745
746 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
747 dma->num_pages = pages;
748
749 for (i = 0; i < pages; i++) {
750 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
751 BCM_PAGE_SIZE,
752 &dma->pg_map_arr[i],
753 GFP_ATOMIC);
754 if (dma->pg_arr[i] == NULL)
755 goto error;
756 }
757 if (!use_pg_tbl)
758 return 0;
759
760 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
761 ~(BCM_PAGE_SIZE - 1);
762 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
763 &dma->pgtbl_map, GFP_ATOMIC);
764 if (dma->pgtbl == NULL)
765 goto error;
766
767 cp->setup_pgtbl(dev, dma);
768
769 return 0;
770
771 error:
772 cnic_free_dma(dev, dma);
773 return -ENOMEM;
774 }
775
776 static void cnic_free_context(struct cnic_dev *dev)
777 {
778 struct cnic_local *cp = dev->cnic_priv;
779 int i;
780
781 for (i = 0; i < cp->ctx_blks; i++) {
782 if (cp->ctx_arr[i].ctx) {
783 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
784 cp->ctx_arr[i].ctx,
785 cp->ctx_arr[i].mapping);
786 cp->ctx_arr[i].ctx = NULL;
787 }
788 }
789 }
790
791 static void __cnic_free_uio(struct cnic_uio_dev *udev)
792 {
793 uio_unregister_device(&udev->cnic_uinfo);
794
795 if (udev->l2_buf) {
796 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
797 udev->l2_buf, udev->l2_buf_map);
798 udev->l2_buf = NULL;
799 }
800
801 if (udev->l2_ring) {
802 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
803 udev->l2_ring, udev->l2_ring_map);
804 udev->l2_ring = NULL;
805 }
806
807 pci_dev_put(udev->pdev);
808 kfree(udev);
809 }
810
811 static void cnic_free_uio(struct cnic_uio_dev *udev)
812 {
813 if (!udev)
814 return;
815
816 write_lock(&cnic_dev_lock);
817 list_del_init(&udev->list);
818 write_unlock(&cnic_dev_lock);
819 __cnic_free_uio(udev);
820 }
821
822 static void cnic_free_resc(struct cnic_dev *dev)
823 {
824 struct cnic_local *cp = dev->cnic_priv;
825 struct cnic_uio_dev *udev = cp->udev;
826
827 if (udev) {
828 udev->dev = NULL;
829 cp->udev = NULL;
830 }
831
832 cnic_free_context(dev);
833 kfree(cp->ctx_arr);
834 cp->ctx_arr = NULL;
835 cp->ctx_blks = 0;
836
837 cnic_free_dma(dev, &cp->gbl_buf_info);
838 cnic_free_dma(dev, &cp->conn_buf_info);
839 cnic_free_dma(dev, &cp->kwq_info);
840 cnic_free_dma(dev, &cp->kwq_16_data_info);
841 cnic_free_dma(dev, &cp->kcq2.dma);
842 cnic_free_dma(dev, &cp->kcq1.dma);
843 kfree(cp->iscsi_tbl);
844 cp->iscsi_tbl = NULL;
845 kfree(cp->ctx_tbl);
846 cp->ctx_tbl = NULL;
847
848 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
849 cnic_free_id_tbl(&cp->cid_tbl);
850 }
851
852 static int cnic_alloc_context(struct cnic_dev *dev)
853 {
854 struct cnic_local *cp = dev->cnic_priv;
855
856 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
857 int i, k, arr_size;
858
859 cp->ctx_blk_size = BCM_PAGE_SIZE;
860 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
861 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
862 sizeof(struct cnic_ctx);
863 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
864 if (cp->ctx_arr == NULL)
865 return -ENOMEM;
866
867 k = 0;
868 for (i = 0; i < 2; i++) {
869 u32 j, reg, off, lo, hi;
870
871 if (i == 0)
872 off = BNX2_PG_CTX_MAP;
873 else
874 off = BNX2_ISCSI_CTX_MAP;
875
876 reg = cnic_reg_rd_ind(dev, off);
877 lo = reg >> 16;
878 hi = reg & 0xffff;
879 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
880 cp->ctx_arr[k].cid = j;
881 }
882
883 cp->ctx_blks = k;
884 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
885 cp->ctx_blks = 0;
886 return -ENOMEM;
887 }
888
889 for (i = 0; i < cp->ctx_blks; i++) {
890 cp->ctx_arr[i].ctx =
891 dma_alloc_coherent(&dev->pcidev->dev,
892 BCM_PAGE_SIZE,
893 &cp->ctx_arr[i].mapping,
894 GFP_KERNEL);
895 if (cp->ctx_arr[i].ctx == NULL)
896 return -ENOMEM;
897 }
898 }
899 return 0;
900 }
901
902 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
903 {
904 int err, i, is_bnx2 = 0;
905 struct kcqe **kcq;
906
907 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
908 is_bnx2 = 1;
909
910 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
911 if (err)
912 return err;
913
914 kcq = (struct kcqe **) info->dma.pg_arr;
915 info->kcq = kcq;
916
917 if (is_bnx2)
918 return 0;
919
920 for (i = 0; i < KCQ_PAGE_CNT; i++) {
921 struct bnx2x_bd_chain_next *next =
922 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
923 int j = i + 1;
924
925 if (j >= KCQ_PAGE_CNT)
926 j = 0;
927 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
928 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
929 }
930 return 0;
931 }
932
933 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
934 {
935 struct cnic_local *cp = dev->cnic_priv;
936 struct cnic_uio_dev *udev;
937
938 read_lock(&cnic_dev_lock);
939 list_for_each_entry(udev, &cnic_udev_list, list) {
940 if (udev->pdev == dev->pcidev) {
941 udev->dev = dev;
942 cp->udev = udev;
943 read_unlock(&cnic_dev_lock);
944 return 0;
945 }
946 }
947 read_unlock(&cnic_dev_lock);
948
949 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
950 if (!udev)
951 return -ENOMEM;
952
953 udev->uio_dev = -1;
954
955 udev->dev = dev;
956 udev->pdev = dev->pcidev;
957 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
958 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
959 &udev->l2_ring_map,
960 GFP_KERNEL | __GFP_COMP);
961 if (!udev->l2_ring)
962 goto err_udev;
963
964 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
965 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
966 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
967 &udev->l2_buf_map,
968 GFP_KERNEL | __GFP_COMP);
969 if (!udev->l2_buf)
970 goto err_dma;
971
972 write_lock(&cnic_dev_lock);
973 list_add(&udev->list, &cnic_udev_list);
974 write_unlock(&cnic_dev_lock);
975
976 pci_dev_get(udev->pdev);
977
978 cp->udev = udev;
979
980 return 0;
981 err_dma:
982 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
983 udev->l2_ring, udev->l2_ring_map);
984 err_udev:
985 kfree(udev);
986 return -ENOMEM;
987 }
988
989 static int cnic_init_uio(struct cnic_dev *dev)
990 {
991 struct cnic_local *cp = dev->cnic_priv;
992 struct cnic_uio_dev *udev = cp->udev;
993 struct uio_info *uinfo;
994 int ret = 0;
995
996 if (!udev)
997 return -ENOMEM;
998
999 uinfo = &udev->cnic_uinfo;
1000
1001 uinfo->mem[0].addr = dev->netdev->base_addr;
1002 uinfo->mem[0].internal_addr = dev->regview;
1003 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
1004 uinfo->mem[0].memtype = UIO_MEM_PHYS;
1005
1006 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1007 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1008 PAGE_MASK;
1009 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1010 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1011 else
1012 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1013
1014 uinfo->name = "bnx2_cnic";
1015 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1016 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1017 PAGE_MASK;
1018 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1019
1020 uinfo->name = "bnx2x_cnic";
1021 }
1022
1023 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1024
1025 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1026 uinfo->mem[2].size = udev->l2_ring_size;
1027 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1028
1029 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1030 uinfo->mem[3].size = udev->l2_buf_size;
1031 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1032
1033 uinfo->version = CNIC_MODULE_VERSION;
1034 uinfo->irq = UIO_IRQ_CUSTOM;
1035
1036 uinfo->open = cnic_uio_open;
1037 uinfo->release = cnic_uio_close;
1038
1039 if (udev->uio_dev == -1) {
1040 if (!uinfo->priv) {
1041 uinfo->priv = udev;
1042
1043 ret = uio_register_device(&udev->pdev->dev, uinfo);
1044 }
1045 } else {
1046 cnic_init_rings(dev);
1047 }
1048
1049 return ret;
1050 }
1051
1052 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1053 {
1054 struct cnic_local *cp = dev->cnic_priv;
1055 int ret;
1056
1057 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1058 if (ret)
1059 goto error;
1060 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1061
1062 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1063 if (ret)
1064 goto error;
1065
1066 ret = cnic_alloc_context(dev);
1067 if (ret)
1068 goto error;
1069
1070 ret = cnic_alloc_uio_rings(dev, 2);
1071 if (ret)
1072 goto error;
1073
1074 ret = cnic_init_uio(dev);
1075 if (ret)
1076 goto error;
1077
1078 return 0;
1079
1080 error:
1081 cnic_free_resc(dev);
1082 return ret;
1083 }
1084
1085 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1086 {
1087 struct cnic_local *cp = dev->cnic_priv;
1088 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1089 int total_mem, blks, i;
1090
1091 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1092 blks = total_mem / ctx_blk_size;
1093 if (total_mem % ctx_blk_size)
1094 blks++;
1095
1096 if (blks > cp->ethdev->ctx_tbl_len)
1097 return -ENOMEM;
1098
1099 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1100 if (cp->ctx_arr == NULL)
1101 return -ENOMEM;
1102
1103 cp->ctx_blks = blks;
1104 cp->ctx_blk_size = ctx_blk_size;
1105 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1106 cp->ctx_align = 0;
1107 else
1108 cp->ctx_align = ctx_blk_size;
1109
1110 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1111
1112 for (i = 0; i < blks; i++) {
1113 cp->ctx_arr[i].ctx =
1114 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1115 &cp->ctx_arr[i].mapping,
1116 GFP_KERNEL);
1117 if (cp->ctx_arr[i].ctx == NULL)
1118 return -ENOMEM;
1119
1120 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1121 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1122 cnic_free_context(dev);
1123 cp->ctx_blk_size += cp->ctx_align;
1124 i = -1;
1125 continue;
1126 }
1127 }
1128 }
1129 return 0;
1130 }
1131
1132 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1133 {
1134 struct cnic_local *cp = dev->cnic_priv;
1135 struct cnic_eth_dev *ethdev = cp->ethdev;
1136 u32 start_cid = ethdev->starting_cid;
1137 int i, j, n, ret, pages;
1138 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1139
1140 cp->iro_arr = ethdev->iro_arr;
1141
1142 cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
1143 cp->iscsi_start_cid = start_cid;
1144 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1145
1146 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1147 cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
1148 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1149 if (!cp->fcoe_init_cid)
1150 cp->fcoe_init_cid = 0x10;
1151 }
1152
1153 if (start_cid < BNX2X_ISCSI_START_CID) {
1154 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1155
1156 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1157 cp->fcoe_start_cid += delta;
1158 cp->max_cid_space += delta;
1159 }
1160
1161 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1162 GFP_KERNEL);
1163 if (!cp->iscsi_tbl)
1164 goto error;
1165
1166 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1167 cp->max_cid_space, GFP_KERNEL);
1168 if (!cp->ctx_tbl)
1169 goto error;
1170
1171 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1172 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1173 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1174 }
1175
1176 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1177 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1178
1179 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1180 PAGE_SIZE;
1181
1182 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1183 if (ret)
1184 return -ENOMEM;
1185
1186 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1187 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1188 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1189
1190 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1191 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1192 off;
1193
1194 if ((i % n) == (n - 1))
1195 j++;
1196 }
1197
1198 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1199 if (ret)
1200 goto error;
1201
1202 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1203 ret = cnic_alloc_kcq(dev, &cp->kcq2);
1204 if (ret)
1205 goto error;
1206 }
1207
1208 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1209 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1210 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1211 if (ret)
1212 goto error;
1213
1214 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1215 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1216 if (ret)
1217 goto error;
1218
1219 ret = cnic_alloc_bnx2x_context(dev);
1220 if (ret)
1221 goto error;
1222
1223 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1224
1225 cp->l2_rx_ring_size = 15;
1226
1227 ret = cnic_alloc_uio_rings(dev, 4);
1228 if (ret)
1229 goto error;
1230
1231 ret = cnic_init_uio(dev);
1232 if (ret)
1233 goto error;
1234
1235 return 0;
1236
1237 error:
1238 cnic_free_resc(dev);
1239 return -ENOMEM;
1240 }
1241
1242 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1243 {
1244 return cp->max_kwq_idx -
1245 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1246 }
1247
1248 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1249 u32 num_wqes)
1250 {
1251 struct cnic_local *cp = dev->cnic_priv;
1252 struct kwqe *prod_qe;
1253 u16 prod, sw_prod, i;
1254
1255 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1256 return -EAGAIN; /* bnx2 is down */
1257
1258 spin_lock_bh(&cp->cnic_ulp_lock);
1259 if (num_wqes > cnic_kwq_avail(cp) &&
1260 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1261 spin_unlock_bh(&cp->cnic_ulp_lock);
1262 return -EAGAIN;
1263 }
1264
1265 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1266
1267 prod = cp->kwq_prod_idx;
1268 sw_prod = prod & MAX_KWQ_IDX;
1269 for (i = 0; i < num_wqes; i++) {
1270 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1271 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1272 prod++;
1273 sw_prod = prod & MAX_KWQ_IDX;
1274 }
1275 cp->kwq_prod_idx = prod;
1276
1277 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1278
1279 spin_unlock_bh(&cp->cnic_ulp_lock);
1280 return 0;
1281 }
1282
1283 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1284 union l5cm_specific_data *l5_data)
1285 {
1286 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1287 dma_addr_t map;
1288
1289 map = ctx->kwqe_data_mapping;
1290 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1291 l5_data->phy_address.hi = (u64) map >> 32;
1292 return ctx->kwqe_data;
1293 }
1294
1295 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1296 u32 type, union l5cm_specific_data *l5_data)
1297 {
1298 struct cnic_local *cp = dev->cnic_priv;
1299 struct l5cm_spe kwqe;
1300 struct kwqe_16 *kwq[1];
1301 u16 type_16;
1302 int ret;
1303
1304 kwqe.hdr.conn_and_cmd_data =
1305 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1306 BNX2X_HW_CID(cp, cid)));
1307
1308 type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1309 type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1310 SPE_HDR_FUNCTION_ID;
1311
1312 kwqe.hdr.type = cpu_to_le16(type_16);
1313 kwqe.hdr.reserved1 = 0;
1314 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1315 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1316
1317 kwq[0] = (struct kwqe_16 *) &kwqe;
1318
1319 spin_lock_bh(&cp->cnic_ulp_lock);
1320 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1321 spin_unlock_bh(&cp->cnic_ulp_lock);
1322
1323 if (ret == 1)
1324 return 0;
1325
1326 return -EBUSY;
1327 }
1328
1329 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1330 struct kcqe *cqes[], u32 num_cqes)
1331 {
1332 struct cnic_local *cp = dev->cnic_priv;
1333 struct cnic_ulp_ops *ulp_ops;
1334
1335 rcu_read_lock();
1336 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1337 if (likely(ulp_ops)) {
1338 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1339 cqes, num_cqes);
1340 }
1341 rcu_read_unlock();
1342 }
1343
1344 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1345 {
1346 struct cnic_local *cp = dev->cnic_priv;
1347 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1348 int hq_bds, pages;
1349 u32 pfid = cp->pfid;
1350
1351 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1352 cp->num_ccells = req1->num_ccells_per_conn;
1353 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1354 cp->num_iscsi_tasks;
1355 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1356 BNX2X_ISCSI_R2TQE_SIZE;
1357 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1358 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1359 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1360 cp->num_cqs = req1->num_cqs;
1361
1362 if (!dev->max_iscsi_conn)
1363 return 0;
1364
1365 /* init Tstorm RAM */
1366 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1367 req1->rq_num_wqes);
1368 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1369 PAGE_SIZE);
1370 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1371 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1372 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1373 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1374 req1->num_tasks_per_conn);
1375
1376 /* init Ustorm RAM */
1377 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1378 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1379 req1->rq_buffer_size);
1380 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1381 PAGE_SIZE);
1382 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1383 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1384 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1385 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1386 req1->num_tasks_per_conn);
1387 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1388 req1->rq_num_wqes);
1389 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1390 req1->cq_num_wqes);
1391 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1392 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1393
1394 /* init Xstorm RAM */
1395 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1396 PAGE_SIZE);
1397 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1398 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1399 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1400 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1401 req1->num_tasks_per_conn);
1402 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1403 hq_bds);
1404 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1405 req1->num_tasks_per_conn);
1406 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1407 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1408
1409 /* init Cstorm RAM */
1410 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1411 PAGE_SIZE);
1412 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1413 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1414 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1415 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1416 req1->num_tasks_per_conn);
1417 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1418 req1->cq_num_wqes);
1419 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1420 hq_bds);
1421
1422 return 0;
1423 }
1424
1425 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1426 {
1427 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1428 struct cnic_local *cp = dev->cnic_priv;
1429 u32 pfid = cp->pfid;
1430 struct iscsi_kcqe kcqe;
1431 struct kcqe *cqes[1];
1432
1433 memset(&kcqe, 0, sizeof(kcqe));
1434 if (!dev->max_iscsi_conn) {
1435 kcqe.completion_status =
1436 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1437 goto done;
1438 }
1439
1440 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1441 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1442 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1443 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1444 req2->error_bit_map[1]);
1445
1446 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1447 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1448 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1449 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1450 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1451 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1452 req2->error_bit_map[1]);
1453
1454 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1455 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1456
1457 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1458
1459 done:
1460 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1461 cqes[0] = (struct kcqe *) &kcqe;
1462 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1463
1464 return 0;
1465 }
1466
1467 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1468 {
1469 struct cnic_local *cp = dev->cnic_priv;
1470 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1471
1472 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1473 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1474
1475 cnic_free_dma(dev, &iscsi->hq_info);
1476 cnic_free_dma(dev, &iscsi->r2tq_info);
1477 cnic_free_dma(dev, &iscsi->task_array_info);
1478 cnic_free_id(&cp->cid_tbl, ctx->cid);
1479 } else {
1480 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1481 }
1482
1483 ctx->cid = 0;
1484 }
1485
1486 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1487 {
1488 u32 cid;
1489 int ret, pages;
1490 struct cnic_local *cp = dev->cnic_priv;
1491 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1492 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1493
1494 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1495 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1496 if (cid == -1) {
1497 ret = -ENOMEM;
1498 goto error;
1499 }
1500 ctx->cid = cid;
1501 return 0;
1502 }
1503
1504 cid = cnic_alloc_new_id(&cp->cid_tbl);
1505 if (cid == -1) {
1506 ret = -ENOMEM;
1507 goto error;
1508 }
1509
1510 ctx->cid = cid;
1511 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1512
1513 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1514 if (ret)
1515 goto error;
1516
1517 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1518 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1519 if (ret)
1520 goto error;
1521
1522 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1523 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1524 if (ret)
1525 goto error;
1526
1527 return 0;
1528
1529 error:
1530 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1531 return ret;
1532 }
1533
1534 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1535 struct regpair *ctx_addr)
1536 {
1537 struct cnic_local *cp = dev->cnic_priv;
1538 struct cnic_eth_dev *ethdev = cp->ethdev;
1539 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1540 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1541 unsigned long align_off = 0;
1542 dma_addr_t ctx_map;
1543 void *ctx;
1544
1545 if (cp->ctx_align) {
1546 unsigned long mask = cp->ctx_align - 1;
1547
1548 if (cp->ctx_arr[blk].mapping & mask)
1549 align_off = cp->ctx_align -
1550 (cp->ctx_arr[blk].mapping & mask);
1551 }
1552 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1553 (off * BNX2X_CONTEXT_MEM_SIZE);
1554 ctx = cp->ctx_arr[blk].ctx + align_off +
1555 (off * BNX2X_CONTEXT_MEM_SIZE);
1556 if (init)
1557 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1558
1559 ctx_addr->lo = ctx_map & 0xffffffff;
1560 ctx_addr->hi = (u64) ctx_map >> 32;
1561 return ctx;
1562 }
1563
1564 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1565 u32 num)
1566 {
1567 struct cnic_local *cp = dev->cnic_priv;
1568 struct iscsi_kwqe_conn_offload1 *req1 =
1569 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1570 struct iscsi_kwqe_conn_offload2 *req2 =
1571 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1572 struct iscsi_kwqe_conn_offload3 *req3;
1573 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1574 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1575 u32 cid = ctx->cid;
1576 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1577 struct iscsi_context *ictx;
1578 struct regpair context_addr;
1579 int i, j, n = 2, n_max;
1580
1581 ctx->ctx_flags = 0;
1582 if (!req2->num_additional_wqes)
1583 return -EINVAL;
1584
1585 n_max = req2->num_additional_wqes + 2;
1586
1587 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1588 if (ictx == NULL)
1589 return -ENOMEM;
1590
1591 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1592
1593 ictx->xstorm_ag_context.hq_prod = 1;
1594
1595 ictx->xstorm_st_context.iscsi.first_burst_length =
1596 ISCSI_DEF_FIRST_BURST_LEN;
1597 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1598 ISCSI_DEF_MAX_RECV_SEG_LEN;
1599 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1600 req1->sq_page_table_addr_lo;
1601 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1602 req1->sq_page_table_addr_hi;
1603 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1604 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1605 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1606 iscsi->hq_info.pgtbl_map & 0xffffffff;
1607 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1608 (u64) iscsi->hq_info.pgtbl_map >> 32;
1609 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1610 iscsi->hq_info.pgtbl[0];
1611 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1612 iscsi->hq_info.pgtbl[1];
1613 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1614 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1615 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1616 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1617 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1618 iscsi->r2tq_info.pgtbl[0];
1619 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1620 iscsi->r2tq_info.pgtbl[1];
1621 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1622 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1623 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1624 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1625 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1626 BNX2X_ISCSI_PBL_NOT_CACHED;
1627 ictx->xstorm_st_context.iscsi.flags.flags |=
1628 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1629 ictx->xstorm_st_context.iscsi.flags.flags |=
1630 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1631
1632 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1633 /* TSTORM requires the base address of RQ DB & not PTE */
1634 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1635 req2->rq_page_table_addr_lo & PAGE_MASK;
1636 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1637 req2->rq_page_table_addr_hi;
1638 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1639 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1640 ictx->tstorm_st_context.tcp.flags2 |=
1641 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1642 ictx->tstorm_st_context.tcp.ooo_support_mode =
1643 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1644
1645 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1646
1647 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1648 req2->rq_page_table_addr_lo;
1649 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1650 req2->rq_page_table_addr_hi;
1651 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1652 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1653 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1654 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1655 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1656 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1657 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1658 iscsi->r2tq_info.pgtbl[0];
1659 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1660 iscsi->r2tq_info.pgtbl[1];
1661 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1662 req1->cq_page_table_addr_lo;
1663 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1664 req1->cq_page_table_addr_hi;
1665 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1666 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1667 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1668 ictx->ustorm_st_context.task_pbe_cache_index =
1669 BNX2X_ISCSI_PBL_NOT_CACHED;
1670 ictx->ustorm_st_context.task_pdu_cache_index =
1671 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1672
1673 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1674 if (j == 3) {
1675 if (n >= n_max)
1676 break;
1677 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1678 j = 0;
1679 }
1680 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1681 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1682 req3->qp_first_pte[j].hi;
1683 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1684 req3->qp_first_pte[j].lo;
1685 }
1686
1687 ictx->ustorm_st_context.task_pbl_base.lo =
1688 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1689 ictx->ustorm_st_context.task_pbl_base.hi =
1690 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1691 ictx->ustorm_st_context.tce_phy_addr.lo =
1692 iscsi->task_array_info.pgtbl[0];
1693 ictx->ustorm_st_context.tce_phy_addr.hi =
1694 iscsi->task_array_info.pgtbl[1];
1695 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1696 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1697 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1698 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1699 ISCSI_DEF_MAX_BURST_LEN;
1700 ictx->ustorm_st_context.negotiated_rx |=
1701 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1702 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1703
1704 ictx->cstorm_st_context.hq_pbl_base.lo =
1705 iscsi->hq_info.pgtbl_map & 0xffffffff;
1706 ictx->cstorm_st_context.hq_pbl_base.hi =
1707 (u64) iscsi->hq_info.pgtbl_map >> 32;
1708 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1709 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1710 ictx->cstorm_st_context.task_pbl_base.lo =
1711 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1712 ictx->cstorm_st_context.task_pbl_base.hi =
1713 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1714 /* CSTORM and USTORM initialization is different, CSTORM requires
1715 * CQ DB base & not PTE addr */
1716 ictx->cstorm_st_context.cq_db_base.lo =
1717 req1->cq_page_table_addr_lo & PAGE_MASK;
1718 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1719 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1720 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1721 for (i = 0; i < cp->num_cqs; i++) {
1722 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1723 ISCSI_INITIAL_SN;
1724 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1725 ISCSI_INITIAL_SN;
1726 }
1727
1728 ictx->xstorm_ag_context.cdu_reserved =
1729 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1730 ISCSI_CONNECTION_TYPE);
1731 ictx->ustorm_ag_context.cdu_usage =
1732 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1733 ISCSI_CONNECTION_TYPE);
1734 return 0;
1735
1736 }
1737
1738 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1739 u32 num, int *work)
1740 {
1741 struct iscsi_kwqe_conn_offload1 *req1;
1742 struct iscsi_kwqe_conn_offload2 *req2;
1743 struct cnic_local *cp = dev->cnic_priv;
1744 struct cnic_context *ctx;
1745 struct iscsi_kcqe kcqe;
1746 struct kcqe *cqes[1];
1747 u32 l5_cid;
1748 int ret = 0;
1749
1750 if (num < 2) {
1751 *work = num;
1752 return -EINVAL;
1753 }
1754
1755 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1756 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1757 if ((num - 2) < req2->num_additional_wqes) {
1758 *work = num;
1759 return -EINVAL;
1760 }
1761 *work = 2 + req2->num_additional_wqes;
1762
1763 l5_cid = req1->iscsi_conn_id;
1764 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1765 return -EINVAL;
1766
1767 memset(&kcqe, 0, sizeof(kcqe));
1768 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1769 kcqe.iscsi_conn_id = l5_cid;
1770 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1771
1772 ctx = &cp->ctx_tbl[l5_cid];
1773 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1774 kcqe.completion_status =
1775 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1776 goto done;
1777 }
1778
1779 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1780 atomic_dec(&cp->iscsi_conn);
1781 goto done;
1782 }
1783 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1784 if (ret) {
1785 atomic_dec(&cp->iscsi_conn);
1786 ret = 0;
1787 goto done;
1788 }
1789 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1790 if (ret < 0) {
1791 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1792 atomic_dec(&cp->iscsi_conn);
1793 goto done;
1794 }
1795
1796 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1797 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1798
1799 done:
1800 cqes[0] = (struct kcqe *) &kcqe;
1801 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1802 return ret;
1803 }
1804
1805
1806 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1807 {
1808 struct cnic_local *cp = dev->cnic_priv;
1809 struct iscsi_kwqe_conn_update *req =
1810 (struct iscsi_kwqe_conn_update *) kwqe;
1811 void *data;
1812 union l5cm_specific_data l5_data;
1813 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1814 int ret;
1815
1816 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1817 return -EINVAL;
1818
1819 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1820 if (!data)
1821 return -ENOMEM;
1822
1823 memcpy(data, kwqe, sizeof(struct kwqe));
1824
1825 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1826 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1827 return ret;
1828 }
1829
1830 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1831 {
1832 struct cnic_local *cp = dev->cnic_priv;
1833 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1834 union l5cm_specific_data l5_data;
1835 int ret;
1836 u32 hw_cid;
1837
1838 init_waitqueue_head(&ctx->waitq);
1839 ctx->wait_cond = 0;
1840 memset(&l5_data, 0, sizeof(l5_data));
1841 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1842
1843 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1844 hw_cid, NONE_CONNECTION_TYPE, &l5_data);
1845
1846 if (ret == 0)
1847 wait_event(ctx->waitq, ctx->wait_cond);
1848
1849 return ret;
1850 }
1851
1852 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1853 {
1854 struct cnic_local *cp = dev->cnic_priv;
1855 struct iscsi_kwqe_conn_destroy *req =
1856 (struct iscsi_kwqe_conn_destroy *) kwqe;
1857 u32 l5_cid = req->reserved0;
1858 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1859 int ret = 0;
1860 struct iscsi_kcqe kcqe;
1861 struct kcqe *cqes[1];
1862
1863 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1864 goto skip_cfc_delete;
1865
1866 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1867 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1868
1869 if (delta > (2 * HZ))
1870 delta = 0;
1871
1872 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1873 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1874 goto destroy_reply;
1875 }
1876
1877 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1878
1879 skip_cfc_delete:
1880 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1881
1882 atomic_dec(&cp->iscsi_conn);
1883 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1884
1885 destroy_reply:
1886 memset(&kcqe, 0, sizeof(kcqe));
1887 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1888 kcqe.iscsi_conn_id = l5_cid;
1889 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1890 kcqe.iscsi_conn_context_id = req->context_id;
1891
1892 cqes[0] = (struct kcqe *) &kcqe;
1893 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1894
1895 return ret;
1896 }
1897
1898 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1899 struct l4_kwq_connect_req1 *kwqe1,
1900 struct l4_kwq_connect_req3 *kwqe3,
1901 struct l5cm_active_conn_buffer *conn_buf)
1902 {
1903 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1904 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1905 &conn_buf->xstorm_conn_buffer;
1906 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1907 &conn_buf->tstorm_conn_buffer;
1908 struct regpair context_addr;
1909 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1910 struct in6_addr src_ip, dst_ip;
1911 int i;
1912 u32 *addrp;
1913
1914 addrp = (u32 *) &conn_addr->local_ip_addr;
1915 for (i = 0; i < 4; i++, addrp++)
1916 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1917
1918 addrp = (u32 *) &conn_addr->remote_ip_addr;
1919 for (i = 0; i < 4; i++, addrp++)
1920 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1921
1922 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1923
1924 xstorm_buf->context_addr.hi = context_addr.hi;
1925 xstorm_buf->context_addr.lo = context_addr.lo;
1926 xstorm_buf->mss = 0xffff;
1927 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1928 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1929 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1930 xstorm_buf->pseudo_header_checksum =
1931 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1932
1933 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1934 tstorm_buf->params |=
1935 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1936 if (kwqe3->ka_timeout) {
1937 tstorm_buf->ka_enable = 1;
1938 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1939 tstorm_buf->ka_interval = kwqe3->ka_interval;
1940 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1941 }
1942 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1943 tstorm_buf->snd_buf = kwqe3->snd_buf;
1944 tstorm_buf->max_rt_time = 0xffffffff;
1945 }
1946
1947 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1948 {
1949 struct cnic_local *cp = dev->cnic_priv;
1950 u32 pfid = cp->pfid;
1951 u8 *mac = dev->mac_addr;
1952
1953 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1954 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1955 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1956 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1957 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1958 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
1959 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1960 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
1961 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1962 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
1963 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1964 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
1965
1966 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1967 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
1968 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1969 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1970 mac[4]);
1971 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1972 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
1973 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1974 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1975 mac[2]);
1976 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1977 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
1978 mac[1]);
1979 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1980 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
1981 mac[0]);
1982 }
1983
1984 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1985 {
1986 struct cnic_local *cp = dev->cnic_priv;
1987 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1988 u16 tstorm_flags = 0;
1989
1990 if (tcp_ts) {
1991 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1992 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1993 }
1994
1995 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1996 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
1997
1998 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1999 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
2000 }
2001
2002 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
2003 u32 num, int *work)
2004 {
2005 struct cnic_local *cp = dev->cnic_priv;
2006 struct l4_kwq_connect_req1 *kwqe1 =
2007 (struct l4_kwq_connect_req1 *) wqes[0];
2008 struct l4_kwq_connect_req3 *kwqe3;
2009 struct l5cm_active_conn_buffer *conn_buf;
2010 struct l5cm_conn_addr_params *conn_addr;
2011 union l5cm_specific_data l5_data;
2012 u32 l5_cid = kwqe1->pg_cid;
2013 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2014 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2015 int ret;
2016
2017 if (num < 2) {
2018 *work = num;
2019 return -EINVAL;
2020 }
2021
2022 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2023 *work = 3;
2024 else
2025 *work = 2;
2026
2027 if (num < *work) {
2028 *work = num;
2029 return -EINVAL;
2030 }
2031
2032 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2033 netdev_err(dev->netdev, "conn_buf size too big\n");
2034 return -ENOMEM;
2035 }
2036 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2037 if (!conn_buf)
2038 return -ENOMEM;
2039
2040 memset(conn_buf, 0, sizeof(*conn_buf));
2041
2042 conn_addr = &conn_buf->conn_addr_buf;
2043 conn_addr->remote_addr_0 = csk->ha[0];
2044 conn_addr->remote_addr_1 = csk->ha[1];
2045 conn_addr->remote_addr_2 = csk->ha[2];
2046 conn_addr->remote_addr_3 = csk->ha[3];
2047 conn_addr->remote_addr_4 = csk->ha[4];
2048 conn_addr->remote_addr_5 = csk->ha[5];
2049
2050 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2051 struct l4_kwq_connect_req2 *kwqe2 =
2052 (struct l4_kwq_connect_req2 *) wqes[1];
2053
2054 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2055 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2056 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2057
2058 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2059 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2060 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2061 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2062 }
2063 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2064
2065 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2066 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2067 conn_addr->local_tcp_port = kwqe1->src_port;
2068 conn_addr->remote_tcp_port = kwqe1->dst_port;
2069
2070 conn_addr->pmtu = kwqe3->pmtu;
2071 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2072
2073 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2074 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2075
2076 cnic_bnx2x_set_tcp_timestamp(dev,
2077 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2078
2079 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2080 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2081 if (!ret)
2082 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2083
2084 return ret;
2085 }
2086
2087 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2088 {
2089 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2090 union l5cm_specific_data l5_data;
2091 int ret;
2092
2093 memset(&l5_data, 0, sizeof(l5_data));
2094 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2095 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2096 return ret;
2097 }
2098
2099 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2100 {
2101 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2102 union l5cm_specific_data l5_data;
2103 int ret;
2104
2105 memset(&l5_data, 0, sizeof(l5_data));
2106 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2107 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2108 return ret;
2109 }
2110 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2111 {
2112 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2113 struct l4_kcq kcqe;
2114 struct kcqe *cqes[1];
2115
2116 memset(&kcqe, 0, sizeof(kcqe));
2117 kcqe.pg_host_opaque = req->host_opaque;
2118 kcqe.pg_cid = req->host_opaque;
2119 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2120 cqes[0] = (struct kcqe *) &kcqe;
2121 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2122 return 0;
2123 }
2124
2125 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2126 {
2127 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2128 struct l4_kcq kcqe;
2129 struct kcqe *cqes[1];
2130
2131 memset(&kcqe, 0, sizeof(kcqe));
2132 kcqe.pg_host_opaque = req->pg_host_opaque;
2133 kcqe.pg_cid = req->pg_cid;
2134 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2135 cqes[0] = (struct kcqe *) &kcqe;
2136 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2137 return 0;
2138 }
2139
2140 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2141 {
2142 struct fcoe_kwqe_stat *req;
2143 struct fcoe_stat_ramrod_params *fcoe_stat;
2144 union l5cm_specific_data l5_data;
2145 struct cnic_local *cp = dev->cnic_priv;
2146 int ret;
2147 u32 cid;
2148
2149 req = (struct fcoe_kwqe_stat *) kwqe;
2150 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2151
2152 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2153 if (!fcoe_stat)
2154 return -ENOMEM;
2155
2156 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2157 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2158
2159 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
2160 FCOE_CONNECTION_TYPE, &l5_data);
2161 return ret;
2162 }
2163
2164 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2165 u32 num, int *work)
2166 {
2167 int ret;
2168 struct cnic_local *cp = dev->cnic_priv;
2169 u32 cid;
2170 struct fcoe_init_ramrod_params *fcoe_init;
2171 struct fcoe_kwqe_init1 *req1;
2172 struct fcoe_kwqe_init2 *req2;
2173 struct fcoe_kwqe_init3 *req3;
2174 union l5cm_specific_data l5_data;
2175
2176 if (num < 3) {
2177 *work = num;
2178 return -EINVAL;
2179 }
2180 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2181 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2182 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2183 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2184 *work = 1;
2185 return -EINVAL;
2186 }
2187 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2188 *work = 2;
2189 return -EINVAL;
2190 }
2191
2192 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2193 netdev_err(dev->netdev, "fcoe_init size too big\n");
2194 return -ENOMEM;
2195 }
2196 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2197 if (!fcoe_init)
2198 return -ENOMEM;
2199
2200 memset(fcoe_init, 0, sizeof(*fcoe_init));
2201 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2202 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2203 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2204 fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
2205 fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
2206 fcoe_init->eq_next_page_addr.lo =
2207 cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
2208 fcoe_init->eq_next_page_addr.hi =
2209 (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
2210
2211 fcoe_init->sb_num = cp->status_blk_num;
2212 fcoe_init->eq_prod = MAX_KCQ_IDX;
2213 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2214 cp->kcq2.sw_prod_idx = 0;
2215
2216 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2217 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
2218 FCOE_CONNECTION_TYPE, &l5_data);
2219 *work = 3;
2220 return ret;
2221 }
2222
2223 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2224 u32 num, int *work)
2225 {
2226 int ret = 0;
2227 u32 cid = -1, l5_cid;
2228 struct cnic_local *cp = dev->cnic_priv;
2229 struct fcoe_kwqe_conn_offload1 *req1;
2230 struct fcoe_kwqe_conn_offload2 *req2;
2231 struct fcoe_kwqe_conn_offload3 *req3;
2232 struct fcoe_kwqe_conn_offload4 *req4;
2233 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2234 struct cnic_context *ctx;
2235 struct fcoe_context *fctx;
2236 struct regpair ctx_addr;
2237 union l5cm_specific_data l5_data;
2238 struct fcoe_kcqe kcqe;
2239 struct kcqe *cqes[1];
2240
2241 if (num < 4) {
2242 *work = num;
2243 return -EINVAL;
2244 }
2245 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2246 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2247 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2248 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2249
2250 *work = 4;
2251
2252 l5_cid = req1->fcoe_conn_id;
2253 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2254 goto err_reply;
2255
2256 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2257
2258 ctx = &cp->ctx_tbl[l5_cid];
2259 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2260 goto err_reply;
2261
2262 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2263 if (ret) {
2264 ret = 0;
2265 goto err_reply;
2266 }
2267 cid = ctx->cid;
2268
2269 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2270 if (fctx) {
2271 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2272 u32 val;
2273
2274 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2275 FCOE_CONNECTION_TYPE);
2276 fctx->xstorm_ag_context.cdu_reserved = val;
2277 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2278 FCOE_CONNECTION_TYPE);
2279 fctx->ustorm_ag_context.cdu_usage = val;
2280 }
2281 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2282 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2283 goto err_reply;
2284 }
2285 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2286 if (!fcoe_offload)
2287 goto err_reply;
2288
2289 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2290 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2291 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2292 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2293 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2294
2295 cid = BNX2X_HW_CID(cp, cid);
2296 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2297 FCOE_CONNECTION_TYPE, &l5_data);
2298 if (!ret)
2299 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2300
2301 return ret;
2302
2303 err_reply:
2304 if (cid != -1)
2305 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2306
2307 memset(&kcqe, 0, sizeof(kcqe));
2308 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2309 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2310 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2311
2312 cqes[0] = (struct kcqe *) &kcqe;
2313 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2314 return ret;
2315 }
2316
2317 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2318 {
2319 struct fcoe_kwqe_conn_enable_disable *req;
2320 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2321 union l5cm_specific_data l5_data;
2322 int ret;
2323 u32 cid, l5_cid;
2324 struct cnic_local *cp = dev->cnic_priv;
2325
2326 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2327 cid = req->context_id;
2328 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2329
2330 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2331 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2332 return -ENOMEM;
2333 }
2334 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2335 if (!fcoe_enable)
2336 return -ENOMEM;
2337
2338 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2339 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2340 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2341 FCOE_CONNECTION_TYPE, &l5_data);
2342 return ret;
2343 }
2344
2345 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2346 {
2347 struct fcoe_kwqe_conn_enable_disable *req;
2348 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2349 union l5cm_specific_data l5_data;
2350 int ret;
2351 u32 cid, l5_cid;
2352 struct cnic_local *cp = dev->cnic_priv;
2353
2354 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2355 cid = req->context_id;
2356 l5_cid = req->conn_id;
2357 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2358 return -EINVAL;
2359
2360 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2361
2362 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2363 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2364 return -ENOMEM;
2365 }
2366 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2367 if (!fcoe_disable)
2368 return -ENOMEM;
2369
2370 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2371 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2372 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2373 FCOE_CONNECTION_TYPE, &l5_data);
2374 return ret;
2375 }
2376
2377 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2378 {
2379 struct fcoe_kwqe_conn_destroy *req;
2380 union l5cm_specific_data l5_data;
2381 int ret;
2382 u32 cid, l5_cid;
2383 struct cnic_local *cp = dev->cnic_priv;
2384 struct cnic_context *ctx;
2385 struct fcoe_kcqe kcqe;
2386 struct kcqe *cqes[1];
2387
2388 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2389 cid = req->context_id;
2390 l5_cid = req->conn_id;
2391 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2392 return -EINVAL;
2393
2394 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2395
2396 ctx = &cp->ctx_tbl[l5_cid];
2397
2398 init_waitqueue_head(&ctx->waitq);
2399 ctx->wait_cond = 0;
2400
2401 memset(&l5_data, 0, sizeof(l5_data));
2402 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2403 FCOE_CONNECTION_TYPE, &l5_data);
2404 if (ret == 0) {
2405 wait_event(ctx->waitq, ctx->wait_cond);
2406 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2407 queue_delayed_work(cnic_wq, &cp->delete_task,
2408 msecs_to_jiffies(2000));
2409 }
2410
2411 memset(&kcqe, 0, sizeof(kcqe));
2412 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2413 kcqe.fcoe_conn_id = req->conn_id;
2414 kcqe.fcoe_conn_context_id = cid;
2415
2416 cqes[0] = (struct kcqe *) &kcqe;
2417 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2418 return ret;
2419 }
2420
2421 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2422 {
2423 struct fcoe_kwqe_destroy *req;
2424 union l5cm_specific_data l5_data;
2425 struct cnic_local *cp = dev->cnic_priv;
2426 int ret;
2427 u32 cid;
2428
2429 req = (struct fcoe_kwqe_destroy *) kwqe;
2430 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2431
2432 memset(&l5_data, 0, sizeof(l5_data));
2433 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
2434 FCOE_CONNECTION_TYPE, &l5_data);
2435 return ret;
2436 }
2437
2438 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2439 struct kwqe *wqes[], u32 num_wqes)
2440 {
2441 int i, work, ret;
2442 u32 opcode;
2443 struct kwqe *kwqe;
2444
2445 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2446 return -EAGAIN; /* bnx2 is down */
2447
2448 for (i = 0; i < num_wqes; ) {
2449 kwqe = wqes[i];
2450 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2451 work = 1;
2452
2453 switch (opcode) {
2454 case ISCSI_KWQE_OPCODE_INIT1:
2455 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2456 break;
2457 case ISCSI_KWQE_OPCODE_INIT2:
2458 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2459 break;
2460 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2461 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2462 num_wqes - i, &work);
2463 break;
2464 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2465 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2466 break;
2467 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2468 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2469 break;
2470 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2471 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2472 &work);
2473 break;
2474 case L4_KWQE_OPCODE_VALUE_CLOSE:
2475 ret = cnic_bnx2x_close(dev, kwqe);
2476 break;
2477 case L4_KWQE_OPCODE_VALUE_RESET:
2478 ret = cnic_bnx2x_reset(dev, kwqe);
2479 break;
2480 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2481 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2482 break;
2483 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2484 ret = cnic_bnx2x_update_pg(dev, kwqe);
2485 break;
2486 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2487 ret = 0;
2488 break;
2489 default:
2490 ret = 0;
2491 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2492 opcode);
2493 break;
2494 }
2495 if (ret < 0)
2496 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2497 opcode);
2498 i += work;
2499 }
2500 return 0;
2501 }
2502
2503 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2504 struct kwqe *wqes[], u32 num_wqes)
2505 {
2506 struct cnic_local *cp = dev->cnic_priv;
2507 int i, work, ret;
2508 u32 opcode;
2509 struct kwqe *kwqe;
2510
2511 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2512 return -EAGAIN; /* bnx2 is down */
2513
2514 if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
2515 return -EINVAL;
2516
2517 for (i = 0; i < num_wqes; ) {
2518 kwqe = wqes[i];
2519 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2520 work = 1;
2521
2522 switch (opcode) {
2523 case FCOE_KWQE_OPCODE_INIT1:
2524 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2525 num_wqes - i, &work);
2526 break;
2527 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2528 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2529 num_wqes - i, &work);
2530 break;
2531 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2532 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2533 break;
2534 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2535 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2536 break;
2537 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2538 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2539 break;
2540 case FCOE_KWQE_OPCODE_DESTROY:
2541 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2542 break;
2543 case FCOE_KWQE_OPCODE_STAT:
2544 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2545 break;
2546 default:
2547 ret = 0;
2548 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2549 opcode);
2550 break;
2551 }
2552 if (ret < 0)
2553 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2554 opcode);
2555 i += work;
2556 }
2557 return 0;
2558 }
2559
2560 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2561 u32 num_wqes)
2562 {
2563 int ret = -EINVAL;
2564 u32 layer_code;
2565
2566 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2567 return -EAGAIN; /* bnx2x is down */
2568
2569 if (!num_wqes)
2570 return 0;
2571
2572 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2573 switch (layer_code) {
2574 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2575 case KWQE_FLAGS_LAYER_MASK_L4:
2576 case KWQE_FLAGS_LAYER_MASK_L2:
2577 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2578 break;
2579
2580 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2581 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2582 break;
2583 }
2584 return ret;
2585 }
2586
2587 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2588 {
2589 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2590 return KCQE_FLAGS_LAYER_MASK_L4;
2591
2592 return opflag & KCQE_FLAGS_LAYER_MASK;
2593 }
2594
2595 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2596 {
2597 struct cnic_local *cp = dev->cnic_priv;
2598 int i, j, comp = 0;
2599
2600 i = 0;
2601 j = 1;
2602 while (num_cqes) {
2603 struct cnic_ulp_ops *ulp_ops;
2604 int ulp_type;
2605 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2606 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2607
2608 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2609 comp++;
2610
2611 while (j < num_cqes) {
2612 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2613
2614 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2615 break;
2616
2617 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2618 comp++;
2619 j++;
2620 }
2621
2622 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2623 ulp_type = CNIC_ULP_RDMA;
2624 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2625 ulp_type = CNIC_ULP_ISCSI;
2626 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2627 ulp_type = CNIC_ULP_FCOE;
2628 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2629 ulp_type = CNIC_ULP_L4;
2630 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2631 goto end;
2632 else {
2633 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2634 kcqe_op_flag);
2635 goto end;
2636 }
2637
2638 rcu_read_lock();
2639 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2640 if (likely(ulp_ops)) {
2641 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2642 cp->completed_kcq + i, j);
2643 }
2644 rcu_read_unlock();
2645 end:
2646 num_cqes -= j;
2647 i += j;
2648 j = 1;
2649 }
2650 if (unlikely(comp))
2651 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2652 }
2653
2654 static u16 cnic_bnx2_next_idx(u16 idx)
2655 {
2656 return idx + 1;
2657 }
2658
2659 static u16 cnic_bnx2_hw_idx(u16 idx)
2660 {
2661 return idx;
2662 }
2663
2664 static u16 cnic_bnx2x_next_idx(u16 idx)
2665 {
2666 idx++;
2667 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2668 idx++;
2669
2670 return idx;
2671 }
2672
2673 static u16 cnic_bnx2x_hw_idx(u16 idx)
2674 {
2675 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2676 idx++;
2677 return idx;
2678 }
2679
2680 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2681 {
2682 struct cnic_local *cp = dev->cnic_priv;
2683 u16 i, ri, hw_prod, last;
2684 struct kcqe *kcqe;
2685 int kcqe_cnt = 0, last_cnt = 0;
2686
2687 i = ri = last = info->sw_prod_idx;
2688 ri &= MAX_KCQ_IDX;
2689 hw_prod = *info->hw_prod_idx_ptr;
2690 hw_prod = cp->hw_idx(hw_prod);
2691
2692 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2693 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2694 cp->completed_kcq[kcqe_cnt++] = kcqe;
2695 i = cp->next_idx(i);
2696 ri = i & MAX_KCQ_IDX;
2697 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2698 last_cnt = kcqe_cnt;
2699 last = i;
2700 }
2701 }
2702
2703 info->sw_prod_idx = last;
2704 return last_cnt;
2705 }
2706
2707 static int cnic_l2_completion(struct cnic_local *cp)
2708 {
2709 u16 hw_cons, sw_cons;
2710 struct cnic_uio_dev *udev = cp->udev;
2711 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2712 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2713 u32 cmd;
2714 int comp = 0;
2715
2716 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2717 return 0;
2718
2719 hw_cons = *cp->rx_cons_ptr;
2720 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2721 hw_cons++;
2722
2723 sw_cons = cp->rx_cons;
2724 while (sw_cons != hw_cons) {
2725 u8 cqe_fp_flags;
2726
2727 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2728 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2729 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2730 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2731 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2732 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2733 cmd == RAMROD_CMD_ID_ETH_HALT)
2734 comp++;
2735 }
2736 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2737 }
2738 return comp;
2739 }
2740
2741 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2742 {
2743 u16 rx_cons, tx_cons;
2744 int comp = 0;
2745
2746 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2747 return;
2748
2749 rx_cons = *cp->rx_cons_ptr;
2750 tx_cons = *cp->tx_cons_ptr;
2751 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2752 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2753 comp = cnic_l2_completion(cp);
2754
2755 cp->tx_cons = tx_cons;
2756 cp->rx_cons = rx_cons;
2757
2758 if (cp->udev)
2759 uio_event_notify(&cp->udev->cnic_uinfo);
2760 }
2761 if (comp)
2762 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2763 }
2764
2765 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2766 {
2767 struct cnic_local *cp = dev->cnic_priv;
2768 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2769 int kcqe_cnt;
2770
2771 /* status block index must be read before reading other fields */
2772 rmb();
2773 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2774
2775 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2776
2777 service_kcqes(dev, kcqe_cnt);
2778
2779 /* Tell compiler that status_blk fields can change. */
2780 barrier();
2781 if (status_idx != *cp->kcq1.status_idx_ptr) {
2782 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2783 /* status block index must be read first */
2784 rmb();
2785 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2786 } else
2787 break;
2788 }
2789
2790 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2791
2792 cnic_chk_pkt_rings(cp);
2793
2794 return status_idx;
2795 }
2796
2797 static int cnic_service_bnx2(void *data, void *status_blk)
2798 {
2799 struct cnic_dev *dev = data;
2800
2801 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2802 struct status_block *sblk = status_blk;
2803
2804 return sblk->status_idx;
2805 }
2806
2807 return cnic_service_bnx2_queues(dev);
2808 }
2809
2810 static void cnic_service_bnx2_msix(unsigned long data)
2811 {
2812 struct cnic_dev *dev = (struct cnic_dev *) data;
2813 struct cnic_local *cp = dev->cnic_priv;
2814
2815 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2816
2817 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2818 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2819 }
2820
2821 static void cnic_doirq(struct cnic_dev *dev)
2822 {
2823 struct cnic_local *cp = dev->cnic_priv;
2824
2825 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2826 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2827
2828 prefetch(cp->status_blk.gen);
2829 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2830
2831 tasklet_schedule(&cp->cnic_irq_task);
2832 }
2833 }
2834
2835 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2836 {
2837 struct cnic_dev *dev = dev_instance;
2838 struct cnic_local *cp = dev->cnic_priv;
2839
2840 if (cp->ack_int)
2841 cp->ack_int(dev);
2842
2843 cnic_doirq(dev);
2844
2845 return IRQ_HANDLED;
2846 }
2847
2848 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2849 u16 index, u8 op, u8 update)
2850 {
2851 struct cnic_local *cp = dev->cnic_priv;
2852 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2853 COMMAND_REG_INT_ACK);
2854 struct igu_ack_register igu_ack;
2855
2856 igu_ack.status_block_index = index;
2857 igu_ack.sb_id_and_flags =
2858 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2859 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2860 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2861 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2862
2863 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2864 }
2865
2866 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
2867 u16 index, u8 op, u8 update)
2868 {
2869 struct igu_regular cmd_data;
2870 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
2871
2872 cmd_data.sb_id_and_flags =
2873 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
2874 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2875 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2876 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
2877
2878
2879 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
2880 }
2881
2882 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2883 {
2884 struct cnic_local *cp = dev->cnic_priv;
2885
2886 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2887 IGU_INT_DISABLE, 0);
2888 }
2889
2890 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
2891 {
2892 struct cnic_local *cp = dev->cnic_priv;
2893
2894 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
2895 IGU_INT_DISABLE, 0);
2896 }
2897
2898 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2899 {
2900 u32 last_status = *info->status_idx_ptr;
2901 int kcqe_cnt;
2902
2903 /* status block index must be read before reading the KCQ */
2904 rmb();
2905 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2906
2907 service_kcqes(dev, kcqe_cnt);
2908
2909 /* Tell compiler that sblk fields can change. */
2910 barrier();
2911 if (last_status == *info->status_idx_ptr)
2912 break;
2913
2914 last_status = *info->status_idx_ptr;
2915 /* status block index must be read before reading the KCQ */
2916 rmb();
2917 }
2918 return last_status;
2919 }
2920
2921 static void cnic_service_bnx2x_bh(unsigned long data)
2922 {
2923 struct cnic_dev *dev = (struct cnic_dev *) data;
2924 struct cnic_local *cp = dev->cnic_priv;
2925 u32 status_idx, new_status_idx;
2926
2927 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2928 return;
2929
2930 while (1) {
2931 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2932
2933 CNIC_WR16(dev, cp->kcq1.io_addr,
2934 cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2935
2936 if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
2937 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2938 status_idx, IGU_INT_ENABLE, 1);
2939 break;
2940 }
2941
2942 new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
2943
2944 if (new_status_idx != status_idx)
2945 continue;
2946
2947 CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
2948 MAX_KCQ_IDX);
2949
2950 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
2951 status_idx, IGU_INT_ENABLE, 1);
2952
2953 break;
2954 }
2955 }
2956
2957 static int cnic_service_bnx2x(void *data, void *status_blk)
2958 {
2959 struct cnic_dev *dev = data;
2960 struct cnic_local *cp = dev->cnic_priv;
2961
2962 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2963 cnic_doirq(dev);
2964
2965 cnic_chk_pkt_rings(cp);
2966
2967 return 0;
2968 }
2969
2970 static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
2971 {
2972 struct cnic_ulp_ops *ulp_ops;
2973
2974 if (if_type == CNIC_ULP_ISCSI)
2975 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2976
2977 mutex_lock(&cnic_lock);
2978 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
2979 lockdep_is_held(&cnic_lock));
2980 if (!ulp_ops) {
2981 mutex_unlock(&cnic_lock);
2982 return;
2983 }
2984 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2985 mutex_unlock(&cnic_lock);
2986
2987 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2988 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2989
2990 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2991 }
2992
2993 static void cnic_ulp_stop(struct cnic_dev *dev)
2994 {
2995 struct cnic_local *cp = dev->cnic_priv;
2996 int if_type;
2997
2998 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
2999 cnic_ulp_stop_one(cp, if_type);
3000 }
3001
3002 static void cnic_ulp_start(struct cnic_dev *dev)
3003 {
3004 struct cnic_local *cp = dev->cnic_priv;
3005 int if_type;
3006
3007 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
3008 struct cnic_ulp_ops *ulp_ops;
3009
3010 mutex_lock(&cnic_lock);
3011 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3012 lockdep_is_held(&cnic_lock));
3013 if (!ulp_ops || !ulp_ops->cnic_start) {
3014 mutex_unlock(&cnic_lock);
3015 continue;
3016 }
3017 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3018 mutex_unlock(&cnic_lock);
3019
3020 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3021 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
3022
3023 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3024 }
3025 }
3026
3027 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
3028 {
3029 struct cnic_dev *dev = data;
3030
3031 switch (info->cmd) {
3032 case CNIC_CTL_STOP_CMD:
3033 cnic_hold(dev);
3034
3035 cnic_ulp_stop(dev);
3036 cnic_stop_hw(dev);
3037
3038 cnic_put(dev);
3039 break;
3040 case CNIC_CTL_START_CMD:
3041 cnic_hold(dev);
3042
3043 if (!cnic_start_hw(dev))
3044 cnic_ulp_start(dev);
3045
3046 cnic_put(dev);
3047 break;
3048 case CNIC_CTL_STOP_ISCSI_CMD: {
3049 struct cnic_local *cp = dev->cnic_priv;
3050 set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
3051 queue_delayed_work(cnic_wq, &cp->delete_task, 0);
3052 break;
3053 }
3054 case CNIC_CTL_COMPLETION_CMD: {
3055 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
3056 u32 l5_cid;
3057 struct cnic_local *cp = dev->cnic_priv;
3058
3059 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3060 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3061
3062 ctx->wait_cond = 1;
3063 wake_up(&ctx->waitq);
3064 }
3065 break;
3066 }
3067 default:
3068 return -EINVAL;
3069 }
3070 return 0;
3071 }
3072
3073 static void cnic_ulp_init(struct cnic_dev *dev)
3074 {
3075 int i;
3076 struct cnic_local *cp = dev->cnic_priv;
3077
3078 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3079 struct cnic_ulp_ops *ulp_ops;
3080
3081 mutex_lock(&cnic_lock);
3082 ulp_ops = cnic_ulp_tbl_prot(i);
3083 if (!ulp_ops || !ulp_ops->cnic_init) {
3084 mutex_unlock(&cnic_lock);
3085 continue;
3086 }
3087 ulp_get(ulp_ops);
3088 mutex_unlock(&cnic_lock);
3089
3090 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3091 ulp_ops->cnic_init(dev);
3092
3093 ulp_put(ulp_ops);
3094 }
3095 }
3096
3097 static void cnic_ulp_exit(struct cnic_dev *dev)
3098 {
3099 int i;
3100 struct cnic_local *cp = dev->cnic_priv;
3101
3102 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3103 struct cnic_ulp_ops *ulp_ops;
3104
3105 mutex_lock(&cnic_lock);
3106 ulp_ops = cnic_ulp_tbl_prot(i);
3107 if (!ulp_ops || !ulp_ops->cnic_exit) {
3108 mutex_unlock(&cnic_lock);
3109 continue;
3110 }
3111 ulp_get(ulp_ops);
3112 mutex_unlock(&cnic_lock);
3113
3114 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3115 ulp_ops->cnic_exit(dev);
3116
3117 ulp_put(ulp_ops);
3118 }
3119 }
3120
3121 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3122 {
3123 struct cnic_dev *dev = csk->dev;
3124 struct l4_kwq_offload_pg *l4kwqe;
3125 struct kwqe *wqes[1];
3126
3127 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3128 memset(l4kwqe, 0, sizeof(*l4kwqe));
3129 wqes[0] = (struct kwqe *) l4kwqe;
3130
3131 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3132 l4kwqe->flags =
3133 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3134 l4kwqe->l2hdr_nbytes = ETH_HLEN;
3135
3136 l4kwqe->da0 = csk->ha[0];
3137 l4kwqe->da1 = csk->ha[1];
3138 l4kwqe->da2 = csk->ha[2];
3139 l4kwqe->da3 = csk->ha[3];
3140 l4kwqe->da4 = csk->ha[4];
3141 l4kwqe->da5 = csk->ha[5];
3142
3143 l4kwqe->sa0 = dev->mac_addr[0];
3144 l4kwqe->sa1 = dev->mac_addr[1];
3145 l4kwqe->sa2 = dev->mac_addr[2];
3146 l4kwqe->sa3 = dev->mac_addr[3];
3147 l4kwqe->sa4 = dev->mac_addr[4];
3148 l4kwqe->sa5 = dev->mac_addr[5];
3149
3150 l4kwqe->etype = ETH_P_IP;
3151 l4kwqe->ipid_start = DEF_IPID_START;
3152 l4kwqe->host_opaque = csk->l5_cid;
3153
3154 if (csk->vlan_id) {
3155 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3156 l4kwqe->vlan_tag = csk->vlan_id;
3157 l4kwqe->l2hdr_nbytes += 4;
3158 }
3159
3160 return dev->submit_kwqes(dev, wqes, 1);
3161 }
3162
3163 static int cnic_cm_update_pg(struct cnic_sock *csk)
3164 {
3165 struct cnic_dev *dev = csk->dev;
3166 struct l4_kwq_update_pg *l4kwqe;
3167 struct kwqe *wqes[1];
3168
3169 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3170 memset(l4kwqe, 0, sizeof(*l4kwqe));
3171 wqes[0] = (struct kwqe *) l4kwqe;
3172
3173 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3174 l4kwqe->flags =
3175 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3176 l4kwqe->pg_cid = csk->pg_cid;
3177
3178 l4kwqe->da0 = csk->ha[0];
3179 l4kwqe->da1 = csk->ha[1];
3180 l4kwqe->da2 = csk->ha[2];
3181 l4kwqe->da3 = csk->ha[3];
3182 l4kwqe->da4 = csk->ha[4];
3183 l4kwqe->da5 = csk->ha[5];
3184
3185 l4kwqe->pg_host_opaque = csk->l5_cid;
3186 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3187
3188 return dev->submit_kwqes(dev, wqes, 1);
3189 }
3190
3191 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3192 {
3193 struct cnic_dev *dev = csk->dev;
3194 struct l4_kwq_upload *l4kwqe;
3195 struct kwqe *wqes[1];
3196
3197 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3198 memset(l4kwqe, 0, sizeof(*l4kwqe));
3199 wqes[0] = (struct kwqe *) l4kwqe;
3200
3201 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3202 l4kwqe->flags =
3203 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3204 l4kwqe->cid = csk->pg_cid;
3205
3206 return dev->submit_kwqes(dev, wqes, 1);
3207 }
3208
3209 static int cnic_cm_conn_req(struct cnic_sock *csk)
3210 {
3211 struct cnic_dev *dev = csk->dev;
3212 struct l4_kwq_connect_req1 *l4kwqe1;
3213 struct l4_kwq_connect_req2 *l4kwqe2;
3214 struct l4_kwq_connect_req3 *l4kwqe3;
3215 struct kwqe *wqes[3];
3216 u8 tcp_flags = 0;
3217 int num_wqes = 2;
3218
3219 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3220 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3221 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3222 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3223 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3224 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3225
3226 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3227 l4kwqe3->flags =
3228 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3229 l4kwqe3->ka_timeout = csk->ka_timeout;
3230 l4kwqe3->ka_interval = csk->ka_interval;
3231 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3232 l4kwqe3->tos = csk->tos;
3233 l4kwqe3->ttl = csk->ttl;
3234 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3235 l4kwqe3->pmtu = csk->mtu;
3236 l4kwqe3->rcv_buf = csk->rcv_buf;
3237 l4kwqe3->snd_buf = csk->snd_buf;
3238 l4kwqe3->seed = csk->seed;
3239
3240 wqes[0] = (struct kwqe *) l4kwqe1;
3241 if (test_bit(SK_F_IPV6, &csk->flags)) {
3242 wqes[1] = (struct kwqe *) l4kwqe2;
3243 wqes[2] = (struct kwqe *) l4kwqe3;
3244 num_wqes = 3;
3245
3246 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3247 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3248 l4kwqe2->flags =
3249 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3250 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3251 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3252 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3253 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3254 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3255 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3256 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3257 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3258 sizeof(struct tcphdr);
3259 } else {
3260 wqes[1] = (struct kwqe *) l4kwqe3;
3261 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3262 sizeof(struct tcphdr);
3263 }
3264
3265 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3266 l4kwqe1->flags =
3267 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3268 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3269 l4kwqe1->cid = csk->cid;
3270 l4kwqe1->pg_cid = csk->pg_cid;
3271 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3272 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3273 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3274 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3275 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3276 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3277 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3278 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3279 if (csk->tcp_flags & SK_TCP_NAGLE)
3280 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3281 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3282 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3283 if (csk->tcp_flags & SK_TCP_SACK)
3284 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3285 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3286 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3287
3288 l4kwqe1->tcp_flags = tcp_flags;
3289
3290 return dev->submit_kwqes(dev, wqes, num_wqes);
3291 }
3292
3293 static int cnic_cm_close_req(struct cnic_sock *csk)
3294 {
3295 struct cnic_dev *dev = csk->dev;
3296 struct l4_kwq_close_req *l4kwqe;
3297 struct kwqe *wqes[1];
3298
3299 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3300 memset(l4kwqe, 0, sizeof(*l4kwqe));
3301 wqes[0] = (struct kwqe *) l4kwqe;
3302
3303 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3304 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3305 l4kwqe->cid = csk->cid;
3306
3307 return dev->submit_kwqes(dev, wqes, 1);
3308 }
3309
3310 static int cnic_cm_abort_req(struct cnic_sock *csk)
3311 {
3312 struct cnic_dev *dev = csk->dev;
3313 struct l4_kwq_reset_req *l4kwqe;
3314 struct kwqe *wqes[1];
3315
3316 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3317 memset(l4kwqe, 0, sizeof(*l4kwqe));
3318 wqes[0] = (struct kwqe *) l4kwqe;
3319
3320 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3321 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3322 l4kwqe->cid = csk->cid;
3323
3324 return dev->submit_kwqes(dev, wqes, 1);
3325 }
3326
3327 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3328 u32 l5_cid, struct cnic_sock **csk, void *context)
3329 {
3330 struct cnic_local *cp = dev->cnic_priv;
3331 struct cnic_sock *csk1;
3332
3333 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3334 return -EINVAL;
3335
3336 if (cp->ctx_tbl) {
3337 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3338
3339 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3340 return -EAGAIN;
3341 }
3342
3343 csk1 = &cp->csk_tbl[l5_cid];
3344 if (atomic_read(&csk1->ref_count))
3345 return -EAGAIN;
3346
3347 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3348 return -EBUSY;
3349
3350 csk1->dev = dev;
3351 csk1->cid = cid;
3352 csk1->l5_cid = l5_cid;
3353 csk1->ulp_type = ulp_type;
3354 csk1->context = context;
3355
3356 csk1->ka_timeout = DEF_KA_TIMEOUT;
3357 csk1->ka_interval = DEF_KA_INTERVAL;
3358 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3359 csk1->tos = DEF_TOS;
3360 csk1->ttl = DEF_TTL;
3361 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3362 csk1->rcv_buf = DEF_RCV_BUF;
3363 csk1->snd_buf = DEF_SND_BUF;
3364 csk1->seed = DEF_SEED;
3365
3366 *csk = csk1;
3367 return 0;
3368 }
3369
3370 static void cnic_cm_cleanup(struct cnic_sock *csk)
3371 {
3372 if (csk->src_port) {
3373 struct cnic_dev *dev = csk->dev;
3374 struct cnic_local *cp = dev->cnic_priv;
3375
3376 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3377 csk->src_port = 0;
3378 }
3379 }
3380
3381 static void cnic_close_conn(struct cnic_sock *csk)
3382 {
3383 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3384 cnic_cm_upload_pg(csk);
3385 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3386 }
3387 cnic_cm_cleanup(csk);
3388 }
3389
3390 static int cnic_cm_destroy(struct cnic_sock *csk)
3391 {
3392 if (!cnic_in_use(csk))
3393 return -EINVAL;
3394
3395 csk_hold(csk);
3396 clear_bit(SK_F_INUSE, &csk->flags);
3397 smp_mb__after_clear_bit();
3398 while (atomic_read(&csk->ref_count) != 1)
3399 msleep(1);
3400 cnic_cm_cleanup(csk);
3401
3402 csk->flags = 0;
3403 csk_put(csk);
3404 return 0;
3405 }
3406
3407 static inline u16 cnic_get_vlan(struct net_device *dev,
3408 struct net_device **vlan_dev)
3409 {
3410 if (dev->priv_flags & IFF_802_1Q_VLAN) {
3411 *vlan_dev = vlan_dev_real_dev(dev);
3412 return vlan_dev_vlan_id(dev);
3413 }
3414 *vlan_dev = dev;
3415 return 0;
3416 }
3417
3418 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3419 struct dst_entry **dst)
3420 {
3421 #if defined(CONFIG_INET)
3422 struct rtable *rt;
3423
3424 rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
3425 if (!IS_ERR(rt)) {
3426 *dst = &rt->dst;
3427 return 0;
3428 }
3429 return PTR_ERR(rt);
3430 #else
3431 return -ENETUNREACH;
3432 #endif
3433 }
3434
3435 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3436 struct dst_entry **dst)
3437 {
3438 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
3439 struct flowi6 fl6;
3440
3441 memset(&fl6, 0, sizeof(fl6));
3442 ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
3443 if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
3444 fl6.flowi6_oif = dst_addr->sin6_scope_id;
3445
3446 *dst = ip6_route_output(&init_net, NULL, &fl6);
3447 if (*dst)
3448 return 0;
3449 #endif
3450
3451 return -ENETUNREACH;
3452 }
3453
3454 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3455 int ulp_type)
3456 {
3457 struct cnic_dev *dev = NULL;
3458 struct dst_entry *dst;
3459 struct net_device *netdev = NULL;
3460 int err = -ENETUNREACH;
3461
3462 if (dst_addr->sin_family == AF_INET)
3463 err = cnic_get_v4_route(dst_addr, &dst);
3464 else if (dst_addr->sin_family == AF_INET6) {
3465 struct sockaddr_in6 *dst_addr6 =
3466 (struct sockaddr_in6 *) dst_addr;
3467
3468 err = cnic_get_v6_route(dst_addr6, &dst);
3469 } else
3470 return NULL;
3471
3472 if (err)
3473 return NULL;
3474
3475 if (!dst->dev)
3476 goto done;
3477
3478 cnic_get_vlan(dst->dev, &netdev);
3479
3480 dev = cnic_from_netdev(netdev);
3481
3482 done:
3483 dst_release(dst);
3484 if (dev)
3485 cnic_put(dev);
3486 return dev;
3487 }
3488
3489 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3490 {
3491 struct cnic_dev *dev = csk->dev;
3492 struct cnic_local *cp = dev->cnic_priv;
3493
3494 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3495 }
3496
3497 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3498 {
3499 struct cnic_dev *dev = csk->dev;
3500 struct cnic_local *cp = dev->cnic_priv;
3501 int is_v6, rc = 0;
3502 struct dst_entry *dst = NULL;
3503 struct net_device *realdev;
3504 __be16 local_port;
3505 u32 port_id;
3506
3507 if (saddr->local.v6.sin6_family == AF_INET6 &&
3508 saddr->remote.v6.sin6_family == AF_INET6)
3509 is_v6 = 1;
3510 else if (saddr->local.v4.sin_family == AF_INET &&
3511 saddr->remote.v4.sin_family == AF_INET)
3512 is_v6 = 0;
3513 else
3514 return -EINVAL;
3515
3516 clear_bit(SK_F_IPV6, &csk->flags);
3517
3518 if (is_v6) {
3519 set_bit(SK_F_IPV6, &csk->flags);
3520 cnic_get_v6_route(&saddr->remote.v6, &dst);
3521
3522 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3523 sizeof(struct in6_addr));
3524 csk->dst_port = saddr->remote.v6.sin6_port;
3525 local_port = saddr->local.v6.sin6_port;
3526
3527 } else {
3528 cnic_get_v4_route(&saddr->remote.v4, &dst);
3529
3530 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3531 csk->dst_port = saddr->remote.v4.sin_port;
3532 local_port = saddr->local.v4.sin_port;
3533 }
3534
3535 csk->vlan_id = 0;
3536 csk->mtu = dev->netdev->mtu;
3537 if (dst && dst->dev) {
3538 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3539 if (realdev == dev->netdev) {
3540 csk->vlan_id = vlan;
3541 csk->mtu = dst_mtu(dst);
3542 }
3543 }
3544
3545 port_id = be16_to_cpu(local_port);
3546 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3547 port_id < CNIC_LOCAL_PORT_MAX) {
3548 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3549 port_id = 0;
3550 } else
3551 port_id = 0;
3552
3553 if (!port_id) {
3554 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3555 if (port_id == -1) {
3556 rc = -ENOMEM;
3557 goto err_out;
3558 }
3559 local_port = cpu_to_be16(port_id);
3560 }
3561 csk->src_port = local_port;
3562
3563 err_out:
3564 dst_release(dst);
3565 return rc;
3566 }
3567
3568 static void cnic_init_csk_state(struct cnic_sock *csk)
3569 {
3570 csk->state = 0;
3571 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3572 clear_bit(SK_F_CLOSING, &csk->flags);
3573 }
3574
3575 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3576 {
3577 struct cnic_local *cp = csk->dev->cnic_priv;
3578 int err = 0;
3579
3580 if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
3581 return -EOPNOTSUPP;
3582
3583 if (!cnic_in_use(csk))
3584 return -EINVAL;
3585
3586 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3587 return -EINVAL;
3588
3589 cnic_init_csk_state(csk);
3590
3591 err = cnic_get_route(csk, saddr);
3592 if (err)
3593 goto err_out;
3594
3595 err = cnic_resolve_addr(csk, saddr);
3596 if (!err)
3597 return 0;
3598
3599 err_out:
3600 clear_bit(SK_F_CONNECT_START, &csk->flags);
3601 return err;
3602 }
3603
3604 static int cnic_cm_abort(struct cnic_sock *csk)
3605 {
3606 struct cnic_local *cp = csk->dev->cnic_priv;
3607 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3608
3609 if (!cnic_in_use(csk))
3610 return -EINVAL;
3611
3612 if (cnic_abort_prep(csk))
3613 return cnic_cm_abort_req(csk);
3614
3615 /* Getting here means that we haven't started connect, or
3616 * connect was not successful.
3617 */
3618
3619 cp->close_conn(csk, opcode);
3620 if (csk->state != opcode)
3621 return -EALREADY;
3622
3623 return 0;
3624 }
3625
3626 static int cnic_cm_close(struct cnic_sock *csk)
3627 {
3628 if (!cnic_in_use(csk))
3629 return -EINVAL;
3630
3631 if (cnic_close_prep(csk)) {
3632 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3633 return cnic_cm_close_req(csk);
3634 } else {
3635 return -EALREADY;
3636 }
3637 return 0;
3638 }
3639
3640 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3641 u8 opcode)
3642 {
3643 struct cnic_ulp_ops *ulp_ops;
3644 int ulp_type = csk->ulp_type;
3645
3646 rcu_read_lock();
3647 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3648 if (ulp_ops) {
3649 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3650 ulp_ops->cm_connect_complete(csk);
3651 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3652 ulp_ops->cm_close_complete(csk);
3653 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3654 ulp_ops->cm_remote_abort(csk);
3655 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3656 ulp_ops->cm_abort_complete(csk);
3657 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3658 ulp_ops->cm_remote_close(csk);
3659 }
3660 rcu_read_unlock();
3661 }
3662
3663 static int cnic_cm_set_pg(struct cnic_sock *csk)
3664 {
3665 if (cnic_offld_prep(csk)) {
3666 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3667 cnic_cm_update_pg(csk);
3668 else
3669 cnic_cm_offload_pg(csk);
3670 }
3671 return 0;
3672 }
3673
3674 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3675 {
3676 struct cnic_local *cp = dev->cnic_priv;
3677 u32 l5_cid = kcqe->pg_host_opaque;
3678 u8 opcode = kcqe->op_code;
3679 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3680
3681 csk_hold(csk);
3682 if (!cnic_in_use(csk))
3683 goto done;
3684
3685 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3686 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3687 goto done;
3688 }
3689 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3690 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3691 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3692 cnic_cm_upcall(cp, csk,
3693 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3694 goto done;
3695 }
3696
3697 csk->pg_cid = kcqe->pg_cid;
3698 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3699 cnic_cm_conn_req(csk);
3700
3701 done:
3702 csk_put(csk);
3703 }
3704
3705 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3706 {
3707 struct cnic_local *cp = dev->cnic_priv;
3708 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3709 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3710 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3711
3712 ctx->timestamp = jiffies;
3713 ctx->wait_cond = 1;
3714 wake_up(&ctx->waitq);
3715 }
3716
3717 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3718 {
3719 struct cnic_local *cp = dev->cnic_priv;
3720 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3721 u8 opcode = l4kcqe->op_code;
3722 u32 l5_cid;
3723 struct cnic_sock *csk;
3724
3725 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3726 cnic_process_fcoe_term_conn(dev, kcqe);
3727 return;
3728 }
3729 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3730 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3731 cnic_cm_process_offld_pg(dev, l4kcqe);
3732 return;
3733 }
3734
3735 l5_cid = l4kcqe->conn_id;
3736 if (opcode & 0x80)
3737 l5_cid = l4kcqe->cid;
3738 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3739 return;
3740
3741 csk = &cp->csk_tbl[l5_cid];
3742 csk_hold(csk);
3743
3744 if (!cnic_in_use(csk)) {
3745 csk_put(csk);
3746 return;
3747 }
3748
3749 switch (opcode) {
3750 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3751 if (l4kcqe->status != 0) {
3752 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3753 cnic_cm_upcall(cp, csk,
3754 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3755 }
3756 break;
3757 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3758 if (l4kcqe->status == 0)
3759 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3760
3761 smp_mb__before_clear_bit();
3762 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3763 cnic_cm_upcall(cp, csk, opcode);
3764 break;
3765
3766 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3767 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3768 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3769 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3770 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3771 cp->close_conn(csk, opcode);
3772 break;
3773
3774 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3775 cnic_cm_upcall(cp, csk, opcode);
3776 break;
3777 }
3778 csk_put(csk);
3779 }
3780
3781 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3782 {
3783 struct cnic_dev *dev = data;
3784 int i;
3785
3786 for (i = 0; i < num; i++)
3787 cnic_cm_process_kcqe(dev, kcqe[i]);
3788 }
3789
3790 static struct cnic_ulp_ops cm_ulp_ops = {
3791 .indicate_kcqes = cnic_cm_indicate_kcqe,
3792 };
3793
3794 static void cnic_cm_free_mem(struct cnic_dev *dev)
3795 {
3796 struct cnic_local *cp = dev->cnic_priv;
3797
3798 kfree(cp->csk_tbl);
3799 cp->csk_tbl = NULL;
3800 cnic_free_id_tbl(&cp->csk_port_tbl);
3801 }
3802
3803 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3804 {
3805 struct cnic_local *cp = dev->cnic_priv;
3806
3807 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3808 GFP_KERNEL);
3809 if (!cp->csk_tbl)
3810 return -ENOMEM;
3811
3812 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3813 CNIC_LOCAL_PORT_MIN)) {
3814 cnic_cm_free_mem(dev);
3815 return -ENOMEM;
3816 }
3817 return 0;
3818 }
3819
3820 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3821 {
3822 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3823 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3824 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3825 csk->state = opcode;
3826 }
3827
3828 /* 1. If event opcode matches the expected event in csk->state
3829 * 2. If the expected event is CLOSE_COMP, we accept any event
3830 * 3. If the expected event is 0, meaning the connection was never
3831 * never established, we accept the opcode from cm_abort.
3832 */
3833 if (opcode == csk->state || csk->state == 0 ||
3834 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3835 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3836 if (csk->state == 0)
3837 csk->state = opcode;
3838 return 1;
3839 }
3840 }
3841 return 0;
3842 }
3843
3844 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3845 {
3846 struct cnic_dev *dev = csk->dev;
3847 struct cnic_local *cp = dev->cnic_priv;
3848
3849 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3850 cnic_cm_upcall(cp, csk, opcode);
3851 return;
3852 }
3853
3854 clear_bit(SK_F_CONNECT_START, &csk->flags);
3855 cnic_close_conn(csk);
3856 csk->state = opcode;
3857 cnic_cm_upcall(cp, csk, opcode);
3858 }
3859
3860 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3861 {
3862 }
3863
3864 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3865 {
3866 u32 seed;
3867
3868 get_random_bytes(&seed, 4);
3869 cnic_ctx_wr(dev, 45, 0, seed);
3870 return 0;
3871 }
3872
3873 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3874 {
3875 struct cnic_dev *dev = csk->dev;
3876 struct cnic_local *cp = dev->cnic_priv;
3877 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3878 union l5cm_specific_data l5_data;
3879 u32 cmd = 0;
3880 int close_complete = 0;
3881
3882 switch (opcode) {
3883 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3884 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3885 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3886 if (cnic_ready_to_close(csk, opcode)) {
3887 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3888 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3889 else
3890 close_complete = 1;
3891 }
3892 break;
3893 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3894 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3895 break;
3896 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3897 close_complete = 1;
3898 break;
3899 }
3900 if (cmd) {
3901 memset(&l5_data, 0, sizeof(l5_data));
3902
3903 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3904 &l5_data);
3905 } else if (close_complete) {
3906 ctx->timestamp = jiffies;
3907 cnic_close_conn(csk);
3908 cnic_cm_upcall(cp, csk, csk->state);
3909 }
3910 }
3911
3912 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3913 {
3914 struct cnic_local *cp = dev->cnic_priv;
3915 int i;
3916
3917 if (!cp->ctx_tbl)
3918 return;
3919
3920 if (!netif_running(dev->netdev))
3921 return;
3922
3923 for (i = 0; i < cp->max_cid_space; i++) {
3924 struct cnic_context *ctx = &cp->ctx_tbl[i];
3925
3926 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3927 msleep(10);
3928
3929 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3930 netdev_warn(dev->netdev, "CID %x not deleted\n",
3931 ctx->cid);
3932 }
3933
3934 cancel_delayed_work(&cp->delete_task);
3935 flush_workqueue(cnic_wq);
3936
3937 if (atomic_read(&cp->iscsi_conn) != 0)
3938 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3939 atomic_read(&cp->iscsi_conn));
3940 }
3941
3942 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3943 {
3944 struct cnic_local *cp = dev->cnic_priv;
3945 u32 pfid = cp->pfid;
3946 u32 port = CNIC_PORT(cp);
3947
3948 cnic_init_bnx2x_mac(dev);
3949 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3950
3951 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3952 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3953
3954 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3955 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3956 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3957 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3958 DEF_MAX_DA_COUNT);
3959
3960 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3961 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3962 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3963 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3964 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3965 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3966 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3967 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
3968
3969 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
3970 DEF_MAX_CWND);
3971 return 0;
3972 }
3973
3974 static void cnic_delete_task(struct work_struct *work)
3975 {
3976 struct cnic_local *cp;
3977 struct cnic_dev *dev;
3978 u32 i;
3979 int need_resched = 0;
3980
3981 cp = container_of(work, struct cnic_local, delete_task.work);
3982 dev = cp->dev;
3983
3984 if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
3985 struct drv_ctl_info info;
3986
3987 cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
3988
3989 info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
3990 cp->ethdev->drv_ctl(dev->netdev, &info);
3991 }
3992
3993 for (i = 0; i < cp->max_cid_space; i++) {
3994 struct cnic_context *ctx = &cp->ctx_tbl[i];
3995
3996 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
3997 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3998 continue;
3999
4000 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
4001 need_resched = 1;
4002 continue;
4003 }
4004
4005 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4006 continue;
4007
4008 cnic_bnx2x_destroy_ramrod(dev, i);
4009
4010 cnic_free_bnx2x_conn_resc(dev, i);
4011 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
4012 atomic_dec(&cp->iscsi_conn);
4013
4014 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
4015 }
4016
4017 if (need_resched)
4018 queue_delayed_work(cnic_wq, &cp->delete_task,
4019 msecs_to_jiffies(10));
4020
4021 }
4022
4023 static int cnic_cm_open(struct cnic_dev *dev)
4024 {
4025 struct cnic_local *cp = dev->cnic_priv;
4026 int err;
4027
4028 err = cnic_cm_alloc_mem(dev);
4029 if (err)
4030 return err;
4031
4032 err = cp->start_cm(dev);
4033
4034 if (err)
4035 goto err_out;
4036
4037 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
4038
4039 dev->cm_create = cnic_cm_create;
4040 dev->cm_destroy = cnic_cm_destroy;
4041 dev->cm_connect = cnic_cm_connect;
4042 dev->cm_abort = cnic_cm_abort;
4043 dev->cm_close = cnic_cm_close;
4044 dev->cm_select_dev = cnic_cm_select_dev;
4045
4046 cp->ulp_handle[CNIC_ULP_L4] = dev;
4047 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
4048 return 0;
4049
4050 err_out:
4051 cnic_cm_free_mem(dev);
4052 return err;
4053 }
4054
4055 static int cnic_cm_shutdown(struct cnic_dev *dev)
4056 {
4057 struct cnic_local *cp = dev->cnic_priv;
4058 int i;
4059
4060 cp->stop_cm(dev);
4061
4062 if (!cp->csk_tbl)
4063 return 0;
4064
4065 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4066 struct cnic_sock *csk = &cp->csk_tbl[i];
4067
4068 clear_bit(SK_F_INUSE, &csk->flags);
4069 cnic_cm_cleanup(csk);
4070 }
4071 cnic_cm_free_mem(dev);
4072
4073 return 0;
4074 }
4075
4076 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4077 {
4078 u32 cid_addr;
4079 int i;
4080
4081 cid_addr = GET_CID_ADDR(cid);
4082
4083 for (i = 0; i < CTX_SIZE; i += 4)
4084 cnic_ctx_wr(dev, cid_addr, i, 0);
4085 }
4086
4087 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4088 {
4089 struct cnic_local *cp = dev->cnic_priv;
4090 int ret = 0, i;
4091 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4092
4093 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4094 return 0;
4095
4096 for (i = 0; i < cp->ctx_blks; i++) {
4097 int j;
4098 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4099 u32 val;
4100
4101 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
4102
4103 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4104 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4105 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4106 (u64) cp->ctx_arr[i].mapping >> 32);
4107 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4108 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4109 for (j = 0; j < 10; j++) {
4110
4111 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4112 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4113 break;
4114 udelay(5);
4115 }
4116 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4117 ret = -EBUSY;
4118 break;
4119 }
4120 }
4121 return ret;
4122 }
4123
4124 static void cnic_free_irq(struct cnic_dev *dev)
4125 {
4126 struct cnic_local *cp = dev->cnic_priv;
4127 struct cnic_eth_dev *ethdev = cp->ethdev;
4128
4129 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4130 cp->disable_int_sync(dev);
4131 tasklet_kill(&cp->cnic_irq_task);
4132 free_irq(ethdev->irq_arr[0].vector, dev);
4133 }
4134 }
4135
4136 static int cnic_request_irq(struct cnic_dev *dev)
4137 {
4138 struct cnic_local *cp = dev->cnic_priv;
4139 struct cnic_eth_dev *ethdev = cp->ethdev;
4140 int err;
4141
4142 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4143 if (err)
4144 tasklet_disable(&cp->cnic_irq_task);
4145
4146 return err;
4147 }
4148
4149 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4150 {
4151 struct cnic_local *cp = dev->cnic_priv;
4152 struct cnic_eth_dev *ethdev = cp->ethdev;
4153
4154 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4155 int err, i = 0;
4156 int sblk_num = cp->status_blk_num;
4157 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4158 BNX2_HC_SB_CONFIG_1;
4159
4160 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4161
4162 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4163 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4164 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4165
4166 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4167 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
4168 (unsigned long) dev);
4169 err = cnic_request_irq(dev);
4170 if (err)
4171 return err;
4172
4173 while (cp->status_blk.bnx2->status_completion_producer_index &&
4174 i < 10) {
4175 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4176 1 << (11 + sblk_num));
4177 udelay(10);
4178 i++;
4179 barrier();
4180 }
4181 if (cp->status_blk.bnx2->status_completion_producer_index) {
4182 cnic_free_irq(dev);
4183 goto failed;
4184 }
4185
4186 } else {
4187 struct status_block *sblk = cp->status_blk.gen;
4188 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4189 int i = 0;
4190
4191 while (sblk->status_completion_producer_index && i < 10) {
4192 CNIC_WR(dev, BNX2_HC_COMMAND,
4193 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4194 udelay(10);
4195 i++;
4196 barrier();
4197 }
4198 if (sblk->status_completion_producer_index)
4199 goto failed;
4200
4201 }
4202 return 0;
4203
4204 failed:
4205 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4206 return -EBUSY;
4207 }
4208
4209 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4210 {
4211 struct cnic_local *cp = dev->cnic_priv;
4212 struct cnic_eth_dev *ethdev = cp->ethdev;
4213
4214 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4215 return;
4216
4217 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4218 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4219 }
4220
4221 static void cnic_get_bnx2_iscsi_info(struct cnic_dev *dev)
4222 {
4223 u32 max_conn;
4224
4225 max_conn = cnic_reg_rd_ind(dev, BNX2_FW_MAX_ISCSI_CONN);
4226 dev->max_iscsi_conn = max_conn;
4227 }
4228
4229 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4230 {
4231 struct cnic_local *cp = dev->cnic_priv;
4232 struct cnic_eth_dev *ethdev = cp->ethdev;
4233
4234 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4235 return;
4236
4237 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4238 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4239 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4240 synchronize_irq(ethdev->irq_arr[0].vector);
4241 }
4242
4243 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4244 {
4245 struct cnic_local *cp = dev->cnic_priv;
4246 struct cnic_eth_dev *ethdev = cp->ethdev;
4247 struct cnic_uio_dev *udev = cp->udev;
4248 u32 cid_addr, tx_cid, sb_id;
4249 u32 val, offset0, offset1, offset2, offset3;
4250 int i;
4251 struct tx_bd *txbd;
4252 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4253 struct status_block *s_blk = cp->status_blk.gen;
4254
4255 sb_id = cp->status_blk_num;
4256 tx_cid = 20;
4257 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4258 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4259 struct status_block_msix *sblk = cp->status_blk.bnx2;
4260
4261 tx_cid = TX_TSS_CID + sb_id - 1;
4262 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4263 (TX_TSS_CID << 7));
4264 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4265 }
4266 cp->tx_cons = *cp->tx_cons_ptr;
4267
4268 cid_addr = GET_CID_ADDR(tx_cid);
4269 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
4270 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4271
4272 for (i = 0; i < PHY_CTX_SIZE; i += 4)
4273 cnic_ctx_wr(dev, cid_addr2, i, 0);
4274
4275 offset0 = BNX2_L2CTX_TYPE_XI;
4276 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4277 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4278 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4279 } else {
4280 cnic_init_context(dev, tx_cid);
4281 cnic_init_context(dev, tx_cid + 1);
4282
4283 offset0 = BNX2_L2CTX_TYPE;
4284 offset1 = BNX2_L2CTX_CMD_TYPE;
4285 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4286 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4287 }
4288 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4289 cnic_ctx_wr(dev, cid_addr, offset0, val);
4290
4291 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4292 cnic_ctx_wr(dev, cid_addr, offset1, val);
4293
4294 txbd = (struct tx_bd *) udev->l2_ring;
4295
4296 buf_map = udev->l2_buf_map;
4297 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
4298 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4299 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4300 }
4301 val = (u64) ring_map >> 32;
4302 cnic_ctx_wr(dev, cid_addr, offset2, val);
4303 txbd->tx_bd_haddr_hi = val;
4304
4305 val = (u64) ring_map & 0xffffffff;
4306 cnic_ctx_wr(dev, cid_addr, offset3, val);
4307 txbd->tx_bd_haddr_lo = val;
4308 }
4309
4310 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4311 {
4312 struct cnic_local *cp = dev->cnic_priv;
4313 struct cnic_eth_dev *ethdev = cp->ethdev;
4314 struct cnic_uio_dev *udev = cp->udev;
4315 u32 cid_addr, sb_id, val, coal_reg, coal_val;
4316 int i;
4317 struct rx_bd *rxbd;
4318 struct status_block *s_blk = cp->status_blk.gen;
4319 dma_addr_t ring_map = udev->l2_ring_map;
4320
4321 sb_id = cp->status_blk_num;
4322 cnic_init_context(dev, 2);
4323 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4324 coal_reg = BNX2_HC_COMMAND;
4325 coal_val = CNIC_RD(dev, coal_reg);
4326 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4327 struct status_block_msix *sblk = cp->status_blk.bnx2;
4328
4329 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4330 coal_reg = BNX2_HC_COALESCE_NOW;
4331 coal_val = 1 << (11 + sb_id);
4332 }
4333 i = 0;
4334 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4335 CNIC_WR(dev, coal_reg, coal_val);
4336 udelay(10);
4337 i++;
4338 barrier();
4339 }
4340 cp->rx_cons = *cp->rx_cons_ptr;
4341
4342 cid_addr = GET_CID_ADDR(2);
4343 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4344 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4345 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4346
4347 if (sb_id == 0)
4348 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4349 else
4350 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4351 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4352
4353 rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
4354 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
4355 dma_addr_t buf_map;
4356 int n = (i % cp->l2_rx_ring_size) + 1;
4357
4358 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4359 rxbd->rx_bd_len = cp->l2_single_buf_size;
4360 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4361 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4362 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4363 }
4364 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4365 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4366 rxbd->rx_bd_haddr_hi = val;
4367
4368 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4369 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4370 rxbd->rx_bd_haddr_lo = val;
4371
4372 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4373 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4374 }
4375
4376 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4377 {
4378 struct kwqe *wqes[1], l2kwqe;
4379
4380 memset(&l2kwqe, 0, sizeof(l2kwqe));
4381 wqes[0] = &l2kwqe;
4382 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4383 (L2_KWQE_OPCODE_VALUE_FLUSH <<
4384 KWQE_OPCODE_SHIFT) | 2;
4385 dev->submit_kwqes(dev, wqes, 1);
4386 }
4387
4388 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4389 {
4390 struct cnic_local *cp = dev->cnic_priv;
4391 u32 val;
4392
4393 val = cp->func << 2;
4394
4395 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4396
4397 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4398 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4399 dev->mac_addr[0] = (u8) (val >> 8);
4400 dev->mac_addr[1] = (u8) val;
4401
4402 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4403
4404 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4405 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4406 dev->mac_addr[2] = (u8) (val >> 24);
4407 dev->mac_addr[3] = (u8) (val >> 16);
4408 dev->mac_addr[4] = (u8) (val >> 8);
4409 dev->mac_addr[5] = (u8) val;
4410
4411 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4412
4413 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4414 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4415 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4416
4417 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4418 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4419 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4420 }
4421
4422 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4423 {
4424 struct cnic_local *cp = dev->cnic_priv;
4425 struct cnic_eth_dev *ethdev = cp->ethdev;
4426 struct status_block *sblk = cp->status_blk.gen;
4427 u32 val, kcq_cid_addr, kwq_cid_addr;
4428 int err;
4429
4430 cnic_set_bnx2_mac(dev);
4431
4432 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4433 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4434 if (BCM_PAGE_BITS > 12)
4435 val |= (12 - 8) << 4;
4436 else
4437 val |= (BCM_PAGE_BITS - 8) << 4;
4438
4439 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4440
4441 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4442 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4443 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4444
4445 err = cnic_setup_5709_context(dev, 1);
4446 if (err)
4447 return err;
4448
4449 cnic_init_context(dev, KWQ_CID);
4450 cnic_init_context(dev, KCQ_CID);
4451
4452 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4453 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4454
4455 cp->max_kwq_idx = MAX_KWQ_IDX;
4456 cp->kwq_prod_idx = 0;
4457 cp->kwq_con_idx = 0;
4458 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4459
4460 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
4461 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4462 else
4463 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4464
4465 /* Initialize the kernel work queue context. */
4466 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4467 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4468 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4469
4470 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4471 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4472
4473 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4474 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4475
4476 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4477 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4478
4479 val = (u32) cp->kwq_info.pgtbl_map;
4480 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4481
4482 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4483 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4484
4485 cp->kcq1.sw_prod_idx = 0;
4486 cp->kcq1.hw_prod_idx_ptr =
4487 (u16 *) &sblk->status_completion_producer_index;
4488
4489 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
4490
4491 /* Initialize the kernel complete queue context. */
4492 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4493 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4494 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4495
4496 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4497 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4498
4499 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4500 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4501
4502 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4503 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4504
4505 val = (u32) cp->kcq1.dma.pgtbl_map;
4506 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4507
4508 cp->int_num = 0;
4509 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4510 struct status_block_msix *msblk = cp->status_blk.bnx2;
4511 u32 sb_id = cp->status_blk_num;
4512 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4513
4514 cp->kcq1.hw_prod_idx_ptr =
4515 (u16 *) &msblk->status_completion_producer_index;
4516 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
4517 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
4518 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4519 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4520 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4521 }
4522
4523 /* Enable Commnad Scheduler notification when we write to the
4524 * host producer index of the kernel contexts. */
4525 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4526
4527 /* Enable Command Scheduler notification when we write to either
4528 * the Send Queue or Receive Queue producer indexes of the kernel
4529 * bypass contexts. */
4530 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4531 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4532
4533 /* Notify COM when the driver post an application buffer. */
4534 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4535
4536 /* Set the CP and COM doorbells. These two processors polls the
4537 * doorbell for a non zero value before running. This must be done
4538 * after setting up the kernel queue contexts. */
4539 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4540 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4541
4542 cnic_init_bnx2_tx_ring(dev);
4543 cnic_init_bnx2_rx_ring(dev);
4544
4545 err = cnic_init_bnx2_irq(dev);
4546 if (err) {
4547 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4548 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4549 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4550 return err;
4551 }
4552
4553 cnic_get_bnx2_iscsi_info(dev);
4554
4555 return 0;
4556 }
4557
4558 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4559 {
4560 struct cnic_local *cp = dev->cnic_priv;
4561 struct cnic_eth_dev *ethdev = cp->ethdev;
4562 u32 start_offset = ethdev->ctx_tbl_offset;
4563 int i;
4564
4565 for (i = 0; i < cp->ctx_blks; i++) {
4566 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4567 dma_addr_t map = ctx->mapping;
4568
4569 if (cp->ctx_align) {
4570 unsigned long mask = cp->ctx_align - 1;
4571
4572 map = (map + mask) & ~mask;
4573 }
4574
4575 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4576 }
4577 }
4578
4579 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4580 {
4581 struct cnic_local *cp = dev->cnic_priv;
4582 struct cnic_eth_dev *ethdev = cp->ethdev;
4583 int err = 0;
4584
4585 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4586 (unsigned long) dev);
4587 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4588 err = cnic_request_irq(dev);
4589
4590 return err;
4591 }
4592
4593 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4594 u16 sb_id, u8 sb_index,
4595 u8 disable)
4596 {
4597
4598 u32 addr = BAR_CSTRORM_INTMEM +
4599 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4600 offsetof(struct hc_status_block_data_e1x, index_data) +
4601 sizeof(struct hc_index_data)*sb_index +
4602 offsetof(struct hc_index_data, flags);
4603 u16 flags = CNIC_RD16(dev, addr);
4604 /* clear and set */
4605 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4606 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4607 HC_INDEX_DATA_HC_ENABLED);
4608 CNIC_WR16(dev, addr, flags);
4609 }
4610
4611 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4612 {
4613 struct cnic_local *cp = dev->cnic_priv;
4614 u8 sb_id = cp->status_blk_num;
4615
4616 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4617 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4618 offsetof(struct hc_status_block_data_e1x, index_data) +
4619 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4620 offsetof(struct hc_index_data, timeout), 64 / 12);
4621 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4622 }
4623
4624 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4625 {
4626 }
4627
4628 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4629 struct client_init_ramrod_data *data)
4630 {
4631 struct cnic_local *cp = dev->cnic_priv;
4632 struct cnic_uio_dev *udev = cp->udev;
4633 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4634 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4635 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4636 int port = CNIC_PORT(cp);
4637 int i;
4638 u32 cli = cp->ethdev->iscsi_l2_client_id;
4639 u32 val;
4640
4641 memset(txbd, 0, BCM_PAGE_SIZE);
4642
4643 buf_map = udev->l2_buf_map;
4644 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4645 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4646 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4647
4648 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4649 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4650 reg_bd->addr_hi = start_bd->addr_hi;
4651 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4652 start_bd->nbytes = cpu_to_le16(0x10);
4653 start_bd->nbd = cpu_to_le16(3);
4654 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4655 start_bd->general_data = (UNICAST_ADDRESS <<
4656 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4657 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4658
4659 }
4660
4661 val = (u64) ring_map >> 32;
4662 txbd->next_bd.addr_hi = cpu_to_le32(val);
4663
4664 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4665
4666 val = (u64) ring_map & 0xffffffff;
4667 txbd->next_bd.addr_lo = cpu_to_le32(val);
4668
4669 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4670
4671 /* Other ramrod params */
4672 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4673 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4674
4675 /* reset xstorm per client statistics */
4676 if (cli < MAX_STAT_COUNTER_ID) {
4677 val = BAR_XSTRORM_INTMEM +
4678 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4679 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
4680 CNIC_WR(dev, val + i * 4, 0);
4681 }
4682
4683 cp->tx_cons_ptr =
4684 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4685 }
4686
4687 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4688 struct client_init_ramrod_data *data)
4689 {
4690 struct cnic_local *cp = dev->cnic_priv;
4691 struct cnic_uio_dev *udev = cp->udev;
4692 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4693 BCM_PAGE_SIZE);
4694 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4695 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4696 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4697 int i;
4698 int port = CNIC_PORT(cp);
4699 u32 cli = cp->ethdev->iscsi_l2_client_id;
4700 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4701 u32 val;
4702 dma_addr_t ring_map = udev->l2_ring_map;
4703
4704 /* General data */
4705 data->general.client_id = cli;
4706 data->general.statistics_en_flg = 1;
4707 data->general.statistics_counter_id = cli;
4708 data->general.activate_flg = 1;
4709 data->general.sp_client_id = cli;
4710
4711 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4712 dma_addr_t buf_map;
4713 int n = (i % cp->l2_rx_ring_size) + 1;
4714
4715 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4716 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4717 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4718 }
4719
4720 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4721 rxbd->addr_hi = cpu_to_le32(val);
4722 data->rx.bd_page_base.hi = cpu_to_le32(val);
4723
4724 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4725 rxbd->addr_lo = cpu_to_le32(val);
4726 data->rx.bd_page_base.lo = cpu_to_le32(val);
4727
4728 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4729 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4730 rxcqe->addr_hi = cpu_to_le32(val);
4731 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4732
4733 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4734 rxcqe->addr_lo = cpu_to_le32(val);
4735 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4736
4737 /* Other ramrod params */
4738 data->rx.client_qzone_id = cl_qzone_id;
4739 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4740 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4741
4742 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4743 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
4744
4745 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4746 data->rx.outer_vlan_removal_enable_flg = 1;
4747
4748 /* reset tstorm and ustorm per client statistics */
4749 if (cli < MAX_STAT_COUNTER_ID) {
4750 val = BAR_TSTRORM_INTMEM +
4751 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4752 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4753 CNIC_WR(dev, val + i * 4, 0);
4754
4755 val = BAR_USTRORM_INTMEM +
4756 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4757 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4758 CNIC_WR(dev, val + i * 4, 0);
4759 }
4760
4761 cp->rx_cons_ptr =
4762 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4763 cp->rx_cons = *cp->rx_cons_ptr;
4764 }
4765
4766 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
4767 {
4768 struct cnic_local *cp = dev->cnic_priv;
4769 u32 pfid = cp->pfid;
4770
4771 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4772 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4773 cp->kcq1.sw_prod_idx = 0;
4774
4775 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4776 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4777
4778 cp->kcq1.hw_prod_idx_ptr =
4779 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4780 cp->kcq1.status_idx_ptr =
4781 &sb->sb.running_index[SM_RX_ID];
4782 } else {
4783 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4784
4785 cp->kcq1.hw_prod_idx_ptr =
4786 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4787 cp->kcq1.status_idx_ptr =
4788 &sb->sb.running_index[SM_RX_ID];
4789 }
4790
4791 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4792 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4793
4794 cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
4795 USTORM_FCOE_EQ_PROD_OFFSET(pfid);
4796 cp->kcq2.sw_prod_idx = 0;
4797 cp->kcq2.hw_prod_idx_ptr =
4798 &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
4799 cp->kcq2.status_idx_ptr =
4800 &sb->sb.running_index[SM_RX_ID];
4801 }
4802 }
4803
4804 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4805 {
4806 struct cnic_local *cp = dev->cnic_priv;
4807 struct cnic_eth_dev *ethdev = cp->ethdev;
4808 int func = CNIC_FUNC(cp), ret, i;
4809 u32 pfid;
4810
4811 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4812 u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
4813
4814 if (!(val & 1))
4815 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
4816 else
4817 val = (val >> 1) & 1;
4818
4819 if (val)
4820 cp->pfid = func >> 1;
4821 else
4822 cp->pfid = func & 0x6;
4823 } else {
4824 cp->pfid = func;
4825 }
4826 pfid = cp->pfid;
4827
4828 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4829 cp->iscsi_start_cid);
4830
4831 if (ret)
4832 return -ENOMEM;
4833
4834 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4835 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
4836 BNX2X_FCOE_NUM_CONNECTIONS,
4837 cp->fcoe_start_cid);
4838
4839 if (ret)
4840 return -ENOMEM;
4841 }
4842
4843 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4844
4845 cnic_init_bnx2x_kcq(dev);
4846
4847 /* Only 1 EQ */
4848 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4849 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4850 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4851 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4852 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4853 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4854 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4855 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4856 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4857 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4858 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4859 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4860 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4861 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4862 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4863 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4864 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4865 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4866 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4867 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4868 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4869 HC_INDEX_ISCSI_EQ_CONS);
4870
4871 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4872 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4873 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
4874 cp->conn_buf_info.pgtbl[2 * i]);
4875 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4876 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
4877 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4878 }
4879
4880 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4881 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4882 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4883 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4884 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4885 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4886
4887 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4888 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4889
4890 cnic_setup_bnx2x_context(dev);
4891
4892 ret = cnic_init_bnx2x_irq(dev);
4893 if (ret)
4894 return ret;
4895
4896 return 0;
4897 }
4898
4899 static void cnic_init_rings(struct cnic_dev *dev)
4900 {
4901 struct cnic_local *cp = dev->cnic_priv;
4902 struct cnic_uio_dev *udev = cp->udev;
4903
4904 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4905 return;
4906
4907 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4908 cnic_init_bnx2_tx_ring(dev);
4909 cnic_init_bnx2_rx_ring(dev);
4910 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4911 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4912 u32 cli = cp->ethdev->iscsi_l2_client_id;
4913 u32 cid = cp->ethdev->iscsi_l2_cid;
4914 u32 cl_qzone_id;
4915 struct client_init_ramrod_data *data;
4916 union l5cm_specific_data l5_data;
4917 struct ustorm_eth_rx_producers rx_prods = {0};
4918 u32 off, i;
4919
4920 rx_prods.bd_prod = 0;
4921 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4922 barrier();
4923
4924 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4925
4926 off = BAR_USTRORM_INTMEM +
4927 (BNX2X_CHIP_IS_E2(cp->chip_id) ?
4928 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
4929 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4930
4931 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4932 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4933
4934 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4935
4936 data = udev->l2_buf;
4937
4938 memset(data, 0, sizeof(*data));
4939
4940 cnic_init_bnx2x_tx_ring(dev, data);
4941 cnic_init_bnx2x_rx_ring(dev, data);
4942
4943 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
4944 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
4945
4946 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4947
4948 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4949 cid, ETH_CONNECTION_TYPE, &l5_data);
4950
4951 i = 0;
4952 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4953 ++i < 10)
4954 msleep(1);
4955
4956 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4957 netdev_err(dev->netdev,
4958 "iSCSI CLIENT_SETUP did not complete\n");
4959 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4960 cnic_ring_ctl(dev, cid, cli, 1);
4961 }
4962 }
4963
4964 static void cnic_shutdown_rings(struct cnic_dev *dev)
4965 {
4966 struct cnic_local *cp = dev->cnic_priv;
4967
4968 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4969 return;
4970
4971 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4972 cnic_shutdown_bnx2_rx_ring(dev);
4973 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4974 struct cnic_local *cp = dev->cnic_priv;
4975 u32 cli = cp->ethdev->iscsi_l2_client_id;
4976 u32 cid = cp->ethdev->iscsi_l2_cid;
4977 union l5cm_specific_data l5_data;
4978 int i;
4979
4980 cnic_ring_ctl(dev, cid, cli, 0);
4981
4982 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4983
4984 l5_data.phy_address.lo = cli;
4985 l5_data.phy_address.hi = 0;
4986 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4987 cid, ETH_CONNECTION_TYPE, &l5_data);
4988 i = 0;
4989 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4990 ++i < 10)
4991 msleep(1);
4992
4993 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4994 netdev_err(dev->netdev,
4995 "iSCSI CLIENT_HALT did not complete\n");
4996 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4997
4998 memset(&l5_data, 0, sizeof(l5_data));
4999 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
5000 cid, NONE_CONNECTION_TYPE, &l5_data);
5001 msleep(10);
5002 }
5003 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5004 }
5005
5006 static int cnic_register_netdev(struct cnic_dev *dev)
5007 {
5008 struct cnic_local *cp = dev->cnic_priv;
5009 struct cnic_eth_dev *ethdev = cp->ethdev;
5010 int err;
5011
5012 if (!ethdev)
5013 return -ENODEV;
5014
5015 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
5016 return 0;
5017
5018 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
5019 if (err)
5020 netdev_err(dev->netdev, "register_cnic failed\n");
5021
5022 return err;
5023 }
5024
5025 static void cnic_unregister_netdev(struct cnic_dev *dev)
5026 {
5027 struct cnic_local *cp = dev->cnic_priv;
5028 struct cnic_eth_dev *ethdev = cp->ethdev;
5029
5030 if (!ethdev)
5031 return;
5032
5033 ethdev->drv_unregister_cnic(dev->netdev);
5034 }
5035
5036 static int cnic_start_hw(struct cnic_dev *dev)
5037 {
5038 struct cnic_local *cp = dev->cnic_priv;
5039 struct cnic_eth_dev *ethdev = cp->ethdev;
5040 int err;
5041
5042 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5043 return -EALREADY;
5044
5045 dev->regview = ethdev->io_base;
5046 pci_dev_get(dev->pcidev);
5047 cp->func = PCI_FUNC(dev->pcidev->devfn);
5048 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5049 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5050
5051 err = cp->alloc_resc(dev);
5052 if (err) {
5053 netdev_err(dev->netdev, "allocate resource failure\n");
5054 goto err1;
5055 }
5056
5057 err = cp->start_hw(dev);
5058 if (err)
5059 goto err1;
5060
5061 err = cnic_cm_open(dev);
5062 if (err)
5063 goto err1;
5064
5065 set_bit(CNIC_F_CNIC_UP, &dev->flags);
5066
5067 cp->enable_int(dev);
5068
5069 return 0;
5070
5071 err1:
5072 cp->free_resc(dev);
5073 pci_dev_put(dev->pcidev);
5074 return err;
5075 }
5076
5077 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5078 {
5079 cnic_disable_bnx2_int_sync(dev);
5080
5081 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5082 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5083
5084 cnic_init_context(dev, KWQ_CID);
5085 cnic_init_context(dev, KCQ_CID);
5086
5087 cnic_setup_5709_context(dev, 0);
5088 cnic_free_irq(dev);
5089
5090 cnic_free_resc(dev);
5091 }
5092
5093
5094 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5095 {
5096 struct cnic_local *cp = dev->cnic_priv;
5097
5098 cnic_free_irq(dev);
5099 *cp->kcq1.hw_prod_idx_ptr = 0;
5100 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5101 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
5102 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5103 cnic_free_resc(dev);
5104 }
5105
5106 static void cnic_stop_hw(struct cnic_dev *dev)
5107 {
5108 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5109 struct cnic_local *cp = dev->cnic_priv;
5110 int i = 0;
5111
5112 /* Need to wait for the ring shutdown event to complete
5113 * before clearing the CNIC_UP flag.
5114 */
5115 while (cp->udev->uio_dev != -1 && i < 15) {
5116 msleep(100);
5117 i++;
5118 }
5119 cnic_shutdown_rings(dev);
5120 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5121 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
5122 synchronize_rcu();
5123 cnic_cm_shutdown(dev);
5124 cp->stop_hw(dev);
5125 pci_dev_put(dev->pcidev);
5126 }
5127 }
5128
5129 static void cnic_free_dev(struct cnic_dev *dev)
5130 {
5131 int i = 0;
5132
5133 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5134 msleep(100);
5135 i++;
5136 }
5137 if (atomic_read(&dev->ref_count) != 0)
5138 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5139
5140 netdev_info(dev->netdev, "Removed CNIC device\n");
5141 dev_put(dev->netdev);
5142 kfree(dev);
5143 }
5144
5145 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5146 struct pci_dev *pdev)
5147 {
5148 struct cnic_dev *cdev;
5149 struct cnic_local *cp;
5150 int alloc_size;
5151
5152 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5153
5154 cdev = kzalloc(alloc_size , GFP_KERNEL);
5155 if (cdev == NULL) {
5156 netdev_err(dev, "allocate dev struct failure\n");
5157 return NULL;
5158 }
5159
5160 cdev->netdev = dev;
5161 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5162 cdev->register_device = cnic_register_device;
5163 cdev->unregister_device = cnic_unregister_device;
5164 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5165
5166 cp = cdev->cnic_priv;
5167 cp->dev = cdev;
5168 cp->l2_single_buf_size = 0x400;
5169 cp->l2_rx_ring_size = 3;
5170
5171 spin_lock_init(&cp->cnic_ulp_lock);
5172
5173 netdev_info(dev, "Added CNIC device\n");
5174
5175 return cdev;
5176 }
5177
5178 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5179 {
5180 struct pci_dev *pdev;
5181 struct cnic_dev *cdev;
5182 struct cnic_local *cp;
5183 struct cnic_eth_dev *ethdev = NULL;
5184 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5185
5186 probe = symbol_get(bnx2_cnic_probe);
5187 if (probe) {
5188 ethdev = (*probe)(dev);
5189 symbol_put(bnx2_cnic_probe);
5190 }
5191 if (!ethdev)
5192 return NULL;
5193
5194 pdev = ethdev->pdev;
5195 if (!pdev)
5196 return NULL;
5197
5198 dev_hold(dev);
5199 pci_dev_get(pdev);
5200 if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5201 pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
5202 (pdev->revision < 0x10)) {
5203 pci_dev_put(pdev);
5204 goto cnic_err;
5205 }
5206 pci_dev_put(pdev);
5207
5208 cdev = cnic_alloc_dev(dev, pdev);
5209 if (cdev == NULL)
5210 goto cnic_err;
5211
5212 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5213 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5214
5215 cp = cdev->cnic_priv;
5216 cp->ethdev = ethdev;
5217 cdev->pcidev = pdev;
5218 cp->chip_id = ethdev->chip_id;
5219
5220 cp->cnic_ops = &cnic_bnx2_ops;
5221 cp->start_hw = cnic_start_bnx2_hw;
5222 cp->stop_hw = cnic_stop_bnx2_hw;
5223 cp->setup_pgtbl = cnic_setup_page_tbl;
5224 cp->alloc_resc = cnic_alloc_bnx2_resc;
5225 cp->free_resc = cnic_free_resc;
5226 cp->start_cm = cnic_cm_init_bnx2_hw;
5227 cp->stop_cm = cnic_cm_stop_bnx2_hw;
5228 cp->enable_int = cnic_enable_bnx2_int;
5229 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5230 cp->close_conn = cnic_close_bnx2_conn;
5231 cp->next_idx = cnic_bnx2_next_idx;
5232 cp->hw_idx = cnic_bnx2_hw_idx;
5233 return cdev;
5234
5235 cnic_err:
5236 dev_put(dev);
5237 return NULL;
5238 }
5239
5240 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5241 {
5242 struct pci_dev *pdev;
5243 struct cnic_dev *cdev;
5244 struct cnic_local *cp;
5245 struct cnic_eth_dev *ethdev = NULL;
5246 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5247
5248 probe = symbol_get(bnx2x_cnic_probe);
5249 if (probe) {
5250 ethdev = (*probe)(dev);
5251 symbol_put(bnx2x_cnic_probe);
5252 }
5253 if (!ethdev)
5254 return NULL;
5255
5256 pdev = ethdev->pdev;
5257 if (!pdev)
5258 return NULL;
5259
5260 dev_hold(dev);
5261 cdev = cnic_alloc_dev(dev, pdev);
5262 if (cdev == NULL) {
5263 dev_put(dev);
5264 return NULL;
5265 }
5266
5267 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5268 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5269
5270 cp = cdev->cnic_priv;
5271 cp->ethdev = ethdev;
5272 cdev->pcidev = pdev;
5273 cp->chip_id = ethdev->chip_id;
5274
5275 if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
5276 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5277 if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
5278 !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
5279 cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
5280
5281 memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
5282
5283 cp->cnic_ops = &cnic_bnx2x_ops;
5284 cp->start_hw = cnic_start_bnx2x_hw;
5285 cp->stop_hw = cnic_stop_bnx2x_hw;
5286 cp->setup_pgtbl = cnic_setup_page_tbl_le;
5287 cp->alloc_resc = cnic_alloc_bnx2x_resc;
5288 cp->free_resc = cnic_free_resc;
5289 cp->start_cm = cnic_cm_init_bnx2x_hw;
5290 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5291 cp->enable_int = cnic_enable_bnx2x_int;
5292 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5293 if (BNX2X_CHIP_IS_E2(cp->chip_id))
5294 cp->ack_int = cnic_ack_bnx2x_e2_msix;
5295 else
5296 cp->ack_int = cnic_ack_bnx2x_msix;
5297 cp->close_conn = cnic_close_bnx2x_conn;
5298 cp->next_idx = cnic_bnx2x_next_idx;
5299 cp->hw_idx = cnic_bnx2x_hw_idx;
5300 return cdev;
5301 }
5302
5303 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5304 {
5305 struct ethtool_drvinfo drvinfo;
5306 struct cnic_dev *cdev = NULL;
5307
5308 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5309 memset(&drvinfo, 0, sizeof(drvinfo));
5310 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5311
5312 if (!strcmp(drvinfo.driver, "bnx2"))
5313 cdev = init_bnx2_cnic(dev);
5314 if (!strcmp(drvinfo.driver, "bnx2x"))
5315 cdev = init_bnx2x_cnic(dev);
5316 if (cdev) {
5317 write_lock(&cnic_dev_lock);
5318 list_add(&cdev->list, &cnic_dev_list);
5319 write_unlock(&cnic_dev_lock);
5320 }
5321 }
5322 return cdev;
5323 }
5324
5325 /**
5326 * netdev event handler
5327 */
5328 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5329 void *ptr)
5330 {
5331 struct net_device *netdev = ptr;
5332 struct cnic_dev *dev;
5333 int if_type;
5334 int new_dev = 0;
5335
5336 dev = cnic_from_netdev(netdev);
5337
5338 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
5339 /* Check for the hot-plug device */
5340 dev = is_cnic_dev(netdev);
5341 if (dev) {
5342 new_dev = 1;
5343 cnic_hold(dev);
5344 }
5345 }
5346 if (dev) {
5347 struct cnic_local *cp = dev->cnic_priv;
5348
5349 if (new_dev)
5350 cnic_ulp_init(dev);
5351 else if (event == NETDEV_UNREGISTER)
5352 cnic_ulp_exit(dev);
5353
5354 if (event == NETDEV_UP) {
5355 if (cnic_register_netdev(dev) != 0) {
5356 cnic_put(dev);
5357 goto done;
5358 }
5359 if (!cnic_start_hw(dev))
5360 cnic_ulp_start(dev);
5361 }
5362
5363 rcu_read_lock();
5364 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5365 struct cnic_ulp_ops *ulp_ops;
5366 void *ctx;
5367
5368 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
5369 if (!ulp_ops || !ulp_ops->indicate_netevent)
5370 continue;
5371
5372 ctx = cp->ulp_handle[if_type];
5373
5374 ulp_ops->indicate_netevent(ctx, event);
5375 }
5376 rcu_read_unlock();
5377
5378 if (event == NETDEV_GOING_DOWN) {
5379 cnic_ulp_stop(dev);
5380 cnic_stop_hw(dev);
5381 cnic_unregister_netdev(dev);
5382 } else if (event == NETDEV_UNREGISTER) {
5383 write_lock(&cnic_dev_lock);
5384 list_del_init(&dev->list);
5385 write_unlock(&cnic_dev_lock);
5386
5387 cnic_put(dev);
5388 cnic_free_dev(dev);
5389 goto done;
5390 }
5391 cnic_put(dev);
5392 }
5393 done:
5394 return NOTIFY_DONE;
5395 }
5396
5397 static struct notifier_block cnic_netdev_notifier = {
5398 .notifier_call = cnic_netdev_event
5399 };
5400
5401 static void cnic_release(void)
5402 {
5403 struct cnic_dev *dev;
5404 struct cnic_uio_dev *udev;
5405
5406 while (!list_empty(&cnic_dev_list)) {
5407 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5408 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5409 cnic_ulp_stop(dev);
5410 cnic_stop_hw(dev);
5411 }
5412
5413 cnic_ulp_exit(dev);
5414 cnic_unregister_netdev(dev);
5415 list_del_init(&dev->list);
5416 cnic_free_dev(dev);
5417 }
5418 while (!list_empty(&cnic_udev_list)) {
5419 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5420 list);
5421 cnic_free_uio(udev);
5422 }
5423 }
5424
5425 static int __init cnic_init(void)
5426 {
5427 int rc = 0;
5428
5429 pr_info("%s", version);
5430
5431 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5432 if (rc) {
5433 cnic_release();
5434 return rc;
5435 }
5436
5437 cnic_wq = create_singlethread_workqueue("cnic_wq");
5438 if (!cnic_wq) {
5439 cnic_release();
5440 unregister_netdevice_notifier(&cnic_netdev_notifier);
5441 return -ENOMEM;
5442 }
5443
5444 return 0;
5445 }
5446
5447 static void __exit cnic_exit(void)
5448 {
5449 unregister_netdevice_notifier(&cnic_netdev_notifier);
5450 cnic_release();
5451 destroy_workqueue(cnic_wq);
5452 }
5453
5454 module_init(cnic_init);
5455 module_exit(cnic_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree