2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
57 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
58 const struct dwc3_event_depevt
*event
);
60 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
69 case EP0_STATUS_PHASE
:
70 return "Status Phase";
78 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
81 struct dwc3_gadget_ep_cmd_params params
;
82 struct dwc3_trb_hw
*trb_hw
;
88 dep
= dwc
->eps
[epnum
];
89 if (dep
->flags
& DWC3_EP_BUSY
) {
90 dev_vdbg(dwc
->dev
, "%s: still busy\n", dep
->name
);
94 trb_hw
= dwc
->ep0_trb
;
95 memset(&trb
, 0, sizeof(trb
));
106 dwc3_trb_to_hw(&trb
, trb_hw
);
108 memset(¶ms
, 0, sizeof(params
));
109 params
.param0
.depstrtxfer
.transfer_desc_addr_high
=
110 upper_32_bits(dwc
->ep0_trb_addr
);
111 params
.param1
.depstrtxfer
.transfer_desc_addr_low
=
112 lower_32_bits(dwc
->ep0_trb_addr
);
114 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
115 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
117 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
121 dep
->flags
|= DWC3_EP_BUSY
;
122 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
128 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
129 struct dwc3_request
*req
)
133 req
->request
.actual
= 0;
134 req
->request
.status
= -EINPROGRESS
;
135 req
->epnum
= dep
->number
;
137 list_add_tail(&req
->list
, &dep
->request_list
);
140 * Gadget driver might not be quick enough to queue a request
141 * before we get a Transfer Not Ready event on this endpoint.
143 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
144 * flag is set, it's telling us that as soon as Gadget queues the
145 * required request, we should kick the transfer here because the
146 * IRQ we were waiting for is long gone.
148 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
149 struct dwc3
*dwc
= dep
->dwc
;
153 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
155 if (dwc
->ep0state
== EP0_STATUS_PHASE
) {
156 type
= dwc
->three_stage_setup
157 ? DWC3_TRBCTL_CONTROL_STATUS3
158 : DWC3_TRBCTL_CONTROL_STATUS2
;
159 } else if (dwc
->ep0state
== EP0_DATA_PHASE
) {
160 type
= DWC3_TRBCTL_CONTROL_DATA
;
162 /* should never happen */
167 ret
= dwc3_ep0_start_trans(dwc
, direction
,
168 req
->request
.dma
, req
->request
.length
, type
);
169 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
176 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
179 struct dwc3_request
*req
= to_dwc3_request(request
);
180 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
181 struct dwc3
*dwc
= dep
->dwc
;
187 spin_lock_irqsave(&dwc
->lock
, flags
);
189 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
195 /* we share one TRB for ep0/1 */
196 if (!list_empty(&dwc
->eps
[0]->request_list
) ||
197 !list_empty(&dwc
->eps
[1]->request_list
) ||
198 dwc
->ep0_status_pending
) {
203 dev_vdbg(dwc
->dev
, "queueing request %p to %s length %d, state '%s'\n",
204 request
, dep
->name
, request
->length
,
205 dwc3_ep0_state_string(dwc
->ep0state
));
207 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
210 spin_unlock_irqrestore(&dwc
->lock
, flags
);
215 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
217 /* stall is always issued on EP0 */
218 __dwc3_gadget_ep_set_halt(dwc
->eps
[0], 1);
219 dwc
->eps
[0]->flags
&= ~DWC3_EP_STALL
;
220 dwc
->ep0state
= EP0_SETUP_PHASE
;
221 dwc3_ep0_out_start(dwc
);
224 void dwc3_ep0_out_start(struct dwc3
*dwc
)
228 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
229 DWC3_TRBCTL_CONTROL_SETUP
);
233 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
236 u32 windex
= le16_to_cpu(wIndex_le
);
239 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
240 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
243 dep
= dwc
->eps
[epnum
];
244 if (dep
->flags
& DWC3_EP_ENABLED
)
250 static void dwc3_ep0_send_status_response(struct dwc3
*dwc
)
252 dwc3_ep0_start_trans(dwc
, 1, dwc
->ctrl_req_addr
,
253 dwc
->ep0_usb_req
.length
,
254 DWC3_TRBCTL_CONTROL_DATA
);
255 dwc
->ep0_status_pending
= 1;
261 static int dwc3_ep0_handle_status(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
266 __le16
*response_pkt
;
268 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
270 case USB_RECIP_DEVICE
:
272 * We are self-powered. U1/U2/LTM will be set later
273 * once we handle this states. RemoteWakeup is 0 on SS
275 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
278 case USB_RECIP_INTERFACE
:
280 * Function Remote Wake Capable D0
281 * Function Remote Wakeup D1
285 case USB_RECIP_ENDPOINT
:
286 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
290 if (dep
->flags
& DWC3_EP_STALL
)
291 usb_status
= 1 << USB_ENDPOINT_HALT
;
297 response_pkt
= (__le16
*) dwc
->setup_buf
;
298 *response_pkt
= cpu_to_le16(usb_status
);
299 dwc
->ep0_usb_req
.length
= sizeof(*response_pkt
);
300 dwc3_ep0_send_status_response(dwc
);
305 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
306 struct usb_ctrlrequest
*ctrl
, int set
)
316 wValue
= le16_to_cpu(ctrl
->wValue
);
317 wIndex
= le16_to_cpu(ctrl
->wIndex
);
318 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
320 case USB_RECIP_DEVICE
:
323 * 9.4.1 says only only for SS, in AddressState only for
324 * default control pipe
327 case USB_DEVICE_U1_ENABLE
:
328 case USB_DEVICE_U2_ENABLE
:
329 case USB_DEVICE_LTM_ENABLE
:
330 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
332 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
336 /* XXX add U[12] & LTM */
338 case USB_DEVICE_REMOTE_WAKEUP
:
340 case USB_DEVICE_U1_ENABLE
:
342 case USB_DEVICE_U2_ENABLE
:
344 case USB_DEVICE_LTM_ENABLE
:
347 case USB_DEVICE_TEST_MODE
:
348 if ((wIndex
& 0xff) != 0)
354 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
355 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
368 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
375 case USB_RECIP_INTERFACE
:
377 case USB_INTRF_FUNC_SUSPEND
:
378 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
379 /* XXX enable Low power suspend */
381 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
382 /* XXX enable remote wakeup */
390 case USB_RECIP_ENDPOINT
:
392 case USB_ENDPOINT_HALT
:
394 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
397 ret
= __dwc3_gadget_ep_set_halt(dep
, set
);
413 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
419 addr
= le16_to_cpu(ctrl
->wValue
);
423 switch (dwc
->dev_state
) {
424 case DWC3_DEFAULT_STATE
:
425 case DWC3_ADDRESS_STATE
:
427 * Not sure if we should program DevAddr now or later
429 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
430 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
431 reg
|= DWC3_DCFG_DEVADDR(addr
);
432 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
435 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
437 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
440 case DWC3_CONFIGURED_STATE
:
448 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
452 spin_unlock(&dwc
->lock
);
453 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
454 spin_lock(&dwc
->lock
);
458 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
463 cfg
= le16_to_cpu(ctrl
->wValue
);
465 switch (dwc
->dev_state
) {
466 case DWC3_DEFAULT_STATE
:
470 case DWC3_ADDRESS_STATE
:
471 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
472 /* if the cfg matches and the cfg is non zero */
474 dwc
->dev_state
= DWC3_CONFIGURED_STATE
;
477 case DWC3_CONFIGURED_STATE
:
478 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
480 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
486 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
490 switch (ctrl
->bRequest
) {
491 case USB_REQ_GET_STATUS
:
492 dev_vdbg(dwc
->dev
, "USB_REQ_GET_STATUS\n");
493 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
495 case USB_REQ_CLEAR_FEATURE
:
496 dev_vdbg(dwc
->dev
, "USB_REQ_CLEAR_FEATURE\n");
497 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
499 case USB_REQ_SET_FEATURE
:
500 dev_vdbg(dwc
->dev
, "USB_REQ_SET_FEATURE\n");
501 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
503 case USB_REQ_SET_ADDRESS
:
504 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ADDRESS\n");
505 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
507 case USB_REQ_SET_CONFIGURATION
:
508 dev_vdbg(dwc
->dev
, "USB_REQ_SET_CONFIGURATION\n");
509 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
512 dev_vdbg(dwc
->dev
, "Forwarding to gadget driver\n");
513 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
520 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
521 const struct dwc3_event_depevt
*event
)
523 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
527 if (!dwc
->gadget_driver
)
530 len
= le16_to_cpu(ctrl
->wLength
);
532 dwc
->three_stage_setup
= 0;
534 dwc
->three_stage_setup
= 1;
536 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
537 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
539 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
545 dwc3_ep0_stall_and_restart(dwc
);
548 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
549 const struct dwc3_event_depevt
*event
)
551 struct dwc3_request
*r
= NULL
;
552 struct usb_request
*ur
;
558 epnum
= event
->endpoint_number
;
559 dep
= dwc
->eps
[epnum
];
561 if (!dwc
->ep0_status_pending
) {
562 r
= next_request(&dwc
->eps
[0]->request_list
);
565 ur
= &dwc
->ep0_usb_req
;
566 dwc
->ep0_status_pending
= 0;
569 dwc3_trb_to_nat(dwc
->ep0_trb
, &trb
);
571 if (dwc
->ep0_bounced
) {
572 struct dwc3_ep
*ep0
= dwc
->eps
[0];
574 transferred
= min_t(u32
, ur
->length
,
575 ep0
->endpoint
.maxpacket
- trb
.length
);
576 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
577 dwc
->ep0_bounced
= false;
579 transferred
= ur
->length
- trb
.length
;
580 ur
->actual
+= transferred
;
583 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
584 /* for some reason we did not get everything out */
586 dwc3_ep0_stall_and_restart(dwc
);
587 dwc3_gadget_giveback(dep
, r
, -ECONNRESET
);
590 * handle the case where we have to send a zero packet. This
591 * seems to be case when req.length > maxpacket. Could it be?
594 dwc3_gadget_giveback(dep
, r
, 0);
598 static void dwc3_ep0_complete_req(struct dwc3
*dwc
,
599 const struct dwc3_event_depevt
*event
)
601 struct dwc3_request
*r
;
606 if (!list_empty(&dep
->request_list
)) {
607 r
= next_request(&dep
->request_list
);
609 dwc3_gadget_giveback(dep
, r
, 0);
612 dwc
->ep0state
= EP0_SETUP_PHASE
;
613 dwc3_ep0_out_start(dwc
);
616 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
617 const struct dwc3_event_depevt
*event
)
619 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
621 dep
->flags
&= ~DWC3_EP_BUSY
;
623 switch (dwc
->ep0state
) {
624 case EP0_SETUP_PHASE
:
625 dev_vdbg(dwc
->dev
, "Inspecting Setup Bytes\n");
626 dwc3_ep0_inspect_setup(dwc
, event
);
630 dev_vdbg(dwc
->dev
, "Data Phase\n");
631 dwc3_ep0_complete_data(dwc
, event
);
634 case EP0_STATUS_PHASE
:
635 dev_vdbg(dwc
->dev
, "Status Phase\n");
636 dwc3_ep0_complete_req(dwc
, event
);
639 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
643 static void dwc3_ep0_do_control_setup(struct dwc3
*dwc
,
644 const struct dwc3_event_depevt
*event
)
646 dwc
->ep0state
= EP0_SETUP_PHASE
;
647 dwc3_ep0_out_start(dwc
);
650 static void dwc3_ep0_do_control_data(struct dwc3
*dwc
,
651 const struct dwc3_event_depevt
*event
)
654 struct dwc3_request
*req
;
658 dwc
->ep0state
= EP0_DATA_PHASE
;
660 if (list_empty(&dep
->request_list
)) {
661 dev_vdbg(dwc
->dev
, "pending request for EP0 Data phase\n");
662 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
664 if (event
->endpoint_number
)
665 dep
->flags
|= DWC3_EP0_DIR_IN
;
669 req
= next_request(&dep
->request_list
);
670 req
->direction
= !!event
->endpoint_number
;
672 dwc
->ep0state
= EP0_DATA_PHASE
;
673 if (req
->request
.length
== 0) {
674 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
675 dwc
->ctrl_req_addr
, 0,
676 DWC3_TRBCTL_CONTROL_DATA
);
677 } else if ((req
->request
.length
% dep
->endpoint
.maxpacket
)
678 && (event
->endpoint_number
== 0)) {
679 dwc3_map_buffer_to_dma(req
);
681 WARN_ON(req
->request
.length
> dep
->endpoint
.maxpacket
);
683 dwc
->ep0_bounced
= true;
686 * REVISIT in case request length is bigger than EP0
687 * wMaxPacketSize, we will need two chained TRBs to handle
690 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
691 dwc
->ep0_bounce_addr
, dep
->endpoint
.maxpacket
,
692 DWC3_TRBCTL_CONTROL_DATA
);
694 dwc3_map_buffer_to_dma(req
);
696 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
697 req
->request
.dma
, req
->request
.length
,
698 DWC3_TRBCTL_CONTROL_DATA
);
704 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
705 const struct dwc3_event_depevt
*event
)
710 dwc
->ep0state
= EP0_STATUS_PHASE
;
712 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
713 : DWC3_TRBCTL_CONTROL_STATUS2
;
715 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
716 dwc
->ctrl_req_addr
, 0, type
);
721 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
722 const struct dwc3_event_depevt
*event
)
724 switch (event
->status
) {
725 case DEPEVT_STATUS_CONTROL_SETUP
:
726 dev_vdbg(dwc
->dev
, "Control Setup\n");
727 dwc3_ep0_do_control_setup(dwc
, event
);
729 case DEPEVT_STATUS_CONTROL_DATA
:
730 dev_vdbg(dwc
->dev
, "Control Data\n");
731 dwc3_ep0_do_control_data(dwc
, event
);
733 case DEPEVT_STATUS_CONTROL_STATUS
:
734 dev_vdbg(dwc
->dev
, "Control Status\n");
735 dwc3_ep0_do_control_status(dwc
, event
);
739 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
740 const const struct dwc3_event_depevt
*event
)
742 u8 epnum
= event
->endpoint_number
;
744 dev_dbg(dwc
->dev
, "%s while ep%d%s in state '%s'\n",
745 dwc3_ep_event_string(event
->endpoint_event
),
746 epnum
, (epnum
& 1) ? "in" : "out",
747 dwc3_ep0_state_string(dwc
->ep0state
));
749 switch (event
->endpoint_event
) {
750 case DWC3_DEPEVT_XFERCOMPLETE
:
751 dwc3_ep0_xfer_complete(dwc
, event
);
754 case DWC3_DEPEVT_XFERNOTREADY
:
755 dwc3_ep0_xfernotready(dwc
, event
);
758 case DWC3_DEPEVT_XFERINPROGRESS
:
759 case DWC3_DEPEVT_RXTXFIFOEVT
:
760 case DWC3_DEPEVT_STREAMEVT
:
761 case DWC3_DEPEVT_EPCMDCMPLT
: