2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
33 #define DRIVER_NAME "sdhci"
35 #define DBG(f, x...) \
36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40 #define SDHCI_USE_LEDS_CLASS
43 #define MAX_TUNING_LOOP 40
45 static unsigned int debug_quirks
= 0;
46 static unsigned int debug_quirks2
;
48 static void sdhci_finish_data(struct sdhci_host
*);
50 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
51 static void sdhci_finish_command(struct sdhci_host
*);
52 static int sdhci_execute_tuning(struct mmc_host
*mmc
);
53 static void sdhci_tuning_timer(unsigned long data
);
55 #ifdef CONFIG_PM_RUNTIME
56 static int sdhci_runtime_pm_get(struct sdhci_host
*host
);
57 static int sdhci_runtime_pm_put(struct sdhci_host
*host
);
59 static inline int sdhci_runtime_pm_get(struct sdhci_host
*host
)
63 static inline int sdhci_runtime_pm_put(struct sdhci_host
*host
)
69 static void sdhci_dumpregs(struct sdhci_host
*host
)
71 pr_debug(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
72 mmc_hostname(host
->mmc
));
74 pr_debug(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
75 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
76 sdhci_readw(host
, SDHCI_HOST_VERSION
));
77 pr_debug(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
78 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
79 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
80 pr_debug(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
81 sdhci_readl(host
, SDHCI_ARGUMENT
),
82 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
83 pr_debug(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
84 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
85 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
86 pr_debug(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
87 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
88 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
89 pr_debug(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
90 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
91 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
92 pr_debug(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
93 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
94 sdhci_readl(host
, SDHCI_INT_STATUS
));
95 pr_debug(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
96 sdhci_readl(host
, SDHCI_INT_ENABLE
),
97 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
98 pr_debug(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
99 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
100 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
101 pr_debug(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
102 sdhci_readl(host
, SDHCI_CAPABILITIES
),
103 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
104 pr_debug(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
105 sdhci_readw(host
, SDHCI_COMMAND
),
106 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
107 pr_debug(DRIVER_NAME
": Host ctl2: 0x%08x\n",
108 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
110 if (host
->flags
& SDHCI_USE_ADMA
)
111 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
112 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
113 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
115 pr_debug(DRIVER_NAME
": ===========================================\n");
118 /*****************************************************************************\
120 * Low level functions *
122 \*****************************************************************************/
124 static void sdhci_clear_set_irqs(struct sdhci_host
*host
, u32 clear
, u32 set
)
128 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
131 sdhci_writel(host
, ier
, SDHCI_INT_ENABLE
);
132 sdhci_writel(host
, ier
, SDHCI_SIGNAL_ENABLE
);
135 static void sdhci_unmask_irqs(struct sdhci_host
*host
, u32 irqs
)
137 sdhci_clear_set_irqs(host
, 0, irqs
);
140 static void sdhci_mask_irqs(struct sdhci_host
*host
, u32 irqs
)
142 sdhci_clear_set_irqs(host
, irqs
, 0);
145 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
149 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
152 if (host
->quirks2
& SDHCI_QUIRK2_OWN_CARD_DETECTION
)
155 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
157 irqs
= present
? SDHCI_INT_CARD_REMOVE
: SDHCI_INT_CARD_INSERT
;
160 sdhci_unmask_irqs(host
, irqs
);
162 sdhci_mask_irqs(host
, irqs
);
165 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
167 sdhci_set_card_detection(host
, true);
170 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
172 sdhci_set_card_detection(host
, false);
175 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
177 unsigned long timeout
;
178 u32
uninitialized_var(ier
);
180 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
181 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
186 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
187 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
189 if (host
->ops
->platform_reset_enter
)
190 host
->ops
->platform_reset_enter(host
, mask
);
192 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
194 if (mask
& SDHCI_RESET_ALL
)
197 /* Wait max 100 ms */
200 /* hw clears the bit when it's done */
201 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
203 pr_err("%s: Reset 0x%x never completed.\n",
204 mmc_hostname(host
->mmc
), (int)mask
);
205 sdhci_dumpregs(host
);
212 if (host
->ops
->platform_reset_exit
)
213 host
->ops
->platform_reset_exit(host
, mask
);
215 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
216 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
, ier
);
219 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
221 static void sdhci_init(struct sdhci_host
*host
, int soft
)
224 sdhci_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
226 sdhci_reset(host
, SDHCI_RESET_ALL
);
228 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
,
229 SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
230 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
231 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
232 SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
);
235 /* force clock reconfiguration */
237 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
241 static void sdhci_reinit(struct sdhci_host
*host
)
244 sdhci_enable_card_detection(host
);
247 static void sdhci_activate_led(struct sdhci_host
*host
)
251 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
252 ctrl
|= SDHCI_CTRL_LED
;
253 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
256 static void sdhci_deactivate_led(struct sdhci_host
*host
)
260 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
261 ctrl
&= ~SDHCI_CTRL_LED
;
262 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
265 #ifdef SDHCI_USE_LEDS_CLASS
266 static void sdhci_led_control(struct led_classdev
*led
,
267 enum led_brightness brightness
)
269 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
272 spin_lock_irqsave(&host
->lock
, flags
);
274 if (host
->runtime_suspended
)
277 if (brightness
== LED_OFF
)
278 sdhci_deactivate_led(host
);
280 sdhci_activate_led(host
);
282 spin_unlock_irqrestore(&host
->lock
, flags
);
286 /*****************************************************************************\
290 \*****************************************************************************/
292 static void sdhci_read_block_pio(struct sdhci_host
*host
)
295 size_t blksize
, len
, chunk
;
296 u32
uninitialized_var(scratch
);
299 DBG("PIO reading\n");
301 blksize
= host
->data
->blksz
;
304 local_irq_save(flags
);
307 if (!sg_miter_next(&host
->sg_miter
))
310 len
= min(host
->sg_miter
.length
, blksize
);
313 host
->sg_miter
.consumed
= len
;
315 buf
= host
->sg_miter
.addr
;
319 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
323 *buf
= scratch
& 0xFF;
332 sg_miter_stop(&host
->sg_miter
);
334 local_irq_restore(flags
);
337 static void sdhci_write_block_pio(struct sdhci_host
*host
)
340 size_t blksize
, len
, chunk
;
344 DBG("PIO writing\n");
346 blksize
= host
->data
->blksz
;
350 local_irq_save(flags
);
353 if (!sg_miter_next(&host
->sg_miter
))
356 len
= min(host
->sg_miter
.length
, blksize
);
359 host
->sg_miter
.consumed
= len
;
361 buf
= host
->sg_miter
.addr
;
364 scratch
|= (u32
)*buf
<< (chunk
* 8);
370 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
371 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
378 sg_miter_stop(&host
->sg_miter
);
380 local_irq_restore(flags
);
383 static void sdhci_transfer_pio(struct sdhci_host
*host
)
389 if (host
->blocks
== 0)
392 if (host
->data
->flags
& MMC_DATA_READ
)
393 mask
= SDHCI_DATA_AVAILABLE
;
395 mask
= SDHCI_SPACE_AVAILABLE
;
398 * Some controllers (JMicron JMB38x) mess up the buffer bits
399 * for transfers < 4 bytes. As long as it is just one block,
400 * we can ignore the bits.
402 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
403 (host
->data
->blocks
== 1))
406 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
407 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
410 if (host
->data
->flags
& MMC_DATA_READ
)
411 sdhci_read_block_pio(host
);
413 sdhci_write_block_pio(host
);
416 if (host
->blocks
== 0)
420 DBG("PIO transfer complete.\n");
423 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
425 local_irq_save(*flags
);
426 return kmap_atomic(sg_page(sg
), KM_BIO_SRC_IRQ
) + sg
->offset
;
429 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
431 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
432 local_irq_restore(*flags
);
435 static void sdhci_set_adma_desc(u8
*desc
, u32 addr
, int len
, unsigned cmd
)
437 __le32
*dataddr
= (__le32 __force
*)(desc
+ 4);
438 __le16
*cmdlen
= (__le16 __force
*)desc
;
440 /* SDHCI specification says ADMA descriptors should be 4 byte
441 * aligned, so using 16 or 32bit operations should be safe. */
443 cmdlen
[0] = cpu_to_le16(cmd
);
444 cmdlen
[1] = cpu_to_le16(len
);
446 dataddr
[0] = cpu_to_le32(addr
);
449 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
450 struct mmc_data
*data
)
457 dma_addr_t align_addr
;
460 struct scatterlist
*sg
;
466 * The spec does not specify endianness of descriptor table.
467 * We currently guess that it is LE.
470 if (data
->flags
& MMC_DATA_READ
)
471 direction
= DMA_FROM_DEVICE
;
473 direction
= DMA_TO_DEVICE
;
476 * The ADMA descriptor table is mapped further down as we
477 * need to fill it with data first.
480 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
481 host
->align_buffer
, 128 * 4, direction
);
482 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
484 BUG_ON(host
->align_addr
& 0x3);
486 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
487 data
->sg
, data
->sg_len
, direction
);
488 if (host
->sg_count
== 0)
491 desc
= host
->adma_desc
;
492 align
= host
->align_buffer
;
494 align_addr
= host
->align_addr
;
496 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
497 addr
= sg_dma_address(sg
);
498 len
= sg_dma_len(sg
);
501 * The SDHCI specification states that ADMA
502 * addresses must be 32-bit aligned. If they
503 * aren't, then we use a bounce buffer for
504 * the (up to three) bytes that screw up the
507 offset
= (4 - (addr
& 0x3)) & 0x3;
509 if (data
->flags
& MMC_DATA_WRITE
) {
510 buffer
= sdhci_kmap_atomic(sg
, &flags
);
511 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
512 memcpy(align
, buffer
, offset
);
513 sdhci_kunmap_atomic(buffer
, &flags
);
517 sdhci_set_adma_desc(desc
, align_addr
, offset
, 0x21);
519 BUG_ON(offset
> 65536);
533 sdhci_set_adma_desc(desc
, addr
, len
, 0x21);
537 * If this triggers then we have a calculation bug
540 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
543 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
545 * Mark the last descriptor as the terminating descriptor
547 if (desc
!= host
->adma_desc
) {
549 desc
[0] |= 0x2; /* end */
553 * Add a terminating entry.
556 /* nop, end, valid */
557 sdhci_set_adma_desc(desc
, 0, 0, 0x3);
561 * Resync align buffer as we might have changed it.
563 if (data
->flags
& MMC_DATA_WRITE
) {
564 dma_sync_single_for_device(mmc_dev(host
->mmc
),
565 host
->align_addr
, 128 * 4, direction
);
568 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
569 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
570 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->adma_addr
))
572 BUG_ON(host
->adma_addr
& 0x3);
577 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
578 data
->sg_len
, direction
);
580 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
586 static void sdhci_adma_table_post(struct sdhci_host
*host
,
587 struct mmc_data
*data
)
591 struct scatterlist
*sg
;
597 if (data
->flags
& MMC_DATA_READ
)
598 direction
= DMA_FROM_DEVICE
;
600 direction
= DMA_TO_DEVICE
;
602 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
603 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
605 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
608 if (data
->flags
& MMC_DATA_READ
) {
609 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
610 data
->sg_len
, direction
);
612 align
= host
->align_buffer
;
614 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
615 if (sg_dma_address(sg
) & 0x3) {
616 size
= 4 - (sg_dma_address(sg
) & 0x3);
618 buffer
= sdhci_kmap_atomic(sg
, &flags
);
619 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
620 memcpy(buffer
, align
, size
);
621 sdhci_kunmap_atomic(buffer
, &flags
);
628 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
629 data
->sg_len
, direction
);
632 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
635 struct mmc_data
*data
= cmd
->data
;
636 unsigned target_timeout
, current_timeout
;
639 * If the host controller provides us with an incorrect timeout
640 * value, just skip the check and use 0xE. The hardware may take
641 * longer to time out, but that's much better than having a too-short
644 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
647 /* Unspecified timeout, assume max */
648 if (!data
&& !cmd
->cmd_timeout_ms
)
653 target_timeout
= cmd
->cmd_timeout_ms
* 1000;
655 target_timeout
= data
->timeout_ns
/ 1000;
657 target_timeout
+= data
->timeout_clks
/ host
->clock
;
661 * Figure out needed cycles.
662 * We do this in steps in order to fit inside a 32 bit int.
663 * The first step is the minimum timeout, which will have a
664 * minimum resolution of 6 bits:
665 * (1) 2^13*1000 > 2^22,
666 * (2) host->timeout_clk < 2^16
671 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
672 while (current_timeout
< target_timeout
) {
674 current_timeout
<<= 1;
680 pr_warning("%s: Too large timeout requested for CMD%d!\n",
681 mmc_hostname(host
->mmc
), cmd
->opcode
);
688 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
690 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
691 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
693 if (host
->flags
& SDHCI_REQ_USE_DMA
)
694 sdhci_clear_set_irqs(host
, pio_irqs
, dma_irqs
);
696 sdhci_clear_set_irqs(host
, dma_irqs
, pio_irqs
);
699 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
703 struct mmc_data
*data
= cmd
->data
;
708 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
)) {
709 count
= sdhci_calc_timeout(host
, cmd
);
710 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
717 BUG_ON(data
->blksz
* data
->blocks
> 524288);
718 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
719 BUG_ON(data
->blocks
> 65535);
722 host
->data_early
= 0;
723 host
->data
->bytes_xfered
= 0;
725 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
726 host
->flags
|= SDHCI_REQ_USE_DMA
;
729 * FIXME: This doesn't account for merging when mapping the
732 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
734 struct scatterlist
*sg
;
737 if (host
->flags
& SDHCI_USE_ADMA
) {
738 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
741 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
745 if (unlikely(broken
)) {
746 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
747 if (sg
->length
& 0x3) {
748 DBG("Reverting to PIO because of "
749 "transfer size (%d)\n",
751 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
759 * The assumption here being that alignment is the same after
760 * translation to device address space.
762 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
764 struct scatterlist
*sg
;
767 if (host
->flags
& SDHCI_USE_ADMA
) {
769 * As we use 3 byte chunks to work around
770 * alignment problems, we need to check this
773 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
776 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
780 if (unlikely(broken
)) {
781 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
782 if (sg
->offset
& 0x3) {
783 DBG("Reverting to PIO because of "
785 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
792 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
793 if (host
->flags
& SDHCI_USE_ADMA
) {
794 ret
= sdhci_adma_table_pre(host
, data
);
797 * This only happens when someone fed
798 * us an invalid request.
801 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
803 sdhci_writel(host
, host
->adma_addr
,
809 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
810 data
->sg
, data
->sg_len
,
811 (data
->flags
& MMC_DATA_READ
) ?
816 * This only happens when someone fed
817 * us an invalid request.
820 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
822 WARN_ON(sg_cnt
!= 1);
823 sdhci_writel(host
, sg_dma_address(data
->sg
),
830 * Always adjust the DMA selection as some controllers
831 * (e.g. JMicron) can't do PIO properly when the selection
834 if (host
->version
>= SDHCI_SPEC_200
) {
835 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
836 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
837 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
838 (host
->flags
& SDHCI_USE_ADMA
))
839 ctrl
|= SDHCI_CTRL_ADMA32
;
841 ctrl
|= SDHCI_CTRL_SDMA
;
842 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
845 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
848 flags
= SG_MITER_ATOMIC
;
849 if (host
->data
->flags
& MMC_DATA_READ
)
850 flags
|= SG_MITER_TO_SG
;
852 flags
|= SG_MITER_FROM_SG
;
853 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
854 host
->blocks
= data
->blocks
;
857 sdhci_set_transfer_irqs(host
);
859 /* Set the DMA boundary value and block size */
860 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
861 data
->blksz
), SDHCI_BLOCK_SIZE
);
862 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
865 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
866 struct mmc_command
*cmd
)
869 struct mmc_data
*data
= cmd
->data
;
874 WARN_ON(!host
->data
);
876 mode
= SDHCI_TRNS_BLK_CNT_EN
;
877 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
878 mode
|= SDHCI_TRNS_MULTI
;
880 * If we are sending CMD23, CMD12 never gets sent
881 * on successful completion (so no Auto-CMD12).
883 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
))
884 mode
|= SDHCI_TRNS_AUTO_CMD12
;
885 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
886 mode
|= SDHCI_TRNS_AUTO_CMD23
;
887 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
891 if (data
->flags
& MMC_DATA_READ
)
892 mode
|= SDHCI_TRNS_READ
;
893 if (host
->flags
& SDHCI_REQ_USE_DMA
)
894 mode
|= SDHCI_TRNS_DMA
;
896 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
899 static void sdhci_finish_data(struct sdhci_host
*host
)
901 struct mmc_data
*data
;
908 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
909 if (host
->flags
& SDHCI_USE_ADMA
)
910 sdhci_adma_table_post(host
, data
);
912 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
913 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
914 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
919 * The specification states that the block count register must
920 * be updated, but it does not specify at what point in the
921 * data flow. That makes the register entirely useless to read
922 * back so we have to assume that nothing made it to the card
923 * in the event of an error.
926 data
->bytes_xfered
= 0;
928 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
931 * Need to send CMD12 if -
932 * a) open-ended multiblock transfer (no CMD23)
933 * b) error in multiblock transfer
940 * The controller needs a reset of internal state machines
941 * upon error conditions.
944 sdhci_reset(host
, SDHCI_RESET_CMD
);
945 sdhci_reset(host
, SDHCI_RESET_DATA
);
948 sdhci_send_command(host
, data
->stop
);
950 tasklet_schedule(&host
->finish_tasklet
);
953 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
957 unsigned long timeout
;
964 mask
= SDHCI_CMD_INHIBIT
;
965 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
966 mask
|= SDHCI_DATA_INHIBIT
;
968 /* We shouldn't wait for data inihibit for stop commands, even
969 though they might use busy signaling */
970 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
971 mask
&= ~SDHCI_DATA_INHIBIT
;
973 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
975 pr_err("%s: Controller never released "
976 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
977 sdhci_dumpregs(host
);
979 tasklet_schedule(&host
->finish_tasklet
);
986 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
990 sdhci_prepare_data(host
, cmd
);
992 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
994 sdhci_set_transfer_mode(host
, cmd
);
996 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
997 pr_err("%s: Unsupported response type!\n",
998 mmc_hostname(host
->mmc
));
999 cmd
->error
= -EINVAL
;
1000 tasklet_schedule(&host
->finish_tasklet
);
1004 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1005 flags
= SDHCI_CMD_RESP_NONE
;
1006 else if (cmd
->flags
& MMC_RSP_136
)
1007 flags
= SDHCI_CMD_RESP_LONG
;
1008 else if (cmd
->flags
& MMC_RSP_BUSY
)
1009 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1011 flags
= SDHCI_CMD_RESP_SHORT
;
1013 if (cmd
->flags
& MMC_RSP_CRC
)
1014 flags
|= SDHCI_CMD_CRC
;
1015 if (cmd
->flags
& MMC_RSP_OPCODE
)
1016 flags
|= SDHCI_CMD_INDEX
;
1018 /* CMD19 is special in that the Data Present Select should be set */
1019 if (cmd
->data
|| (cmd
->opcode
== MMC_SEND_TUNING_BLOCK
))
1020 flags
|= SDHCI_CMD_DATA
;
1022 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1025 static void sdhci_finish_command(struct sdhci_host
*host
)
1029 BUG_ON(host
->cmd
== NULL
);
1031 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1032 if (host
->cmd
->flags
& MMC_RSP_136
) {
1033 /* CRC is stripped so we need to do some shifting. */
1034 for (i
= 0;i
< 4;i
++) {
1035 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1036 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1038 host
->cmd
->resp
[i
] |=
1040 SDHCI_RESPONSE
+ (3-i
)*4-1);
1043 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1047 host
->cmd
->error
= 0;
1049 /* Finished CMD23, now send actual command. */
1050 if (host
->cmd
== host
->mrq
->sbc
) {
1052 sdhci_send_command(host
, host
->mrq
->cmd
);
1055 /* Processed actual command. */
1056 if (host
->data
&& host
->data_early
)
1057 sdhci_finish_data(host
);
1059 if (!host
->cmd
->data
)
1060 tasklet_schedule(&host
->finish_tasklet
);
1066 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1068 int div
= 0; /* Initialized for compiler warning */
1070 unsigned long timeout
;
1072 if (clock
== host
->clock
)
1075 if (host
->ops
->set_clock
) {
1076 host
->ops
->set_clock(host
, clock
);
1077 if (host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
)
1081 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1086 if (host
->version
>= SDHCI_SPEC_300
) {
1088 * Check if the Host Controller supports Programmable Clock
1091 if (host
->clk_mul
) {
1095 * We need to figure out whether the Host Driver needs
1096 * to select Programmable Clock Mode, or the value can
1097 * be set automatically by the Host Controller based on
1098 * the Preset Value registers.
1100 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1101 if (!(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1102 for (div
= 1; div
<= 1024; div
++) {
1103 if (((host
->max_clk
* host
->clk_mul
) /
1108 * Set Programmable Clock Mode in the Clock
1111 clk
= SDHCI_PROG_CLOCK_MODE
;
1115 /* Version 3.00 divisors must be a multiple of 2. */
1116 if (host
->max_clk
<= clock
)
1119 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1121 if ((host
->max_clk
/ div
) <= clock
)
1128 /* Version 2.00 divisors must be a power of 2. */
1129 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1130 if ((host
->max_clk
/ div
) <= clock
)
1136 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1137 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1138 << SDHCI_DIVIDER_HI_SHIFT
;
1139 clk
|= SDHCI_CLOCK_INT_EN
;
1140 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1142 /* Wait max 20 ms */
1144 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1145 & SDHCI_CLOCK_INT_STABLE
)) {
1147 pr_err("%s: Internal clock never "
1148 "stabilised.\n", mmc_hostname(host
->mmc
));
1149 sdhci_dumpregs(host
);
1156 clk
|= SDHCI_CLOCK_CARD_EN
;
1157 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1160 host
->clock
= clock
;
1163 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
1167 if (power
!= (unsigned short)-1) {
1168 switch (1 << power
) {
1169 case MMC_VDD_165_195
:
1170 pwr
= SDHCI_POWER_180
;
1174 pwr
= SDHCI_POWER_300
;
1178 pwr
= SDHCI_POWER_330
;
1185 if (host
->pwr
== pwr
)
1191 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1196 * Spec says that we should clear the power reg before setting
1197 * a new value. Some controllers don't seem to like this though.
1199 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1200 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1203 * At least the Marvell CaFe chip gets confused if we set the voltage
1204 * and set turn on power at the same time, so set the voltage first.
1206 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1207 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1209 pwr
|= SDHCI_POWER_ON
;
1211 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1214 * Some controllers need an extra 10ms delay of 10ms before they
1215 * can apply clock after applying power
1217 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1221 /*****************************************************************************\
1225 \*****************************************************************************/
1227 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1229 struct sdhci_host
*host
;
1231 unsigned long flags
;
1233 host
= mmc_priv(mmc
);
1235 sdhci_runtime_pm_get(host
);
1237 spin_lock_irqsave(&host
->lock
, flags
);
1239 WARN_ON(host
->mrq
!= NULL
);
1241 #ifndef SDHCI_USE_LEDS_CLASS
1242 sdhci_activate_led(host
);
1246 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1247 * requests if Auto-CMD12 is enabled.
1249 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1251 mrq
->data
->stop
= NULL
;
1258 /* If polling, assume that the card is always present. */
1259 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1262 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
1265 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1266 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1267 tasklet_schedule(&host
->finish_tasklet
);
1271 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1273 * Check if the re-tuning timer has already expired and there
1274 * is no on-going data transfer. If so, we need to execute
1275 * tuning procedure before sending command.
1277 if ((host
->flags
& SDHCI_NEEDS_RETUNING
) &&
1278 !(present_state
& (SDHCI_DOING_WRITE
| SDHCI_DOING_READ
))) {
1279 spin_unlock_irqrestore(&host
->lock
, flags
);
1280 sdhci_execute_tuning(mmc
);
1281 spin_lock_irqsave(&host
->lock
, flags
);
1283 /* Restore original mmc_request structure */
1287 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1288 sdhci_send_command(host
, mrq
->sbc
);
1290 sdhci_send_command(host
, mrq
->cmd
);
1294 spin_unlock_irqrestore(&host
->lock
, flags
);
1297 static void sdhci_do_set_ios(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1299 unsigned long flags
;
1302 spin_lock_irqsave(&host
->lock
, flags
);
1304 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1308 * Reset the chip on each power off.
1309 * Should clear out any weird states.
1311 if (ios
->power_mode
== MMC_POWER_OFF
) {
1312 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1316 sdhci_set_clock(host
, ios
->clock
);
1318 if (ios
->power_mode
== MMC_POWER_OFF
)
1319 sdhci_set_power(host
, -1);
1321 sdhci_set_power(host
, ios
->vdd
);
1323 if (host
->ops
->platform_send_init_74_clocks
)
1324 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1327 * If your platform has 8-bit width support but is not a v3 controller,
1328 * or if it requires special setup code, you should implement that in
1329 * platform_8bit_width().
1331 if (host
->ops
->platform_8bit_width
)
1332 host
->ops
->platform_8bit_width(host
, ios
->bus_width
);
1334 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1335 if (ios
->bus_width
== MMC_BUS_WIDTH_8
) {
1336 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1337 if (host
->version
>= SDHCI_SPEC_300
)
1338 ctrl
|= SDHCI_CTRL_8BITBUS
;
1340 if (host
->version
>= SDHCI_SPEC_300
)
1341 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1342 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1343 ctrl
|= SDHCI_CTRL_4BITBUS
;
1345 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1347 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1350 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1352 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1353 ios
->timing
== MMC_TIMING_MMC_HS
)
1354 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1355 ctrl
|= SDHCI_CTRL_HISPD
;
1357 ctrl
&= ~SDHCI_CTRL_HISPD
;
1359 if (host
->version
>= SDHCI_SPEC_300
) {
1363 /* In case of UHS-I modes, set High Speed Enable */
1364 if ((ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1365 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1366 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1367 (ios
->timing
== MMC_TIMING_UHS_SDR25
))
1368 ctrl
|= SDHCI_CTRL_HISPD
;
1370 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1371 if (!(ctrl_2
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1372 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1374 * We only need to set Driver Strength if the
1375 * preset value enable is not set.
1377 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1378 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1379 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1380 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1381 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1383 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1386 * According to SDHC Spec v3.00, if the Preset Value
1387 * Enable in the Host Control 2 register is set, we
1388 * need to reset SD Clock Enable before changing High
1389 * Speed Enable to avoid generating clock gliches.
1392 /* Reset SD Clock Enable */
1393 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1394 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1395 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1397 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1399 /* Re-enable SD Clock */
1400 clock
= host
->clock
;
1402 sdhci_set_clock(host
, clock
);
1406 /* Reset SD Clock Enable */
1407 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1408 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1409 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1411 if (host
->ops
->set_uhs_signaling
)
1412 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1414 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1415 /* Select Bus Speed Mode for host */
1416 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1417 if (ios
->timing
== MMC_TIMING_UHS_SDR12
)
1418 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1419 else if (ios
->timing
== MMC_TIMING_UHS_SDR25
)
1420 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1421 else if (ios
->timing
== MMC_TIMING_UHS_SDR50
)
1422 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1423 else if (ios
->timing
== MMC_TIMING_UHS_SDR104
)
1424 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1425 else if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
1426 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1427 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1430 /* Re-enable SD Clock */
1431 clock
= host
->clock
;
1433 sdhci_set_clock(host
, clock
);
1435 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1438 * Some (ENE) controllers go apeshit on some ios operation,
1439 * signalling timeout and CRC errors even on CMD0. Resetting
1440 * it on each ios seems to solve the problem.
1442 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1443 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1447 spin_unlock_irqrestore(&host
->lock
, flags
);
1450 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1452 struct sdhci_host
*host
= mmc_priv(mmc
);
1454 sdhci_runtime_pm_get(host
);
1455 sdhci_do_set_ios(host
, ios
);
1456 sdhci_runtime_pm_put(host
);
1459 static int sdhci_check_ro(struct sdhci_host
*host
)
1461 unsigned long flags
;
1464 spin_lock_irqsave(&host
->lock
, flags
);
1466 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1468 else if (host
->ops
->get_ro
)
1469 is_readonly
= host
->ops
->get_ro(host
);
1471 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1472 & SDHCI_WRITE_PROTECT
);
1474 spin_unlock_irqrestore(&host
->lock
, flags
);
1476 /* This quirk needs to be replaced by a callback-function later */
1477 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1478 !is_readonly
: is_readonly
;
1481 #define SAMPLE_COUNT 5
1483 static int sdhci_do_get_ro(struct sdhci_host
*host
)
1487 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1488 return sdhci_check_ro(host
);
1491 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1492 if (sdhci_check_ro(host
)) {
1493 if (++ro_count
> SAMPLE_COUNT
/ 2)
1501 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1503 struct sdhci_host
*host
= mmc_priv(mmc
);
1505 if (host
->ops
&& host
->ops
->hw_reset
)
1506 host
->ops
->hw_reset(host
);
1509 static int sdhci_get_ro(struct mmc_host
*mmc
)
1511 struct sdhci_host
*host
= mmc_priv(mmc
);
1514 sdhci_runtime_pm_get(host
);
1515 ret
= sdhci_do_get_ro(host
);
1516 sdhci_runtime_pm_put(host
);
1520 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1522 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1526 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1528 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1530 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1531 if (host
->runtime_suspended
)
1535 sdhci_unmask_irqs(host
, SDHCI_INT_CARD_INT
);
1537 sdhci_mask_irqs(host
, SDHCI_INT_CARD_INT
);
1542 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1544 struct sdhci_host
*host
= mmc_priv(mmc
);
1545 unsigned long flags
;
1547 spin_lock_irqsave(&host
->lock
, flags
);
1548 sdhci_enable_sdio_irq_nolock(host
, enable
);
1549 spin_unlock_irqrestore(&host
->lock
, flags
);
1552 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host
*host
,
1553 struct mmc_ios
*ios
)
1560 * Signal Voltage Switching is only applicable for Host Controllers
1563 if (host
->version
< SDHCI_SPEC_300
)
1567 * We first check whether the request is to set signalling voltage
1568 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1570 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1571 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
) {
1572 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1573 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1574 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1577 usleep_range(5000, 5500);
1579 /* 3.3V regulator output should be stable within 5 ms */
1580 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1581 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1584 pr_info(DRIVER_NAME
": Switching to 3.3V "
1585 "signalling voltage failed\n");
1588 } else if (!(ctrl
& SDHCI_CTRL_VDD_180
) &&
1589 (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_180
)) {
1591 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1592 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1593 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1595 /* Check whether DAT[3:0] is 0000 */
1596 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1597 if (!((present_state
& SDHCI_DATA_LVL_MASK
) >>
1598 SDHCI_DATA_LVL_SHIFT
)) {
1600 * Enable 1.8V Signal Enable in the Host Control2
1603 ctrl
|= SDHCI_CTRL_VDD_180
;
1604 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1607 usleep_range(5000, 5500);
1609 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1610 if (ctrl
& SDHCI_CTRL_VDD_180
) {
1611 /* Provide SDCLK again and wait for 1ms*/
1612 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1613 clk
|= SDHCI_CLOCK_CARD_EN
;
1614 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1615 usleep_range(1000, 1500);
1618 * If DAT[3:0] level is 1111b, then the card
1619 * was successfully switched to 1.8V signaling.
1621 present_state
= sdhci_readl(host
,
1622 SDHCI_PRESENT_STATE
);
1623 if ((present_state
& SDHCI_DATA_LVL_MASK
) ==
1624 SDHCI_DATA_LVL_MASK
)
1630 * If we are here, that means the switch to 1.8V signaling
1631 * failed. We power cycle the card, and retry initialization
1632 * sequence by setting S18R to 0.
1634 pwr
= sdhci_readb(host
, SDHCI_POWER_CONTROL
);
1635 pwr
&= ~SDHCI_POWER_ON
;
1636 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1638 /* Wait for 1ms as per the spec */
1639 usleep_range(1000, 1500);
1640 pwr
|= SDHCI_POWER_ON
;
1641 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1643 pr_info(DRIVER_NAME
": Switching to 1.8V signalling "
1644 "voltage failed, retrying with S18R set to 0\n");
1647 /* No signal voltage switch required */
1651 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1652 struct mmc_ios
*ios
)
1654 struct sdhci_host
*host
= mmc_priv(mmc
);
1657 if (host
->version
< SDHCI_SPEC_300
)
1659 sdhci_runtime_pm_get(host
);
1660 err
= sdhci_do_start_signal_voltage_switch(host
, ios
);
1661 sdhci_runtime_pm_put(host
);
1665 static int sdhci_execute_tuning(struct mmc_host
*mmc
)
1667 struct sdhci_host
*host
;
1670 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1671 unsigned long timeout
;
1674 host
= mmc_priv(mmc
);
1676 sdhci_runtime_pm_get(host
);
1677 disable_irq(host
->irq
);
1678 spin_lock(&host
->lock
);
1680 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1683 * Host Controller needs tuning only in case of SDR104 mode
1684 * and for SDR50 mode when Use Tuning for SDR50 is set in
1685 * Capabilities register.
1687 if (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR104
) ||
1688 (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR50
) &&
1689 (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
)))
1690 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1692 spin_unlock(&host
->lock
);
1693 enable_irq(host
->irq
);
1694 sdhci_runtime_pm_put(host
);
1698 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1701 * As per the Host Controller spec v3.00, tuning command
1702 * generates Buffer Read Ready interrupt, so enable that.
1704 * Note: The spec clearly says that when tuning sequence
1705 * is being performed, the controller does not generate
1706 * interrupts other than Buffer Read Ready interrupt. But
1707 * to make sure we don't hit a controller bug, we _only_
1708 * enable Buffer Read Ready interrupt here.
1710 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
1711 sdhci_clear_set_irqs(host
, ier
, SDHCI_INT_DATA_AVAIL
);
1714 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1715 * of loops reaches 40 times or a timeout of 150ms occurs.
1719 struct mmc_command cmd
= {0};
1720 struct mmc_request mrq
= {NULL
};
1722 if (!tuning_loop_counter
&& !timeout
)
1725 cmd
.opcode
= MMC_SEND_TUNING_BLOCK
;
1727 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1736 * In response to CMD19, the card sends 64 bytes of tuning
1737 * block to the Host Controller. So we set the block size
1740 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE
);
1743 * The tuning block is sent by the card to the host controller.
1744 * So we set the TRNS_READ bit in the Transfer Mode register.
1745 * This also takes care of setting DMA Enable and Multi Block
1746 * Select in the same register to 0.
1748 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
1750 sdhci_send_command(host
, &cmd
);
1755 spin_unlock(&host
->lock
);
1756 enable_irq(host
->irq
);
1758 /* Wait for Buffer Read Ready interrupt */
1759 wait_event_interruptible_timeout(host
->buf_ready_int
,
1760 (host
->tuning_done
== 1),
1761 msecs_to_jiffies(50));
1762 disable_irq(host
->irq
);
1763 spin_lock(&host
->lock
);
1765 if (!host
->tuning_done
) {
1766 pr_info(DRIVER_NAME
": Timeout waiting for "
1767 "Buffer Read Ready interrupt during tuning "
1768 "procedure, falling back to fixed sampling "
1770 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1771 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1772 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
1773 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1779 host
->tuning_done
= 0;
1781 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1782 tuning_loop_counter
--;
1785 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
1788 * The Host Driver has exhausted the maximum number of loops allowed,
1789 * so use fixed sampling frequency.
1791 if (!tuning_loop_counter
|| !timeout
) {
1792 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1793 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1795 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
1796 pr_info(DRIVER_NAME
": Tuning procedure"
1797 " failed, falling back to fixed sampling"
1805 * If this is the very first time we are here, we start the retuning
1806 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1807 * flag won't be set, we check this condition before actually starting
1810 if (!(host
->flags
& SDHCI_NEEDS_RETUNING
) && host
->tuning_count
&&
1811 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)) {
1812 mod_timer(&host
->tuning_timer
, jiffies
+
1813 host
->tuning_count
* HZ
);
1814 /* Tuning mode 1 limits the maximum data length to 4MB */
1815 mmc
->max_blk_count
= (4 * 1024 * 1024) / mmc
->max_blk_size
;
1817 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
1818 /* Reload the new initial value for timer */
1819 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1820 mod_timer(&host
->tuning_timer
, jiffies
+
1821 host
->tuning_count
* HZ
);
1825 * In case tuning fails, host controllers which support re-tuning can
1826 * try tuning again at a later time, when the re-tuning timer expires.
1827 * So for these controllers, we return 0. Since there might be other
1828 * controllers who do not have this capability, we return error for
1831 if (err
&& host
->tuning_count
&&
1832 host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1835 sdhci_clear_set_irqs(host
, SDHCI_INT_DATA_AVAIL
, ier
);
1836 spin_unlock(&host
->lock
);
1837 enable_irq(host
->irq
);
1838 sdhci_runtime_pm_put(host
);
1843 static void sdhci_do_enable_preset_value(struct sdhci_host
*host
, bool enable
)
1846 unsigned long flags
;
1848 /* Host Controller v3.00 defines preset value registers */
1849 if (host
->version
< SDHCI_SPEC_300
)
1852 spin_lock_irqsave(&host
->lock
, flags
);
1854 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1857 * We only enable or disable Preset Value if they are not already
1858 * enabled or disabled respectively. Otherwise, we bail out.
1860 if (enable
&& !(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1861 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
1862 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1863 host
->flags
|= SDHCI_PV_ENABLED
;
1864 } else if (!enable
&& (ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1865 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
1866 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1867 host
->flags
&= ~SDHCI_PV_ENABLED
;
1870 spin_unlock_irqrestore(&host
->lock
, flags
);
1873 static void sdhci_enable_preset_value(struct mmc_host
*mmc
, bool enable
)
1875 struct sdhci_host
*host
= mmc_priv(mmc
);
1877 sdhci_runtime_pm_get(host
);
1878 sdhci_do_enable_preset_value(host
, enable
);
1879 sdhci_runtime_pm_put(host
);
1882 static const struct mmc_host_ops sdhci_ops
= {
1883 .request
= sdhci_request
,
1884 .set_ios
= sdhci_set_ios
,
1885 .get_ro
= sdhci_get_ro
,
1886 .hw_reset
= sdhci_hw_reset
,
1887 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1888 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
1889 .execute_tuning
= sdhci_execute_tuning
,
1890 .enable_preset_value
= sdhci_enable_preset_value
,
1893 /*****************************************************************************\
1897 \*****************************************************************************/
1899 static void sdhci_tasklet_card(unsigned long param
)
1901 struct sdhci_host
*host
;
1902 unsigned long flags
;
1904 host
= (struct sdhci_host
*)param
;
1906 spin_lock_irqsave(&host
->lock
, flags
);
1908 /* Check host->mrq first in case we are runtime suspended */
1910 !(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1911 pr_err("%s: Card removed during transfer!\n",
1912 mmc_hostname(host
->mmc
));
1913 pr_err("%s: Resetting controller.\n",
1914 mmc_hostname(host
->mmc
));
1916 sdhci_reset(host
, SDHCI_RESET_CMD
);
1917 sdhci_reset(host
, SDHCI_RESET_DATA
);
1919 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1920 tasklet_schedule(&host
->finish_tasklet
);
1923 spin_unlock_irqrestore(&host
->lock
, flags
);
1925 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
1928 static void sdhci_tasklet_finish(unsigned long param
)
1930 struct sdhci_host
*host
;
1931 unsigned long flags
;
1932 struct mmc_request
*mrq
;
1934 host
= (struct sdhci_host
*)param
;
1936 spin_lock_irqsave(&host
->lock
, flags
);
1939 * If this tasklet gets rescheduled while running, it will
1940 * be run again afterwards but without any active request.
1943 spin_unlock_irqrestore(&host
->lock
, flags
);
1947 del_timer(&host
->timer
);
1952 * The controller needs a reset of internal state machines
1953 * upon error conditions.
1955 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1956 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
1957 (mrq
->data
&& (mrq
->data
->error
||
1958 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1959 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1961 /* Some controllers need this kick or reset won't work here */
1962 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1965 /* This is to force an update */
1966 clock
= host
->clock
;
1968 sdhci_set_clock(host
, clock
);
1971 /* Spec says we should do both at the same time, but Ricoh
1972 controllers do not like that. */
1973 sdhci_reset(host
, SDHCI_RESET_CMD
);
1974 sdhci_reset(host
, SDHCI_RESET_DATA
);
1981 #ifndef SDHCI_USE_LEDS_CLASS
1982 sdhci_deactivate_led(host
);
1986 spin_unlock_irqrestore(&host
->lock
, flags
);
1988 mmc_request_done(host
->mmc
, mrq
);
1989 sdhci_runtime_pm_put(host
);
1992 static void sdhci_timeout_timer(unsigned long data
)
1994 struct sdhci_host
*host
;
1995 unsigned long flags
;
1997 host
= (struct sdhci_host
*)data
;
1999 spin_lock_irqsave(&host
->lock
, flags
);
2002 pr_err("%s: Timeout waiting for hardware "
2003 "interrupt.\n", mmc_hostname(host
->mmc
));
2004 sdhci_dumpregs(host
);
2007 host
->data
->error
= -ETIMEDOUT
;
2008 sdhci_finish_data(host
);
2011 host
->cmd
->error
= -ETIMEDOUT
;
2013 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2015 tasklet_schedule(&host
->finish_tasklet
);
2020 spin_unlock_irqrestore(&host
->lock
, flags
);
2023 static void sdhci_tuning_timer(unsigned long data
)
2025 struct sdhci_host
*host
;
2026 unsigned long flags
;
2028 host
= (struct sdhci_host
*)data
;
2030 spin_lock_irqsave(&host
->lock
, flags
);
2032 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2034 spin_unlock_irqrestore(&host
->lock
, flags
);
2037 /*****************************************************************************\
2039 * Interrupt handling *
2041 \*****************************************************************************/
2043 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
2045 BUG_ON(intmask
== 0);
2048 pr_err("%s: Got command interrupt 0x%08x even "
2049 "though no command operation was in progress.\n",
2050 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2051 sdhci_dumpregs(host
);
2055 if (intmask
& SDHCI_INT_TIMEOUT
)
2056 host
->cmd
->error
= -ETIMEDOUT
;
2057 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
2059 host
->cmd
->error
= -EILSEQ
;
2061 if (host
->cmd
->error
) {
2062 tasklet_schedule(&host
->finish_tasklet
);
2067 * The host can send and interrupt when the busy state has
2068 * ended, allowing us to wait without wasting CPU cycles.
2069 * Unfortunately this is overloaded on the "data complete"
2070 * interrupt, so we need to take some care when handling
2073 * Note: The 1.0 specification is a bit ambiguous about this
2074 * feature so there might be some problems with older
2077 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
2078 if (host
->cmd
->data
)
2079 DBG("Cannot wait for busy signal when also "
2080 "doing a data transfer");
2081 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
))
2084 /* The controller does not support the end-of-busy IRQ,
2085 * fall through and take the SDHCI_INT_RESPONSE */
2088 if (intmask
& SDHCI_INT_RESPONSE
)
2089 sdhci_finish_command(host
);
2092 #ifdef CONFIG_MMC_DEBUG
2093 static void sdhci_show_adma_error(struct sdhci_host
*host
)
2095 const char *name
= mmc_hostname(host
->mmc
);
2096 u8
*desc
= host
->adma_desc
;
2101 sdhci_dumpregs(host
);
2104 dma
= (__le32
*)(desc
+ 4);
2105 len
= (__le16
*)(desc
+ 2);
2108 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2109 name
, desc
, le32_to_cpu(*dma
), le16_to_cpu(*len
), attr
);
2118 static void sdhci_show_adma_error(struct sdhci_host
*host
) { }
2121 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2123 BUG_ON(intmask
== 0);
2125 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2126 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2127 if (SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
)) ==
2128 MMC_SEND_TUNING_BLOCK
) {
2129 host
->tuning_done
= 1;
2130 wake_up(&host
->buf_ready_int
);
2137 * The "data complete" interrupt is also used to
2138 * indicate that a busy state has ended. See comment
2139 * above in sdhci_cmd_irq().
2141 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2142 if (intmask
& SDHCI_INT_DATA_END
) {
2143 sdhci_finish_command(host
);
2148 pr_err("%s: Got data interrupt 0x%08x even "
2149 "though no data operation was in progress.\n",
2150 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2151 sdhci_dumpregs(host
);
2156 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2157 host
->data
->error
= -ETIMEDOUT
;
2158 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2159 host
->data
->error
= -EILSEQ
;
2160 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2161 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2163 host
->data
->error
= -EILSEQ
;
2164 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2165 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2166 sdhci_show_adma_error(host
);
2167 host
->data
->error
= -EIO
;
2170 if (host
->data
->error
)
2171 sdhci_finish_data(host
);
2173 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2174 sdhci_transfer_pio(host
);
2177 * We currently don't do anything fancy with DMA
2178 * boundaries, but as we can't disable the feature
2179 * we need to at least restart the transfer.
2181 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2182 * should return a valid address to continue from, but as
2183 * some controllers are faulty, don't trust them.
2185 if (intmask
& SDHCI_INT_DMA_END
) {
2186 u32 dmastart
, dmanow
;
2187 dmastart
= sg_dma_address(host
->data
->sg
);
2188 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2190 * Force update to the next DMA block boundary.
2193 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2194 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2195 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2196 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2198 mmc_hostname(host
->mmc
), dmastart
,
2199 host
->data
->bytes_xfered
, dmanow
);
2200 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2203 if (intmask
& SDHCI_INT_DATA_END
) {
2206 * Data managed to finish before the
2207 * command completed. Make sure we do
2208 * things in the proper order.
2210 host
->data_early
= 1;
2212 sdhci_finish_data(host
);
2218 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2221 struct sdhci_host
*host
= dev_id
;
2225 spin_lock(&host
->lock
);
2227 if (host
->runtime_suspended
) {
2228 spin_unlock(&host
->lock
);
2229 pr_warning("%s: got irq while runtime suspended\n",
2230 mmc_hostname(host
->mmc
));
2234 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2236 if (!intmask
|| intmask
== 0xffffffff) {
2241 DBG("*** %s got interrupt: 0x%08x\n",
2242 mmc_hostname(host
->mmc
), intmask
);
2244 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2245 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2249 * There is a observation on i.mx esdhc. INSERT bit will be
2250 * immediately set again when it gets cleared, if a card is
2251 * inserted. We have to mask the irq to prevent interrupt
2252 * storm which will freeze the system. And the REMOVE gets
2253 * the same situation.
2255 * More testing are needed here to ensure it works for other
2258 sdhci_mask_irqs(host
, present
? SDHCI_INT_CARD_INSERT
:
2259 SDHCI_INT_CARD_REMOVE
);
2260 sdhci_unmask_irqs(host
, present
? SDHCI_INT_CARD_REMOVE
:
2261 SDHCI_INT_CARD_INSERT
);
2263 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2264 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2265 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
2266 tasklet_schedule(&host
->card_tasklet
);
2269 if (intmask
& SDHCI_INT_CMD_MASK
) {
2270 sdhci_writel(host
, intmask
& SDHCI_INT_CMD_MASK
,
2272 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
2275 if (intmask
& SDHCI_INT_DATA_MASK
) {
2276 sdhci_writel(host
, intmask
& SDHCI_INT_DATA_MASK
,
2278 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2281 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
2283 intmask
&= ~SDHCI_INT_ERROR
;
2285 if (intmask
& SDHCI_INT_BUS_POWER
) {
2286 pr_err("%s: Card is consuming too much power!\n",
2287 mmc_hostname(host
->mmc
));
2288 sdhci_writel(host
, SDHCI_INT_BUS_POWER
, SDHCI_INT_STATUS
);
2291 intmask
&= ~SDHCI_INT_BUS_POWER
;
2293 if (intmask
& SDHCI_INT_CARD_INT
)
2296 intmask
&= ~SDHCI_INT_CARD_INT
;
2299 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2300 mmc_hostname(host
->mmc
), intmask
);
2301 sdhci_dumpregs(host
);
2303 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2306 result
= IRQ_HANDLED
;
2310 spin_unlock(&host
->lock
);
2313 * We have to delay this as it calls back into the driver.
2316 mmc_signal_sdio_irq(host
->mmc
);
2321 /*****************************************************************************\
2325 \*****************************************************************************/
2329 int sdhci_suspend_host(struct sdhci_host
*host
)
2333 sdhci_disable_card_detection(host
);
2335 /* Disable tuning since we are suspending */
2336 if (host
->version
>= SDHCI_SPEC_300
&& host
->tuning_count
&&
2337 host
->tuning_mode
== SDHCI_TUNING_MODE_1
) {
2338 del_timer_sync(&host
->tuning_timer
);
2339 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2342 ret
= mmc_suspend_host(host
->mmc
);
2346 free_irq(host
->irq
, host
);
2349 ret
= regulator_disable(host
->vmmc
);
2354 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2356 int sdhci_resume_host(struct sdhci_host
*host
)
2361 int ret
= regulator_enable(host
->vmmc
);
2366 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2367 if (host
->ops
->enable_dma
)
2368 host
->ops
->enable_dma(host
);
2371 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2372 mmc_hostname(host
->mmc
), host
);
2376 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2379 ret
= mmc_resume_host(host
->mmc
);
2380 sdhci_enable_card_detection(host
);
2382 /* Set the re-tuning expiration flag */
2383 if ((host
->version
>= SDHCI_SPEC_300
) && host
->tuning_count
&&
2384 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
))
2385 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2390 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2392 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2395 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2396 val
|= SDHCI_WAKE_ON_INT
;
2397 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2400 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2402 #endif /* CONFIG_PM */
2404 #ifdef CONFIG_PM_RUNTIME
2406 static int sdhci_runtime_pm_get(struct sdhci_host
*host
)
2408 return pm_runtime_get_sync(host
->mmc
->parent
);
2411 static int sdhci_runtime_pm_put(struct sdhci_host
*host
)
2413 pm_runtime_mark_last_busy(host
->mmc
->parent
);
2414 return pm_runtime_put_autosuspend(host
->mmc
->parent
);
2417 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2419 unsigned long flags
;
2422 /* Disable tuning since we are suspending */
2423 if (host
->version
>= SDHCI_SPEC_300
&&
2424 host
->tuning_mode
== SDHCI_TUNING_MODE_1
) {
2425 del_timer_sync(&host
->tuning_timer
);
2426 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2429 spin_lock_irqsave(&host
->lock
, flags
);
2430 sdhci_mask_irqs(host
, SDHCI_INT_ALL_MASK
);
2431 spin_unlock_irqrestore(&host
->lock
, flags
);
2433 synchronize_irq(host
->irq
);
2435 spin_lock_irqsave(&host
->lock
, flags
);
2436 host
->runtime_suspended
= true;
2437 spin_unlock_irqrestore(&host
->lock
, flags
);
2441 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2443 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2445 unsigned long flags
;
2446 int ret
= 0, host_flags
= host
->flags
;
2448 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2449 if (host
->ops
->enable_dma
)
2450 host
->ops
->enable_dma(host
);
2453 sdhci_init(host
, 0);
2455 /* Force clock and power re-program */
2458 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2460 sdhci_do_start_signal_voltage_switch(host
, &host
->mmc
->ios
);
2461 if (host_flags
& SDHCI_PV_ENABLED
)
2462 sdhci_do_enable_preset_value(host
, true);
2464 /* Set the re-tuning expiration flag */
2465 if ((host
->version
>= SDHCI_SPEC_300
) && host
->tuning_count
&&
2466 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
))
2467 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2469 spin_lock_irqsave(&host
->lock
, flags
);
2471 host
->runtime_suspended
= false;
2473 /* Enable SDIO IRQ */
2474 if ((host
->flags
& SDHCI_SDIO_IRQ_ENABLED
))
2475 sdhci_enable_sdio_irq_nolock(host
, true);
2477 /* Enable Card Detection */
2478 sdhci_enable_card_detection(host
);
2480 spin_unlock_irqrestore(&host
->lock
, flags
);
2484 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2488 /*****************************************************************************\
2490 * Device allocation/registration *
2492 \*****************************************************************************/
2494 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2497 struct mmc_host
*mmc
;
2498 struct sdhci_host
*host
;
2500 WARN_ON(dev
== NULL
);
2502 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2504 return ERR_PTR(-ENOMEM
);
2506 host
= mmc_priv(mmc
);
2512 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2514 int sdhci_add_host(struct sdhci_host
*host
)
2516 struct mmc_host
*mmc
;
2518 u32 max_current_caps
;
2519 unsigned int ocr_avail
;
2522 WARN_ON(host
== NULL
);
2529 host
->quirks
= debug_quirks
;
2531 host
->quirks2
= debug_quirks2
;
2533 sdhci_reset(host
, SDHCI_RESET_ALL
);
2535 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2536 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2537 >> SDHCI_SPEC_VER_SHIFT
;
2538 if (host
->version
> SDHCI_SPEC_300
) {
2539 pr_err("%s: Unknown controller version (%d). "
2540 "You may experience problems.\n", mmc_hostname(mmc
),
2544 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2545 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2547 caps
[1] = (host
->version
>= SDHCI_SPEC_300
) ?
2548 sdhci_readl(host
, SDHCI_CAPABILITIES_1
) : 0;
2550 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2551 host
->flags
|= SDHCI_USE_SDMA
;
2552 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2553 DBG("Controller doesn't have SDMA capability\n");
2555 host
->flags
|= SDHCI_USE_SDMA
;
2557 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2558 (host
->flags
& SDHCI_USE_SDMA
)) {
2559 DBG("Disabling DMA as it is marked broken\n");
2560 host
->flags
&= ~SDHCI_USE_SDMA
;
2563 if ((host
->version
>= SDHCI_SPEC_200
) &&
2564 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2565 host
->flags
|= SDHCI_USE_ADMA
;
2567 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2568 (host
->flags
& SDHCI_USE_ADMA
)) {
2569 DBG("Disabling ADMA as it is marked broken\n");
2570 host
->flags
&= ~SDHCI_USE_ADMA
;
2573 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2574 if (host
->ops
->enable_dma
) {
2575 if (host
->ops
->enable_dma(host
)) {
2576 pr_warning("%s: No suitable DMA "
2577 "available. Falling back to PIO.\n",
2580 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2585 if (host
->flags
& SDHCI_USE_ADMA
) {
2587 * We need to allocate descriptors for all sg entries
2588 * (128) and potentially one alignment transfer for
2589 * each of those entries.
2591 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
2592 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
2593 if (!host
->adma_desc
|| !host
->align_buffer
) {
2594 kfree(host
->adma_desc
);
2595 kfree(host
->align_buffer
);
2596 pr_warning("%s: Unable to allocate ADMA "
2597 "buffers. Falling back to standard DMA.\n",
2599 host
->flags
&= ~SDHCI_USE_ADMA
;
2604 * If we use DMA, then it's up to the caller to set the DMA
2605 * mask, but PIO does not need the hw shim so we set a new
2606 * mask here in that case.
2608 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
2609 host
->dma_mask
= DMA_BIT_MASK(64);
2610 mmc_dev(host
->mmc
)->dma_mask
= &host
->dma_mask
;
2613 if (host
->version
>= SDHCI_SPEC_300
)
2614 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
2615 >> SDHCI_CLOCK_BASE_SHIFT
;
2617 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
2618 >> SDHCI_CLOCK_BASE_SHIFT
;
2620 host
->max_clk
*= 1000000;
2621 if (host
->max_clk
== 0 || host
->quirks
&
2622 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
2623 if (!host
->ops
->get_max_clock
) {
2624 pr_err("%s: Hardware doesn't specify base clock "
2625 "frequency.\n", mmc_hostname(mmc
));
2628 host
->max_clk
= host
->ops
->get_max_clock(host
);
2632 * In case of Host Controller v3.00, find out whether clock
2633 * multiplier is supported.
2635 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
2636 SDHCI_CLOCK_MUL_SHIFT
;
2639 * In case the value in Clock Multiplier is 0, then programmable
2640 * clock mode is not supported, otherwise the actual clock
2641 * multiplier is one more than the value of Clock Multiplier
2642 * in the Capabilities Register.
2648 * Set host parameters.
2650 mmc
->ops
= &sdhci_ops
;
2651 mmc
->f_max
= host
->max_clk
;
2652 if (host
->ops
->get_min_clock
)
2653 mmc
->f_min
= host
->ops
->get_min_clock(host
);
2654 else if (host
->version
>= SDHCI_SPEC_300
) {
2655 if (host
->clk_mul
) {
2656 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
2657 mmc
->f_max
= host
->max_clk
* host
->clk_mul
;
2659 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
2661 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
2664 (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
2665 if (host
->timeout_clk
== 0) {
2666 if (host
->ops
->get_timeout_clock
) {
2667 host
->timeout_clk
= host
->ops
->get_timeout_clock(host
);
2668 } else if (!(host
->quirks
&
2669 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
2670 pr_err("%s: Hardware doesn't specify timeout clock "
2671 "frequency.\n", mmc_hostname(mmc
));
2675 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
2676 host
->timeout_clk
*= 1000;
2678 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)
2679 host
->timeout_clk
= mmc
->f_max
/ 1000;
2681 mmc
->max_discard_to
= (1 << 27) / host
->timeout_clk
;
2683 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
2685 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
2686 host
->flags
|= SDHCI_AUTO_CMD12
;
2688 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2689 if ((host
->version
>= SDHCI_SPEC_300
) &&
2690 ((host
->flags
& SDHCI_USE_ADMA
) ||
2691 !(host
->flags
& SDHCI_USE_SDMA
))) {
2692 host
->flags
|= SDHCI_AUTO_CMD23
;
2693 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
2695 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
2699 * A controller may support 8-bit width, but the board itself
2700 * might not have the pins brought out. Boards that support
2701 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2702 * their platform code before calling sdhci_add_host(), and we
2703 * won't assume 8-bit width for hosts without that CAP.
2705 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
2706 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2708 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
2709 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
2711 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
2712 mmc_card_is_removable(mmc
))
2713 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2715 /* UHS-I mode(s) supported by the host controller. */
2716 if (host
->version
>= SDHCI_SPEC_300
)
2717 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
2719 /* SDR104 supports also implies SDR50 support */
2720 if (caps
[1] & SDHCI_SUPPORT_SDR104
)
2721 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
2722 else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
2723 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
2725 if (caps
[1] & SDHCI_SUPPORT_DDR50
)
2726 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
2728 /* Does the host needs tuning for SDR50? */
2729 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
2730 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
2732 /* Driver Type(s) (A, C, D) supported by the host */
2733 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
2734 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
2735 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
2736 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
2737 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
2738 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
2741 * If Power Off Notify capability is enabled by the host,
2742 * set notify to short power off notify timeout value.
2744 if (mmc
->caps2
& MMC_CAP2_POWEROFF_NOTIFY
)
2745 mmc
->power_notify_type
= MMC_HOST_PW_NOTIFY_SHORT
;
2747 mmc
->power_notify_type
= MMC_HOST_PW_NOTIFY_NONE
;
2749 /* Initial value for re-tuning timer count */
2750 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
2751 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
2754 * In case Re-tuning Timer is not disabled, the actual value of
2755 * re-tuning timer will be 2 ^ (n - 1).
2757 if (host
->tuning_count
)
2758 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
2760 /* Re-tuning mode supported by the Host Controller */
2761 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
2762 SDHCI_RETUNING_MODE_SHIFT
;
2766 * According to SD Host Controller spec v3.00, if the Host System
2767 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2768 * the value is meaningful only if Voltage Support in the Capabilities
2769 * register is set. The actual current value is 4 times the register
2772 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
2774 if (caps
[0] & SDHCI_CAN_VDD_330
) {
2775 int max_current_330
;
2777 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
2779 max_current_330
= ((max_current_caps
&
2780 SDHCI_MAX_CURRENT_330_MASK
) >>
2781 SDHCI_MAX_CURRENT_330_SHIFT
) *
2782 SDHCI_MAX_CURRENT_MULTIPLIER
;
2784 if (max_current_330
> 150)
2785 mmc
->caps
|= MMC_CAP_SET_XPC_330
;
2787 if (caps
[0] & SDHCI_CAN_VDD_300
) {
2788 int max_current_300
;
2790 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
2792 max_current_300
= ((max_current_caps
&
2793 SDHCI_MAX_CURRENT_300_MASK
) >>
2794 SDHCI_MAX_CURRENT_300_SHIFT
) *
2795 SDHCI_MAX_CURRENT_MULTIPLIER
;
2797 if (max_current_300
> 150)
2798 mmc
->caps
|= MMC_CAP_SET_XPC_300
;
2800 if (caps
[0] & SDHCI_CAN_VDD_180
) {
2801 int max_current_180
;
2803 ocr_avail
|= MMC_VDD_165_195
;
2805 max_current_180
= ((max_current_caps
&
2806 SDHCI_MAX_CURRENT_180_MASK
) >>
2807 SDHCI_MAX_CURRENT_180_SHIFT
) *
2808 SDHCI_MAX_CURRENT_MULTIPLIER
;
2810 if (max_current_180
> 150)
2811 mmc
->caps
|= MMC_CAP_SET_XPC_180
;
2813 /* Maximum current capabilities of the host at 1.8V */
2814 if (max_current_180
>= 800)
2815 mmc
->caps
|= MMC_CAP_MAX_CURRENT_800
;
2816 else if (max_current_180
>= 600)
2817 mmc
->caps
|= MMC_CAP_MAX_CURRENT_600
;
2818 else if (max_current_180
>= 400)
2819 mmc
->caps
|= MMC_CAP_MAX_CURRENT_400
;
2821 mmc
->caps
|= MMC_CAP_MAX_CURRENT_200
;
2824 mmc
->ocr_avail
= ocr_avail
;
2825 mmc
->ocr_avail_sdio
= ocr_avail
;
2826 if (host
->ocr_avail_sdio
)
2827 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
2828 mmc
->ocr_avail_sd
= ocr_avail
;
2829 if (host
->ocr_avail_sd
)
2830 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
2831 else /* normal SD controllers don't support 1.8V */
2832 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
2833 mmc
->ocr_avail_mmc
= ocr_avail
;
2834 if (host
->ocr_avail_mmc
)
2835 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
2837 if (mmc
->ocr_avail
== 0) {
2838 pr_err("%s: Hardware doesn't report any "
2839 "support voltages.\n", mmc_hostname(mmc
));
2843 spin_lock_init(&host
->lock
);
2846 * Maximum number of segments. Depends on if the hardware
2847 * can do scatter/gather or not.
2849 if (host
->flags
& SDHCI_USE_ADMA
)
2850 mmc
->max_segs
= 128;
2851 else if (host
->flags
& SDHCI_USE_SDMA
)
2854 mmc
->max_segs
= 128;
2857 * Maximum number of sectors in one transfer. Limited by DMA boundary
2860 mmc
->max_req_size
= 524288;
2863 * Maximum segment size. Could be one segment with the maximum number
2864 * of bytes. When doing hardware scatter/gather, each entry cannot
2865 * be larger than 64 KiB though.
2867 if (host
->flags
& SDHCI_USE_ADMA
) {
2868 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
2869 mmc
->max_seg_size
= 65535;
2871 mmc
->max_seg_size
= 65536;
2873 mmc
->max_seg_size
= mmc
->max_req_size
;
2877 * Maximum block size. This varies from controller to controller and
2878 * is specified in the capabilities register.
2880 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
2881 mmc
->max_blk_size
= 2;
2883 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
2884 SDHCI_MAX_BLOCK_SHIFT
;
2885 if (mmc
->max_blk_size
>= 3) {
2886 pr_warning("%s: Invalid maximum block size, "
2887 "assuming 512 bytes\n", mmc_hostname(mmc
));
2888 mmc
->max_blk_size
= 0;
2892 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
2895 * Maximum block count.
2897 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
2902 tasklet_init(&host
->card_tasklet
,
2903 sdhci_tasklet_card
, (unsigned long)host
);
2904 tasklet_init(&host
->finish_tasklet
,
2905 sdhci_tasklet_finish
, (unsigned long)host
);
2907 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
2909 if (host
->version
>= SDHCI_SPEC_300
) {
2910 init_waitqueue_head(&host
->buf_ready_int
);
2912 /* Initialize re-tuning timer */
2913 init_timer(&host
->tuning_timer
);
2914 host
->tuning_timer
.data
= (unsigned long)host
;
2915 host
->tuning_timer
.function
= sdhci_tuning_timer
;
2918 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2919 mmc_hostname(mmc
), host
);
2923 host
->vmmc
= regulator_get(mmc_dev(mmc
), "vmmc");
2924 if (IS_ERR(host
->vmmc
)) {
2925 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc
));
2928 regulator_enable(host
->vmmc
);
2931 sdhci_init(host
, 0);
2933 #ifdef CONFIG_MMC_DEBUG
2934 sdhci_dumpregs(host
);
2937 #ifdef SDHCI_USE_LEDS_CLASS
2938 snprintf(host
->led_name
, sizeof(host
->led_name
),
2939 "%s::", mmc_hostname(mmc
));
2940 host
->led
.name
= host
->led_name
;
2941 host
->led
.brightness
= LED_OFF
;
2942 host
->led
.default_trigger
= mmc_hostname(mmc
);
2943 host
->led
.brightness_set
= sdhci_led_control
;
2945 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
2954 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2955 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
2956 (host
->flags
& SDHCI_USE_ADMA
) ? "ADMA" :
2957 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
2959 sdhci_enable_card_detection(host
);
2963 #ifdef SDHCI_USE_LEDS_CLASS
2965 sdhci_reset(host
, SDHCI_RESET_ALL
);
2966 free_irq(host
->irq
, host
);
2969 tasklet_kill(&host
->card_tasklet
);
2970 tasklet_kill(&host
->finish_tasklet
);
2975 EXPORT_SYMBOL_GPL(sdhci_add_host
);
2977 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
2979 unsigned long flags
;
2982 spin_lock_irqsave(&host
->lock
, flags
);
2984 host
->flags
|= SDHCI_DEVICE_DEAD
;
2987 pr_err("%s: Controller removed during "
2988 " transfer!\n", mmc_hostname(host
->mmc
));
2990 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2991 tasklet_schedule(&host
->finish_tasklet
);
2994 spin_unlock_irqrestore(&host
->lock
, flags
);
2997 sdhci_disable_card_detection(host
);
2999 mmc_remove_host(host
->mmc
);
3001 #ifdef SDHCI_USE_LEDS_CLASS
3002 led_classdev_unregister(&host
->led
);
3006 sdhci_reset(host
, SDHCI_RESET_ALL
);
3008 free_irq(host
->irq
, host
);
3010 del_timer_sync(&host
->timer
);
3011 if (host
->version
>= SDHCI_SPEC_300
)
3012 del_timer_sync(&host
->tuning_timer
);
3014 tasklet_kill(&host
->card_tasklet
);
3015 tasklet_kill(&host
->finish_tasklet
);
3018 regulator_disable(host
->vmmc
);
3019 regulator_put(host
->vmmc
);
3022 kfree(host
->adma_desc
);
3023 kfree(host
->align_buffer
);
3025 host
->adma_desc
= NULL
;
3026 host
->align_buffer
= NULL
;
3029 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3031 void sdhci_free_host(struct sdhci_host
*host
)
3033 mmc_free_host(host
->mmc
);
3036 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3038 /*****************************************************************************\
3040 * Driver init/exit *
3042 \*****************************************************************************/
3044 static int __init
sdhci_drv_init(void)
3047 ": Secure Digital Host Controller Interface driver\n");
3048 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3053 static void __exit
sdhci_drv_exit(void)
3057 module_init(sdhci_drv_init
);
3058 module_exit(sdhci_drv_exit
);
3060 module_param(debug_quirks
, uint
, 0444);
3061 module_param(debug_quirks2
, uint
, 0444);
3063 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3064 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3065 MODULE_LICENSE("GPL");
3067 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3068 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");