net/fec: replace hardcoded irq num with macro
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / freescale / fec.c
blob1794ea446a9e9ced8b1a96168dc22fff4cdcf02e
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
41 #include <linux/io.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
47 #include <linux/of.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
52 #include <asm/cacheflush.h>
54 #ifndef CONFIG_ARM
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
57 #endif
59 #include "fec.h"
61 #if defined(CONFIG_ARM)
62 #define FEC_ALIGNMENT 0xf
63 #else
64 #define FEC_ALIGNMENT 0x3
65 #endif
67 #define DRIVER_NAME "fec"
69 /* Controller is ENET-MAC */
70 #define FEC_QUIRK_ENET_MAC (1 << 0)
71 /* Controller needs driver to swap frame */
72 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
73 /* Controller uses gasket */
74 #define FEC_QUIRK_USE_GASKET (1 << 2)
75 /* Controller has GBIT support */
76 #define FEC_QUIRK_HAS_GBIT (1 << 3)
78 static struct platform_device_id fec_devtype[] = {
80 /* keep it for coldfire */
81 .name = DRIVER_NAME,
82 .driver_data = 0,
83 }, {
84 .name = "imx25-fec",
85 .driver_data = FEC_QUIRK_USE_GASKET,
86 }, {
87 .name = "imx27-fec",
88 .driver_data = 0,
89 }, {
90 .name = "imx28-fec",
91 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
92 }, {
93 .name = "imx6q-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
95 }, {
96 /* sentinel */
99 MODULE_DEVICE_TABLE(platform, fec_devtype);
101 enum imx_fec_type {
102 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
103 IMX27_FEC, /* runs on i.mx27/35/51 */
104 IMX28_FEC,
105 IMX6Q_FEC,
108 static const struct of_device_id fec_dt_ids[] = {
109 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
110 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
111 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
112 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
113 { /* sentinel */ }
115 MODULE_DEVICE_TABLE(of, fec_dt_ids);
117 static unsigned char macaddr[ETH_ALEN];
118 module_param_array(macaddr, byte, NULL, 0);
119 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
121 #if defined(CONFIG_M5272)
123 * Some hardware gets it MAC address out of local flash memory.
124 * if this is non-zero then assume it is the address to get MAC from.
126 #if defined(CONFIG_NETtel)
127 #define FEC_FLASHMAC 0xf0006006
128 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
129 #define FEC_FLASHMAC 0xf0006000
130 #elif defined(CONFIG_CANCam)
131 #define FEC_FLASHMAC 0xf0020000
132 #elif defined (CONFIG_M5272C3)
133 #define FEC_FLASHMAC (0xffe04000 + 4)
134 #elif defined(CONFIG_MOD5272)
135 #define FEC_FLASHMAC 0xffc0406b
136 #else
137 #define FEC_FLASHMAC 0
138 #endif
139 #endif /* CONFIG_M5272 */
141 /* The number of Tx and Rx buffers. These are allocated from the page
142 * pool. The code may assume these are power of two, so it it best
143 * to keep them that size.
144 * We don't need to allocate pages for the transmitter. We just use
145 * the skbuffer directly.
147 #define FEC_ENET_RX_PAGES 8
148 #define FEC_ENET_RX_FRSIZE 2048
149 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
150 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
151 #define FEC_ENET_TX_FRSIZE 2048
152 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
153 #define TX_RING_SIZE 16 /* Must be power of two */
154 #define TX_RING_MOD_MASK 15 /* for this to work */
156 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
157 #error "FEC: descriptor ring size constants too large"
158 #endif
160 /* Interrupt events/masks. */
161 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
162 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
163 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
164 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
165 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
166 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
167 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
168 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
169 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
170 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
172 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
180 /* This device has up to three irqs on some platforms */
181 #define FEC_IRQ_NUM 3
184 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
185 * size bits. Other FEC hardware does not, so we need to take that into
186 * account when setting it.
188 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
189 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
190 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
191 #else
192 #define OPT_FRAME_SIZE 0
193 #endif
195 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
196 * tx_bd_base always point to the base of the buffer descriptors. The
197 * cur_rx and cur_tx point to the currently available buffer.
198 * The dirty_tx tracks the current buffer that is being sent by the
199 * controller. The cur_tx and dirty_tx are equal under both completely
200 * empty and completely full conditions. The empty/ready indicator in
201 * the buffer descriptor determines the actual condition.
203 struct fec_enet_private {
204 /* Hardware registers of the FEC device */
205 void __iomem *hwp;
207 struct net_device *netdev;
209 struct clk *clk;
211 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
212 unsigned char *tx_bounce[TX_RING_SIZE];
213 struct sk_buff* tx_skbuff[TX_RING_SIZE];
214 struct sk_buff* rx_skbuff[RX_RING_SIZE];
215 ushort skb_cur;
216 ushort skb_dirty;
218 /* CPM dual port RAM relative addresses */
219 dma_addr_t bd_dma;
220 /* Address of Rx and Tx buffers */
221 struct bufdesc *rx_bd_base;
222 struct bufdesc *tx_bd_base;
223 /* The next free ring entry */
224 struct bufdesc *cur_rx, *cur_tx;
225 /* The ring entries to be free()ed */
226 struct bufdesc *dirty_tx;
228 uint tx_full;
229 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
230 spinlock_t hw_lock;
232 struct platform_device *pdev;
234 int opened;
236 /* Phylib and MDIO interface */
237 struct mii_bus *mii_bus;
238 struct phy_device *phy_dev;
239 int mii_timeout;
240 uint phy_speed;
241 phy_interface_t phy_interface;
242 int link;
243 int full_duplex;
244 struct completion mdio_done;
247 /* FEC MII MMFR bits definition */
248 #define FEC_MMFR_ST (1 << 30)
249 #define FEC_MMFR_OP_READ (2 << 28)
250 #define FEC_MMFR_OP_WRITE (1 << 28)
251 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
252 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
253 #define FEC_MMFR_TA (2 << 16)
254 #define FEC_MMFR_DATA(v) (v & 0xffff)
256 #define FEC_MII_TIMEOUT 1000 /* us */
258 /* Transmitter timeout */
259 #define TX_TIMEOUT (2 * HZ)
261 static void *swap_buffer(void *bufaddr, int len)
263 int i;
264 unsigned int *buf = bufaddr;
266 for (i = 0; i < (len + 3) / 4; i++, buf++)
267 *buf = cpu_to_be32(*buf);
269 return bufaddr;
272 static netdev_tx_t
273 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
275 struct fec_enet_private *fep = netdev_priv(ndev);
276 const struct platform_device_id *id_entry =
277 platform_get_device_id(fep->pdev);
278 struct bufdesc *bdp;
279 void *bufaddr;
280 unsigned short status;
281 unsigned long flags;
283 if (!fep->link) {
284 /* Link is down or autonegotiation is in progress. */
285 return NETDEV_TX_BUSY;
288 spin_lock_irqsave(&fep->hw_lock, flags);
289 /* Fill in a Tx ring entry */
290 bdp = fep->cur_tx;
292 status = bdp->cbd_sc;
294 if (status & BD_ENET_TX_READY) {
295 /* Ooops. All transmit buffers are full. Bail out.
296 * This should not happen, since ndev->tbusy should be set.
298 printk("%s: tx queue full!.\n", ndev->name);
299 spin_unlock_irqrestore(&fep->hw_lock, flags);
300 return NETDEV_TX_BUSY;
303 /* Clear all of the status flags */
304 status &= ~BD_ENET_TX_STATS;
306 /* Set buffer length and buffer pointer */
307 bufaddr = skb->data;
308 bdp->cbd_datlen = skb->len;
311 * On some FEC implementations data must be aligned on
312 * 4-byte boundaries. Use bounce buffers to copy data
313 * and get it aligned. Ugh.
315 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
316 unsigned int index;
317 index = bdp - fep->tx_bd_base;
318 memcpy(fep->tx_bounce[index], skb->data, skb->len);
319 bufaddr = fep->tx_bounce[index];
323 * Some design made an incorrect assumption on endian mode of
324 * the system that it's running on. As the result, driver has to
325 * swap every frame going to and coming from the controller.
327 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
328 swap_buffer(bufaddr, skb->len);
330 /* Save skb pointer */
331 fep->tx_skbuff[fep->skb_cur] = skb;
333 ndev->stats.tx_bytes += skb->len;
334 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
336 /* Push the data cache so the CPM does not get stale memory
337 * data.
339 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
340 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
342 /* Send it on its way. Tell FEC it's ready, interrupt when done,
343 * it's the last BD of the frame, and to put the CRC on the end.
345 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
346 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
347 bdp->cbd_sc = status;
349 /* Trigger transmission start */
350 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
352 /* If this was the last BD in the ring, start at the beginning again. */
353 if (status & BD_ENET_TX_WRAP)
354 bdp = fep->tx_bd_base;
355 else
356 bdp++;
358 if (bdp == fep->dirty_tx) {
359 fep->tx_full = 1;
360 netif_stop_queue(ndev);
363 fep->cur_tx = bdp;
365 skb_tx_timestamp(skb);
367 spin_unlock_irqrestore(&fep->hw_lock, flags);
369 return NETDEV_TX_OK;
372 /* This function is called to start or restart the FEC during a link
373 * change. This only happens when switching between half and full
374 * duplex.
376 static void
377 fec_restart(struct net_device *ndev, int duplex)
379 struct fec_enet_private *fep = netdev_priv(ndev);
380 const struct platform_device_id *id_entry =
381 platform_get_device_id(fep->pdev);
382 int i;
383 u32 temp_mac[2];
384 u32 rcntl = OPT_FRAME_SIZE | 0x04;
385 u32 ecntl = 0x2; /* ETHEREN */
387 /* Whack a reset. We should wait for this. */
388 writel(1, fep->hwp + FEC_ECNTRL);
389 udelay(10);
392 * enet-mac reset will reset mac address registers too,
393 * so need to reconfigure it.
395 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
396 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
397 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
398 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
401 /* Clear any outstanding interrupt. */
402 writel(0xffc00000, fep->hwp + FEC_IEVENT);
404 /* Reset all multicast. */
405 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
406 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
407 #ifndef CONFIG_M5272
408 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
409 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
410 #endif
412 /* Set maximum receive buffer size. */
413 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
415 /* Set receive and transmit descriptor base. */
416 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
417 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
418 fep->hwp + FEC_X_DES_START);
420 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
421 fep->cur_rx = fep->rx_bd_base;
423 /* Reset SKB transmit buffers. */
424 fep->skb_cur = fep->skb_dirty = 0;
425 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
426 if (fep->tx_skbuff[i]) {
427 dev_kfree_skb_any(fep->tx_skbuff[i]);
428 fep->tx_skbuff[i] = NULL;
432 /* Enable MII mode */
433 if (duplex) {
434 /* FD enable */
435 writel(0x04, fep->hwp + FEC_X_CNTRL);
436 } else {
437 /* No Rcv on Xmit */
438 rcntl |= 0x02;
439 writel(0x0, fep->hwp + FEC_X_CNTRL);
442 fep->full_duplex = duplex;
444 /* Set MII speed */
445 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
448 * The phy interface and speed need to get configured
449 * differently on enet-mac.
451 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
452 /* Enable flow control and length check */
453 rcntl |= 0x40000000 | 0x00000020;
455 /* RGMII, RMII or MII */
456 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
457 rcntl |= (1 << 6);
458 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
459 rcntl |= (1 << 8);
460 else
461 rcntl &= ~(1 << 8);
463 /* 1G, 100M or 10M */
464 if (fep->phy_dev) {
465 if (fep->phy_dev->speed == SPEED_1000)
466 ecntl |= (1 << 5);
467 else if (fep->phy_dev->speed == SPEED_100)
468 rcntl &= ~(1 << 9);
469 else
470 rcntl |= (1 << 9);
472 } else {
473 #ifdef FEC_MIIGSK_ENR
474 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
475 /* disable the gasket and wait */
476 writel(0, fep->hwp + FEC_MIIGSK_ENR);
477 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
478 udelay(1);
481 * configure the gasket:
482 * RMII, 50 MHz, no loopback, no echo
483 * MII, 25 MHz, no loopback, no echo
485 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
486 1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
489 /* re-enable the gasket */
490 writel(2, fep->hwp + FEC_MIIGSK_ENR);
492 #endif
494 writel(rcntl, fep->hwp + FEC_R_CNTRL);
496 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
497 /* enable ENET endian swap */
498 ecntl |= (1 << 8);
499 /* enable ENET store and forward mode */
500 writel(1 << 8, fep->hwp + FEC_X_WMRK);
503 /* And last, enable the transmit and receive processing */
504 writel(ecntl, fep->hwp + FEC_ECNTRL);
505 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
507 /* Enable interrupts we wish to service */
508 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
511 static void
512 fec_stop(struct net_device *ndev)
514 struct fec_enet_private *fep = netdev_priv(ndev);
515 const struct platform_device_id *id_entry =
516 platform_get_device_id(fep->pdev);
518 /* We cannot expect a graceful transmit stop without link !!! */
519 if (fep->link) {
520 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
521 udelay(10);
522 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
523 printk("fec_stop : Graceful transmit stop did not complete !\n");
526 /* Whack a reset. We should wait for this. */
527 writel(1, fep->hwp + FEC_ECNTRL);
528 udelay(10);
529 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
530 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
532 /* We have to keep ENET enabled to have MII interrupt stay working */
533 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
534 writel(2, fep->hwp + FEC_ECNTRL);
538 static void
539 fec_timeout(struct net_device *ndev)
541 struct fec_enet_private *fep = netdev_priv(ndev);
543 ndev->stats.tx_errors++;
545 fec_restart(ndev, fep->full_duplex);
546 netif_wake_queue(ndev);
549 static void
550 fec_enet_tx(struct net_device *ndev)
552 struct fec_enet_private *fep;
553 struct bufdesc *bdp;
554 unsigned short status;
555 struct sk_buff *skb;
557 fep = netdev_priv(ndev);
558 spin_lock(&fep->hw_lock);
559 bdp = fep->dirty_tx;
561 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
562 if (bdp == fep->cur_tx && fep->tx_full == 0)
563 break;
565 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
566 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
567 bdp->cbd_bufaddr = 0;
569 skb = fep->tx_skbuff[fep->skb_dirty];
570 /* Check for errors. */
571 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
572 BD_ENET_TX_RL | BD_ENET_TX_UN |
573 BD_ENET_TX_CSL)) {
574 ndev->stats.tx_errors++;
575 if (status & BD_ENET_TX_HB) /* No heartbeat */
576 ndev->stats.tx_heartbeat_errors++;
577 if (status & BD_ENET_TX_LC) /* Late collision */
578 ndev->stats.tx_window_errors++;
579 if (status & BD_ENET_TX_RL) /* Retrans limit */
580 ndev->stats.tx_aborted_errors++;
581 if (status & BD_ENET_TX_UN) /* Underrun */
582 ndev->stats.tx_fifo_errors++;
583 if (status & BD_ENET_TX_CSL) /* Carrier lost */
584 ndev->stats.tx_carrier_errors++;
585 } else {
586 ndev->stats.tx_packets++;
589 if (status & BD_ENET_TX_READY)
590 printk("HEY! Enet xmit interrupt and TX_READY.\n");
592 /* Deferred means some collisions occurred during transmit,
593 * but we eventually sent the packet OK.
595 if (status & BD_ENET_TX_DEF)
596 ndev->stats.collisions++;
598 /* Free the sk buffer associated with this last transmit */
599 dev_kfree_skb_any(skb);
600 fep->tx_skbuff[fep->skb_dirty] = NULL;
601 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
603 /* Update pointer to next buffer descriptor to be transmitted */
604 if (status & BD_ENET_TX_WRAP)
605 bdp = fep->tx_bd_base;
606 else
607 bdp++;
609 /* Since we have freed up a buffer, the ring is no longer full
611 if (fep->tx_full) {
612 fep->tx_full = 0;
613 if (netif_queue_stopped(ndev))
614 netif_wake_queue(ndev);
617 fep->dirty_tx = bdp;
618 spin_unlock(&fep->hw_lock);
622 /* During a receive, the cur_rx points to the current incoming buffer.
623 * When we update through the ring, if the next incoming buffer has
624 * not been given to the system, we just set the empty indicator,
625 * effectively tossing the packet.
627 static void
628 fec_enet_rx(struct net_device *ndev)
630 struct fec_enet_private *fep = netdev_priv(ndev);
631 const struct platform_device_id *id_entry =
632 platform_get_device_id(fep->pdev);
633 struct bufdesc *bdp;
634 unsigned short status;
635 struct sk_buff *skb;
636 ushort pkt_len;
637 __u8 *data;
639 #ifdef CONFIG_M532x
640 flush_cache_all();
641 #endif
643 spin_lock(&fep->hw_lock);
645 /* First, grab all of the stats for the incoming packet.
646 * These get messed up if we get called due to a busy condition.
648 bdp = fep->cur_rx;
650 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
652 /* Since we have allocated space to hold a complete frame,
653 * the last indicator should be set.
655 if ((status & BD_ENET_RX_LAST) == 0)
656 printk("FEC ENET: rcv is not +last\n");
658 if (!fep->opened)
659 goto rx_processing_done;
661 /* Check for errors. */
662 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
663 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
664 ndev->stats.rx_errors++;
665 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
666 /* Frame too long or too short. */
667 ndev->stats.rx_length_errors++;
669 if (status & BD_ENET_RX_NO) /* Frame alignment */
670 ndev->stats.rx_frame_errors++;
671 if (status & BD_ENET_RX_CR) /* CRC Error */
672 ndev->stats.rx_crc_errors++;
673 if (status & BD_ENET_RX_OV) /* FIFO overrun */
674 ndev->stats.rx_fifo_errors++;
677 /* Report late collisions as a frame error.
678 * On this error, the BD is closed, but we don't know what we
679 * have in the buffer. So, just drop this frame on the floor.
681 if (status & BD_ENET_RX_CL) {
682 ndev->stats.rx_errors++;
683 ndev->stats.rx_frame_errors++;
684 goto rx_processing_done;
687 /* Process the incoming frame. */
688 ndev->stats.rx_packets++;
689 pkt_len = bdp->cbd_datlen;
690 ndev->stats.rx_bytes += pkt_len;
691 data = (__u8*)__va(bdp->cbd_bufaddr);
693 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
694 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
696 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
697 swap_buffer(data, pkt_len);
699 /* This does 16 byte alignment, exactly what we need.
700 * The packet length includes FCS, but we don't want to
701 * include that when passing upstream as it messes up
702 * bridging applications.
704 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
706 if (unlikely(!skb)) {
707 printk("%s: Memory squeeze, dropping packet.\n",
708 ndev->name);
709 ndev->stats.rx_dropped++;
710 } else {
711 skb_reserve(skb, NET_IP_ALIGN);
712 skb_put(skb, pkt_len - 4); /* Make room */
713 skb_copy_to_linear_data(skb, data, pkt_len - 4);
714 skb->protocol = eth_type_trans(skb, ndev);
715 if (!skb_defer_rx_timestamp(skb))
716 netif_rx(skb);
719 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
720 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
721 rx_processing_done:
722 /* Clear the status flags for this buffer */
723 status &= ~BD_ENET_RX_STATS;
725 /* Mark the buffer empty */
726 status |= BD_ENET_RX_EMPTY;
727 bdp->cbd_sc = status;
729 /* Update BD pointer to next entry */
730 if (status & BD_ENET_RX_WRAP)
731 bdp = fep->rx_bd_base;
732 else
733 bdp++;
734 /* Doing this here will keep the FEC running while we process
735 * incoming frames. On a heavily loaded network, we should be
736 * able to keep up at the expense of system resources.
738 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
740 fep->cur_rx = bdp;
742 spin_unlock(&fep->hw_lock);
745 static irqreturn_t
746 fec_enet_interrupt(int irq, void *dev_id)
748 struct net_device *ndev = dev_id;
749 struct fec_enet_private *fep = netdev_priv(ndev);
750 uint int_events;
751 irqreturn_t ret = IRQ_NONE;
753 do {
754 int_events = readl(fep->hwp + FEC_IEVENT);
755 writel(int_events, fep->hwp + FEC_IEVENT);
757 if (int_events & FEC_ENET_RXF) {
758 ret = IRQ_HANDLED;
759 fec_enet_rx(ndev);
762 /* Transmit OK, or non-fatal error. Update the buffer
763 * descriptors. FEC handles all errors, we just discover
764 * them as part of the transmit process.
766 if (int_events & FEC_ENET_TXF) {
767 ret = IRQ_HANDLED;
768 fec_enet_tx(ndev);
771 if (int_events & FEC_ENET_MII) {
772 ret = IRQ_HANDLED;
773 complete(&fep->mdio_done);
775 } while (int_events);
777 return ret;
782 /* ------------------------------------------------------------------------- */
783 static void __inline__ fec_get_mac(struct net_device *ndev)
785 struct fec_enet_private *fep = netdev_priv(ndev);
786 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
787 unsigned char *iap, tmpaddr[ETH_ALEN];
790 * try to get mac address in following order:
792 * 1) module parameter via kernel command line in form
793 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
795 iap = macaddr;
797 #ifdef CONFIG_OF
799 * 2) from device tree data
801 if (!is_valid_ether_addr(iap)) {
802 struct device_node *np = fep->pdev->dev.of_node;
803 if (np) {
804 const char *mac = of_get_mac_address(np);
805 if (mac)
806 iap = (unsigned char *) mac;
809 #endif
812 * 3) from flash or fuse (via platform data)
814 if (!is_valid_ether_addr(iap)) {
815 #ifdef CONFIG_M5272
816 if (FEC_FLASHMAC)
817 iap = (unsigned char *)FEC_FLASHMAC;
818 #else
819 if (pdata)
820 memcpy(iap, pdata->mac, ETH_ALEN);
821 #endif
825 * 4) FEC mac registers set by bootloader
827 if (!is_valid_ether_addr(iap)) {
828 *((unsigned long *) &tmpaddr[0]) =
829 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
830 *((unsigned short *) &tmpaddr[4]) =
831 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
832 iap = &tmpaddr[0];
835 memcpy(ndev->dev_addr, iap, ETH_ALEN);
837 /* Adjust MAC if using macaddr */
838 if (iap == macaddr)
839 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
842 /* ------------------------------------------------------------------------- */
845 * Phy section
847 static void fec_enet_adjust_link(struct net_device *ndev)
849 struct fec_enet_private *fep = netdev_priv(ndev);
850 struct phy_device *phy_dev = fep->phy_dev;
851 unsigned long flags;
853 int status_change = 0;
855 spin_lock_irqsave(&fep->hw_lock, flags);
857 /* Prevent a state halted on mii error */
858 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
859 phy_dev->state = PHY_RESUMING;
860 goto spin_unlock;
863 /* Duplex link change */
864 if (phy_dev->link) {
865 if (fep->full_duplex != phy_dev->duplex) {
866 fec_restart(ndev, phy_dev->duplex);
867 status_change = 1;
871 /* Link on or off change */
872 if (phy_dev->link != fep->link) {
873 fep->link = phy_dev->link;
874 if (phy_dev->link)
875 fec_restart(ndev, phy_dev->duplex);
876 else
877 fec_stop(ndev);
878 status_change = 1;
881 spin_unlock:
882 spin_unlock_irqrestore(&fep->hw_lock, flags);
884 if (status_change)
885 phy_print_status(phy_dev);
888 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
890 struct fec_enet_private *fep = bus->priv;
891 unsigned long time_left;
893 fep->mii_timeout = 0;
894 init_completion(&fep->mdio_done);
896 /* start a read op */
897 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
898 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
899 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
901 /* wait for end of transfer */
902 time_left = wait_for_completion_timeout(&fep->mdio_done,
903 usecs_to_jiffies(FEC_MII_TIMEOUT));
904 if (time_left == 0) {
905 fep->mii_timeout = 1;
906 printk(KERN_ERR "FEC: MDIO read timeout\n");
907 return -ETIMEDOUT;
910 /* return value */
911 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
914 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
915 u16 value)
917 struct fec_enet_private *fep = bus->priv;
918 unsigned long time_left;
920 fep->mii_timeout = 0;
921 init_completion(&fep->mdio_done);
923 /* start a write op */
924 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
925 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
926 FEC_MMFR_TA | FEC_MMFR_DATA(value),
927 fep->hwp + FEC_MII_DATA);
929 /* wait for end of transfer */
930 time_left = wait_for_completion_timeout(&fep->mdio_done,
931 usecs_to_jiffies(FEC_MII_TIMEOUT));
932 if (time_left == 0) {
933 fep->mii_timeout = 1;
934 printk(KERN_ERR "FEC: MDIO write timeout\n");
935 return -ETIMEDOUT;
938 return 0;
941 static int fec_enet_mdio_reset(struct mii_bus *bus)
943 return 0;
946 static int fec_enet_mii_probe(struct net_device *ndev)
948 struct fec_enet_private *fep = netdev_priv(ndev);
949 const struct platform_device_id *id_entry =
950 platform_get_device_id(fep->pdev);
951 struct phy_device *phy_dev = NULL;
952 char mdio_bus_id[MII_BUS_ID_SIZE];
953 char phy_name[MII_BUS_ID_SIZE + 3];
954 int phy_id;
955 int dev_id = fep->pdev->id;
957 fep->phy_dev = NULL;
959 /* check for attached phy */
960 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
961 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
962 continue;
963 if (fep->mii_bus->phy_map[phy_id] == NULL)
964 continue;
965 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
966 continue;
967 if (dev_id--)
968 continue;
969 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
970 break;
973 if (phy_id >= PHY_MAX_ADDR) {
974 printk(KERN_INFO "%s: no PHY, assuming direct connection "
975 "to switch\n", ndev->name);
976 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
977 phy_id = 0;
980 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
981 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
982 fep->phy_interface);
983 if (IS_ERR(phy_dev)) {
984 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
985 return PTR_ERR(phy_dev);
988 /* mask with MAC supported features */
989 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
990 phy_dev->supported &= PHY_GBIT_FEATURES;
991 else
992 phy_dev->supported &= PHY_BASIC_FEATURES;
994 phy_dev->advertising = phy_dev->supported;
996 fep->phy_dev = phy_dev;
997 fep->link = 0;
998 fep->full_duplex = 0;
1000 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
1001 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
1002 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1003 fep->phy_dev->irq);
1005 return 0;
1008 static int fec_enet_mii_init(struct platform_device *pdev)
1010 static struct mii_bus *fec0_mii_bus;
1011 struct net_device *ndev = platform_get_drvdata(pdev);
1012 struct fec_enet_private *fep = netdev_priv(ndev);
1013 const struct platform_device_id *id_entry =
1014 platform_get_device_id(fep->pdev);
1015 int err = -ENXIO, i;
1018 * The dual fec interfaces are not equivalent with enet-mac.
1019 * Here are the differences:
1021 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1022 * - fec0 acts as the 1588 time master while fec1 is slave
1023 * - external phys can only be configured by fec0
1025 * That is to say fec1 can not work independently. It only works
1026 * when fec0 is working. The reason behind this design is that the
1027 * second interface is added primarily for Switch mode.
1029 * Because of the last point above, both phys are attached on fec0
1030 * mdio interface in board design, and need to be configured by
1031 * fec0 mii_bus.
1033 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id > 0) {
1034 /* fec1 uses fec0 mii_bus */
1035 fep->mii_bus = fec0_mii_bus;
1036 return 0;
1039 fep->mii_timeout = 0;
1042 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1044 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1045 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1046 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1047 * document.
1049 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000);
1050 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1051 fep->phy_speed--;
1052 fep->phy_speed <<= 1;
1053 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1055 fep->mii_bus = mdiobus_alloc();
1056 if (fep->mii_bus == NULL) {
1057 err = -ENOMEM;
1058 goto err_out;
1061 fep->mii_bus->name = "fec_enet_mii_bus";
1062 fep->mii_bus->read = fec_enet_mdio_read;
1063 fep->mii_bus->write = fec_enet_mdio_write;
1064 fep->mii_bus->reset = fec_enet_mdio_reset;
1065 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
1066 fep->mii_bus->priv = fep;
1067 fep->mii_bus->parent = &pdev->dev;
1069 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1070 if (!fep->mii_bus->irq) {
1071 err = -ENOMEM;
1072 goto err_out_free_mdiobus;
1075 for (i = 0; i < PHY_MAX_ADDR; i++)
1076 fep->mii_bus->irq[i] = PHY_POLL;
1078 if (mdiobus_register(fep->mii_bus))
1079 goto err_out_free_mdio_irq;
1081 /* save fec0 mii_bus */
1082 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1083 fec0_mii_bus = fep->mii_bus;
1085 return 0;
1087 err_out_free_mdio_irq:
1088 kfree(fep->mii_bus->irq);
1089 err_out_free_mdiobus:
1090 mdiobus_free(fep->mii_bus);
1091 err_out:
1092 return err;
1095 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1097 if (fep->phy_dev)
1098 phy_disconnect(fep->phy_dev);
1099 mdiobus_unregister(fep->mii_bus);
1100 kfree(fep->mii_bus->irq);
1101 mdiobus_free(fep->mii_bus);
1104 static int fec_enet_get_settings(struct net_device *ndev,
1105 struct ethtool_cmd *cmd)
1107 struct fec_enet_private *fep = netdev_priv(ndev);
1108 struct phy_device *phydev = fep->phy_dev;
1110 if (!phydev)
1111 return -ENODEV;
1113 return phy_ethtool_gset(phydev, cmd);
1116 static int fec_enet_set_settings(struct net_device *ndev,
1117 struct ethtool_cmd *cmd)
1119 struct fec_enet_private *fep = netdev_priv(ndev);
1120 struct phy_device *phydev = fep->phy_dev;
1122 if (!phydev)
1123 return -ENODEV;
1125 return phy_ethtool_sset(phydev, cmd);
1128 static void fec_enet_get_drvinfo(struct net_device *ndev,
1129 struct ethtool_drvinfo *info)
1131 struct fec_enet_private *fep = netdev_priv(ndev);
1133 strcpy(info->driver, fep->pdev->dev.driver->name);
1134 strcpy(info->version, "Revision: 1.0");
1135 strcpy(info->bus_info, dev_name(&ndev->dev));
1138 static struct ethtool_ops fec_enet_ethtool_ops = {
1139 .get_settings = fec_enet_get_settings,
1140 .set_settings = fec_enet_set_settings,
1141 .get_drvinfo = fec_enet_get_drvinfo,
1142 .get_link = ethtool_op_get_link,
1145 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1147 struct fec_enet_private *fep = netdev_priv(ndev);
1148 struct phy_device *phydev = fep->phy_dev;
1150 if (!netif_running(ndev))
1151 return -EINVAL;
1153 if (!phydev)
1154 return -ENODEV;
1156 return phy_mii_ioctl(phydev, rq, cmd);
1159 static void fec_enet_free_buffers(struct net_device *ndev)
1161 struct fec_enet_private *fep = netdev_priv(ndev);
1162 int i;
1163 struct sk_buff *skb;
1164 struct bufdesc *bdp;
1166 bdp = fep->rx_bd_base;
1167 for (i = 0; i < RX_RING_SIZE; i++) {
1168 skb = fep->rx_skbuff[i];
1170 if (bdp->cbd_bufaddr)
1171 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1172 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1173 if (skb)
1174 dev_kfree_skb(skb);
1175 bdp++;
1178 bdp = fep->tx_bd_base;
1179 for (i = 0; i < TX_RING_SIZE; i++)
1180 kfree(fep->tx_bounce[i]);
1183 static int fec_enet_alloc_buffers(struct net_device *ndev)
1185 struct fec_enet_private *fep = netdev_priv(ndev);
1186 int i;
1187 struct sk_buff *skb;
1188 struct bufdesc *bdp;
1190 bdp = fep->rx_bd_base;
1191 for (i = 0; i < RX_RING_SIZE; i++) {
1192 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1193 if (!skb) {
1194 fec_enet_free_buffers(ndev);
1195 return -ENOMEM;
1197 fep->rx_skbuff[i] = skb;
1199 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1200 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1201 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1202 bdp++;
1205 /* Set the last buffer to wrap. */
1206 bdp--;
1207 bdp->cbd_sc |= BD_SC_WRAP;
1209 bdp = fep->tx_bd_base;
1210 for (i = 0; i < TX_RING_SIZE; i++) {
1211 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1213 bdp->cbd_sc = 0;
1214 bdp->cbd_bufaddr = 0;
1215 bdp++;
1218 /* Set the last buffer to wrap. */
1219 bdp--;
1220 bdp->cbd_sc |= BD_SC_WRAP;
1222 return 0;
1225 static int
1226 fec_enet_open(struct net_device *ndev)
1228 struct fec_enet_private *fep = netdev_priv(ndev);
1229 int ret;
1231 /* I should reset the ring buffers here, but I don't yet know
1232 * a simple way to do that.
1235 ret = fec_enet_alloc_buffers(ndev);
1236 if (ret)
1237 return ret;
1239 /* Probe and connect to PHY when open the interface */
1240 ret = fec_enet_mii_probe(ndev);
1241 if (ret) {
1242 fec_enet_free_buffers(ndev);
1243 return ret;
1245 phy_start(fep->phy_dev);
1246 netif_start_queue(ndev);
1247 fep->opened = 1;
1248 return 0;
1251 static int
1252 fec_enet_close(struct net_device *ndev)
1254 struct fec_enet_private *fep = netdev_priv(ndev);
1256 /* Don't know what to do yet. */
1257 fep->opened = 0;
1258 netif_stop_queue(ndev);
1259 fec_stop(ndev);
1261 if (fep->phy_dev) {
1262 phy_stop(fep->phy_dev);
1263 phy_disconnect(fep->phy_dev);
1266 fec_enet_free_buffers(ndev);
1268 return 0;
1271 /* Set or clear the multicast filter for this adaptor.
1272 * Skeleton taken from sunlance driver.
1273 * The CPM Ethernet implementation allows Multicast as well as individual
1274 * MAC address filtering. Some of the drivers check to make sure it is
1275 * a group multicast address, and discard those that are not. I guess I
1276 * will do the same for now, but just remove the test if you want
1277 * individual filtering as well (do the upper net layers want or support
1278 * this kind of feature?).
1281 #define HASH_BITS 6 /* #bits in hash */
1282 #define CRC32_POLY 0xEDB88320
1284 static void set_multicast_list(struct net_device *ndev)
1286 struct fec_enet_private *fep = netdev_priv(ndev);
1287 struct netdev_hw_addr *ha;
1288 unsigned int i, bit, data, crc, tmp;
1289 unsigned char hash;
1291 if (ndev->flags & IFF_PROMISC) {
1292 tmp = readl(fep->hwp + FEC_R_CNTRL);
1293 tmp |= 0x8;
1294 writel(tmp, fep->hwp + FEC_R_CNTRL);
1295 return;
1298 tmp = readl(fep->hwp + FEC_R_CNTRL);
1299 tmp &= ~0x8;
1300 writel(tmp, fep->hwp + FEC_R_CNTRL);
1302 if (ndev->flags & IFF_ALLMULTI) {
1303 /* Catch all multicast addresses, so set the
1304 * filter to all 1's
1306 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1307 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1309 return;
1312 /* Clear filter and add the addresses in hash register
1314 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1315 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1317 netdev_for_each_mc_addr(ha, ndev) {
1318 /* calculate crc32 value of mac address */
1319 crc = 0xffffffff;
1321 for (i = 0; i < ndev->addr_len; i++) {
1322 data = ha->addr[i];
1323 for (bit = 0; bit < 8; bit++, data >>= 1) {
1324 crc = (crc >> 1) ^
1325 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1329 /* only upper 6 bits (HASH_BITS) are used
1330 * which point to specific bit in he hash registers
1332 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1334 if (hash > 31) {
1335 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1336 tmp |= 1 << (hash - 32);
1337 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1338 } else {
1339 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1340 tmp |= 1 << hash;
1341 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1346 /* Set a MAC change in hardware. */
1347 static int
1348 fec_set_mac_address(struct net_device *ndev, void *p)
1350 struct fec_enet_private *fep = netdev_priv(ndev);
1351 struct sockaddr *addr = p;
1353 if (!is_valid_ether_addr(addr->sa_data))
1354 return -EADDRNOTAVAIL;
1356 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1358 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1359 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1360 fep->hwp + FEC_ADDR_LOW);
1361 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1362 fep->hwp + FEC_ADDR_HIGH);
1363 return 0;
1366 static const struct net_device_ops fec_netdev_ops = {
1367 .ndo_open = fec_enet_open,
1368 .ndo_stop = fec_enet_close,
1369 .ndo_start_xmit = fec_enet_start_xmit,
1370 .ndo_set_rx_mode = set_multicast_list,
1371 .ndo_change_mtu = eth_change_mtu,
1372 .ndo_validate_addr = eth_validate_addr,
1373 .ndo_tx_timeout = fec_timeout,
1374 .ndo_set_mac_address = fec_set_mac_address,
1375 .ndo_do_ioctl = fec_enet_ioctl,
1379 * XXX: We need to clean up on failure exits here.
1382 static int fec_enet_init(struct net_device *ndev)
1384 struct fec_enet_private *fep = netdev_priv(ndev);
1385 struct bufdesc *cbd_base;
1386 struct bufdesc *bdp;
1387 int i;
1389 /* Allocate memory for buffer descriptors. */
1390 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1391 GFP_KERNEL);
1392 if (!cbd_base) {
1393 printk("FEC: allocate descriptor memory failed?\n");
1394 return -ENOMEM;
1397 spin_lock_init(&fep->hw_lock);
1399 fep->netdev = ndev;
1401 /* Get the Ethernet address */
1402 fec_get_mac(ndev);
1404 /* Set receive and transmit descriptor base. */
1405 fep->rx_bd_base = cbd_base;
1406 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1408 /* The FEC Ethernet specific entries in the device structure */
1409 ndev->watchdog_timeo = TX_TIMEOUT;
1410 ndev->netdev_ops = &fec_netdev_ops;
1411 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1413 /* Initialize the receive buffer descriptors. */
1414 bdp = fep->rx_bd_base;
1415 for (i = 0; i < RX_RING_SIZE; i++) {
1417 /* Initialize the BD for every fragment in the page. */
1418 bdp->cbd_sc = 0;
1419 bdp++;
1422 /* Set the last buffer to wrap */
1423 bdp--;
1424 bdp->cbd_sc |= BD_SC_WRAP;
1426 /* ...and the same for transmit */
1427 bdp = fep->tx_bd_base;
1428 for (i = 0; i < TX_RING_SIZE; i++) {
1430 /* Initialize the BD for every fragment in the page. */
1431 bdp->cbd_sc = 0;
1432 bdp->cbd_bufaddr = 0;
1433 bdp++;
1436 /* Set the last buffer to wrap */
1437 bdp--;
1438 bdp->cbd_sc |= BD_SC_WRAP;
1440 fec_restart(ndev, 0);
1442 return 0;
1445 #ifdef CONFIG_OF
1446 static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1448 struct device_node *np = pdev->dev.of_node;
1450 if (np)
1451 return of_get_phy_mode(np);
1453 return -ENODEV;
1456 static void __devinit fec_reset_phy(struct platform_device *pdev)
1458 int err, phy_reset;
1459 struct device_node *np = pdev->dev.of_node;
1461 if (!np)
1462 return;
1464 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1465 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
1466 if (err) {
1467 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1468 return;
1470 msleep(1);
1471 gpio_set_value(phy_reset, 1);
1473 #else /* CONFIG_OF */
1474 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1476 return -ENODEV;
1479 static inline void fec_reset_phy(struct platform_device *pdev)
1482 * In case of platform probe, the reset has been done
1483 * by machine code.
1486 #endif /* CONFIG_OF */
1488 static int __devinit
1489 fec_probe(struct platform_device *pdev)
1491 struct fec_enet_private *fep;
1492 struct fec_platform_data *pdata;
1493 struct net_device *ndev;
1494 int i, irq, ret = 0;
1495 struct resource *r;
1496 const struct of_device_id *of_id;
1498 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1499 if (of_id)
1500 pdev->id_entry = of_id->data;
1502 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1503 if (!r)
1504 return -ENXIO;
1506 r = request_mem_region(r->start, resource_size(r), pdev->name);
1507 if (!r)
1508 return -EBUSY;
1510 /* Init network device */
1511 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1512 if (!ndev) {
1513 ret = -ENOMEM;
1514 goto failed_alloc_etherdev;
1517 SET_NETDEV_DEV(ndev, &pdev->dev);
1519 /* setup board info structure */
1520 fep = netdev_priv(ndev);
1522 fep->hwp = ioremap(r->start, resource_size(r));
1523 fep->pdev = pdev;
1525 if (!fep->hwp) {
1526 ret = -ENOMEM;
1527 goto failed_ioremap;
1530 platform_set_drvdata(pdev, ndev);
1532 ret = fec_get_phy_mode_dt(pdev);
1533 if (ret < 0) {
1534 pdata = pdev->dev.platform_data;
1535 if (pdata)
1536 fep->phy_interface = pdata->phy;
1537 else
1538 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1539 } else {
1540 fep->phy_interface = ret;
1543 fec_reset_phy(pdev);
1545 for (i = 0; i < FEC_IRQ_NUM; i++) {
1546 irq = platform_get_irq(pdev, i);
1547 if (i && irq < 0)
1548 break;
1549 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1550 if (ret) {
1551 while (--i >= 0) {
1552 irq = platform_get_irq(pdev, i);
1553 free_irq(irq, ndev);
1555 goto failed_irq;
1559 fep->clk = clk_get(&pdev->dev, "fec_clk");
1560 if (IS_ERR(fep->clk)) {
1561 ret = PTR_ERR(fep->clk);
1562 goto failed_clk;
1564 clk_enable(fep->clk);
1566 ret = fec_enet_init(ndev);
1567 if (ret)
1568 goto failed_init;
1570 ret = fec_enet_mii_init(pdev);
1571 if (ret)
1572 goto failed_mii_init;
1574 /* Carrier starts down, phylib will bring it up */
1575 netif_carrier_off(ndev);
1577 ret = register_netdev(ndev);
1578 if (ret)
1579 goto failed_register;
1581 return 0;
1583 failed_register:
1584 fec_enet_mii_remove(fep);
1585 failed_mii_init:
1586 failed_init:
1587 clk_disable(fep->clk);
1588 clk_put(fep->clk);
1589 failed_clk:
1590 for (i = 0; i < FEC_IRQ_NUM; i++) {
1591 irq = platform_get_irq(pdev, i);
1592 if (irq > 0)
1593 free_irq(irq, ndev);
1595 failed_irq:
1596 iounmap(fep->hwp);
1597 failed_ioremap:
1598 free_netdev(ndev);
1599 failed_alloc_etherdev:
1600 release_mem_region(r->start, resource_size(r));
1602 return ret;
1605 static int __devexit
1606 fec_drv_remove(struct platform_device *pdev)
1608 struct net_device *ndev = platform_get_drvdata(pdev);
1609 struct fec_enet_private *fep = netdev_priv(ndev);
1610 struct resource *r;
1612 fec_stop(ndev);
1613 fec_enet_mii_remove(fep);
1614 clk_disable(fep->clk);
1615 clk_put(fep->clk);
1616 iounmap(fep->hwp);
1617 unregister_netdev(ndev);
1618 free_netdev(ndev);
1620 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1621 BUG_ON(!r);
1622 release_mem_region(r->start, resource_size(r));
1624 platform_set_drvdata(pdev, NULL);
1626 return 0;
1629 #ifdef CONFIG_PM
1630 static int
1631 fec_suspend(struct device *dev)
1633 struct net_device *ndev = dev_get_drvdata(dev);
1634 struct fec_enet_private *fep = netdev_priv(ndev);
1636 if (netif_running(ndev)) {
1637 fec_stop(ndev);
1638 netif_device_detach(ndev);
1640 clk_disable(fep->clk);
1642 return 0;
1645 static int
1646 fec_resume(struct device *dev)
1648 struct net_device *ndev = dev_get_drvdata(dev);
1649 struct fec_enet_private *fep = netdev_priv(ndev);
1651 clk_enable(fep->clk);
1652 if (netif_running(ndev)) {
1653 fec_restart(ndev, fep->full_duplex);
1654 netif_device_attach(ndev);
1657 return 0;
1660 static const struct dev_pm_ops fec_pm_ops = {
1661 .suspend = fec_suspend,
1662 .resume = fec_resume,
1663 .freeze = fec_suspend,
1664 .thaw = fec_resume,
1665 .poweroff = fec_suspend,
1666 .restore = fec_resume,
1668 #endif
1670 static struct platform_driver fec_driver = {
1671 .driver = {
1672 .name = DRIVER_NAME,
1673 .owner = THIS_MODULE,
1674 #ifdef CONFIG_PM
1675 .pm = &fec_pm_ops,
1676 #endif
1677 .of_match_table = fec_dt_ids,
1679 .id_table = fec_devtype,
1680 .probe = fec_probe,
1681 .remove = __devexit_p(fec_drv_remove),
1684 static int __init
1685 fec_enet_module_init(void)
1687 printk(KERN_INFO "FEC Ethernet Driver\n");
1689 return platform_driver_register(&fec_driver);
1692 static void __exit
1693 fec_enet_cleanup(void)
1695 platform_driver_unregister(&fec_driver);
1698 module_exit(fec_enet_cleanup);
1699 module_init(fec_enet_module_init);
1701 MODULE_LICENSE("GPL");