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ALSA: snd-usb-us122l: Delete calls to preempt_disable
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / r8169.c
blob3ebe50c27cec2bdc965a7bb8693240250eb59a7f
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pci-aspm.h>
27
28 #include <asm/system.h>
29 #include <asm/io.h>
30 #include <asm/irq.h>
31
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
35
36 #ifdef RTL8169_DEBUG
37 #define assert(expr) \
38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
41 }
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #else
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
48
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit = 32;
58
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
61
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
80
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
84
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
92
93 enum mac_version {
94 RTL_GIGA_MAC_NONE = 0x00,
95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
122 };
123
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
127 static const struct {
128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
159 };
160 #undef _R
161
162 enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166 };
167
168 static void rtl_hw_start_8169(struct net_device *);
169 static void rtl_hw_start_8168(struct net_device *);
170 static void rtl_hw_start_8101(struct net_device *);
171
172 static struct pci_device_id rtl8169_pci_tbl[] = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
185 {0,},
186 };
187
188 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
190 /*
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
193 * rtl8169_open()
194 */
195 static int rx_copybreak = 16383;
196 static int use_dac;
197 static struct {
198 u32 msg_enable;
199 } debug = { -1 };
200
201 enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAC4 = 4,
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec,
236 FuncEvent = 0xf0,
237 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8,
239 FuncForceEvent = 0xfc,
240 };
241
242 enum rtl8110_registers {
243 TBICSR = 0x64,
244 TBI_ANAR = 0x68,
245 TBI_LPAR = 0x6a,
246 };
247
248 enum rtl8168_8101_registers {
249 CSIDR = 0x64,
250 CSIAR = 0x68,
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0f
254 #define CSIAR_BYTE_ENABLE_SHIFT 12
255 #define CSIAR_ADDR_MASK 0x0fff
256
257 EPHYAR = 0x80,
258 #define EPHYAR_FLAG 0x80000000
259 #define EPHYAR_WRITE_CMD 0x80000000
260 #define EPHYAR_REG_MASK 0x1f
261 #define EPHYAR_REG_SHIFT 16
262 #define EPHYAR_DATA_MASK 0xffff
263 DBG_REG = 0xd1,
264 #define FIX_NAK_1 (1 << 4)
265 #define FIX_NAK_2 (1 << 3)
266 EFUSEAR = 0xdc,
267 #define EFUSEAR_FLAG 0x80000000
268 #define EFUSEAR_WRITE_CMD 0x80000000
269 #define EFUSEAR_READ_CMD 0x00000000
270 #define EFUSEAR_REG_MASK 0x03ff
271 #define EFUSEAR_REG_SHIFT 8
272 #define EFUSEAR_DATA_MASK 0xff
273 };
274
275 enum rtl_register_content {
276 /* InterruptStatusBits */
277 SYSErr = 0x8000,
278 PCSTimeout = 0x4000,
279 SWInt = 0x0100,
280 TxDescUnavail = 0x0080,
281 RxFIFOOver = 0x0040,
282 LinkChg = 0x0020,
283 RxOverflow = 0x0010,
284 TxErr = 0x0008,
285 TxOK = 0x0004,
286 RxErr = 0x0002,
287 RxOK = 0x0001,
288
289 /* RxStatusDesc */
290 RxFOVF = (1 << 23),
291 RxRWT = (1 << 22),
292 RxRES = (1 << 21),
293 RxRUNT = (1 << 20),
294 RxCRC = (1 << 19),
295
296 /* ChipCmdBits */
297 CmdReset = 0x10,
298 CmdRxEnb = 0x08,
299 CmdTxEnb = 0x04,
300 RxBufEmpty = 0x01,
301
302 /* TXPoll register p.5 */
303 HPQ = 0x80, /* Poll cmd on the high prio queue */
304 NPQ = 0x40, /* Poll cmd on the low prio queue */
305 FSWInt = 0x01, /* Forced software interrupt */
306
307 /* Cfg9346Bits */
308 Cfg9346_Lock = 0x00,
309 Cfg9346_Unlock = 0xc0,
310
311 /* rx_mode_bits */
312 AcceptErr = 0x20,
313 AcceptRunt = 0x10,
314 AcceptBroadcast = 0x08,
315 AcceptMulticast = 0x04,
316 AcceptMyPhys = 0x02,
317 AcceptAllPhys = 0x01,
318
319 /* RxConfigBits */
320 RxCfgFIFOShift = 13,
321 RxCfgDMAShift = 8,
322
323 /* TxConfigBits */
324 TxInterFrameGapShift = 24,
325 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
326
327 /* Config1 register p.24 */
328 LEDS1 = (1 << 7),
329 LEDS0 = (1 << 6),
330 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
331 Speed_down = (1 << 4),
332 MEMMAP = (1 << 3),
333 IOMAP = (1 << 2),
334 VPD = (1 << 1),
335 PMEnable = (1 << 0), /* Power Management Enable */
336
337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz = 0x01,
339 PCI_Clock_33MHz = 0x00,
340
341 /* Config3 register p.25 */
342 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
344 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
345
346 /* Config5 register p.27 */
347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake = (1 << 1), /* LanWake enable/disable */
351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
352
353 /* TBICSR p.28 */
354 TBIReset = 0x80000000,
355 TBILoopback = 0x40000000,
356 TBINwEnable = 0x20000000,
357 TBINwRestart = 0x10000000,
358 TBILinkOk = 0x02000000,
359 TBINwComplete = 0x01000000,
360
361 /* CPlusCmd p.31 */
362 EnableBist = (1 << 15), // 8168 8101
363 Mac_dbgo_oe = (1 << 14), // 8168 8101
364 Normal_mode = (1 << 13), // unused
365 Force_half_dup = (1 << 12), // 8168 8101
366 Force_rxflow_en = (1 << 11), // 8168 8101
367 Force_txflow_en = (1 << 10), // 8168 8101
368 Cxpl_dbg_sel = (1 << 9), // 8168 8101
369 ASF = (1 << 8), // 8168 8101
370 PktCntrDisable = (1 << 7), // 8168 8101
371 Mac_dbgo_sel = 0x001c, // 8168
372 RxVlan = (1 << 6),
373 RxChkSum = (1 << 5),
374 PCIDAC = (1 << 4),
375 PCIMulRW = (1 << 3),
376 INTT_0 = 0x0000, // 8168
377 INTT_1 = 0x0001, // 8168
378 INTT_2 = 0x0002, // 8168
379 INTT_3 = 0x0003, // 8168
380
381 /* rtl8169_PHYstatus */
382 TBI_Enable = 0x80,
383 TxFlowCtrl = 0x40,
384 RxFlowCtrl = 0x20,
385 _1000bpsF = 0x10,
386 _100bps = 0x08,
387 _10bps = 0x04,
388 LinkStatus = 0x02,
389 FullDup = 0x01,
390
391 /* _TBICSRBit */
392 TBILinkOK = 0x02000000,
393
394 /* DumpCounterCommand */
395 CounterDump = 0x8,
396 };
397
398 enum desc_status_bit {
399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
403
404 /* Tx private */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
412
413 /* Rx private */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
416
417 #define RxProtoUDP (PID1)
418 #define RxProtoTCP (PID0)
419 #define RxProtoIP (PID1 | PID0)
420 #define RxProtoMask RxProtoIP
421
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
426 };
427
428 #define RsvdMask 0x3fffc000
429
430 struct TxDesc {
431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
434 };
435
436 struct RxDesc {
437 __le32 opts1;
438 __le32 opts2;
439 __le64 addr;
440 };
441
442 struct ring_info {
443 struct sk_buff *skb;
444 u32 len;
445 u8 __pad[sizeof(void *) - sizeof(u32)];
446 };
447
448 enum features {
449 RTL_FEATURE_WOL = (1 << 0),
450 RTL_FEATURE_MSI = (1 << 1),
451 RTL_FEATURE_GMII = (1 << 2),
452 };
453
454 struct rtl8169_counters {
455 __le64 tx_packets;
456 __le64 rx_packets;
457 __le64 tx_errors;
458 __le32 rx_errors;
459 __le16 rx_missed;
460 __le16 align_errors;
461 __le32 tx_one_collision;
462 __le32 tx_multi_collision;
463 __le64 rx_unicast;
464 __le64 rx_broadcast;
465 __le32 rx_multicast;
466 __le16 tx_aborted;
467 __le16 tx_underun;
468 };
469
470 struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */
473 struct net_device *dev;
474 struct napi_struct napi;
475 spinlock_t lock; /* spin lock flag */
476 u32 msg_enable;
477 int chipset;
478 int mac_version;
479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
481 u32 dirty_rx;
482 u32 dirty_tx;
483 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
489 unsigned align;
490 unsigned rx_buf_sz;
491 struct timer_list timer;
492 u16 cp_cmd;
493 u16 intr_event;
494 u16 napi_event;
495 u16 intr_mask;
496 int phy_1000_ctrl_reg;
497 #ifdef CONFIG_R8169_VLAN
498 struct vlan_group *vlgrp;
499 #endif
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
501 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
502 void (*phy_reset_enable)(void __iomem *);
503 void (*hw_start)(struct net_device *);
504 unsigned int (*phy_reset_pending)(void __iomem *);
505 unsigned int (*link_ok)(void __iomem *);
506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
507 int pcie_cap;
508 struct delayed_work task;
509 unsigned features;
510
511 struct mii_if_info mii;
512 struct rtl8169_counters counters;
513 };
514
515 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
516 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
517 module_param(rx_copybreak, int, 0);
518 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
519 module_param(use_dac, int, 0);
520 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
521 module_param_named(debug, debug.msg_enable, int, 0);
522 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
523 MODULE_LICENSE("GPL");
524 MODULE_VERSION(RTL8169_VERSION);
525
526 static int rtl8169_open(struct net_device *dev);
527 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
528 struct net_device *dev);
529 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
530 static int rtl8169_init_ring(struct net_device *dev);
531 static void rtl_hw_start(struct net_device *dev);
532 static int rtl8169_close(struct net_device *dev);
533 static void rtl_set_rx_mode(struct net_device *dev);
534 static void rtl8169_tx_timeout(struct net_device *dev);
535 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
536 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
537 void __iomem *, u32 budget);
538 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
539 static void rtl8169_down(struct net_device *dev);
540 static void rtl8169_rx_clear(struct rtl8169_private *tp);
541 static int rtl8169_poll(struct napi_struct *napi, int budget);
542
543 static const unsigned int rtl8169_rx_config =
544 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
545
546 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
547 {
548 int i;
549
550 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
551
552 for (i = 20; i > 0; i--) {
553 /*
554 * Check if the RTL8169 has completed writing to the specified
555 * MII register.
556 */
557 if (!(RTL_R32(PHYAR) & 0x80000000))
558 break;
559 udelay(25);
560 }
561 /*
562 * According to hardware specs a 20us delay is required after write
563 * complete indication, but before sending next command.
564 */
565 udelay(20);
566 }
567
568 static int mdio_read(void __iomem *ioaddr, int reg_addr)
569 {
570 int i, value = -1;
571
572 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
573
574 for (i = 20; i > 0; i--) {
575 /*
576 * Check if the RTL8169 has completed retrieving data from
577 * the specified MII register.
578 */
579 if (RTL_R32(PHYAR) & 0x80000000) {
580 value = RTL_R32(PHYAR) & 0xffff;
581 break;
582 }
583 udelay(25);
584 }
585 /*
586 * According to hardware specs a 20us delay is required after read
587 * complete indication, but before sending next command.
588 */
589 udelay(20);
590
591 return value;
592 }
593
594 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
595 {
596 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
597 }
598
599 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
600 {
601 int val;
602
603 val = mdio_read(ioaddr, reg_addr);
604 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
605 }
606
607 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
608 int val)
609 {
610 struct rtl8169_private *tp = netdev_priv(dev);
611 void __iomem *ioaddr = tp->mmio_addr;
612
613 mdio_write(ioaddr, location, val);
614 }
615
616 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
617 {
618 struct rtl8169_private *tp = netdev_priv(dev);
619 void __iomem *ioaddr = tp->mmio_addr;
620
621 return mdio_read(ioaddr, location);
622 }
623
624 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
625 {
626 unsigned int i;
627
628 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
629 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
630
631 for (i = 0; i < 100; i++) {
632 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
633 break;
634 udelay(10);
635 }
636 }
637
638 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
639 {
640 u16 value = 0xffff;
641 unsigned int i;
642
643 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
644
645 for (i = 0; i < 100; i++) {
646 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
647 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
648 break;
649 }
650 udelay(10);
651 }
652
653 return value;
654 }
655
656 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
657 {
658 unsigned int i;
659
660 RTL_W32(CSIDR, value);
661 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
662 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
663
664 for (i = 0; i < 100; i++) {
665 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
666 break;
667 udelay(10);
668 }
669 }
670
671 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
672 {
673 u32 value = ~0x00;
674 unsigned int i;
675
676 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
677 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
678
679 for (i = 0; i < 100; i++) {
680 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
681 value = RTL_R32(CSIDR);
682 break;
683 }
684 udelay(10);
685 }
686
687 return value;
688 }
689
690 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
691 {
692 u8 value = 0xff;
693 unsigned int i;
694
695 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
696
697 for (i = 0; i < 300; i++) {
698 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
699 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
700 break;
701 }
702 udelay(100);
703 }
704
705 return value;
706 }
707
708 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
709 {
710 RTL_W16(IntrMask, 0x0000);
711
712 RTL_W16(IntrStatus, 0xffff);
713 }
714
715 static void rtl8169_asic_down(void __iomem *ioaddr)
716 {
717 RTL_W8(ChipCmd, 0x00);
718 rtl8169_irq_mask_and_ack(ioaddr);
719 RTL_R16(CPlusCmd);
720 }
721
722 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
723 {
724 return RTL_R32(TBICSR) & TBIReset;
725 }
726
727 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
728 {
729 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
730 }
731
732 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
733 {
734 return RTL_R32(TBICSR) & TBILinkOk;
735 }
736
737 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
738 {
739 return RTL_R8(PHYstatus) & LinkStatus;
740 }
741
742 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
743 {
744 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
745 }
746
747 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
748 {
749 unsigned int val;
750
751 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
752 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
753 }
754
755 static void rtl8169_check_link_status(struct net_device *dev,
756 struct rtl8169_private *tp,
757 void __iomem *ioaddr)
758 {
759 unsigned long flags;
760
761 spin_lock_irqsave(&tp->lock, flags);
762 if (tp->link_ok(ioaddr)) {
763 netif_carrier_on(dev);
764 if (netif_msg_ifup(tp))
765 printk(KERN_INFO PFX "%s: link up\n", dev->name);
766 } else {
767 if (netif_msg_ifdown(tp))
768 printk(KERN_INFO PFX "%s: link down\n", dev->name);
769 netif_carrier_off(dev);
770 }
771 spin_unlock_irqrestore(&tp->lock, flags);
772 }
773
774 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
775 {
776 struct rtl8169_private *tp = netdev_priv(dev);
777 void __iomem *ioaddr = tp->mmio_addr;
778 u8 options;
779
780 wol->wolopts = 0;
781
782 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
783 wol->supported = WAKE_ANY;
784
785 spin_lock_irq(&tp->lock);
786
787 options = RTL_R8(Config1);
788 if (!(options & PMEnable))
789 goto out_unlock;
790
791 options = RTL_R8(Config3);
792 if (options & LinkUp)
793 wol->wolopts |= WAKE_PHY;
794 if (options & MagicPacket)
795 wol->wolopts |= WAKE_MAGIC;
796
797 options = RTL_R8(Config5);
798 if (options & UWF)
799 wol->wolopts |= WAKE_UCAST;
800 if (options & BWF)
801 wol->wolopts |= WAKE_BCAST;
802 if (options & MWF)
803 wol->wolopts |= WAKE_MCAST;
804
805 out_unlock:
806 spin_unlock_irq(&tp->lock);
807 }
808
809 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
810 {
811 struct rtl8169_private *tp = netdev_priv(dev);
812 void __iomem *ioaddr = tp->mmio_addr;
813 unsigned int i;
814 static struct {
815 u32 opt;
816 u16 reg;
817 u8 mask;
818 } cfg[] = {
819 { WAKE_ANY, Config1, PMEnable },
820 { WAKE_PHY, Config3, LinkUp },
821 { WAKE_MAGIC, Config3, MagicPacket },
822 { WAKE_UCAST, Config5, UWF },
823 { WAKE_BCAST, Config5, BWF },
824 { WAKE_MCAST, Config5, MWF },
825 { WAKE_ANY, Config5, LanWake }
826 };
827
828 spin_lock_irq(&tp->lock);
829
830 RTL_W8(Cfg9346, Cfg9346_Unlock);
831
832 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
833 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
834 if (wol->wolopts & cfg[i].opt)
835 options |= cfg[i].mask;
836 RTL_W8(cfg[i].reg, options);
837 }
838
839 RTL_W8(Cfg9346, Cfg9346_Lock);
840
841 if (wol->wolopts)
842 tp->features |= RTL_FEATURE_WOL;
843 else
844 tp->features &= ~RTL_FEATURE_WOL;
845 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
846
847 spin_unlock_irq(&tp->lock);
848
849 return 0;
850 }
851
852 static void rtl8169_get_drvinfo(struct net_device *dev,
853 struct ethtool_drvinfo *info)
854 {
855 struct rtl8169_private *tp = netdev_priv(dev);
856
857 strcpy(info->driver, MODULENAME);
858 strcpy(info->version, RTL8169_VERSION);
859 strcpy(info->bus_info, pci_name(tp->pci_dev));
860 }
861
862 static int rtl8169_get_regs_len(struct net_device *dev)
863 {
864 return R8169_REGS_SIZE;
865 }
866
867 static int rtl8169_set_speed_tbi(struct net_device *dev,
868 u8 autoneg, u16 speed, u8 duplex)
869 {
870 struct rtl8169_private *tp = netdev_priv(dev);
871 void __iomem *ioaddr = tp->mmio_addr;
872 int ret = 0;
873 u32 reg;
874
875 reg = RTL_R32(TBICSR);
876 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
877 (duplex == DUPLEX_FULL)) {
878 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
879 } else if (autoneg == AUTONEG_ENABLE)
880 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
881 else {
882 if (netif_msg_link(tp)) {
883 printk(KERN_WARNING "%s: "
884 "incorrect speed setting refused in TBI mode\n",
885 dev->name);
886 }
887 ret = -EOPNOTSUPP;
888 }
889
890 return ret;
891 }
892
893 static int rtl8169_set_speed_xmii(struct net_device *dev,
894 u8 autoneg, u16 speed, u8 duplex)
895 {
896 struct rtl8169_private *tp = netdev_priv(dev);
897 void __iomem *ioaddr = tp->mmio_addr;
898 int giga_ctrl, bmcr;
899
900 if (autoneg == AUTONEG_ENABLE) {
901 int auto_nego;
902
903 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
904 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
905 ADVERTISE_100HALF | ADVERTISE_100FULL);
906 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
907
908 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
909 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
910
911 /* The 8100e/8101e/8102e do Fast Ethernet only. */
912 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
913 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
914 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
915 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
916 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
917 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
918 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
919 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
920 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
921 } else if (netif_msg_link(tp)) {
922 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
923 dev->name);
924 }
925
926 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
927
928 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
929 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
930 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
931 /*
932 * Wake up the PHY.
933 * Vendor specific (0x1f) and reserved (0x0e) MII
934 * registers.
935 */
936 mdio_write(ioaddr, 0x1f, 0x0000);
937 mdio_write(ioaddr, 0x0e, 0x0000);
938 }
939
940 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
941 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
942 } else {
943 giga_ctrl = 0;
944
945 if (speed == SPEED_10)
946 bmcr = 0;
947 else if (speed == SPEED_100)
948 bmcr = BMCR_SPEED100;
949 else
950 return -EINVAL;
951
952 if (duplex == DUPLEX_FULL)
953 bmcr |= BMCR_FULLDPLX;
954
955 mdio_write(ioaddr, 0x1f, 0x0000);
956 }
957
958 tp->phy_1000_ctrl_reg = giga_ctrl;
959
960 mdio_write(ioaddr, MII_BMCR, bmcr);
961
962 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
963 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
964 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
965 mdio_write(ioaddr, 0x17, 0x2138);
966 mdio_write(ioaddr, 0x0e, 0x0260);
967 } else {
968 mdio_write(ioaddr, 0x17, 0x2108);
969 mdio_write(ioaddr, 0x0e, 0x0000);
970 }
971 }
972
973 return 0;
974 }
975
976 static int rtl8169_set_speed(struct net_device *dev,
977 u8 autoneg, u16 speed, u8 duplex)
978 {
979 struct rtl8169_private *tp = netdev_priv(dev);
980 int ret;
981
982 ret = tp->set_speed(dev, autoneg, speed, duplex);
983
984 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
985 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
986
987 return ret;
988 }
989
990 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
991 {
992 struct rtl8169_private *tp = netdev_priv(dev);
993 unsigned long flags;
994 int ret;
995
996 spin_lock_irqsave(&tp->lock, flags);
997 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
998 spin_unlock_irqrestore(&tp->lock, flags);
999
1000 return ret;
1001 }
1002
1003 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1004 {
1005 struct rtl8169_private *tp = netdev_priv(dev);
1006
1007 return tp->cp_cmd & RxChkSum;
1008 }
1009
1010 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1011 {
1012 struct rtl8169_private *tp = netdev_priv(dev);
1013 void __iomem *ioaddr = tp->mmio_addr;
1014 unsigned long flags;
1015
1016 spin_lock_irqsave(&tp->lock, flags);
1017
1018 if (data)
1019 tp->cp_cmd |= RxChkSum;
1020 else
1021 tp->cp_cmd &= ~RxChkSum;
1022
1023 RTL_W16(CPlusCmd, tp->cp_cmd);
1024 RTL_R16(CPlusCmd);
1025
1026 spin_unlock_irqrestore(&tp->lock, flags);
1027
1028 return 0;
1029 }
1030
1031 #ifdef CONFIG_R8169_VLAN
1032
1033 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1034 struct sk_buff *skb)
1035 {
1036 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1037 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1038 }
1039
1040 static void rtl8169_vlan_rx_register(struct net_device *dev,
1041 struct vlan_group *grp)
1042 {
1043 struct rtl8169_private *tp = netdev_priv(dev);
1044 void __iomem *ioaddr = tp->mmio_addr;
1045 unsigned long flags;
1046
1047 spin_lock_irqsave(&tp->lock, flags);
1048 tp->vlgrp = grp;
1049 /*
1050 * Do not disable RxVlan on 8110SCd.
1051 */
1052 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1053 tp->cp_cmd |= RxVlan;
1054 else
1055 tp->cp_cmd &= ~RxVlan;
1056 RTL_W16(CPlusCmd, tp->cp_cmd);
1057 RTL_R16(CPlusCmd);
1058 spin_unlock_irqrestore(&tp->lock, flags);
1059 }
1060
1061 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1062 struct sk_buff *skb)
1063 {
1064 u32 opts2 = le32_to_cpu(desc->opts2);
1065 struct vlan_group *vlgrp = tp->vlgrp;
1066 int ret;
1067
1068 if (vlgrp && (opts2 & RxVlanTag)) {
1069 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1070 ret = 0;
1071 } else
1072 ret = -1;
1073 desc->opts2 = 0;
1074 return ret;
1075 }
1076
1077 #else /* !CONFIG_R8169_VLAN */
1078
1079 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1080 struct sk_buff *skb)
1081 {
1082 return 0;
1083 }
1084
1085 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1086 struct sk_buff *skb)
1087 {
1088 return -1;
1089 }
1090
1091 #endif
1092
1093 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1094 {
1095 struct rtl8169_private *tp = netdev_priv(dev);
1096 void __iomem *ioaddr = tp->mmio_addr;
1097 u32 status;
1098
1099 cmd->supported =
1100 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1101 cmd->port = PORT_FIBRE;
1102 cmd->transceiver = XCVR_INTERNAL;
1103
1104 status = RTL_R32(TBICSR);
1105 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1106 cmd->autoneg = !!(status & TBINwEnable);
1107
1108 cmd->speed = SPEED_1000;
1109 cmd->duplex = DUPLEX_FULL; /* Always set */
1110
1111 return 0;
1112 }
1113
1114 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1115 {
1116 struct rtl8169_private *tp = netdev_priv(dev);
1117
1118 return mii_ethtool_gset(&tp->mii, cmd);
1119 }
1120
1121 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1122 {
1123 struct rtl8169_private *tp = netdev_priv(dev);
1124 unsigned long flags;
1125 int rc;
1126
1127 spin_lock_irqsave(&tp->lock, flags);
1128
1129 rc = tp->get_settings(dev, cmd);
1130
1131 spin_unlock_irqrestore(&tp->lock, flags);
1132 return rc;
1133 }
1134
1135 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1136 void *p)
1137 {
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139 unsigned long flags;
1140
1141 if (regs->len > R8169_REGS_SIZE)
1142 regs->len = R8169_REGS_SIZE;
1143
1144 spin_lock_irqsave(&tp->lock, flags);
1145 memcpy_fromio(p, tp->mmio_addr, regs->len);
1146 spin_unlock_irqrestore(&tp->lock, flags);
1147 }
1148
1149 static u32 rtl8169_get_msglevel(struct net_device *dev)
1150 {
1151 struct rtl8169_private *tp = netdev_priv(dev);
1152
1153 return tp->msg_enable;
1154 }
1155
1156 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1157 {
1158 struct rtl8169_private *tp = netdev_priv(dev);
1159
1160 tp->msg_enable = value;
1161 }
1162
1163 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1164 "tx_packets",
1165 "rx_packets",
1166 "tx_errors",
1167 "rx_errors",
1168 "rx_missed",
1169 "align_errors",
1170 "tx_single_collisions",
1171 "tx_multi_collisions",
1172 "unicast",
1173 "broadcast",
1174 "multicast",
1175 "tx_aborted",
1176 "tx_underrun",
1177 };
1178
1179 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1180 {
1181 switch (sset) {
1182 case ETH_SS_STATS:
1183 return ARRAY_SIZE(rtl8169_gstrings);
1184 default:
1185 return -EOPNOTSUPP;
1186 }
1187 }
1188
1189 static void rtl8169_update_counters(struct net_device *dev)
1190 {
1191 struct rtl8169_private *tp = netdev_priv(dev);
1192 void __iomem *ioaddr = tp->mmio_addr;
1193 struct rtl8169_counters *counters;
1194 dma_addr_t paddr;
1195 u32 cmd;
1196 int wait = 1000;
1197
1198 /*
1199 * Some chips are unable to dump tally counters when the receiver
1200 * is disabled.
1201 */
1202 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1203 return;
1204
1205 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1206 if (!counters)
1207 return;
1208
1209 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1210 cmd = (u64)paddr & DMA_BIT_MASK(32);
1211 RTL_W32(CounterAddrLow, cmd);
1212 RTL_W32(CounterAddrLow, cmd | CounterDump);
1213
1214 while (wait--) {
1215 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1216 /* copy updated counters */
1217 memcpy(&tp->counters, counters, sizeof(*counters));
1218 break;
1219 }
1220 udelay(10);
1221 }
1222
1223 RTL_W32(CounterAddrLow, 0);
1224 RTL_W32(CounterAddrHigh, 0);
1225
1226 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1227 }
1228
1229 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1230 struct ethtool_stats *stats, u64 *data)
1231 {
1232 struct rtl8169_private *tp = netdev_priv(dev);
1233
1234 ASSERT_RTNL();
1235
1236 rtl8169_update_counters(dev);
1237
1238 data[0] = le64_to_cpu(tp->counters.tx_packets);
1239 data[1] = le64_to_cpu(tp->counters.rx_packets);
1240 data[2] = le64_to_cpu(tp->counters.tx_errors);
1241 data[3] = le32_to_cpu(tp->counters.rx_errors);
1242 data[4] = le16_to_cpu(tp->counters.rx_missed);
1243 data[5] = le16_to_cpu(tp->counters.align_errors);
1244 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1245 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1246 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1247 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1248 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1249 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1250 data[12] = le16_to_cpu(tp->counters.tx_underun);
1251 }
1252
1253 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1254 {
1255 switch(stringset) {
1256 case ETH_SS_STATS:
1257 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1258 break;
1259 }
1260 }
1261
1262 static const struct ethtool_ops rtl8169_ethtool_ops = {
1263 .get_drvinfo = rtl8169_get_drvinfo,
1264 .get_regs_len = rtl8169_get_regs_len,
1265 .get_link = ethtool_op_get_link,
1266 .get_settings = rtl8169_get_settings,
1267 .set_settings = rtl8169_set_settings,
1268 .get_msglevel = rtl8169_get_msglevel,
1269 .set_msglevel = rtl8169_set_msglevel,
1270 .get_rx_csum = rtl8169_get_rx_csum,
1271 .set_rx_csum = rtl8169_set_rx_csum,
1272 .set_tx_csum = ethtool_op_set_tx_csum,
1273 .set_sg = ethtool_op_set_sg,
1274 .set_tso = ethtool_op_set_tso,
1275 .get_regs = rtl8169_get_regs,
1276 .get_wol = rtl8169_get_wol,
1277 .set_wol = rtl8169_set_wol,
1278 .get_strings = rtl8169_get_strings,
1279 .get_sset_count = rtl8169_get_sset_count,
1280 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1281 };
1282
1283 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1284 void __iomem *ioaddr)
1285 {
1286 /*
1287 * The driver currently handles the 8168Bf and the 8168Be identically
1288 * but they can be identified more specifically through the test below
1289 * if needed:
1290 *
1291 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1292 *
1293 * Same thing for the 8101Eb and the 8101Ec:
1294 *
1295 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1296 */
1297 const struct {
1298 u32 mask;
1299 u32 val;
1300 int mac_version;
1301 } mac_info[] = {
1302 /* 8168D family. */
1303 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1304 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1305 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1306 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1307
1308 /* 8168C family. */
1309 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1310 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1311 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1312 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1313 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1314 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1315 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1316 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1317 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1318
1319 /* 8168B family. */
1320 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1321 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1322 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1323 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1324
1325 /* 8101 family. */
1326 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1327 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1328 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1329 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1330 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1331 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1332 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1333 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1334 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1335 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1336 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1337 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1338 /* FIXME: where did these entries come from ? -- FR */
1339 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1340 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1341
1342 /* 8110 family. */
1343 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1344 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1345 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1346 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1347 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1348 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1349
1350 /* Catch-all */
1351 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1352 }, *p = mac_info;
1353 u32 reg;
1354
1355 reg = RTL_R32(TxConfig);
1356 while ((reg & p->mask) != p->val)
1357 p++;
1358 tp->mac_version = p->mac_version;
1359 }
1360
1361 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1362 {
1363 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1364 }
1365
1366 struct phy_reg {
1367 u16 reg;
1368 u16 val;
1369 };
1370
1371 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1372 {
1373 while (len-- > 0) {
1374 mdio_write(ioaddr, regs->reg, regs->val);
1375 regs++;
1376 }
1377 }
1378
1379 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1380 {
1381 struct phy_reg phy_reg_init[] = {
1382 { 0x1f, 0x0001 },
1383 { 0x06, 0x006e },
1384 { 0x08, 0x0708 },
1385 { 0x15, 0x4000 },
1386 { 0x18, 0x65c7 },
1387
1388 { 0x1f, 0x0001 },
1389 { 0x03, 0x00a1 },
1390 { 0x02, 0x0008 },
1391 { 0x01, 0x0120 },
1392 { 0x00, 0x1000 },
1393 { 0x04, 0x0800 },
1394 { 0x04, 0x0000 },
1395
1396 { 0x03, 0xff41 },
1397 { 0x02, 0xdf60 },
1398 { 0x01, 0x0140 },
1399 { 0x00, 0x0077 },
1400 { 0x04, 0x7800 },
1401 { 0x04, 0x7000 },
1402
1403 { 0x03, 0x802f },
1404 { 0x02, 0x4f02 },
1405 { 0x01, 0x0409 },
1406 { 0x00, 0xf0f9 },
1407 { 0x04, 0x9800 },
1408 { 0x04, 0x9000 },
1409
1410 { 0x03, 0xdf01 },
1411 { 0x02, 0xdf20 },
1412 { 0x01, 0xff95 },
1413 { 0x00, 0xba00 },
1414 { 0x04, 0xa800 },
1415 { 0x04, 0xa000 },
1416
1417 { 0x03, 0xff41 },
1418 { 0x02, 0xdf20 },
1419 { 0x01, 0x0140 },
1420 { 0x00, 0x00bb },
1421 { 0x04, 0xb800 },
1422 { 0x04, 0xb000 },
1423
1424 { 0x03, 0xdf41 },
1425 { 0x02, 0xdc60 },
1426 { 0x01, 0x6340 },
1427 { 0x00, 0x007d },
1428 { 0x04, 0xd800 },
1429 { 0x04, 0xd000 },
1430
1431 { 0x03, 0xdf01 },
1432 { 0x02, 0xdf20 },
1433 { 0x01, 0x100a },
1434 { 0x00, 0xa0ff },
1435 { 0x04, 0xf800 },
1436 { 0x04, 0xf000 },
1437
1438 { 0x1f, 0x0000 },
1439 { 0x0b, 0x0000 },
1440 { 0x00, 0x9200 }
1441 };
1442
1443 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1444 }
1445
1446 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1447 {
1448 struct phy_reg phy_reg_init[] = {
1449 { 0x1f, 0x0002 },
1450 { 0x01, 0x90d0 },
1451 { 0x1f, 0x0000 }
1452 };
1453
1454 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1455 }
1456
1457 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1458 void __iomem *ioaddr)
1459 {
1460 struct pci_dev *pdev = tp->pci_dev;
1461 u16 vendor_id, device_id;
1462
1463 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1464 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1465
1466 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1467 return;
1468
1469 mdio_write(ioaddr, 0x1f, 0x0001);
1470 mdio_write(ioaddr, 0x10, 0xf01b);
1471 mdio_write(ioaddr, 0x1f, 0x0000);
1472 }
1473
1474 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1475 void __iomem *ioaddr)
1476 {
1477 struct phy_reg phy_reg_init[] = {
1478 { 0x1f, 0x0001 },
1479 { 0x04, 0x0000 },
1480 { 0x03, 0x00a1 },
1481 { 0x02, 0x0008 },
1482 { 0x01, 0x0120 },
1483 { 0x00, 0x1000 },
1484 { 0x04, 0x0800 },
1485 { 0x04, 0x9000 },
1486 { 0x03, 0x802f },
1487 { 0x02, 0x4f02 },
1488 { 0x01, 0x0409 },
1489 { 0x00, 0xf099 },
1490 { 0x04, 0x9800 },
1491 { 0x04, 0xa000 },
1492 { 0x03, 0xdf01 },
1493 { 0x02, 0xdf20 },
1494 { 0x01, 0xff95 },
1495 { 0x00, 0xba00 },
1496 { 0x04, 0xa800 },
1497 { 0x04, 0xf000 },
1498 { 0x03, 0xdf01 },
1499 { 0x02, 0xdf20 },
1500 { 0x01, 0x101a },
1501 { 0x00, 0xa0ff },
1502 { 0x04, 0xf800 },
1503 { 0x04, 0x0000 },
1504 { 0x1f, 0x0000 },
1505
1506 { 0x1f, 0x0001 },
1507 { 0x10, 0xf41b },
1508 { 0x14, 0xfb54 },
1509 { 0x18, 0xf5c7 },
1510 { 0x1f, 0x0000 },
1511
1512 { 0x1f, 0x0001 },
1513 { 0x17, 0x0cc0 },
1514 { 0x1f, 0x0000 }
1515 };
1516
1517 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1518
1519 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1520 }
1521
1522 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1523 {
1524 struct phy_reg phy_reg_init[] = {
1525 { 0x1f, 0x0001 },
1526 { 0x04, 0x0000 },
1527 { 0x03, 0x00a1 },
1528 { 0x02, 0x0008 },
1529 { 0x01, 0x0120 },
1530 { 0x00, 0x1000 },
1531 { 0x04, 0x0800 },
1532 { 0x04, 0x9000 },
1533 { 0x03, 0x802f },
1534 { 0x02, 0x4f02 },
1535 { 0x01, 0x0409 },
1536 { 0x00, 0xf099 },
1537 { 0x04, 0x9800 },
1538 { 0x04, 0xa000 },
1539 { 0x03, 0xdf01 },
1540 { 0x02, 0xdf20 },
1541 { 0x01, 0xff95 },
1542 { 0x00, 0xba00 },
1543 { 0x04, 0xa800 },
1544 { 0x04, 0xf000 },
1545 { 0x03, 0xdf01 },
1546 { 0x02, 0xdf20 },
1547 { 0x01, 0x101a },
1548 { 0x00, 0xa0ff },
1549 { 0x04, 0xf800 },
1550 { 0x04, 0x0000 },
1551 { 0x1f, 0x0000 },
1552
1553 { 0x1f, 0x0001 },
1554 { 0x0b, 0x8480 },
1555 { 0x1f, 0x0000 },
1556
1557 { 0x1f, 0x0001 },
1558 { 0x18, 0x67c7 },
1559 { 0x04, 0x2000 },
1560 { 0x03, 0x002f },
1561 { 0x02, 0x4360 },
1562 { 0x01, 0x0109 },
1563 { 0x00, 0x3022 },
1564 { 0x04, 0x2800 },
1565 { 0x1f, 0x0000 },
1566
1567 { 0x1f, 0x0001 },
1568 { 0x17, 0x0cc0 },
1569 { 0x1f, 0x0000 }
1570 };
1571
1572 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1573 }
1574
1575 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1576 {
1577 struct phy_reg phy_reg_init[] = {
1578 { 0x10, 0xf41b },
1579 { 0x1f, 0x0000 }
1580 };
1581
1582 mdio_write(ioaddr, 0x1f, 0x0001);
1583 mdio_patch(ioaddr, 0x16, 1 << 0);
1584
1585 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1586 }
1587
1588 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1589 {
1590 struct phy_reg phy_reg_init[] = {
1591 { 0x1f, 0x0001 },
1592 { 0x10, 0xf41b },
1593 { 0x1f, 0x0000 }
1594 };
1595
1596 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1597 }
1598
1599 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1600 {
1601 struct phy_reg phy_reg_init[] = {
1602 { 0x1f, 0x0000 },
1603 { 0x1d, 0x0f00 },
1604 { 0x1f, 0x0002 },
1605 { 0x0c, 0x1ec8 },
1606 { 0x1f, 0x0000 }
1607 };
1608
1609 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1610 }
1611
1612 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1613 {
1614 struct phy_reg phy_reg_init[] = {
1615 { 0x1f, 0x0001 },
1616 { 0x1d, 0x3d98 },
1617 { 0x1f, 0x0000 }
1618 };
1619
1620 mdio_write(ioaddr, 0x1f, 0x0000);
1621 mdio_patch(ioaddr, 0x14, 1 << 5);
1622 mdio_patch(ioaddr, 0x0d, 1 << 5);
1623
1624 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1625 }
1626
1627 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1628 {
1629 struct phy_reg phy_reg_init[] = {
1630 { 0x1f, 0x0001 },
1631 { 0x12, 0x2300 },
1632 { 0x1f, 0x0002 },
1633 { 0x00, 0x88d4 },
1634 { 0x01, 0x82b1 },
1635 { 0x03, 0x7002 },
1636 { 0x08, 0x9e30 },
1637 { 0x09, 0x01f0 },
1638 { 0x0a, 0x5500 },
1639 { 0x0c, 0x00c8 },
1640 { 0x1f, 0x0003 },
1641 { 0x12, 0xc096 },
1642 { 0x16, 0x000a },
1643 { 0x1f, 0x0000 },
1644 { 0x1f, 0x0000 },
1645 { 0x09, 0x2000 },
1646 { 0x09, 0x0000 }
1647 };
1648
1649 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1650
1651 mdio_patch(ioaddr, 0x14, 1 << 5);
1652 mdio_patch(ioaddr, 0x0d, 1 << 5);
1653 mdio_write(ioaddr, 0x1f, 0x0000);
1654 }
1655
1656 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1657 {
1658 struct phy_reg phy_reg_init[] = {
1659 { 0x1f, 0x0001 },
1660 { 0x12, 0x2300 },
1661 { 0x03, 0x802f },
1662 { 0x02, 0x4f02 },
1663 { 0x01, 0x0409 },
1664 { 0x00, 0xf099 },
1665 { 0x04, 0x9800 },
1666 { 0x04, 0x9000 },
1667 { 0x1d, 0x3d98 },
1668 { 0x1f, 0x0002 },
1669 { 0x0c, 0x7eb8 },
1670 { 0x06, 0x0761 },
1671 { 0x1f, 0x0003 },
1672 { 0x16, 0x0f0a },
1673 { 0x1f, 0x0000 }
1674 };
1675
1676 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1677
1678 mdio_patch(ioaddr, 0x16, 1 << 0);
1679 mdio_patch(ioaddr, 0x14, 1 << 5);
1680 mdio_patch(ioaddr, 0x0d, 1 << 5);
1681 mdio_write(ioaddr, 0x1f, 0x0000);
1682 }
1683
1684 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1685 {
1686 struct phy_reg phy_reg_init[] = {
1687 { 0x1f, 0x0001 },
1688 { 0x12, 0x2300 },
1689 { 0x1d, 0x3d98 },
1690 { 0x1f, 0x0002 },
1691 { 0x0c, 0x7eb8 },
1692 { 0x06, 0x5461 },
1693 { 0x1f, 0x0003 },
1694 { 0x16, 0x0f0a },
1695 { 0x1f, 0x0000 }
1696 };
1697
1698 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1699
1700 mdio_patch(ioaddr, 0x16, 1 << 0);
1701 mdio_patch(ioaddr, 0x14, 1 << 5);
1702 mdio_patch(ioaddr, 0x0d, 1 << 5);
1703 mdio_write(ioaddr, 0x1f, 0x0000);
1704 }
1705
1706 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1707 {
1708 rtl8168c_3_hw_phy_config(ioaddr);
1709 }
1710
1711 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1712 {
1713 static struct phy_reg phy_reg_init_0[] = {
1714 { 0x1f, 0x0001 },
1715 { 0x06, 0x4064 },
1716 { 0x07, 0x2863 },
1717 { 0x08, 0x059c },
1718 { 0x09, 0x26b4 },
1719 { 0x0a, 0x6a19 },
1720 { 0x0b, 0xdcc8 },
1721 { 0x10, 0xf06d },
1722 { 0x14, 0x7f68 },
1723 { 0x18, 0x7fd9 },
1724 { 0x1c, 0xf0ff },
1725 { 0x1d, 0x3d9c },
1726 { 0x1f, 0x0003 },
1727 { 0x12, 0xf49f },
1728 { 0x13, 0x070b },
1729 { 0x1a, 0x05ad },
1730 { 0x14, 0x94c0 }
1731 };
1732 static struct phy_reg phy_reg_init_1[] = {
1733 { 0x1f, 0x0002 },
1734 { 0x06, 0x5561 },
1735 { 0x1f, 0x0005 },
1736 { 0x05, 0x8332 },
1737 { 0x06, 0x5561 }
1738 };
1739 static struct phy_reg phy_reg_init_2[] = {
1740 { 0x1f, 0x0005 },
1741 { 0x05, 0xffc2 },
1742 { 0x1f, 0x0005 },
1743 { 0x05, 0x8000 },
1744 { 0x06, 0xf8f9 },
1745 { 0x06, 0xfaef },
1746 { 0x06, 0x59ee },
1747 { 0x06, 0xf8ea },
1748 { 0x06, 0x00ee },
1749 { 0x06, 0xf8eb },
1750 { 0x06, 0x00e0 },
1751 { 0x06, 0xf87c },
1752 { 0x06, 0xe1f8 },
1753 { 0x06, 0x7d59 },
1754 { 0x06, 0x0fef },
1755 { 0x06, 0x0139 },
1756 { 0x06, 0x029e },
1757 { 0x06, 0x06ef },
1758 { 0x06, 0x1039 },
1759 { 0x06, 0x089f },
1760 { 0x06, 0x2aee },
1761 { 0x06, 0xf8ea },
1762 { 0x06, 0x00ee },
1763 { 0x06, 0xf8eb },
1764 { 0x06, 0x01e0 },
1765 { 0x06, 0xf87c },
1766 { 0x06, 0xe1f8 },
1767 { 0x06, 0x7d58 },
1768 { 0x06, 0x409e },
1769 { 0x06, 0x0f39 },
1770 { 0x06, 0x46aa },
1771 { 0x06, 0x0bbf },
1772 { 0x06, 0x8290 },
1773 { 0x06, 0xd682 },
1774 { 0x06, 0x9802 },
1775 { 0x06, 0x014f },
1776 { 0x06, 0xae09 },
1777 { 0x06, 0xbf82 },
1778 { 0x06, 0x98d6 },
1779 { 0x06, 0x82a0 },
1780 { 0x06, 0x0201 },
1781 { 0x06, 0x4fef },
1782 { 0x06, 0x95fe },
1783 { 0x06, 0xfdfc },
1784 { 0x06, 0x05f8 },
1785 { 0x06, 0xf9fa },
1786 { 0x06, 0xeef8 },
1787 { 0x06, 0xea00 },
1788 { 0x06, 0xeef8 },
1789 { 0x06, 0xeb00 },
1790 { 0x06, 0xe2f8 },
1791 { 0x06, 0x7ce3 },
1792 { 0x06, 0xf87d },
1793 { 0x06, 0xa511 },
1794 { 0x06, 0x1112 },
1795 { 0x06, 0xd240 },
1796 { 0x06, 0xd644 },
1797 { 0x06, 0x4402 },
1798 { 0x06, 0x8217 },
1799 { 0x06, 0xd2a0 },
1800 { 0x06, 0xd6aa },
1801 { 0x06, 0xaa02 },
1802 { 0x06, 0x8217 },
1803 { 0x06, 0xae0f },
1804 { 0x06, 0xa544 },
1805 { 0x06, 0x4402 },
1806 { 0x06, 0xae4d },
1807 { 0x06, 0xa5aa },
1808 { 0x06, 0xaa02 },
1809 { 0x06, 0xae47 },
1810 { 0x06, 0xaf82 },
1811 { 0x06, 0x13ee },
1812 { 0x06, 0x834e },
1813 { 0x06, 0x00ee },
1814 { 0x06, 0x834d },
1815 { 0x06, 0x0fee },
1816 { 0x06, 0x834c },
1817 { 0x06, 0x0fee },
1818 { 0x06, 0x834f },
1819 { 0x06, 0x00ee },
1820 { 0x06, 0x8351 },
1821 { 0x06, 0x00ee },
1822 { 0x06, 0x834a },
1823 { 0x06, 0xffee },
1824 { 0x06, 0x834b },
1825 { 0x06, 0xffe0 },
1826 { 0x06, 0x8330 },
1827 { 0x06, 0xe183 },
1828 { 0x06, 0x3158 },
1829 { 0x06, 0xfee4 },
1830 { 0x06, 0xf88a },
1831 { 0x06, 0xe5f8 },
1832 { 0x06, 0x8be0 },
1833 { 0x06, 0x8332 },
1834 { 0x06, 0xe183 },
1835 { 0x06, 0x3359 },
1836 { 0x06, 0x0fe2 },
1837 { 0x06, 0x834d },
1838 { 0x06, 0x0c24 },
1839 { 0x06, 0x5af0 },
1840 { 0x06, 0x1e12 },
1841 { 0x06, 0xe4f8 },
1842 { 0x06, 0x8ce5 },
1843 { 0x06, 0xf88d },
1844 { 0x06, 0xaf82 },
1845 { 0x06, 0x13e0 },
1846 { 0x06, 0x834f },
1847 { 0x06, 0x10e4 },
1848 { 0x06, 0x834f },
1849 { 0x06, 0xe083 },
1850 { 0x06, 0x4e78 },
1851 { 0x06, 0x009f },
1852 { 0x06, 0x0ae0 },
1853 { 0x06, 0x834f },
1854 { 0x06, 0xa010 },
1855 { 0x06, 0xa5ee },
1856 { 0x06, 0x834e },
1857 { 0x06, 0x01e0 },
1858 { 0x06, 0x834e },
1859 { 0x06, 0x7805 },
1860 { 0x06, 0x9e9a },
1861 { 0x06, 0xe083 },
1862 { 0x06, 0x4e78 },
1863 { 0x06, 0x049e },
1864 { 0x06, 0x10e0 },
1865 { 0x06, 0x834e },
1866 { 0x06, 0x7803 },
1867 { 0x06, 0x9e0f },
1868 { 0x06, 0xe083 },
1869 { 0x06, 0x4e78 },
1870 { 0x06, 0x019e },
1871 { 0x06, 0x05ae },
1872 { 0x06, 0x0caf },
1873 { 0x06, 0x81f8 },
1874 { 0x06, 0xaf81 },
1875 { 0x06, 0xa3af },
1876 { 0x06, 0x81dc },
1877 { 0x06, 0xaf82 },
1878 { 0x06, 0x13ee },
1879 { 0x06, 0x8348 },
1880 { 0x06, 0x00ee },
1881 { 0x06, 0x8349 },
1882 { 0x06, 0x00e0 },
1883 { 0x06, 0x8351 },
1884 { 0x06, 0x10e4 },
1885 { 0x06, 0x8351 },
1886 { 0x06, 0x5801 },
1887 { 0x06, 0x9fea },
1888 { 0x06, 0xd000 },
1889 { 0x06, 0xd180 },
1890 { 0x06, 0x1f66 },
1891 { 0x06, 0xe2f8 },
1892 { 0x06, 0xeae3 },
1893 { 0x06, 0xf8eb },
1894 { 0x06, 0x5af8 },
1895 { 0x06, 0x1e20 },
1896 { 0x06, 0xe6f8 },
1897 { 0x06, 0xeae5 },
1898 { 0x06, 0xf8eb },
1899 { 0x06, 0xd302 },
1900 { 0x06, 0xb3fe },
1901 { 0x06, 0xe2f8 },
1902 { 0x06, 0x7cef },
1903 { 0x06, 0x325b },
1904 { 0x06, 0x80e3 },
1905 { 0x06, 0xf87d },
1906 { 0x06, 0x9e03 },
1907 { 0x06, 0x7dff },
1908 { 0x06, 0xff0d },
1909 { 0x06, 0x581c },
1910 { 0x06, 0x551a },
1911 { 0x06, 0x6511 },
1912 { 0x06, 0xa190 },
1913 { 0x06, 0xd3e2 },
1914 { 0x06, 0x8348 },
1915 { 0x06, 0xe383 },
1916 { 0x06, 0x491b },
1917 { 0x06, 0x56ab },
1918 { 0x06, 0x08ef },
1919 { 0x06, 0x56e6 },
1920 { 0x06, 0x8348 },
1921 { 0x06, 0xe783 },
1922 { 0x06, 0x4910 },
1923 { 0x06, 0xd180 },
1924 { 0x06, 0x1f66 },
1925 { 0x06, 0xa004 },
1926 { 0x06, 0xb9e2 },
1927 { 0x06, 0x8348 },
1928 { 0x06, 0xe383 },
1929 { 0x06, 0x49ef },
1930 { 0x06, 0x65e2 },
1931 { 0x06, 0x834a },
1932 { 0x06, 0xe383 },
1933 { 0x06, 0x4b1b },
1934 { 0x06, 0x56aa },
1935 { 0x06, 0x0eef },
1936 { 0x06, 0x56e6 },
1937 { 0x06, 0x834a },
1938 { 0x06, 0xe783 },
1939 { 0x06, 0x4be2 },
1940 { 0x06, 0x834d },
1941 { 0x06, 0xe683 },
1942 { 0x06, 0x4ce0 },
1943 { 0x06, 0x834d },
1944 { 0x06, 0xa000 },
1945 { 0x06, 0x0caf },
1946 { 0x06, 0x81dc },
1947 { 0x06, 0xe083 },
1948 { 0x06, 0x4d10 },
1949 { 0x06, 0xe483 },
1950 { 0x06, 0x4dae },
1951 { 0x06, 0x0480 },
1952 { 0x06, 0xe483 },
1953 { 0x06, 0x4de0 },
1954 { 0x06, 0x834e },
1955 { 0x06, 0x7803 },
1956 { 0x06, 0x9e0b },
1957 { 0x06, 0xe083 },
1958 { 0x06, 0x4e78 },
1959 { 0x06, 0x049e },
1960 { 0x06, 0x04ee },
1961 { 0x06, 0x834e },
1962 { 0x06, 0x02e0 },
1963 { 0x06, 0x8332 },
1964 { 0x06, 0xe183 },
1965 { 0x06, 0x3359 },
1966 { 0x06, 0x0fe2 },
1967 { 0x06, 0x834d },
1968 { 0x06, 0x0c24 },
1969 { 0x06, 0x5af0 },
1970 { 0x06, 0x1e12 },
1971 { 0x06, 0xe4f8 },
1972 { 0x06, 0x8ce5 },
1973 { 0x06, 0xf88d },
1974 { 0x06, 0xe083 },
1975 { 0x06, 0x30e1 },
1976 { 0x06, 0x8331 },
1977 { 0x06, 0x6801 },
1978 { 0x06, 0xe4f8 },
1979 { 0x06, 0x8ae5 },
1980 { 0x06, 0xf88b },
1981 { 0x06, 0xae37 },
1982 { 0x06, 0xee83 },
1983 { 0x06, 0x4e03 },
1984 { 0x06, 0xe083 },
1985 { 0x06, 0x4ce1 },
1986 { 0x06, 0x834d },
1987 { 0x06, 0x1b01 },
1988 { 0x06, 0x9e04 },
1989 { 0x06, 0xaaa1 },
1990 { 0x06, 0xaea8 },
1991 { 0x06, 0xee83 },
1992 { 0x06, 0x4e04 },
1993 { 0x06, 0xee83 },
1994 { 0x06, 0x4f00 },
1995 { 0x06, 0xaeab },
1996 { 0x06, 0xe083 },
1997 { 0x06, 0x4f78 },
1998 { 0x06, 0x039f },
1999 { 0x06, 0x14ee },
2000 { 0x06, 0x834e },
2001 { 0x06, 0x05d2 },
2002 { 0x06, 0x40d6 },
2003 { 0x06, 0x5554 },
2004 { 0x06, 0x0282 },
2005 { 0x06, 0x17d2 },
2006 { 0x06, 0xa0d6 },
2007 { 0x06, 0xba00 },
2008 { 0x06, 0x0282 },
2009 { 0x06, 0x17fe },
2010 { 0x06, 0xfdfc },
2011 { 0x06, 0x05f8 },
2012 { 0x06, 0xe0f8 },
2013 { 0x06, 0x60e1 },
2014 { 0x06, 0xf861 },
2015 { 0x06, 0x6802 },
2016 { 0x06, 0xe4f8 },
2017 { 0x06, 0x60e5 },
2018 { 0x06, 0xf861 },
2019 { 0x06, 0xe0f8 },
2020 { 0x06, 0x48e1 },
2021 { 0x06, 0xf849 },
2022 { 0x06, 0x580f },
2023 { 0x06, 0x1e02 },
2024 { 0x06, 0xe4f8 },
2025 { 0x06, 0x48e5 },
2026 { 0x06, 0xf849 },
2027 { 0x06, 0xd000 },
2028 { 0x06, 0x0282 },
2029 { 0x06, 0x5bbf },
2030 { 0x06, 0x8350 },
2031 { 0x06, 0xef46 },
2032 { 0x06, 0xdc19 },
2033 { 0x06, 0xddd0 },
2034 { 0x06, 0x0102 },
2035 { 0x06, 0x825b },
2036 { 0x06, 0x0282 },
2037 { 0x06, 0x77e0 },
2038 { 0x06, 0xf860 },
2039 { 0x06, 0xe1f8 },
2040 { 0x06, 0x6158 },
2041 { 0x06, 0xfde4 },
2042 { 0x06, 0xf860 },
2043 { 0x06, 0xe5f8 },
2044 { 0x06, 0x61fc },
2045 { 0x06, 0x04f9 },
2046 { 0x06, 0xfafb },
2047 { 0x06, 0xc6bf },
2048 { 0x06, 0xf840 },
2049 { 0x06, 0xbe83 },
2050 { 0x06, 0x50a0 },
2051 { 0x06, 0x0101 },
2052 { 0x06, 0x071b },
2053 { 0x06, 0x89cf },
2054 { 0x06, 0xd208 },
2055 { 0x06, 0xebdb },
2056 { 0x06, 0x19b2 },
2057 { 0x06, 0xfbff },
2058 { 0x06, 0xfefd },
2059 { 0x06, 0x04f8 },
2060 { 0x06, 0xe0f8 },
2061 { 0x06, 0x48e1 },
2062 { 0x06, 0xf849 },
2063 { 0x06, 0x6808 },
2064 { 0x06, 0xe4f8 },
2065 { 0x06, 0x48e5 },
2066 { 0x06, 0xf849 },
2067 { 0x06, 0x58f7 },
2068 { 0x06, 0xe4f8 },
2069 { 0x06, 0x48e5 },
2070 { 0x06, 0xf849 },
2071 { 0x06, 0xfc04 },
2072 { 0x06, 0x4d20 },
2073 { 0x06, 0x0002 },
2074 { 0x06, 0x4e22 },
2075 { 0x06, 0x0002 },
2076 { 0x06, 0x4ddf },
2077 { 0x06, 0xff01 },
2078 { 0x06, 0x4edd },
2079 { 0x06, 0xff01 },
2080 { 0x05, 0x83d4 },
2081 { 0x06, 0x8000 },
2082 { 0x05, 0x83d8 },
2083 { 0x06, 0x8051 },
2084 { 0x02, 0x6010 },
2085 { 0x03, 0xdc00 },
2086 { 0x05, 0xfff6 },
2087 { 0x06, 0x00fc },
2088 { 0x1f, 0x0000 },
2089
2090 { 0x1f, 0x0000 },
2091 { 0x0d, 0xf880 },
2092 { 0x1f, 0x0000 }
2093 };
2094
2095 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2096
2097 mdio_write(ioaddr, 0x1f, 0x0002);
2098 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2099 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2100
2101 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2102
2103 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2104 struct phy_reg phy_reg_init[] = {
2105 { 0x1f, 0x0002 },
2106 { 0x05, 0x669a },
2107 { 0x1f, 0x0005 },
2108 { 0x05, 0x8330 },
2109 { 0x06, 0x669a },
2110 { 0x1f, 0x0002 }
2111 };
2112 int val;
2113
2114 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2115
2116 val = mdio_read(ioaddr, 0x0d);
2117
2118 if ((val & 0x00ff) != 0x006c) {
2119 u32 set[] = {
2120 0x0065, 0x0066, 0x0067, 0x0068,
2121 0x0069, 0x006a, 0x006b, 0x006c
2122 };
2123 int i;
2124
2125 mdio_write(ioaddr, 0x1f, 0x0002);
2126
2127 val &= 0xff00;
2128 for (i = 0; i < ARRAY_SIZE(set); i++)
2129 mdio_write(ioaddr, 0x0d, val | set[i]);
2130 }
2131 } else {
2132 struct phy_reg phy_reg_init[] = {
2133 { 0x1f, 0x0002 },
2134 { 0x05, 0x6662 },
2135 { 0x1f, 0x0005 },
2136 { 0x05, 0x8330 },
2137 { 0x06, 0x6662 }
2138 };
2139
2140 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2141 }
2142
2143 mdio_write(ioaddr, 0x1f, 0x0002);
2144 mdio_patch(ioaddr, 0x0d, 0x0300);
2145 mdio_patch(ioaddr, 0x0f, 0x0010);
2146
2147 mdio_write(ioaddr, 0x1f, 0x0002);
2148 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2149 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2150
2151 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2152 }
2153
2154 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2155 {
2156 static struct phy_reg phy_reg_init_0[] = {
2157 { 0x1f, 0x0001 },
2158 { 0x06, 0x4064 },
2159 { 0x07, 0x2863 },
2160 { 0x08, 0x059c },
2161 { 0x09, 0x26b4 },
2162 { 0x0a, 0x6a19 },
2163 { 0x0b, 0xdcc8 },
2164 { 0x10, 0xf06d },
2165 { 0x14, 0x7f68 },
2166 { 0x18, 0x7fd9 },
2167 { 0x1c, 0xf0ff },
2168 { 0x1d, 0x3d9c },
2169 { 0x1f, 0x0003 },
2170 { 0x12, 0xf49f },
2171 { 0x13, 0x070b },
2172 { 0x1a, 0x05ad },
2173 { 0x14, 0x94c0 },
2174
2175 { 0x1f, 0x0002 },
2176 { 0x06, 0x5561 },
2177 { 0x1f, 0x0005 },
2178 { 0x05, 0x8332 },
2179 { 0x06, 0x5561 }
2180 };
2181 static struct phy_reg phy_reg_init_1[] = {
2182 { 0x1f, 0x0005 },
2183 { 0x05, 0xffc2 },
2184 { 0x1f, 0x0005 },
2185 { 0x05, 0x8000 },
2186 { 0x06, 0xf8f9 },
2187 { 0x06, 0xfaee },
2188 { 0x06, 0xf8ea },
2189 { 0x06, 0x00ee },
2190 { 0x06, 0xf8eb },
2191 { 0x06, 0x00e2 },
2192 { 0x06, 0xf87c },
2193 { 0x06, 0xe3f8 },
2194 { 0x06, 0x7da5 },
2195 { 0x06, 0x1111 },
2196 { 0x06, 0x12d2 },
2197 { 0x06, 0x40d6 },
2198 { 0x06, 0x4444 },
2199 { 0x06, 0x0281 },
2200 { 0x06, 0xc6d2 },
2201 { 0x06, 0xa0d6 },
2202 { 0x06, 0xaaaa },
2203 { 0x06, 0x0281 },
2204 { 0x06, 0xc6ae },
2205 { 0x06, 0x0fa5 },
2206 { 0x06, 0x4444 },
2207 { 0x06, 0x02ae },
2208 { 0x06, 0x4da5 },
2209 { 0x06, 0xaaaa },
2210 { 0x06, 0x02ae },
2211 { 0x06, 0x47af },
2212 { 0x06, 0x81c2 },
2213 { 0x06, 0xee83 },
2214 { 0x06, 0x4e00 },
2215 { 0x06, 0xee83 },
2216 { 0x06, 0x4d0f },
2217 { 0x06, 0xee83 },
2218 { 0x06, 0x4c0f },
2219 { 0x06, 0xee83 },
2220 { 0x06, 0x4f00 },
2221 { 0x06, 0xee83 },
2222 { 0x06, 0x5100 },
2223 { 0x06, 0xee83 },
2224 { 0x06, 0x4aff },
2225 { 0x06, 0xee83 },
2226 { 0x06, 0x4bff },
2227 { 0x06, 0xe083 },
2228 { 0x06, 0x30e1 },
2229 { 0x06, 0x8331 },
2230 { 0x06, 0x58fe },
2231 { 0x06, 0xe4f8 },
2232 { 0x06, 0x8ae5 },
2233 { 0x06, 0xf88b },
2234 { 0x06, 0xe083 },
2235 { 0x06, 0x32e1 },
2236 { 0x06, 0x8333 },
2237 { 0x06, 0x590f },
2238 { 0x06, 0xe283 },
2239 { 0x06, 0x4d0c },
2240 { 0x06, 0x245a },
2241 { 0x06, 0xf01e },
2242 { 0x06, 0x12e4 },
2243 { 0x06, 0xf88c },
2244 { 0x06, 0xe5f8 },
2245 { 0x06, 0x8daf },
2246 { 0x06, 0x81c2 },
2247 { 0x06, 0xe083 },
2248 { 0x06, 0x4f10 },
2249 { 0x06, 0xe483 },
2250 { 0x06, 0x4fe0 },
2251 { 0x06, 0x834e },
2252 { 0x06, 0x7800 },
2253 { 0x06, 0x9f0a },
2254 { 0x06, 0xe083 },
2255 { 0x06, 0x4fa0 },
2256 { 0x06, 0x10a5 },
2257 { 0x06, 0xee83 },
2258 { 0x06, 0x4e01 },
2259 { 0x06, 0xe083 },
2260 { 0x06, 0x4e78 },
2261 { 0x06, 0x059e },
2262 { 0x06, 0x9ae0 },
2263 { 0x06, 0x834e },
2264 { 0x06, 0x7804 },
2265 { 0x06, 0x9e10 },
2266 { 0x06, 0xe083 },
2267 { 0x06, 0x4e78 },
2268 { 0x06, 0x039e },
2269 { 0x06, 0x0fe0 },
2270 { 0x06, 0x834e },
2271 { 0x06, 0x7801 },
2272 { 0x06, 0x9e05 },
2273 { 0x06, 0xae0c },
2274 { 0x06, 0xaf81 },
2275 { 0x06, 0xa7af },
2276 { 0x06, 0x8152 },
2277 { 0x06, 0xaf81 },
2278 { 0x06, 0x8baf },
2279 { 0x06, 0x81c2 },
2280 { 0x06, 0xee83 },
2281 { 0x06, 0x4800 },
2282 { 0x06, 0xee83 },
2283 { 0x06, 0x4900 },
2284 { 0x06, 0xe083 },
2285 { 0x06, 0x5110 },
2286 { 0x06, 0xe483 },
2287 { 0x06, 0x5158 },
2288 { 0x06, 0x019f },
2289 { 0x06, 0xead0 },
2290 { 0x06, 0x00d1 },
2291 { 0x06, 0x801f },
2292 { 0x06, 0x66e2 },
2293 { 0x06, 0xf8ea },
2294 { 0x06, 0xe3f8 },
2295 { 0x06, 0xeb5a },
2296 { 0x06, 0xf81e },
2297 { 0x06, 0x20e6 },
2298 { 0x06, 0xf8ea },
2299 { 0x06, 0xe5f8 },
2300 { 0x06, 0xebd3 },
2301 { 0x06, 0x02b3 },
2302 { 0x06, 0xfee2 },
2303 { 0x06, 0xf87c },
2304 { 0x06, 0xef32 },
2305 { 0x06, 0x5b80 },
2306 { 0x06, 0xe3f8 },
2307 { 0x06, 0x7d9e },
2308 { 0x06, 0x037d },
2309 { 0x06, 0xffff },
2310 { 0x06, 0x0d58 },
2311 { 0x06, 0x1c55 },
2312 { 0x06, 0x1a65 },
2313 { 0x06, 0x11a1 },
2314 { 0x06, 0x90d3 },
2315 { 0x06, 0xe283 },
2316 { 0x06, 0x48e3 },
2317 { 0x06, 0x8349 },
2318 { 0x06, 0x1b56 },
2319 { 0x06, 0xab08 },
2320 { 0x06, 0xef56 },
2321 { 0x06, 0xe683 },
2322 { 0x06, 0x48e7 },
2323 { 0x06, 0x8349 },
2324 { 0x06, 0x10d1 },
2325 { 0x06, 0x801f },
2326 { 0x06, 0x66a0 },
2327 { 0x06, 0x04b9 },
2328 { 0x06, 0xe283 },
2329 { 0x06, 0x48e3 },
2330 { 0x06, 0x8349 },
2331 { 0x06, 0xef65 },
2332 { 0x06, 0xe283 },
2333 { 0x06, 0x4ae3 },
2334 { 0x06, 0x834b },
2335 { 0x06, 0x1b56 },
2336 { 0x06, 0xaa0e },
2337 { 0x06, 0xef56 },
2338 { 0x06, 0xe683 },
2339 { 0x06, 0x4ae7 },
2340 { 0x06, 0x834b },
2341 { 0x06, 0xe283 },
2342 { 0x06, 0x4de6 },
2343 { 0x06, 0x834c },
2344 { 0x06, 0xe083 },
2345 { 0x06, 0x4da0 },
2346 { 0x06, 0x000c },
2347 { 0x06, 0xaf81 },
2348 { 0x06, 0x8be0 },
2349 { 0x06, 0x834d },
2350 { 0x06, 0x10e4 },
2351 { 0x06, 0x834d },
2352 { 0x06, 0xae04 },
2353 { 0x06, 0x80e4 },
2354 { 0x06, 0x834d },
2355 { 0x06, 0xe083 },
2356 { 0x06, 0x4e78 },
2357 { 0x06, 0x039e },
2358 { 0x06, 0x0be0 },
2359 { 0x06, 0x834e },
2360 { 0x06, 0x7804 },
2361 { 0x06, 0x9e04 },
2362 { 0x06, 0xee83 },
2363 { 0x06, 0x4e02 },
2364 { 0x06, 0xe083 },
2365 { 0x06, 0x32e1 },
2366 { 0x06, 0x8333 },
2367 { 0x06, 0x590f },
2368 { 0x06, 0xe283 },
2369 { 0x06, 0x4d0c },
2370 { 0x06, 0x245a },
2371 { 0x06, 0xf01e },
2372 { 0x06, 0x12e4 },
2373 { 0x06, 0xf88c },
2374 { 0x06, 0xe5f8 },
2375 { 0x06, 0x8de0 },
2376 { 0x06, 0x8330 },
2377 { 0x06, 0xe183 },
2378 { 0x06, 0x3168 },
2379 { 0x06, 0x01e4 },
2380 { 0x06, 0xf88a },
2381 { 0x06, 0xe5f8 },
2382 { 0x06, 0x8bae },
2383 { 0x06, 0x37ee },
2384 { 0x06, 0x834e },
2385 { 0x06, 0x03e0 },
2386 { 0x06, 0x834c },
2387 { 0x06, 0xe183 },
2388 { 0x06, 0x4d1b },
2389 { 0x06, 0x019e },
2390 { 0x06, 0x04aa },
2391 { 0x06, 0xa1ae },
2392 { 0x06, 0xa8ee },
2393 { 0x06, 0x834e },
2394 { 0x06, 0x04ee },
2395 { 0x06, 0x834f },
2396 { 0x06, 0x00ae },
2397 { 0x06, 0xabe0 },
2398 { 0x06, 0x834f },
2399 { 0x06, 0x7803 },
2400 { 0x06, 0x9f14 },
2401 { 0x06, 0xee83 },
2402 { 0x06, 0x4e05 },
2403 { 0x06, 0xd240 },
2404 { 0x06, 0xd655 },
2405 { 0x06, 0x5402 },
2406 { 0x06, 0x81c6 },
2407 { 0x06, 0xd2a0 },
2408 { 0x06, 0xd6ba },
2409 { 0x06, 0x0002 },
2410 { 0x06, 0x81c6 },
2411 { 0x06, 0xfefd },
2412 { 0x06, 0xfc05 },
2413 { 0x06, 0xf8e0 },
2414 { 0x06, 0xf860 },
2415 { 0x06, 0xe1f8 },
2416 { 0x06, 0x6168 },
2417 { 0x06, 0x02e4 },
2418 { 0x06, 0xf860 },
2419 { 0x06, 0xe5f8 },
2420 { 0x06, 0x61e0 },
2421 { 0x06, 0xf848 },
2422 { 0x06, 0xe1f8 },
2423 { 0x06, 0x4958 },
2424 { 0x06, 0x0f1e },
2425 { 0x06, 0x02e4 },
2426 { 0x06, 0xf848 },
2427 { 0x06, 0xe5f8 },
2428 { 0x06, 0x49d0 },
2429 { 0x06, 0x0002 },
2430 { 0x06, 0x820a },
2431 { 0x06, 0xbf83 },
2432 { 0x06, 0x50ef },
2433 { 0x06, 0x46dc },
2434 { 0x06, 0x19dd },
2435 { 0x06, 0xd001 },
2436 { 0x06, 0x0282 },
2437 { 0x06, 0x0a02 },
2438 { 0x06, 0x8226 },
2439 { 0x06, 0xe0f8 },
2440 { 0x06, 0x60e1 },
2441 { 0x06, 0xf861 },
2442 { 0x06, 0x58fd },
2443 { 0x06, 0xe4f8 },
2444 { 0x06, 0x60e5 },
2445 { 0x06, 0xf861 },
2446 { 0x06, 0xfc04 },
2447 { 0x06, 0xf9fa },
2448 { 0x06, 0xfbc6 },
2449 { 0x06, 0xbff8 },
2450 { 0x06, 0x40be },
2451 { 0x06, 0x8350 },
2452 { 0x06, 0xa001 },
2453 { 0x06, 0x0107 },
2454 { 0x06, 0x1b89 },
2455 { 0x06, 0xcfd2 },
2456 { 0x06, 0x08eb },
2457 { 0x06, 0xdb19 },
2458 { 0x06, 0xb2fb },
2459 { 0x06, 0xfffe },
2460 { 0x06, 0xfd04 },
2461 { 0x06, 0xf8e0 },
2462 { 0x06, 0xf848 },
2463 { 0x06, 0xe1f8 },
2464 { 0x06, 0x4968 },
2465 { 0x06, 0x08e4 },
2466 { 0x06, 0xf848 },
2467 { 0x06, 0xe5f8 },
2468 { 0x06, 0x4958 },
2469 { 0x06, 0xf7e4 },
2470 { 0x06, 0xf848 },
2471 { 0x06, 0xe5f8 },
2472 { 0x06, 0x49fc },
2473 { 0x06, 0x044d },
2474 { 0x06, 0x2000 },
2475 { 0x06, 0x024e },
2476 { 0x06, 0x2200 },
2477 { 0x06, 0x024d },
2478 { 0x06, 0xdfff },
2479 { 0x06, 0x014e },
2480 { 0x06, 0xddff },
2481 { 0x06, 0x0100 },
2482 { 0x05, 0x83d8 },
2483 { 0x06, 0x8000 },
2484 { 0x03, 0xdc00 },
2485 { 0x05, 0xfff6 },
2486 { 0x06, 0x00fc },
2487 { 0x1f, 0x0000 },
2488
2489 { 0x1f, 0x0000 },
2490 { 0x0d, 0xf880 },
2491 { 0x1f, 0x0000 }
2492 };
2493
2494 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2495
2496 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2497 struct phy_reg phy_reg_init[] = {
2498 { 0x1f, 0x0002 },
2499 { 0x05, 0x669a },
2500 { 0x1f, 0x0005 },
2501 { 0x05, 0x8330 },
2502 { 0x06, 0x669a },
2503
2504 { 0x1f, 0x0002 }
2505 };
2506 int val;
2507
2508 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2509
2510 val = mdio_read(ioaddr, 0x0d);
2511 if ((val & 0x00ff) != 0x006c) {
2512 u32 set[] = {
2513 0x0065, 0x0066, 0x0067, 0x0068,
2514 0x0069, 0x006a, 0x006b, 0x006c
2515 };
2516 int i;
2517
2518 mdio_write(ioaddr, 0x1f, 0x0002);
2519
2520 val &= 0xff00;
2521 for (i = 0; i < ARRAY_SIZE(set); i++)
2522 mdio_write(ioaddr, 0x0d, val | set[i]);
2523 }
2524 } else {
2525 struct phy_reg phy_reg_init[] = {
2526 { 0x1f, 0x0002 },
2527 { 0x05, 0x2642 },
2528 { 0x1f, 0x0005 },
2529 { 0x05, 0x8330 },
2530 { 0x06, 0x2642 }
2531 };
2532
2533 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2534 }
2535
2536 mdio_write(ioaddr, 0x1f, 0x0002);
2537 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2538 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2539
2540 mdio_write(ioaddr, 0x1f, 0x0001);
2541 mdio_write(ioaddr, 0x17, 0x0cc0);
2542
2543 mdio_write(ioaddr, 0x1f, 0x0002);
2544 mdio_patch(ioaddr, 0x0f, 0x0017);
2545
2546 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2547 }
2548
2549 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2550 {
2551 struct phy_reg phy_reg_init[] = {
2552 { 0x1f, 0x0002 },
2553 { 0x10, 0x0008 },
2554 { 0x0d, 0x006c },
2555
2556 { 0x1f, 0x0000 },
2557 { 0x0d, 0xf880 },
2558
2559 { 0x1f, 0x0001 },
2560 { 0x17, 0x0cc0 },
2561
2562 { 0x1f, 0x0001 },
2563 { 0x0b, 0xa4d8 },
2564 { 0x09, 0x281c },
2565 { 0x07, 0x2883 },
2566 { 0x0a, 0x6b35 },
2567 { 0x1d, 0x3da4 },
2568 { 0x1c, 0xeffd },
2569 { 0x14, 0x7f52 },
2570 { 0x18, 0x7fc6 },
2571 { 0x08, 0x0601 },
2572 { 0x06, 0x4063 },
2573 { 0x10, 0xf074 },
2574 { 0x1f, 0x0003 },
2575 { 0x13, 0x0789 },
2576 { 0x12, 0xf4bd },
2577 { 0x1a, 0x04fd },
2578 { 0x14, 0x84b0 },
2579 { 0x1f, 0x0000 },
2580 { 0x00, 0x9200 },
2581
2582 { 0x1f, 0x0005 },
2583 { 0x01, 0x0340 },
2584 { 0x1f, 0x0001 },
2585 { 0x04, 0x4000 },
2586 { 0x03, 0x1d21 },
2587 { 0x02, 0x0c32 },
2588 { 0x01, 0x0200 },
2589 { 0x00, 0x5554 },
2590 { 0x04, 0x4800 },
2591 { 0x04, 0x4000 },
2592 { 0x04, 0xf000 },
2593 { 0x03, 0xdf01 },
2594 { 0x02, 0xdf20 },
2595 { 0x01, 0x101a },
2596 { 0x00, 0xa0ff },
2597 { 0x04, 0xf800 },
2598 { 0x04, 0xf000 },
2599 { 0x1f, 0x0000 },
2600
2601 { 0x1f, 0x0007 },
2602 { 0x1e, 0x0023 },
2603 { 0x16, 0x0000 },
2604 { 0x1f, 0x0000 }
2605 };
2606
2607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2608 }
2609
2610 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2611 {
2612 struct phy_reg phy_reg_init[] = {
2613 { 0x1f, 0x0003 },
2614 { 0x08, 0x441d },
2615 { 0x01, 0x9100 },
2616 { 0x1f, 0x0000 }
2617 };
2618
2619 mdio_write(ioaddr, 0x1f, 0x0000);
2620 mdio_patch(ioaddr, 0x11, 1 << 12);
2621 mdio_patch(ioaddr, 0x19, 1 << 13);
2622 mdio_patch(ioaddr, 0x10, 1 << 15);
2623
2624 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2625 }
2626
2627 static void rtl_hw_phy_config(struct net_device *dev)
2628 {
2629 struct rtl8169_private *tp = netdev_priv(dev);
2630 void __iomem *ioaddr = tp->mmio_addr;
2631
2632 rtl8169_print_mac_version(tp);
2633
2634 switch (tp->mac_version) {
2635 case RTL_GIGA_MAC_VER_01:
2636 break;
2637 case RTL_GIGA_MAC_VER_02:
2638 case RTL_GIGA_MAC_VER_03:
2639 rtl8169s_hw_phy_config(ioaddr);
2640 break;
2641 case RTL_GIGA_MAC_VER_04:
2642 rtl8169sb_hw_phy_config(ioaddr);
2643 break;
2644 case RTL_GIGA_MAC_VER_05:
2645 rtl8169scd_hw_phy_config(tp, ioaddr);
2646 break;
2647 case RTL_GIGA_MAC_VER_06:
2648 rtl8169sce_hw_phy_config(ioaddr);
2649 break;
2650 case RTL_GIGA_MAC_VER_07:
2651 case RTL_GIGA_MAC_VER_08:
2652 case RTL_GIGA_MAC_VER_09:
2653 rtl8102e_hw_phy_config(ioaddr);
2654 break;
2655 case RTL_GIGA_MAC_VER_11:
2656 rtl8168bb_hw_phy_config(ioaddr);
2657 break;
2658 case RTL_GIGA_MAC_VER_12:
2659 rtl8168bef_hw_phy_config(ioaddr);
2660 break;
2661 case RTL_GIGA_MAC_VER_17:
2662 rtl8168bef_hw_phy_config(ioaddr);
2663 break;
2664 case RTL_GIGA_MAC_VER_18:
2665 rtl8168cp_1_hw_phy_config(ioaddr);
2666 break;
2667 case RTL_GIGA_MAC_VER_19:
2668 rtl8168c_1_hw_phy_config(ioaddr);
2669 break;
2670 case RTL_GIGA_MAC_VER_20:
2671 rtl8168c_2_hw_phy_config(ioaddr);
2672 break;
2673 case RTL_GIGA_MAC_VER_21:
2674 rtl8168c_3_hw_phy_config(ioaddr);
2675 break;
2676 case RTL_GIGA_MAC_VER_22:
2677 rtl8168c_4_hw_phy_config(ioaddr);
2678 break;
2679 case RTL_GIGA_MAC_VER_23:
2680 case RTL_GIGA_MAC_VER_24:
2681 rtl8168cp_2_hw_phy_config(ioaddr);
2682 break;
2683 case RTL_GIGA_MAC_VER_25:
2684 rtl8168d_1_hw_phy_config(ioaddr);
2685 break;
2686 case RTL_GIGA_MAC_VER_26:
2687 rtl8168d_2_hw_phy_config(ioaddr);
2688 break;
2689 case RTL_GIGA_MAC_VER_27:
2690 rtl8168d_3_hw_phy_config(ioaddr);
2691 break;
2692
2693 default:
2694 break;
2695 }
2696 }
2697
2698 static void rtl8169_phy_timer(unsigned long __opaque)
2699 {
2700 struct net_device *dev = (struct net_device *)__opaque;
2701 struct rtl8169_private *tp = netdev_priv(dev);
2702 struct timer_list *timer = &tp->timer;
2703 void __iomem *ioaddr = tp->mmio_addr;
2704 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2705
2706 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2707
2708 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2709 return;
2710
2711 spin_lock_irq(&tp->lock);
2712
2713 if (tp->phy_reset_pending(ioaddr)) {
2714 /*
2715 * A busy loop could burn quite a few cycles on nowadays CPU.
2716 * Let's delay the execution of the timer for a few ticks.
2717 */
2718 timeout = HZ/10;
2719 goto out_mod_timer;
2720 }
2721
2722 if (tp->link_ok(ioaddr))
2723 goto out_unlock;
2724
2725 if (netif_msg_link(tp))
2726 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
2727
2728 tp->phy_reset_enable(ioaddr);
2729
2730 out_mod_timer:
2731 mod_timer(timer, jiffies + timeout);
2732 out_unlock:
2733 spin_unlock_irq(&tp->lock);
2734 }
2735
2736 static inline void rtl8169_delete_timer(struct net_device *dev)
2737 {
2738 struct rtl8169_private *tp = netdev_priv(dev);
2739 struct timer_list *timer = &tp->timer;
2740
2741 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2742 return;
2743
2744 del_timer_sync(timer);
2745 }
2746
2747 static inline void rtl8169_request_timer(struct net_device *dev)
2748 {
2749 struct rtl8169_private *tp = netdev_priv(dev);
2750 struct timer_list *timer = &tp->timer;
2751
2752 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2753 return;
2754
2755 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2756 }
2757
2758 #ifdef CONFIG_NET_POLL_CONTROLLER
2759 /*
2760 * Polling 'interrupt' - used by things like netconsole to send skbs
2761 * without having to re-enable interrupts. It's not called while
2762 * the interrupt routine is executing.
2763 */
2764 static void rtl8169_netpoll(struct net_device *dev)
2765 {
2766 struct rtl8169_private *tp = netdev_priv(dev);
2767 struct pci_dev *pdev = tp->pci_dev;
2768
2769 disable_irq(pdev->irq);
2770 rtl8169_interrupt(pdev->irq, dev);
2771 enable_irq(pdev->irq);
2772 }
2773 #endif
2774
2775 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2776 void __iomem *ioaddr)
2777 {
2778 iounmap(ioaddr);
2779 pci_release_regions(pdev);
2780 pci_disable_device(pdev);
2781 free_netdev(dev);
2782 }
2783
2784 static void rtl8169_phy_reset(struct net_device *dev,
2785 struct rtl8169_private *tp)
2786 {
2787 void __iomem *ioaddr = tp->mmio_addr;
2788 unsigned int i;
2789
2790 tp->phy_reset_enable(ioaddr);
2791 for (i = 0; i < 100; i++) {
2792 if (!tp->phy_reset_pending(ioaddr))
2793 return;
2794 msleep(1);
2795 }
2796 if (netif_msg_link(tp))
2797 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
2798 }
2799
2800 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2801 {
2802 void __iomem *ioaddr = tp->mmio_addr;
2803
2804 rtl_hw_phy_config(dev);
2805
2806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2807 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2808 RTL_W8(0x82, 0x01);
2809 }
2810
2811 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2812
2813 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2814 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2815
2816 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2817 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 RTL_W8(0x82, 0x01);
2819 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2820 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2821 }
2822
2823 rtl8169_phy_reset(dev, tp);
2824
2825 /*
2826 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2827 * only 8101. Don't panic.
2828 */
2829 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2830
2831 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
2832 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
2833 }
2834
2835 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2836 {
2837 void __iomem *ioaddr = tp->mmio_addr;
2838 u32 high;
2839 u32 low;
2840
2841 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2842 high = addr[4] | (addr[5] << 8);
2843
2844 spin_lock_irq(&tp->lock);
2845
2846 RTL_W8(Cfg9346, Cfg9346_Unlock);
2847
2848 RTL_W32(MAC4, high);
2849 RTL_R32(MAC4);
2850
2851 RTL_W32(MAC0, low);
2852 RTL_R32(MAC0);
2853
2854 RTL_W8(Cfg9346, Cfg9346_Lock);
2855
2856 spin_unlock_irq(&tp->lock);
2857 }
2858
2859 static int rtl_set_mac_address(struct net_device *dev, void *p)
2860 {
2861 struct rtl8169_private *tp = netdev_priv(dev);
2862 struct sockaddr *addr = p;
2863
2864 if (!is_valid_ether_addr(addr->sa_data))
2865 return -EADDRNOTAVAIL;
2866
2867 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2868
2869 rtl_rar_set(tp, dev->dev_addr);
2870
2871 return 0;
2872 }
2873
2874 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2875 {
2876 struct rtl8169_private *tp = netdev_priv(dev);
2877 struct mii_ioctl_data *data = if_mii(ifr);
2878
2879 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2880 }
2881
2882 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2883 {
2884 switch (cmd) {
2885 case SIOCGMIIPHY:
2886 data->phy_id = 32; /* Internal PHY */
2887 return 0;
2888
2889 case SIOCGMIIREG:
2890 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2891 return 0;
2892
2893 case SIOCSMIIREG:
2894 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2895 return 0;
2896 }
2897 return -EOPNOTSUPP;
2898 }
2899
2900 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2901 {
2902 return -EOPNOTSUPP;
2903 }
2904
2905 static const struct rtl_cfg_info {
2906 void (*hw_start)(struct net_device *);
2907 unsigned int region;
2908 unsigned int align;
2909 u16 intr_event;
2910 u16 napi_event;
2911 unsigned features;
2912 u8 default_ver;
2913 } rtl_cfg_infos [] = {
2914 [RTL_CFG_0] = {
2915 .hw_start = rtl_hw_start_8169,
2916 .region = 1,
2917 .align = 0,
2918 .intr_event = SYSErr | LinkChg | RxOverflow |
2919 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2920 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2921 .features = RTL_FEATURE_GMII,
2922 .default_ver = RTL_GIGA_MAC_VER_01,
2923 },
2924 [RTL_CFG_1] = {
2925 .hw_start = rtl_hw_start_8168,
2926 .region = 2,
2927 .align = 8,
2928 .intr_event = SYSErr | LinkChg | RxOverflow |
2929 TxErr | TxOK | RxOK | RxErr,
2930 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2931 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2932 .default_ver = RTL_GIGA_MAC_VER_11,
2933 },
2934 [RTL_CFG_2] = {
2935 .hw_start = rtl_hw_start_8101,
2936 .region = 2,
2937 .align = 8,
2938 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2939 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2940 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2941 .features = RTL_FEATURE_MSI,
2942 .default_ver = RTL_GIGA_MAC_VER_13,
2943 }
2944 };
2945
2946 /* Cfg9346_Unlock assumed. */
2947 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2948 const struct rtl_cfg_info *cfg)
2949 {
2950 unsigned msi = 0;
2951 u8 cfg2;
2952
2953 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2954 if (cfg->features & RTL_FEATURE_MSI) {
2955 if (pci_enable_msi(pdev)) {
2956 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2957 } else {
2958 cfg2 |= MSIEnable;
2959 msi = RTL_FEATURE_MSI;
2960 }
2961 }
2962 RTL_W8(Config2, cfg2);
2963 return msi;
2964 }
2965
2966 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2967 {
2968 if (tp->features & RTL_FEATURE_MSI) {
2969 pci_disable_msi(pdev);
2970 tp->features &= ~RTL_FEATURE_MSI;
2971 }
2972 }
2973
2974 static const struct net_device_ops rtl8169_netdev_ops = {
2975 .ndo_open = rtl8169_open,
2976 .ndo_stop = rtl8169_close,
2977 .ndo_get_stats = rtl8169_get_stats,
2978 .ndo_start_xmit = rtl8169_start_xmit,
2979 .ndo_tx_timeout = rtl8169_tx_timeout,
2980 .ndo_validate_addr = eth_validate_addr,
2981 .ndo_change_mtu = rtl8169_change_mtu,
2982 .ndo_set_mac_address = rtl_set_mac_address,
2983 .ndo_do_ioctl = rtl8169_ioctl,
2984 .ndo_set_multicast_list = rtl_set_rx_mode,
2985 #ifdef CONFIG_R8169_VLAN
2986 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2987 #endif
2988 #ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller = rtl8169_netpoll,
2990 #endif
2991
2992 };
2993
2994 static int __devinit
2995 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2996 {
2997 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2998 const unsigned int region = cfg->region;
2999 struct rtl8169_private *tp;
3000 struct mii_if_info *mii;
3001 struct net_device *dev;
3002 void __iomem *ioaddr;
3003 unsigned int i;
3004 int rc;
3005
3006 if (netif_msg_drv(&debug)) {
3007 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3008 MODULENAME, RTL8169_VERSION);
3009 }
3010
3011 dev = alloc_etherdev(sizeof (*tp));
3012 if (!dev) {
3013 if (netif_msg_drv(&debug))
3014 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3015 rc = -ENOMEM;
3016 goto out;
3017 }
3018
3019 SET_NETDEV_DEV(dev, &pdev->dev);
3020 dev->netdev_ops = &rtl8169_netdev_ops;
3021 tp = netdev_priv(dev);
3022 tp->dev = dev;
3023 tp->pci_dev = pdev;
3024 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3025
3026 mii = &tp->mii;
3027 mii->dev = dev;
3028 mii->mdio_read = rtl_mdio_read;
3029 mii->mdio_write = rtl_mdio_write;
3030 mii->phy_id_mask = 0x1f;
3031 mii->reg_num_mask = 0x1f;
3032 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3033
3034 /* disable ASPM completely as that cause random device stop working
3035 * problems as well as full system hangs for some PCIe devices users */
3036 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3037 PCIE_LINK_STATE_CLKPM);
3038
3039 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3040 rc = pci_enable_device(pdev);
3041 if (rc < 0) {
3042 if (netif_msg_probe(tp))
3043 dev_err(&pdev->dev, "enable failure\n");
3044 goto err_out_free_dev_1;
3045 }
3046
3047 rc = pci_set_mwi(pdev);
3048 if (rc < 0)
3049 goto err_out_disable_2;
3050
3051 /* make sure PCI base addr 1 is MMIO */
3052 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3053 if (netif_msg_probe(tp)) {
3054 dev_err(&pdev->dev,
3055 "region #%d not an MMIO resource, aborting\n",
3056 region);
3057 }
3058 rc = -ENODEV;
3059 goto err_out_mwi_3;
3060 }
3061
3062 /* check for weird/broken PCI region reporting */
3063 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3064 if (netif_msg_probe(tp)) {
3065 dev_err(&pdev->dev,
3066 "Invalid PCI region size(s), aborting\n");
3067 }
3068 rc = -ENODEV;
3069 goto err_out_mwi_3;
3070 }
3071
3072 rc = pci_request_regions(pdev, MODULENAME);
3073 if (rc < 0) {
3074 if (netif_msg_probe(tp))
3075 dev_err(&pdev->dev, "could not request regions.\n");
3076 goto err_out_mwi_3;
3077 }
3078
3079 tp->cp_cmd = PCIMulRW | RxChkSum;
3080
3081 if ((sizeof(dma_addr_t) > 4) &&
3082 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3083 tp->cp_cmd |= PCIDAC;
3084 dev->features |= NETIF_F_HIGHDMA;
3085 } else {
3086 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3087 if (rc < 0) {
3088 if (netif_msg_probe(tp)) {
3089 dev_err(&pdev->dev,
3090 "DMA configuration failed.\n");
3091 }
3092 goto err_out_free_res_4;
3093 }
3094 }
3095
3096 /* ioremap MMIO region */
3097 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3098 if (!ioaddr) {
3099 if (netif_msg_probe(tp))
3100 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
3101 rc = -EIO;
3102 goto err_out_free_res_4;
3103 }
3104
3105 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3106 if (!tp->pcie_cap && netif_msg_probe(tp))
3107 dev_info(&pdev->dev, "no PCI Express capability\n");
3108
3109 RTL_W16(IntrMask, 0x0000);
3110
3111 /* Soft reset the chip. */
3112 RTL_W8(ChipCmd, CmdReset);
3113
3114 /* Check that the chip has finished the reset. */
3115 for (i = 0; i < 100; i++) {
3116 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3117 break;
3118 msleep_interruptible(1);
3119 }
3120
3121 RTL_W16(IntrStatus, 0xffff);
3122
3123 pci_set_master(pdev);
3124
3125 /* Identify chip attached to board */
3126 rtl8169_get_mac_version(tp, ioaddr);
3127
3128 /* Use appropriate default if unknown */
3129 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3130 if (netif_msg_probe(tp)) {
3131 dev_notice(&pdev->dev,
3132 "unknown MAC, using family default\n");
3133 }
3134 tp->mac_version = cfg->default_ver;
3135 }
3136
3137 rtl8169_print_mac_version(tp);
3138
3139 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3140 if (tp->mac_version == rtl_chip_info[i].mac_version)
3141 break;
3142 }
3143 if (i == ARRAY_SIZE(rtl_chip_info)) {
3144 dev_err(&pdev->dev,
3145 "driver bug, MAC version not found in rtl_chip_info\n");
3146 goto err_out_msi_5;
3147 }
3148 tp->chipset = i;
3149
3150 RTL_W8(Cfg9346, Cfg9346_Unlock);
3151 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3152 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3153 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3154 tp->features |= RTL_FEATURE_WOL;
3155 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3156 tp->features |= RTL_FEATURE_WOL;
3157 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3158 RTL_W8(Cfg9346, Cfg9346_Lock);
3159
3160 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3161 (RTL_R8(PHYstatus) & TBI_Enable)) {
3162 tp->set_speed = rtl8169_set_speed_tbi;
3163 tp->get_settings = rtl8169_gset_tbi;
3164 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3165 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3166 tp->link_ok = rtl8169_tbi_link_ok;
3167 tp->do_ioctl = rtl_tbi_ioctl;
3168
3169 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3170 } else {
3171 tp->set_speed = rtl8169_set_speed_xmii;
3172 tp->get_settings = rtl8169_gset_xmii;
3173 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3174 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3175 tp->link_ok = rtl8169_xmii_link_ok;
3176 tp->do_ioctl = rtl_xmii_ioctl;
3177 }
3178
3179 spin_lock_init(&tp->lock);
3180
3181 tp->mmio_addr = ioaddr;
3182
3183 /* Get MAC address */
3184 for (i = 0; i < MAC_ADDR_LEN; i++)
3185 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3186 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3187
3188 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3189 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3190 dev->irq = pdev->irq;
3191 dev->base_addr = (unsigned long) ioaddr;
3192
3193 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3194
3195 #ifdef CONFIG_R8169_VLAN
3196 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3197 #endif
3198
3199 tp->intr_mask = 0xffff;
3200 tp->align = cfg->align;
3201 tp->hw_start = cfg->hw_start;
3202 tp->intr_event = cfg->intr_event;
3203 tp->napi_event = cfg->napi_event;
3204
3205 init_timer(&tp->timer);
3206 tp->timer.data = (unsigned long) dev;
3207 tp->timer.function = rtl8169_phy_timer;
3208
3209 rc = register_netdev(dev);
3210 if (rc < 0)
3211 goto err_out_msi_5;
3212
3213 pci_set_drvdata(pdev, dev);
3214
3215 if (netif_msg_probe(tp)) {
3216 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
3217
3218 printk(KERN_INFO "%s: %s at 0x%lx, "
3219 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3220 "XID %08x IRQ %d\n",
3221 dev->name,
3222 rtl_chip_info[tp->chipset].name,
3223 dev->base_addr,
3224 dev->dev_addr[0], dev->dev_addr[1],
3225 dev->dev_addr[2], dev->dev_addr[3],
3226 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
3227 }
3228
3229 rtl8169_init_phy(dev, tp);
3230
3231 /*
3232 * Pretend we are using VLANs; This bypasses a nasty bug where
3233 * Interrupts stop flowing on high load on 8110SCd controllers.
3234 */
3235 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3236 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3237
3238 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3239
3240 out:
3241 return rc;
3242
3243 err_out_msi_5:
3244 rtl_disable_msi(pdev, tp);
3245 iounmap(ioaddr);
3246 err_out_free_res_4:
3247 pci_release_regions(pdev);
3248 err_out_mwi_3:
3249 pci_clear_mwi(pdev);
3250 err_out_disable_2:
3251 pci_disable_device(pdev);
3252 err_out_free_dev_1:
3253 free_netdev(dev);
3254 goto out;
3255 }
3256
3257 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3258 {
3259 struct net_device *dev = pci_get_drvdata(pdev);
3260 struct rtl8169_private *tp = netdev_priv(dev);
3261
3262 flush_scheduled_work();
3263
3264 unregister_netdev(dev);
3265
3266 /* restore original MAC address */
3267 rtl_rar_set(tp, dev->perm_addr);
3268
3269 rtl_disable_msi(pdev, tp);
3270 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3271 pci_set_drvdata(pdev, NULL);
3272 }
3273
3274 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3275 unsigned int mtu)
3276 {
3277 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3278
3279 if (max_frame != 16383)
3280 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3281 "NIC may lead to frame reception errors!\n");
3282
3283 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3284 }
3285
3286 static int rtl8169_open(struct net_device *dev)
3287 {
3288 struct rtl8169_private *tp = netdev_priv(dev);
3289 struct pci_dev *pdev = tp->pci_dev;
3290 int retval = -ENOMEM;
3291
3292
3293 /*
3294 * Note that we use a magic value here, its wierd I know
3295 * its done because, some subset of rtl8169 hardware suffers from
3296 * a problem in which frames received that are longer than
3297 * the size set in RxMaxSize register return garbage sizes
3298 * when received. To avoid this we need to turn off filtering,
3299 * which is done by setting a value of 16383 in the RxMaxSize register
3300 * and allocating 16k frames to handle the largest possible rx value
3301 * thats what the magic math below does.
3302 */
3303 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3304
3305 /*
3306 * Rx and Tx desscriptors needs 256 bytes alignment.
3307 * pci_alloc_consistent provides more.
3308 */
3309 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3310 &tp->TxPhyAddr);
3311 if (!tp->TxDescArray)
3312 goto out;
3313
3314 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3315 &tp->RxPhyAddr);
3316 if (!tp->RxDescArray)
3317 goto err_free_tx_0;
3318
3319 retval = rtl8169_init_ring(dev);
3320 if (retval < 0)
3321 goto err_free_rx_1;
3322
3323 INIT_DELAYED_WORK(&tp->task, NULL);
3324
3325 smp_mb();
3326
3327 retval = request_irq(dev->irq, rtl8169_interrupt,
3328 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3329 dev->name, dev);
3330 if (retval < 0)
3331 goto err_release_ring_2;
3332
3333 napi_enable(&tp->napi);
3334
3335 rtl_hw_start(dev);
3336
3337 rtl8169_request_timer(dev);
3338
3339 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3340 out:
3341 return retval;
3342
3343 err_release_ring_2:
3344 rtl8169_rx_clear(tp);
3345 err_free_rx_1:
3346 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3347 tp->RxPhyAddr);
3348 err_free_tx_0:
3349 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3350 tp->TxPhyAddr);
3351 goto out;
3352 }
3353
3354 static void rtl8169_hw_reset(void __iomem *ioaddr)
3355 {
3356 /* Disable interrupts */
3357 rtl8169_irq_mask_and_ack(ioaddr);
3358
3359 /* Reset the chipset */
3360 RTL_W8(ChipCmd, CmdReset);
3361
3362 /* PCI commit */
3363 RTL_R8(ChipCmd);
3364 }
3365
3366 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3367 {
3368 void __iomem *ioaddr = tp->mmio_addr;
3369 u32 cfg = rtl8169_rx_config;
3370
3371 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3372 RTL_W32(RxConfig, cfg);
3373
3374 /* Set DMA burst size and Interframe Gap Time */
3375 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3376 (InterFrameGap << TxInterFrameGapShift));
3377 }
3378
3379 static void rtl_hw_start(struct net_device *dev)
3380 {
3381 struct rtl8169_private *tp = netdev_priv(dev);
3382 void __iomem *ioaddr = tp->mmio_addr;
3383 unsigned int i;
3384
3385 /* Soft reset the chip. */
3386 RTL_W8(ChipCmd, CmdReset);
3387
3388 /* Check that the chip has finished the reset. */
3389 for (i = 0; i < 100; i++) {
3390 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3391 break;
3392 msleep_interruptible(1);
3393 }
3394
3395 tp->hw_start(dev);
3396
3397 netif_start_queue(dev);
3398 }
3399
3400
3401 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3402 void __iomem *ioaddr)
3403 {
3404 /*
3405 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3406 * register to be written before TxDescAddrLow to work.
3407 * Switching from MMIO to I/O access fixes the issue as well.
3408 */
3409 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3410 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3411 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3412 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3413 }
3414
3415 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3416 {
3417 u16 cmd;
3418
3419 cmd = RTL_R16(CPlusCmd);
3420 RTL_W16(CPlusCmd, cmd);
3421 return cmd;
3422 }
3423
3424 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3425 {
3426 /* Low hurts. Let's disable the filtering. */
3427 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3428 }
3429
3430 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3431 {
3432 struct {
3433 u32 mac_version;
3434 u32 clk;
3435 u32 val;
3436 } cfg2_info [] = {
3437 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3438 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3439 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3440 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3441 }, *p = cfg2_info;
3442 unsigned int i;
3443 u32 clk;
3444
3445 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3446 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3447 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3448 RTL_W32(0x7c, p->val);
3449 break;
3450 }
3451 }
3452 }
3453
3454 static void rtl_hw_start_8169(struct net_device *dev)
3455 {
3456 struct rtl8169_private *tp = netdev_priv(dev);
3457 void __iomem *ioaddr = tp->mmio_addr;
3458 struct pci_dev *pdev = tp->pci_dev;
3459
3460 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3461 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3462 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3463 }
3464
3465 RTL_W8(Cfg9346, Cfg9346_Unlock);
3466 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3467 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3468 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3469 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3470 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3471
3472 RTL_W8(EarlyTxThres, EarlyTxThld);
3473
3474 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3475
3476 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3477 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3478 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3479 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3480 rtl_set_rx_tx_config_registers(tp);
3481
3482 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3483
3484 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3485 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3486 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3487 "Bit-3 and bit-14 MUST be 1\n");
3488 tp->cp_cmd |= (1 << 14);
3489 }
3490
3491 RTL_W16(CPlusCmd, tp->cp_cmd);
3492
3493 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3494
3495 /*
3496 * Undocumented corner. Supposedly:
3497 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3498 */
3499 RTL_W16(IntrMitigate, 0x0000);
3500
3501 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3502
3503 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3504 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3505 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3506 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3507 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3508 rtl_set_rx_tx_config_registers(tp);
3509 }
3510
3511 RTL_W8(Cfg9346, Cfg9346_Lock);
3512
3513 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3514 RTL_R8(IntrMask);
3515
3516 RTL_W32(RxMissed, 0);
3517
3518 rtl_set_rx_mode(dev);
3519
3520 /* no early-rx interrupts */
3521 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3522
3523 /* Enable all known interrupts by setting the interrupt mask. */
3524 RTL_W16(IntrMask, tp->intr_event);
3525 }
3526
3527 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3528 {
3529 struct net_device *dev = pci_get_drvdata(pdev);
3530 struct rtl8169_private *tp = netdev_priv(dev);
3531 int cap = tp->pcie_cap;
3532
3533 if (cap) {
3534 u16 ctl;
3535
3536 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3537 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3538 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3539 }
3540 }
3541
3542 static void rtl_csi_access_enable(void __iomem *ioaddr)
3543 {
3544 u32 csi;
3545
3546 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3547 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3548 }
3549
3550 struct ephy_info {
3551 unsigned int offset;
3552 u16 mask;
3553 u16 bits;
3554 };
3555
3556 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
3557 {
3558 u16 w;
3559
3560 while (len-- > 0) {
3561 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3562 rtl_ephy_write(ioaddr, e->offset, w);
3563 e++;
3564 }
3565 }
3566
3567 static void rtl_disable_clock_request(struct pci_dev *pdev)
3568 {
3569 struct net_device *dev = pci_get_drvdata(pdev);
3570 struct rtl8169_private *tp = netdev_priv(dev);
3571 int cap = tp->pcie_cap;
3572
3573 if (cap) {
3574 u16 ctl;
3575
3576 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3577 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3578 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3579 }
3580 }
3581
3582 #define R8168_CPCMD_QUIRK_MASK (\
3583 EnableBist | \
3584 Mac_dbgo_oe | \
3585 Force_half_dup | \
3586 Force_rxflow_en | \
3587 Force_txflow_en | \
3588 Cxpl_dbg_sel | \
3589 ASF | \
3590 PktCntrDisable | \
3591 Mac_dbgo_sel)
3592
3593 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3594 {
3595 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3596
3597 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3598
3599 rtl_tx_performance_tweak(pdev,
3600 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3601 }
3602
3603 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3604 {
3605 rtl_hw_start_8168bb(ioaddr, pdev);
3606
3607 RTL_W8(EarlyTxThres, EarlyTxThld);
3608
3609 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3610 }
3611
3612 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3613 {
3614 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3615
3616 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3617
3618 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3619
3620 rtl_disable_clock_request(pdev);
3621
3622 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3623 }
3624
3625 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3626 {
3627 static struct ephy_info e_info_8168cp[] = {
3628 { 0x01, 0, 0x0001 },
3629 { 0x02, 0x0800, 0x1000 },
3630 { 0x03, 0, 0x0042 },
3631 { 0x06, 0x0080, 0x0000 },
3632 { 0x07, 0, 0x2000 }
3633 };
3634
3635 rtl_csi_access_enable(ioaddr);
3636
3637 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3638
3639 __rtl_hw_start_8168cp(ioaddr, pdev);
3640 }
3641
3642 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3643 {
3644 rtl_csi_access_enable(ioaddr);
3645
3646 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3647
3648 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3649
3650 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3651 }
3652
3653 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3654 {
3655 rtl_csi_access_enable(ioaddr);
3656
3657 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3658
3659 /* Magic. */
3660 RTL_W8(DBG_REG, 0x20);
3661
3662 RTL_W8(EarlyTxThres, EarlyTxThld);
3663
3664 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3665
3666 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3667 }
3668
3669 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3670 {
3671 static struct ephy_info e_info_8168c_1[] = {
3672 { 0x02, 0x0800, 0x1000 },
3673 { 0x03, 0, 0x0002 },
3674 { 0x06, 0x0080, 0x0000 }
3675 };
3676
3677 rtl_csi_access_enable(ioaddr);
3678
3679 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3680
3681 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3682
3683 __rtl_hw_start_8168cp(ioaddr, pdev);
3684 }
3685
3686 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3687 {
3688 static struct ephy_info e_info_8168c_2[] = {
3689 { 0x01, 0, 0x0001 },
3690 { 0x03, 0x0400, 0x0220 }
3691 };
3692
3693 rtl_csi_access_enable(ioaddr);
3694
3695 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3696
3697 __rtl_hw_start_8168cp(ioaddr, pdev);
3698 }
3699
3700 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3701 {
3702 rtl_hw_start_8168c_2(ioaddr, pdev);
3703 }
3704
3705 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3706 {
3707 rtl_csi_access_enable(ioaddr);
3708
3709 __rtl_hw_start_8168cp(ioaddr, pdev);
3710 }
3711
3712 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3713 {
3714 rtl_csi_access_enable(ioaddr);
3715
3716 rtl_disable_clock_request(pdev);
3717
3718 RTL_W8(EarlyTxThres, EarlyTxThld);
3719
3720 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3721
3722 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3723 }
3724
3725 static void rtl_hw_start_8168(struct net_device *dev)
3726 {
3727 struct rtl8169_private *tp = netdev_priv(dev);
3728 void __iomem *ioaddr = tp->mmio_addr;
3729 struct pci_dev *pdev = tp->pci_dev;
3730
3731 RTL_W8(Cfg9346, Cfg9346_Unlock);
3732
3733 RTL_W8(EarlyTxThres, EarlyTxThld);
3734
3735 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3736
3737 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3738
3739 RTL_W16(CPlusCmd, tp->cp_cmd);
3740
3741 RTL_W16(IntrMitigate, 0x5151);
3742
3743 /* Work around for RxFIFO overflow. */
3744 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3745 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3746 tp->intr_event |= RxFIFOOver | PCSTimeout;
3747 tp->intr_event &= ~RxOverflow;
3748 }
3749
3750 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3751
3752 rtl_set_rx_mode(dev);
3753
3754 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3755 (InterFrameGap << TxInterFrameGapShift));
3756
3757 RTL_R8(IntrMask);
3758
3759 switch (tp->mac_version) {
3760 case RTL_GIGA_MAC_VER_11:
3761 rtl_hw_start_8168bb(ioaddr, pdev);
3762 break;
3763
3764 case RTL_GIGA_MAC_VER_12:
3765 case RTL_GIGA_MAC_VER_17:
3766 rtl_hw_start_8168bef(ioaddr, pdev);
3767 break;
3768
3769 case RTL_GIGA_MAC_VER_18:
3770 rtl_hw_start_8168cp_1(ioaddr, pdev);
3771 break;
3772
3773 case RTL_GIGA_MAC_VER_19:
3774 rtl_hw_start_8168c_1(ioaddr, pdev);
3775 break;
3776
3777 case RTL_GIGA_MAC_VER_20:
3778 rtl_hw_start_8168c_2(ioaddr, pdev);
3779 break;
3780
3781 case RTL_GIGA_MAC_VER_21:
3782 rtl_hw_start_8168c_3(ioaddr, pdev);
3783 break;
3784
3785 case RTL_GIGA_MAC_VER_22:
3786 rtl_hw_start_8168c_4(ioaddr, pdev);
3787 break;
3788
3789 case RTL_GIGA_MAC_VER_23:
3790 rtl_hw_start_8168cp_2(ioaddr, pdev);
3791 break;
3792
3793 case RTL_GIGA_MAC_VER_24:
3794 rtl_hw_start_8168cp_3(ioaddr, pdev);
3795 break;
3796
3797 case RTL_GIGA_MAC_VER_25:
3798 case RTL_GIGA_MAC_VER_26:
3799 case RTL_GIGA_MAC_VER_27:
3800 rtl_hw_start_8168d(ioaddr, pdev);
3801 break;
3802
3803 default:
3804 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3805 dev->name, tp->mac_version);
3806 break;
3807 }
3808
3809 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3810
3811 RTL_W8(Cfg9346, Cfg9346_Lock);
3812
3813 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3814
3815 RTL_W16(IntrMask, tp->intr_event);
3816 }
3817
3818 #define R810X_CPCMD_QUIRK_MASK (\
3819 EnableBist | \
3820 Mac_dbgo_oe | \
3821 Force_half_dup | \
3822 Force_rxflow_en | \
3823 Force_txflow_en | \
3824 Cxpl_dbg_sel | \
3825 ASF | \
3826 PktCntrDisable | \
3827 PCIDAC | \
3828 PCIMulRW)
3829
3830 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3831 {
3832 static struct ephy_info e_info_8102e_1[] = {
3833 { 0x01, 0, 0x6e65 },
3834 { 0x02, 0, 0x091f },
3835 { 0x03, 0, 0xc2f9 },
3836 { 0x06, 0, 0xafb5 },
3837 { 0x07, 0, 0x0e00 },
3838 { 0x19, 0, 0xec80 },
3839 { 0x01, 0, 0x2e65 },
3840 { 0x01, 0, 0x6e65 }
3841 };
3842 u8 cfg1;
3843
3844 rtl_csi_access_enable(ioaddr);
3845
3846 RTL_W8(DBG_REG, FIX_NAK_1);
3847
3848 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3849
3850 RTL_W8(Config1,
3851 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3852 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3853
3854 cfg1 = RTL_R8(Config1);
3855 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3856 RTL_W8(Config1, cfg1 & ~LEDS0);
3857
3858 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3859
3860 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3861 }
3862
3863 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3864 {
3865 rtl_csi_access_enable(ioaddr);
3866
3867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3868
3869 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3870 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3871
3872 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3873 }
3874
3875 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3876 {
3877 rtl_hw_start_8102e_2(ioaddr, pdev);
3878
3879 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3880 }
3881
3882 static void rtl_hw_start_8101(struct net_device *dev)
3883 {
3884 struct rtl8169_private *tp = netdev_priv(dev);
3885 void __iomem *ioaddr = tp->mmio_addr;
3886 struct pci_dev *pdev = tp->pci_dev;
3887
3888 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3889 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3890 int cap = tp->pcie_cap;
3891
3892 if (cap) {
3893 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3894 PCI_EXP_DEVCTL_NOSNOOP_EN);
3895 }
3896 }
3897
3898 switch (tp->mac_version) {
3899 case RTL_GIGA_MAC_VER_07:
3900 rtl_hw_start_8102e_1(ioaddr, pdev);
3901 break;
3902
3903 case RTL_GIGA_MAC_VER_08:
3904 rtl_hw_start_8102e_3(ioaddr, pdev);
3905 break;
3906
3907 case RTL_GIGA_MAC_VER_09:
3908 rtl_hw_start_8102e_2(ioaddr, pdev);
3909 break;
3910 }
3911
3912 RTL_W8(Cfg9346, Cfg9346_Unlock);
3913
3914 RTL_W8(EarlyTxThres, EarlyTxThld);
3915
3916 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3917
3918 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3919
3920 RTL_W16(CPlusCmd, tp->cp_cmd);
3921
3922 RTL_W16(IntrMitigate, 0x0000);
3923
3924 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3925
3926 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3927 rtl_set_rx_tx_config_registers(tp);
3928
3929 RTL_W8(Cfg9346, Cfg9346_Lock);
3930
3931 RTL_R8(IntrMask);
3932
3933 rtl_set_rx_mode(dev);
3934
3935 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3936
3937 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3938
3939 RTL_W16(IntrMask, tp->intr_event);
3940 }
3941
3942 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3943 {
3944 struct rtl8169_private *tp = netdev_priv(dev);
3945 int ret = 0;
3946
3947 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3948 return -EINVAL;
3949
3950 dev->mtu = new_mtu;
3951
3952 if (!netif_running(dev))
3953 goto out;
3954
3955 rtl8169_down(dev);
3956
3957 rtl8169_set_rxbufsize(tp, dev->mtu);
3958
3959 ret = rtl8169_init_ring(dev);
3960 if (ret < 0)
3961 goto out;
3962
3963 napi_enable(&tp->napi);
3964
3965 rtl_hw_start(dev);
3966
3967 rtl8169_request_timer(dev);
3968
3969 out:
3970 return ret;
3971 }
3972
3973 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3974 {
3975 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3976 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3977 }
3978
3979 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3980 struct sk_buff **sk_buff, struct RxDesc *desc)
3981 {
3982 struct pci_dev *pdev = tp->pci_dev;
3983
3984 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3985 PCI_DMA_FROMDEVICE);
3986 dev_kfree_skb(*sk_buff);
3987 *sk_buff = NULL;
3988 rtl8169_make_unusable_by_asic(desc);
3989 }
3990
3991 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3992 {
3993 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3994
3995 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3996 }
3997
3998 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3999 u32 rx_buf_sz)
4000 {
4001 desc->addr = cpu_to_le64(mapping);
4002 wmb();
4003 rtl8169_mark_to_asic(desc, rx_buf_sz);
4004 }
4005
4006 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
4007 struct net_device *dev,
4008 struct RxDesc *desc, int rx_buf_sz,
4009 unsigned int align, gfp_t gfp)
4010 {
4011 struct sk_buff *skb;
4012 dma_addr_t mapping;
4013 unsigned int pad;
4014
4015 pad = align ? align : NET_IP_ALIGN;
4016
4017 skb = __netdev_alloc_skb(dev, rx_buf_sz + pad, gfp);
4018 if (!skb)
4019 goto err_out;
4020
4021 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
4022
4023 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
4024 PCI_DMA_FROMDEVICE);
4025
4026 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4027 out:
4028 return skb;
4029
4030 err_out:
4031 rtl8169_make_unusable_by_asic(desc);
4032 goto out;
4033 }
4034
4035 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4036 {
4037 unsigned int i;
4038
4039 for (i = 0; i < NUM_RX_DESC; i++) {
4040 if (tp->Rx_skbuff[i]) {
4041 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4042 tp->RxDescArray + i);
4043 }
4044 }
4045 }
4046
4047 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4048 u32 start, u32 end, gfp_t gfp)
4049 {
4050 u32 cur;
4051
4052 for (cur = start; end - cur != 0; cur++) {
4053 struct sk_buff *skb;
4054 unsigned int i = cur % NUM_RX_DESC;
4055
4056 WARN_ON((s32)(end - cur) < 0);
4057
4058 if (tp->Rx_skbuff[i])
4059 continue;
4060
4061 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4062 tp->RxDescArray + i,
4063 tp->rx_buf_sz, tp->align, gfp);
4064 if (!skb)
4065 break;
4066
4067 tp->Rx_skbuff[i] = skb;
4068 }
4069 return cur - start;
4070 }
4071
4072 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4073 {
4074 desc->opts1 |= cpu_to_le32(RingEnd);
4075 }
4076
4077 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4078 {
4079 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4080 }
4081
4082 static int rtl8169_init_ring(struct net_device *dev)
4083 {
4084 struct rtl8169_private *tp = netdev_priv(dev);
4085
4086 rtl8169_init_ring_indexes(tp);
4087
4088 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4089 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4090
4091 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC, GFP_KERNEL) != NUM_RX_DESC)
4092 goto err_out;
4093
4094 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4095
4096 return 0;
4097
4098 err_out:
4099 rtl8169_rx_clear(tp);
4100 return -ENOMEM;
4101 }
4102
4103 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4104 struct TxDesc *desc)
4105 {
4106 unsigned int len = tx_skb->len;
4107
4108 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4109 desc->opts1 = 0x00;
4110 desc->opts2 = 0x00;
4111 desc->addr = 0x00;
4112 tx_skb->len = 0;
4113 }
4114
4115 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4116 {
4117 unsigned int i;
4118
4119 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4120 unsigned int entry = i % NUM_TX_DESC;
4121 struct ring_info *tx_skb = tp->tx_skb + entry;
4122 unsigned int len = tx_skb->len;
4123
4124 if (len) {
4125 struct sk_buff *skb = tx_skb->skb;
4126
4127 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4128 tp->TxDescArray + entry);
4129 if (skb) {
4130 dev_kfree_skb(skb);
4131 tx_skb->skb = NULL;
4132 }
4133 tp->dev->stats.tx_dropped++;
4134 }
4135 }
4136 tp->cur_tx = tp->dirty_tx = 0;
4137 }
4138
4139 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4140 {
4141 struct rtl8169_private *tp = netdev_priv(dev);
4142
4143 PREPARE_DELAYED_WORK(&tp->task, task);
4144 schedule_delayed_work(&tp->task, 4);
4145 }
4146
4147 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4148 {
4149 struct rtl8169_private *tp = netdev_priv(dev);
4150 void __iomem *ioaddr = tp->mmio_addr;
4151
4152 synchronize_irq(dev->irq);
4153
4154 /* Wait for any pending NAPI task to complete */
4155 napi_disable(&tp->napi);
4156
4157 rtl8169_irq_mask_and_ack(ioaddr);
4158
4159 tp->intr_mask = 0xffff;
4160 RTL_W16(IntrMask, tp->intr_event);
4161 napi_enable(&tp->napi);
4162 }
4163
4164 static void rtl8169_reinit_task(struct work_struct *work)
4165 {
4166 struct rtl8169_private *tp =
4167 container_of(work, struct rtl8169_private, task.work);
4168 struct net_device *dev = tp->dev;
4169 int ret;
4170
4171 rtnl_lock();
4172
4173 if (!netif_running(dev))
4174 goto out_unlock;
4175
4176 rtl8169_wait_for_quiescence(dev);
4177 rtl8169_close(dev);
4178
4179 ret = rtl8169_open(dev);
4180 if (unlikely(ret < 0)) {
4181 if (net_ratelimit() && netif_msg_drv(tp)) {
4182 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
4183 " Rescheduling.\n", dev->name, ret);
4184 }
4185 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4186 }
4187
4188 out_unlock:
4189 rtnl_unlock();
4190 }
4191
4192 static void rtl8169_reset_task(struct work_struct *work)
4193 {
4194 struct rtl8169_private *tp =
4195 container_of(work, struct rtl8169_private, task.work);
4196 struct net_device *dev = tp->dev;
4197
4198 rtnl_lock();
4199
4200 if (!netif_running(dev))
4201 goto out_unlock;
4202
4203 rtl8169_wait_for_quiescence(dev);
4204
4205 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4206 rtl8169_tx_clear(tp);
4207
4208 if (tp->dirty_rx == tp->cur_rx) {
4209 rtl8169_init_ring_indexes(tp);
4210 rtl_hw_start(dev);
4211 netif_wake_queue(dev);
4212 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4213 } else {
4214 if (net_ratelimit() && netif_msg_intr(tp)) {
4215 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
4216 dev->name);
4217 }
4218 rtl8169_schedule_work(dev, rtl8169_reset_task);
4219 }
4220
4221 out_unlock:
4222 rtnl_unlock();
4223 }
4224
4225 static void rtl8169_tx_timeout(struct net_device *dev)
4226 {
4227 struct rtl8169_private *tp = netdev_priv(dev);
4228
4229 rtl8169_hw_reset(tp->mmio_addr);
4230
4231 /* Let's wait a bit while any (async) irq lands on */
4232 rtl8169_schedule_work(dev, rtl8169_reset_task);
4233 }
4234
4235 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4236 u32 opts1)
4237 {
4238 struct skb_shared_info *info = skb_shinfo(skb);
4239 unsigned int cur_frag, entry;
4240 struct TxDesc * uninitialized_var(txd);
4241
4242 entry = tp->cur_tx;
4243 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4244 skb_frag_t *frag = info->frags + cur_frag;
4245 dma_addr_t mapping;
4246 u32 status, len;
4247 void *addr;
4248
4249 entry = (entry + 1) % NUM_TX_DESC;
4250
4251 txd = tp->TxDescArray + entry;
4252 len = frag->size;
4253 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4254 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4255
4256 /* anti gcc 2.95.3 bugware (sic) */
4257 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4258
4259 txd->opts1 = cpu_to_le32(status);
4260 txd->addr = cpu_to_le64(mapping);
4261
4262 tp->tx_skb[entry].len = len;
4263 }
4264
4265 if (cur_frag) {
4266 tp->tx_skb[entry].skb = skb;
4267 txd->opts1 |= cpu_to_le32(LastFrag);
4268 }
4269
4270 return cur_frag;
4271 }
4272
4273 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4274 {
4275 if (dev->features & NETIF_F_TSO) {
4276 u32 mss = skb_shinfo(skb)->gso_size;
4277
4278 if (mss)
4279 return LargeSend | ((mss & MSSMask) << MSSShift);
4280 }
4281 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4282 const struct iphdr *ip = ip_hdr(skb);
4283
4284 if (ip->protocol == IPPROTO_TCP)
4285 return IPCS | TCPCS;
4286 else if (ip->protocol == IPPROTO_UDP)
4287 return IPCS | UDPCS;
4288 WARN_ON(1); /* we need a WARN() */
4289 }
4290 return 0;
4291 }
4292
4293 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4294 struct net_device *dev)
4295 {
4296 struct rtl8169_private *tp = netdev_priv(dev);
4297 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4298 struct TxDesc *txd = tp->TxDescArray + entry;
4299 void __iomem *ioaddr = tp->mmio_addr;
4300 dma_addr_t mapping;
4301 u32 status, len;
4302 u32 opts1;
4303
4304 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4305 if (netif_msg_drv(tp)) {
4306 printk(KERN_ERR
4307 "%s: BUG! Tx Ring full when queue awake!\n",
4308 dev->name);
4309 }
4310 goto err_stop;
4311 }
4312
4313 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4314 goto err_stop;
4315
4316 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4317
4318 frags = rtl8169_xmit_frags(tp, skb, opts1);
4319 if (frags) {
4320 len = skb_headlen(skb);
4321 opts1 |= FirstFrag;
4322 } else {
4323 len = skb->len;
4324 opts1 |= FirstFrag | LastFrag;
4325 tp->tx_skb[entry].skb = skb;
4326 }
4327
4328 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4329
4330 tp->tx_skb[entry].len = len;
4331 txd->addr = cpu_to_le64(mapping);
4332 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4333
4334 wmb();
4335
4336 /* anti gcc 2.95.3 bugware (sic) */
4337 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4338 txd->opts1 = cpu_to_le32(status);
4339
4340 tp->cur_tx += frags + 1;
4341
4342 wmb();
4343
4344 RTL_W8(TxPoll, NPQ); /* set polling bit */
4345
4346 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4347 netif_stop_queue(dev);
4348 smp_rmb();
4349 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4350 netif_wake_queue(dev);
4351 }
4352
4353 return NETDEV_TX_OK;
4354
4355 err_stop:
4356 netif_stop_queue(dev);
4357 dev->stats.tx_dropped++;
4358 return NETDEV_TX_BUSY;
4359 }
4360
4361 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4362 {
4363 struct rtl8169_private *tp = netdev_priv(dev);
4364 struct pci_dev *pdev = tp->pci_dev;
4365 void __iomem *ioaddr = tp->mmio_addr;
4366 u16 pci_status, pci_cmd;
4367
4368 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4369 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4370
4371 if (netif_msg_intr(tp)) {
4372 printk(KERN_ERR
4373 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4374 dev->name, pci_cmd, pci_status);
4375 }
4376
4377 /*
4378 * The recovery sequence below admits a very elaborated explanation:
4379 * - it seems to work;
4380 * - I did not see what else could be done;
4381 * - it makes iop3xx happy.
4382 *
4383 * Feel free to adjust to your needs.
4384 */
4385 if (pdev->broken_parity_status)
4386 pci_cmd &= ~PCI_COMMAND_PARITY;
4387 else
4388 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4389
4390 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4391
4392 pci_write_config_word(pdev, PCI_STATUS,
4393 pci_status & (PCI_STATUS_DETECTED_PARITY |
4394 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4395 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4396
4397 /* The infamous DAC f*ckup only happens at boot time */
4398 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4399 if (netif_msg_intr(tp))
4400 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
4401 tp->cp_cmd &= ~PCIDAC;
4402 RTL_W16(CPlusCmd, tp->cp_cmd);
4403 dev->features &= ~NETIF_F_HIGHDMA;
4404 }
4405
4406 rtl8169_hw_reset(ioaddr);
4407
4408 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4409 }
4410
4411 static void rtl8169_tx_interrupt(struct net_device *dev,
4412 struct rtl8169_private *tp,
4413 void __iomem *ioaddr)
4414 {
4415 unsigned int dirty_tx, tx_left;
4416
4417 dirty_tx = tp->dirty_tx;
4418 smp_rmb();
4419 tx_left = tp->cur_tx - dirty_tx;
4420
4421 while (tx_left > 0) {
4422 unsigned int entry = dirty_tx % NUM_TX_DESC;
4423 struct ring_info *tx_skb = tp->tx_skb + entry;
4424 u32 len = tx_skb->len;
4425 u32 status;
4426
4427 rmb();
4428 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4429 if (status & DescOwn)
4430 break;
4431
4432 dev->stats.tx_bytes += len;
4433 dev->stats.tx_packets++;
4434
4435 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4436
4437 if (status & LastFrag) {
4438 dev_kfree_skb(tx_skb->skb);
4439 tx_skb->skb = NULL;
4440 }
4441 dirty_tx++;
4442 tx_left--;
4443 }
4444
4445 if (tp->dirty_tx != dirty_tx) {
4446 tp->dirty_tx = dirty_tx;
4447 smp_wmb();
4448 if (netif_queue_stopped(dev) &&
4449 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4450 netif_wake_queue(dev);
4451 }
4452 /*
4453 * 8168 hack: TxPoll requests are lost when the Tx packets are
4454 * too close. Let's kick an extra TxPoll request when a burst
4455 * of start_xmit activity is detected (if it is not detected,
4456 * it is slow enough). -- FR
4457 */
4458 smp_rmb();
4459 if (tp->cur_tx != dirty_tx)
4460 RTL_W8(TxPoll, NPQ);
4461 }
4462 }
4463
4464 static inline int rtl8169_fragmented_frame(u32 status)
4465 {
4466 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4467 }
4468
4469 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4470 {
4471 u32 opts1 = le32_to_cpu(desc->opts1);
4472 u32 status = opts1 & RxProtoMask;
4473
4474 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4475 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4476 ((status == RxProtoIP) && !(opts1 & IPFail)))
4477 skb->ip_summed = CHECKSUM_UNNECESSARY;
4478 else
4479 skb->ip_summed = CHECKSUM_NONE;
4480 }
4481
4482 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4483 struct rtl8169_private *tp, int pkt_size,
4484 dma_addr_t addr)
4485 {
4486 struct sk_buff *skb;
4487 bool done = false;
4488
4489 if (pkt_size >= rx_copybreak)
4490 goto out;
4491
4492 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
4493 if (!skb)
4494 goto out;
4495
4496 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4497 PCI_DMA_FROMDEVICE);
4498 skb_reserve(skb, NET_IP_ALIGN);
4499 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4500 *sk_buff = skb;
4501 done = true;
4502 out:
4503 return done;
4504 }
4505
4506 static int rtl8169_rx_interrupt(struct net_device *dev,
4507 struct rtl8169_private *tp,
4508 void __iomem *ioaddr, u32 budget)
4509 {
4510 unsigned int cur_rx, rx_left;
4511 unsigned int delta, count;
4512
4513 cur_rx = tp->cur_rx;
4514 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4515 rx_left = min(rx_left, budget);
4516
4517 for (; rx_left > 0; rx_left--, cur_rx++) {
4518 unsigned int entry = cur_rx % NUM_RX_DESC;
4519 struct RxDesc *desc = tp->RxDescArray + entry;
4520 u32 status;
4521
4522 rmb();
4523 status = le32_to_cpu(desc->opts1);
4524
4525 if (status & DescOwn)
4526 break;
4527 if (unlikely(status & RxRES)) {
4528 if (netif_msg_rx_err(tp)) {
4529 printk(KERN_INFO
4530 "%s: Rx ERROR. status = %08x\n",
4531 dev->name, status);
4532 }
4533 dev->stats.rx_errors++;
4534 if (status & (RxRWT | RxRUNT))
4535 dev->stats.rx_length_errors++;
4536 if (status & RxCRC)
4537 dev->stats.rx_crc_errors++;
4538 if (status & RxFOVF) {
4539 rtl8169_schedule_work(dev, rtl8169_reset_task);
4540 dev->stats.rx_fifo_errors++;
4541 }
4542 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4543 } else {
4544 struct sk_buff *skb = tp->Rx_skbuff[entry];
4545 dma_addr_t addr = le64_to_cpu(desc->addr);
4546 int pkt_size = (status & 0x00001FFF) - 4;
4547 struct pci_dev *pdev = tp->pci_dev;
4548
4549 /*
4550 * The driver does not support incoming fragmented
4551 * frames. They are seen as a symptom of over-mtu
4552 * sized frames.
4553 */
4554 if (unlikely(rtl8169_fragmented_frame(status))) {
4555 dev->stats.rx_dropped++;
4556 dev->stats.rx_length_errors++;
4557 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4558 continue;
4559 }
4560
4561 rtl8169_rx_csum(skb, desc);
4562
4563 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4564 pci_dma_sync_single_for_device(pdev, addr,
4565 pkt_size, PCI_DMA_FROMDEVICE);
4566 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4567 } else {
4568 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4569 PCI_DMA_FROMDEVICE);
4570 tp->Rx_skbuff[entry] = NULL;
4571 }
4572
4573 skb_put(skb, pkt_size);
4574 skb->protocol = eth_type_trans(skb, dev);
4575
4576 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4577 netif_receive_skb(skb);
4578
4579 dev->stats.rx_bytes += pkt_size;
4580 dev->stats.rx_packets++;
4581 }
4582
4583 /* Work around for AMD plateform. */
4584 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4585 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4586 desc->opts2 = 0;
4587 cur_rx++;
4588 }
4589 }
4590
4591 count = cur_rx - tp->cur_rx;
4592 tp->cur_rx = cur_rx;
4593
4594 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx, GFP_ATOMIC);
4595 if (!delta && count && netif_msg_intr(tp))
4596 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
4597 tp->dirty_rx += delta;
4598
4599 /*
4600 * FIXME: until there is periodic timer to try and refill the ring,
4601 * a temporary shortage may definitely kill the Rx process.
4602 * - disable the asic to try and avoid an overflow and kick it again
4603 * after refill ?
4604 * - how do others driver handle this condition (Uh oh...).
4605 */
4606 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
4607 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
4608
4609 return count;
4610 }
4611
4612 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4613 {
4614 struct net_device *dev = dev_instance;
4615 struct rtl8169_private *tp = netdev_priv(dev);
4616 void __iomem *ioaddr = tp->mmio_addr;
4617 int handled = 0;
4618 int status;
4619
4620 /* loop handling interrupts until we have no new ones or
4621 * we hit a invalid/hotplug case.
4622 */
4623 status = RTL_R16(IntrStatus);
4624 while (status && status != 0xffff) {
4625 handled = 1;
4626
4627 /* Handle all of the error cases first. These will reset
4628 * the chip, so just exit the loop.
4629 */
4630 if (unlikely(!netif_running(dev))) {
4631 rtl8169_asic_down(ioaddr);
4632 break;
4633 }
4634
4635 /* Work around for rx fifo overflow */
4636 if (unlikely(status & RxFIFOOver) &&
4637 (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4638 tp->mac_version == RTL_GIGA_MAC_VER_22)) {
4639 netif_stop_queue(dev);
4640 rtl8169_tx_timeout(dev);
4641 break;
4642 }
4643
4644 if (unlikely(status & SYSErr)) {
4645 rtl8169_pcierr_interrupt(dev);
4646 break;
4647 }
4648
4649 if (status & LinkChg)
4650 rtl8169_check_link_status(dev, tp, ioaddr);
4651
4652 /* We need to see the lastest version of tp->intr_mask to
4653 * avoid ignoring an MSI interrupt and having to wait for
4654 * another event which may never come.
4655 */
4656 smp_rmb();
4657 if (status & tp->intr_mask & tp->napi_event) {
4658 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4659 tp->intr_mask = ~tp->napi_event;
4660
4661 if (likely(napi_schedule_prep(&tp->napi)))
4662 __napi_schedule(&tp->napi);
4663 else if (netif_msg_intr(tp)) {
4664 printk(KERN_INFO "%s: interrupt %04x in poll\n",
4665 dev->name, status);
4666 }
4667 }
4668
4669 /* We only get a new MSI interrupt when all active irq
4670 * sources on the chip have been acknowledged. So, ack
4671 * everything we've seen and check if new sources have become
4672 * active to avoid blocking all interrupts from the chip.
4673 */
4674 RTL_W16(IntrStatus,
4675 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4676 status = RTL_R16(IntrStatus);
4677 }
4678
4679 return IRQ_RETVAL(handled);
4680 }
4681
4682 static int rtl8169_poll(struct napi_struct *napi, int budget)
4683 {
4684 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4685 struct net_device *dev = tp->dev;
4686 void __iomem *ioaddr = tp->mmio_addr;
4687 int work_done;
4688
4689 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4690 rtl8169_tx_interrupt(dev, tp, ioaddr);
4691
4692 if (work_done < budget) {
4693 napi_complete(napi);
4694
4695 /* We need for force the visibility of tp->intr_mask
4696 * for other CPUs, as we can loose an MSI interrupt
4697 * and potentially wait for a retransmit timeout if we don't.
4698 * The posted write to IntrMask is safe, as it will
4699 * eventually make it to the chip and we won't loose anything
4700 * until it does.
4701 */
4702 tp->intr_mask = 0xffff;
4703 wmb();
4704 RTL_W16(IntrMask, tp->intr_event);
4705 }
4706
4707 return work_done;
4708 }
4709
4710 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4711 {
4712 struct rtl8169_private *tp = netdev_priv(dev);
4713
4714 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4715 return;
4716
4717 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4718 RTL_W32(RxMissed, 0);
4719 }
4720
4721 static void rtl8169_down(struct net_device *dev)
4722 {
4723 struct rtl8169_private *tp = netdev_priv(dev);
4724 void __iomem *ioaddr = tp->mmio_addr;
4725 unsigned int intrmask;
4726
4727 rtl8169_delete_timer(dev);
4728
4729 netif_stop_queue(dev);
4730
4731 napi_disable(&tp->napi);
4732
4733 core_down:
4734 spin_lock_irq(&tp->lock);
4735
4736 rtl8169_asic_down(ioaddr);
4737
4738 rtl8169_rx_missed(dev, ioaddr);
4739
4740 spin_unlock_irq(&tp->lock);
4741
4742 synchronize_irq(dev->irq);
4743
4744 /* Give a racing hard_start_xmit a few cycles to complete. */
4745 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4746
4747 /*
4748 * And now for the 50k$ question: are IRQ disabled or not ?
4749 *
4750 * Two paths lead here:
4751 * 1) dev->close
4752 * -> netif_running() is available to sync the current code and the
4753 * IRQ handler. See rtl8169_interrupt for details.
4754 * 2) dev->change_mtu
4755 * -> rtl8169_poll can not be issued again and re-enable the
4756 * interruptions. Let's simply issue the IRQ down sequence again.
4757 *
4758 * No loop if hotpluged or major error (0xffff).
4759 */
4760 intrmask = RTL_R16(IntrMask);
4761 if (intrmask && (intrmask != 0xffff))
4762 goto core_down;
4763
4764 rtl8169_tx_clear(tp);
4765
4766 rtl8169_rx_clear(tp);
4767 }
4768
4769 static int rtl8169_close(struct net_device *dev)
4770 {
4771 struct rtl8169_private *tp = netdev_priv(dev);
4772 struct pci_dev *pdev = tp->pci_dev;
4773
4774 /* update counters before going down */
4775 rtl8169_update_counters(dev);
4776
4777 rtl8169_down(dev);
4778
4779 free_irq(dev->irq, dev);
4780
4781 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4782 tp->RxPhyAddr);
4783 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4784 tp->TxPhyAddr);
4785 tp->TxDescArray = NULL;
4786 tp->RxDescArray = NULL;
4787
4788 return 0;
4789 }
4790
4791 static void rtl_set_rx_mode(struct net_device *dev)
4792 {
4793 struct rtl8169_private *tp = netdev_priv(dev);
4794 void __iomem *ioaddr = tp->mmio_addr;
4795 unsigned long flags;
4796 u32 mc_filter[2]; /* Multicast hash filter */
4797 int rx_mode;
4798 u32 tmp = 0;
4799
4800 if (dev->flags & IFF_PROMISC) {
4801 /* Unconditionally log net taps. */
4802 if (netif_msg_link(tp)) {
4803 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
4804 dev->name);
4805 }
4806 rx_mode =
4807 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4808 AcceptAllPhys;
4809 mc_filter[1] = mc_filter[0] = 0xffffffff;
4810 } else if ((dev->mc_count > multicast_filter_limit)
4811 || (dev->flags & IFF_ALLMULTI)) {
4812 /* Too many to filter perfectly -- accept all multicasts. */
4813 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4814 mc_filter[1] = mc_filter[0] = 0xffffffff;
4815 } else {
4816 struct dev_mc_list *mclist;
4817 unsigned int i;
4818
4819 rx_mode = AcceptBroadcast | AcceptMyPhys;
4820 mc_filter[1] = mc_filter[0] = 0;
4821 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
4822 i++, mclist = mclist->next) {
4823 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4824 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4825 rx_mode |= AcceptMulticast;
4826 }
4827 }
4828
4829 spin_lock_irqsave(&tp->lock, flags);
4830
4831 tmp = rtl8169_rx_config | rx_mode |
4832 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4833
4834 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4835 u32 data = mc_filter[0];
4836
4837 mc_filter[0] = swab32(mc_filter[1]);
4838 mc_filter[1] = swab32(data);
4839 }
4840
4841 RTL_W32(MAR0 + 4, mc_filter[1]);
4842 RTL_W32(MAR0 + 0, mc_filter[0]);
4843
4844 RTL_W32(RxConfig, tmp);
4845
4846 spin_unlock_irqrestore(&tp->lock, flags);
4847 }
4848
4849 /**
4850 * rtl8169_get_stats - Get rtl8169 read/write statistics
4851 * @dev: The Ethernet Device to get statistics for
4852 *
4853 * Get TX/RX statistics for rtl8169
4854 */
4855 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4856 {
4857 struct rtl8169_private *tp = netdev_priv(dev);
4858 void __iomem *ioaddr = tp->mmio_addr;
4859 unsigned long flags;
4860
4861 if (netif_running(dev)) {
4862 spin_lock_irqsave(&tp->lock, flags);
4863 rtl8169_rx_missed(dev, ioaddr);
4864 spin_unlock_irqrestore(&tp->lock, flags);
4865 }
4866
4867 return &dev->stats;
4868 }
4869
4870 static void rtl8169_net_suspend(struct net_device *dev)
4871 {
4872 if (!netif_running(dev))
4873 return;
4874
4875 netif_device_detach(dev);
4876 netif_stop_queue(dev);
4877 }
4878
4879 #ifdef CONFIG_PM
4880
4881 static int rtl8169_suspend(struct device *device)
4882 {
4883 struct pci_dev *pdev = to_pci_dev(device);
4884 struct net_device *dev = pci_get_drvdata(pdev);
4885
4886 rtl8169_net_suspend(dev);
4887
4888 return 0;
4889 }
4890
4891 static int rtl8169_resume(struct device *device)
4892 {
4893 struct pci_dev *pdev = to_pci_dev(device);
4894 struct net_device *dev = pci_get_drvdata(pdev);
4895
4896 if (!netif_running(dev))
4897 goto out;
4898
4899 netif_device_attach(dev);
4900
4901 rtl8169_schedule_work(dev, rtl8169_reset_task);
4902 out:
4903 return 0;
4904 }
4905
4906 static struct dev_pm_ops rtl8169_pm_ops = {
4907 .suspend = rtl8169_suspend,
4908 .resume = rtl8169_resume,
4909 .freeze = rtl8169_suspend,
4910 .thaw = rtl8169_resume,
4911 .poweroff = rtl8169_suspend,
4912 .restore = rtl8169_resume,
4913 };
4914
4915 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4916
4917 #else /* !CONFIG_PM */
4918
4919 #define RTL8169_PM_OPS NULL
4920
4921 #endif /* !CONFIG_PM */
4922
4923 static void rtl_shutdown(struct pci_dev *pdev)
4924 {
4925 struct net_device *dev = pci_get_drvdata(pdev);
4926 struct rtl8169_private *tp = netdev_priv(dev);
4927 void __iomem *ioaddr = tp->mmio_addr;
4928
4929 rtl8169_net_suspend(dev);
4930
4931 /* restore original MAC address */
4932 rtl_rar_set(tp, dev->perm_addr);
4933
4934 spin_lock_irq(&tp->lock);
4935
4936 rtl8169_asic_down(ioaddr);
4937
4938 spin_unlock_irq(&tp->lock);
4939
4940 if (system_state == SYSTEM_POWER_OFF) {
4941 /* WoL fails with some 8168 when the receiver is disabled. */
4942 if (tp->features & RTL_FEATURE_WOL) {
4943 pci_clear_master(pdev);
4944
4945 RTL_W8(ChipCmd, CmdRxEnb);
4946 /* PCI commit */
4947 RTL_R8(ChipCmd);
4948 }
4949
4950 pci_wake_from_d3(pdev, true);
4951 pci_set_power_state(pdev, PCI_D3hot);
4952 }
4953 }
4954
4955 static struct pci_driver rtl8169_pci_driver = {
4956 .name = MODULENAME,
4957 .id_table = rtl8169_pci_tbl,
4958 .probe = rtl8169_init_one,
4959 .remove = __devexit_p(rtl8169_remove_one),
4960 .shutdown = rtl_shutdown,
4961 .driver.pm = RTL8169_PM_OPS,
4962 };
4963
4964 static int __init rtl8169_init_module(void)
4965 {
4966 return pci_register_driver(&rtl8169_pci_driver);
4967 }
4968
4969 static void __exit rtl8169_cleanup_module(void)
4970 {
4971 pci_unregister_driver(&rtl8169_pci_driver);
4972 }
4973
4974 module_init(rtl8169_init_module);
4975 module_exit(rtl8169_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree