USB: EHCI: Refactor "if (handshake()) state = HC_STATE_HALT"
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / host / ehci-sched.c
blob38c606c13db16c7ec9f009659a1bdb674f6ec7e1
1 /*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
50 switch (hc32_to_cpu(ehci, tag)) {
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
63 /* caller must hold ehci->lock */
64 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
66 union ehci_shadow *prev_p = &ehci->pshadow[frame];
67 __hc32 *hw_p = &ehci->periodic[frame];
68 union ehci_shadow here = *prev_p;
70 /* find predecessor of "ptr"; hw and shadow lists are in sync */
71 while (here.ptr && here.ptr != ptr) {
72 prev_p = periodic_next_shadow(ehci, prev_p,
73 Q_NEXT_TYPE(ehci, *hw_p));
74 hw_p = here.hw_next;
75 here = *prev_p;
77 /* an interrupt entry (at list end) could have been shared */
78 if (!here.ptr)
79 return;
81 /* update shadow and hardware lists ... the old "next" pointers
82 * from ptr may still be in use, the caller updates them.
84 *prev_p = *periodic_next_shadow(ehci, &here,
85 Q_NEXT_TYPE(ehci, *hw_p));
86 *hw_p = *here.hw_next;
89 /* how many of the uframe's 125 usecs are allocated? */
90 static unsigned short
91 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
93 __hc32 *hw_p = &ehci->periodic [frame];
94 union ehci_shadow *q = &ehci->pshadow [frame];
95 unsigned usecs = 0;
97 while (q->ptr) {
98 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
99 case Q_TYPE_QH:
100 /* is it in the S-mask? */
101 if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
102 usecs += q->qh->usecs;
103 /* ... or C-mask? */
104 if (q->qh->hw_info2 & cpu_to_hc32(ehci,
105 1 << (8 + uframe)))
106 usecs += q->qh->c_usecs;
107 hw_p = &q->qh->hw_next;
108 q = &q->qh->qh_next;
109 break;
110 // case Q_TYPE_FSTN:
111 default:
112 /* for "save place" FSTNs, count the relevant INTR
113 * bandwidth from the previous frame
115 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
116 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
118 hw_p = &q->fstn->hw_next;
119 q = &q->fstn->fstn_next;
120 break;
121 case Q_TYPE_ITD:
122 if (q->itd->hw_transaction[uframe])
123 usecs += q->itd->stream->usecs;
124 hw_p = &q->itd->hw_next;
125 q = &q->itd->itd_next;
126 break;
127 case Q_TYPE_SITD:
128 /* is it in the S-mask? (count SPLIT, DATA) */
129 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
130 1 << uframe)) {
131 if (q->sitd->hw_fullspeed_ep &
132 cpu_to_hc32(ehci, 1<<31))
133 usecs += q->sitd->stream->usecs;
134 else /* worst case for OUT start-split */
135 usecs += HS_USECS_ISO (188);
138 /* ... C-mask? (count CSPLIT, DATA) */
139 if (q->sitd->hw_uframe &
140 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
141 /* worst case for IN complete-split */
142 usecs += q->sitd->stream->c_usecs;
145 hw_p = &q->sitd->hw_next;
146 q = &q->sitd->sitd_next;
147 break;
150 #ifdef DEBUG
151 if (usecs > 100)
152 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
153 frame * 8 + uframe, usecs);
154 #endif
155 return usecs;
158 /*-------------------------------------------------------------------------*/
160 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
162 if (!dev1->tt || !dev2->tt)
163 return 0;
164 if (dev1->tt != dev2->tt)
165 return 0;
166 if (dev1->tt->multi)
167 return dev1->ttport == dev2->ttport;
168 else
169 return 1;
172 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
174 /* Which uframe does the low/fullspeed transfer start in?
176 * The parameter is the mask of ssplits in "H-frame" terms
177 * and this returns the transfer start uframe in "B-frame" terms,
178 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
179 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
180 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
182 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
184 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
185 if (!smask) {
186 ehci_err(ehci, "invalid empty smask!\n");
187 /* uframe 7 can't have bw so this will indicate failure */
188 return 7;
190 return ffs(smask) - 1;
193 static const unsigned char
194 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
196 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
197 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
199 int i;
200 for (i=0; i<7; i++) {
201 if (max_tt_usecs[i] < tt_usecs[i]) {
202 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
203 tt_usecs[i] = max_tt_usecs[i];
208 /* How many of the tt's periodic downstream 1000 usecs are allocated?
210 * While this measures the bandwidth in terms of usecs/uframe,
211 * the low/fullspeed bus has no notion of uframes, so any particular
212 * low/fullspeed transfer can "carry over" from one uframe to the next,
213 * since the TT just performs downstream transfers in sequence.
215 * For example two separate 100 usec transfers can start in the same uframe,
216 * and the second one would "carry over" 75 usecs into the next uframe.
218 static void
219 periodic_tt_usecs (
220 struct ehci_hcd *ehci,
221 struct usb_device *dev,
222 unsigned frame,
223 unsigned short tt_usecs[8]
226 __hc32 *hw_p = &ehci->periodic [frame];
227 union ehci_shadow *q = &ehci->pshadow [frame];
228 unsigned char uf;
230 memset(tt_usecs, 0, 16);
232 while (q->ptr) {
233 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
234 case Q_TYPE_ITD:
235 hw_p = &q->itd->hw_next;
236 q = &q->itd->itd_next;
237 continue;
238 case Q_TYPE_QH:
239 if (same_tt(dev, q->qh->dev)) {
240 uf = tt_start_uframe(ehci, q->qh->hw_info2);
241 tt_usecs[uf] += q->qh->tt_usecs;
243 hw_p = &q->qh->hw_next;
244 q = &q->qh->qh_next;
245 continue;
246 case Q_TYPE_SITD:
247 if (same_tt(dev, q->sitd->urb->dev)) {
248 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
249 tt_usecs[uf] += q->sitd->stream->tt_usecs;
251 hw_p = &q->sitd->hw_next;
252 q = &q->sitd->sitd_next;
253 continue;
254 // case Q_TYPE_FSTN:
255 default:
256 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
257 frame);
258 hw_p = &q->fstn->hw_next;
259 q = &q->fstn->fstn_next;
263 carryover_tt_bandwidth(tt_usecs);
265 if (max_tt_usecs[7] < tt_usecs[7])
266 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
267 frame, tt_usecs[7] - max_tt_usecs[7]);
271 * Return true if the device's tt's downstream bus is available for a
272 * periodic transfer of the specified length (usecs), starting at the
273 * specified frame/uframe. Note that (as summarized in section 11.19
274 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
275 * uframe.
277 * The uframe parameter is when the fullspeed/lowspeed transfer
278 * should be executed in "B-frame" terms, which is the same as the
279 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
280 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
281 * See the EHCI spec sec 4.5 and fig 4.7.
283 * This checks if the full/lowspeed bus, at the specified starting uframe,
284 * has the specified bandwidth available, according to rules listed
285 * in USB 2.0 spec section 11.18.1 fig 11-60.
287 * This does not check if the transfer would exceed the max ssplit
288 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
289 * since proper scheduling limits ssplits to less than 16 per uframe.
291 static int tt_available (
292 struct ehci_hcd *ehci,
293 unsigned period,
294 struct usb_device *dev,
295 unsigned frame,
296 unsigned uframe,
297 u16 usecs
300 if ((period == 0) || (uframe >= 7)) /* error */
301 return 0;
303 for (; frame < ehci->periodic_size; frame += period) {
304 unsigned short tt_usecs[8];
306 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
308 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
309 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
310 frame, usecs, uframe,
311 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
312 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
314 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
315 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
316 frame, uframe);
317 return 0;
320 /* special case for isoc transfers larger than 125us:
321 * the first and each subsequent fully used uframe
322 * must be empty, so as to not illegally delay
323 * already scheduled transactions
325 if (125 < usecs) {
326 int ufs = (usecs / 125) - 1;
327 int i;
328 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
329 if (0 < tt_usecs[i]) {
330 ehci_vdbg(ehci,
331 "multi-uframe xfer can't fit "
332 "in frame %d uframe %d\n",
333 frame, i);
334 return 0;
338 tt_usecs[uframe] += usecs;
340 carryover_tt_bandwidth(tt_usecs);
342 /* fail if the carryover pushed bw past the last uframe's limit */
343 if (max_tt_usecs[7] < tt_usecs[7]) {
344 ehci_vdbg(ehci,
345 "tt unavailable usecs %d frame %d uframe %d\n",
346 usecs, frame, uframe);
347 return 0;
351 return 1;
354 #else
356 /* return true iff the device's transaction translator is available
357 * for a periodic transfer starting at the specified frame, using
358 * all the uframes in the mask.
360 static int tt_no_collision (
361 struct ehci_hcd *ehci,
362 unsigned period,
363 struct usb_device *dev,
364 unsigned frame,
365 u32 uf_mask
368 if (period == 0) /* error */
369 return 0;
371 /* note bandwidth wastage: split never follows csplit
372 * (different dev or endpoint) until the next uframe.
373 * calling convention doesn't make that distinction.
375 for (; frame < ehci->periodic_size; frame += period) {
376 union ehci_shadow here;
377 __hc32 type;
379 here = ehci->pshadow [frame];
380 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
381 while (here.ptr) {
382 switch (hc32_to_cpu(ehci, type)) {
383 case Q_TYPE_ITD:
384 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
385 here = here.itd->itd_next;
386 continue;
387 case Q_TYPE_QH:
388 if (same_tt (dev, here.qh->dev)) {
389 u32 mask;
391 mask = hc32_to_cpu(ehci,
392 here.qh->hw_info2);
393 /* "knows" no gap is needed */
394 mask |= mask >> 8;
395 if (mask & uf_mask)
396 break;
398 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
399 here = here.qh->qh_next;
400 continue;
401 case Q_TYPE_SITD:
402 if (same_tt (dev, here.sitd->urb->dev)) {
403 u16 mask;
405 mask = hc32_to_cpu(ehci, here.sitd
406 ->hw_uframe);
407 /* FIXME assumes no gap for IN! */
408 mask |= mask >> 8;
409 if (mask & uf_mask)
410 break;
412 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
413 here = here.sitd->sitd_next;
414 continue;
415 // case Q_TYPE_FSTN:
416 default:
417 ehci_dbg (ehci,
418 "periodic frame %d bogus type %d\n",
419 frame, type);
422 /* collision or error */
423 return 0;
427 /* no collision */
428 return 1;
431 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
433 /*-------------------------------------------------------------------------*/
435 static int enable_periodic (struct ehci_hcd *ehci)
437 u32 cmd;
438 int status;
440 /* did clearing PSE did take effect yet?
441 * takes effect only at frame boundaries...
443 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
444 STS_PSS, 0, 9 * 125);
445 if (status)
446 return status;
448 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
449 ehci_writel(ehci, cmd, &ehci->regs->command);
450 /* posted write ... PSS happens later */
451 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
453 /* make sure ehci_work scans these */
454 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
455 % (ehci->periodic_size << 3);
456 return 0;
459 static int disable_periodic (struct ehci_hcd *ehci)
461 u32 cmd;
462 int status;
464 /* did setting PSE not take effect yet?
465 * takes effect only at frame boundaries...
467 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
468 STS_PSS, STS_PSS, 9 * 125);
469 if (status)
470 return status;
472 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
473 ehci_writel(ehci, cmd, &ehci->regs->command);
474 /* posted write ... */
476 ehci->next_uframe = -1;
477 return 0;
480 /*-------------------------------------------------------------------------*/
482 /* periodic schedule slots have iso tds (normal or split) first, then a
483 * sparse tree for active interrupt transfers.
485 * this just links in a qh; caller guarantees uframe masks are set right.
486 * no FSTN support (yet; ehci 0.96+)
488 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
490 unsigned i;
491 unsigned period = qh->period;
493 dev_dbg (&qh->dev->dev,
494 "link qh%d-%04x/%p start %d [%d/%d us]\n",
495 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
496 qh, qh->start, qh->usecs, qh->c_usecs);
498 /* high bandwidth, or otherwise every microframe */
499 if (period == 0)
500 period = 1;
502 for (i = qh->start; i < ehci->periodic_size; i += period) {
503 union ehci_shadow *prev = &ehci->pshadow[i];
504 __hc32 *hw_p = &ehci->periodic[i];
505 union ehci_shadow here = *prev;
506 __hc32 type = 0;
508 /* skip the iso nodes at list head */
509 while (here.ptr) {
510 type = Q_NEXT_TYPE(ehci, *hw_p);
511 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
512 break;
513 prev = periodic_next_shadow(ehci, prev, type);
514 hw_p = &here.qh->hw_next;
515 here = *prev;
518 /* sorting each branch by period (slow-->fast)
519 * enables sharing interior tree nodes
521 while (here.ptr && qh != here.qh) {
522 if (qh->period > here.qh->period)
523 break;
524 prev = &here.qh->qh_next;
525 hw_p = &here.qh->hw_next;
526 here = *prev;
528 /* link in this qh, unless some earlier pass did that */
529 if (qh != here.qh) {
530 qh->qh_next = here;
531 if (here.qh)
532 qh->hw_next = *hw_p;
533 wmb ();
534 prev->qh = qh;
535 *hw_p = QH_NEXT (ehci, qh->qh_dma);
538 qh->qh_state = QH_STATE_LINKED;
539 qh_get (qh);
541 /* update per-qh bandwidth for usbfs */
542 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
543 ? ((qh->usecs + qh->c_usecs) / qh->period)
544 : (qh->usecs * 8);
546 /* maybe enable periodic schedule processing */
547 if (!ehci->periodic_sched++)
548 return enable_periodic (ehci);
550 return 0;
553 static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
555 unsigned i;
556 unsigned period;
558 // FIXME:
559 // IF this isn't high speed
560 // and this qh is active in the current uframe
561 // (and overlay token SplitXstate is false?)
562 // THEN
563 // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
565 /* high bandwidth, or otherwise part of every microframe */
566 if ((period = qh->period) == 0)
567 period = 1;
569 for (i = qh->start; i < ehci->periodic_size; i += period)
570 periodic_unlink (ehci, i, qh);
572 /* update per-qh bandwidth for usbfs */
573 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
574 ? ((qh->usecs + qh->c_usecs) / qh->period)
575 : (qh->usecs * 8);
577 dev_dbg (&qh->dev->dev,
578 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
579 qh->period,
580 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
581 qh, qh->start, qh->usecs, qh->c_usecs);
583 /* qh->qh_next still "live" to HC */
584 qh->qh_state = QH_STATE_UNLINK;
585 qh->qh_next.ptr = NULL;
586 qh_put (qh);
588 /* maybe turn off periodic schedule */
589 ehci->periodic_sched--;
590 if (!ehci->periodic_sched)
591 (void) disable_periodic (ehci);
594 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
596 unsigned wait;
598 qh_unlink_periodic (ehci, qh);
600 /* simple/paranoid: always delay, expecting the HC needs to read
601 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
602 * expect khubd to clean up after any CSPLITs we won't issue.
603 * active high speed queues may need bigger delays...
605 if (list_empty (&qh->qtd_list)
606 || (cpu_to_hc32(ehci, QH_CMASK)
607 & qh->hw_info2) != 0)
608 wait = 2;
609 else
610 wait = 55; /* worst case: 3 * 1024 */
612 udelay (wait);
613 qh->qh_state = QH_STATE_IDLE;
614 qh->hw_next = EHCI_LIST_END(ehci);
615 wmb ();
618 /*-------------------------------------------------------------------------*/
620 static int check_period (
621 struct ehci_hcd *ehci,
622 unsigned frame,
623 unsigned uframe,
624 unsigned period,
625 unsigned usecs
627 int claimed;
629 /* complete split running into next frame?
630 * given FSTN support, we could sometimes check...
632 if (uframe >= 8)
633 return 0;
636 * 80% periodic == 100 usec/uframe available
637 * convert "usecs we need" to "max already claimed"
639 usecs = 100 - usecs;
641 /* we "know" 2 and 4 uframe intervals were rejected; so
642 * for period 0, check _every_ microframe in the schedule.
644 if (unlikely (period == 0)) {
645 do {
646 for (uframe = 0; uframe < 7; uframe++) {
647 claimed = periodic_usecs (ehci, frame, uframe);
648 if (claimed > usecs)
649 return 0;
651 } while ((frame += 1) < ehci->periodic_size);
653 /* just check the specified uframe, at that period */
654 } else {
655 do {
656 claimed = periodic_usecs (ehci, frame, uframe);
657 if (claimed > usecs)
658 return 0;
659 } while ((frame += period) < ehci->periodic_size);
662 // success!
663 return 1;
666 static int check_intr_schedule (
667 struct ehci_hcd *ehci,
668 unsigned frame,
669 unsigned uframe,
670 const struct ehci_qh *qh,
671 __hc32 *c_maskp
674 int retval = -ENOSPC;
675 u8 mask = 0;
677 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
678 goto done;
680 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
681 goto done;
682 if (!qh->c_usecs) {
683 retval = 0;
684 *c_maskp = 0;
685 goto done;
688 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
689 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
690 qh->tt_usecs)) {
691 unsigned i;
693 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
694 for (i=uframe+1; i<8 && i<uframe+4; i++)
695 if (!check_period (ehci, frame, i,
696 qh->period, qh->c_usecs))
697 goto done;
698 else
699 mask |= 1 << i;
701 retval = 0;
703 *c_maskp = cpu_to_hc32(ehci, mask << 8);
705 #else
706 /* Make sure this tt's buffer is also available for CSPLITs.
707 * We pessimize a bit; probably the typical full speed case
708 * doesn't need the second CSPLIT.
710 * NOTE: both SPLIT and CSPLIT could be checked in just
711 * one smart pass...
713 mask = 0x03 << (uframe + qh->gap_uf);
714 *c_maskp = cpu_to_hc32(ehci, mask << 8);
716 mask |= 1 << uframe;
717 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
718 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
719 qh->period, qh->c_usecs))
720 goto done;
721 if (!check_period (ehci, frame, uframe + qh->gap_uf,
722 qh->period, qh->c_usecs))
723 goto done;
724 retval = 0;
726 #endif
727 done:
728 return retval;
731 /* "first fit" scheduling policy used the first time through,
732 * or when the previous schedule slot can't be re-used.
734 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
736 int status;
737 unsigned uframe;
738 __hc32 c_mask;
739 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
741 qh_refresh(ehci, qh);
742 qh->hw_next = EHCI_LIST_END(ehci);
743 frame = qh->start;
745 /* reuse the previous schedule slots, if we can */
746 if (frame < qh->period) {
747 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
748 status = check_intr_schedule (ehci, frame, --uframe,
749 qh, &c_mask);
750 } else {
751 uframe = 0;
752 c_mask = 0;
753 status = -ENOSPC;
756 /* else scan the schedule to find a group of slots such that all
757 * uframes have enough periodic bandwidth available.
759 if (status) {
760 /* "normal" case, uframing flexible except with splits */
761 if (qh->period) {
762 frame = qh->period - 1;
763 do {
764 for (uframe = 0; uframe < 8; uframe++) {
765 status = check_intr_schedule (ehci,
766 frame, uframe, qh,
767 &c_mask);
768 if (status == 0)
769 break;
771 } while (status && frame--);
773 /* qh->period == 0 means every uframe */
774 } else {
775 frame = 0;
776 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
778 if (status)
779 goto done;
780 qh->start = frame;
782 /* reset S-frame and (maybe) C-frame masks */
783 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
784 qh->hw_info2 |= qh->period
785 ? cpu_to_hc32(ehci, 1 << uframe)
786 : cpu_to_hc32(ehci, QH_SMASK);
787 qh->hw_info2 |= c_mask;
788 } else
789 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
791 /* stuff into the periodic schedule */
792 status = qh_link_periodic (ehci, qh);
793 done:
794 return status;
797 static int intr_submit (
798 struct ehci_hcd *ehci,
799 struct urb *urb,
800 struct list_head *qtd_list,
801 gfp_t mem_flags
803 unsigned epnum;
804 unsigned long flags;
805 struct ehci_qh *qh;
806 int status;
807 struct list_head empty;
809 /* get endpoint and transfer/schedule data */
810 epnum = urb->ep->desc.bEndpointAddress;
812 spin_lock_irqsave (&ehci->lock, flags);
814 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
815 &ehci_to_hcd(ehci)->flags))) {
816 status = -ESHUTDOWN;
817 goto done_not_linked;
819 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
820 if (unlikely(status))
821 goto done_not_linked;
823 /* get qh and force any scheduling errors */
824 INIT_LIST_HEAD (&empty);
825 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
826 if (qh == NULL) {
827 status = -ENOMEM;
828 goto done;
830 if (qh->qh_state == QH_STATE_IDLE) {
831 if ((status = qh_schedule (ehci, qh)) != 0)
832 goto done;
835 /* then queue the urb's tds to the qh */
836 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
837 BUG_ON (qh == NULL);
839 /* ... update usbfs periodic stats */
840 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
842 done:
843 if (unlikely(status))
844 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
845 done_not_linked:
846 spin_unlock_irqrestore (&ehci->lock, flags);
847 if (status)
848 qtd_list_free (ehci, urb, qtd_list);
850 return status;
853 /*-------------------------------------------------------------------------*/
855 /* ehci_iso_stream ops work with both ITD and SITD */
857 static struct ehci_iso_stream *
858 iso_stream_alloc (gfp_t mem_flags)
860 struct ehci_iso_stream *stream;
862 stream = kzalloc(sizeof *stream, mem_flags);
863 if (likely (stream != NULL)) {
864 INIT_LIST_HEAD(&stream->td_list);
865 INIT_LIST_HEAD(&stream->free_list);
866 stream->next_uframe = -1;
867 stream->refcount = 1;
869 return stream;
872 static void
873 iso_stream_init (
874 struct ehci_hcd *ehci,
875 struct ehci_iso_stream *stream,
876 struct usb_device *dev,
877 int pipe,
878 unsigned interval
881 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
883 u32 buf1;
884 unsigned epnum, maxp;
885 int is_input;
886 long bandwidth;
889 * this might be a "high bandwidth" highspeed endpoint,
890 * as encoded in the ep descriptor's wMaxPacket field
892 epnum = usb_pipeendpoint (pipe);
893 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
894 maxp = usb_maxpacket(dev, pipe, !is_input);
895 if (is_input) {
896 buf1 = (1 << 11);
897 } else {
898 buf1 = 0;
901 /* knows about ITD vs SITD */
902 if (dev->speed == USB_SPEED_HIGH) {
903 unsigned multi = hb_mult(maxp);
905 stream->highspeed = 1;
907 maxp = max_packet(maxp);
908 buf1 |= maxp;
909 maxp *= multi;
911 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
912 stream->buf1 = cpu_to_hc32(ehci, buf1);
913 stream->buf2 = cpu_to_hc32(ehci, multi);
915 /* usbfs wants to report the average usecs per frame tied up
916 * when transfers on this endpoint are scheduled ...
918 stream->usecs = HS_USECS_ISO (maxp);
919 bandwidth = stream->usecs * 8;
920 bandwidth /= 1 << (interval - 1);
922 } else {
923 u32 addr;
924 int think_time;
925 int hs_transfers;
927 addr = dev->ttport << 24;
928 if (!ehci_is_TDI(ehci)
929 || (dev->tt->hub !=
930 ehci_to_hcd(ehci)->self.root_hub))
931 addr |= dev->tt->hub->devnum << 16;
932 addr |= epnum << 8;
933 addr |= dev->devnum;
934 stream->usecs = HS_USECS_ISO (maxp);
935 think_time = dev->tt ? dev->tt->think_time : 0;
936 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
937 dev->speed, is_input, 1, maxp));
938 hs_transfers = max (1u, (maxp + 187) / 188);
939 if (is_input) {
940 u32 tmp;
942 addr |= 1 << 31;
943 stream->c_usecs = stream->usecs;
944 stream->usecs = HS_USECS_ISO (1);
945 stream->raw_mask = 1;
947 /* c-mask as specified in USB 2.0 11.18.4 3.c */
948 tmp = (1 << (hs_transfers + 2)) - 1;
949 stream->raw_mask |= tmp << (8 + 2);
950 } else
951 stream->raw_mask = smask_out [hs_transfers - 1];
952 bandwidth = stream->usecs + stream->c_usecs;
953 bandwidth /= 1 << (interval + 2);
955 /* stream->splits gets created from raw_mask later */
956 stream->address = cpu_to_hc32(ehci, addr);
958 stream->bandwidth = bandwidth;
960 stream->udev = dev;
962 stream->bEndpointAddress = is_input | epnum;
963 stream->interval = interval;
964 stream->maxp = maxp;
967 static void
968 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
970 stream->refcount--;
972 /* free whenever just a dev->ep reference remains.
973 * not like a QH -- no persistent state (toggle, halt)
975 if (stream->refcount == 1) {
976 int is_in;
978 // BUG_ON (!list_empty(&stream->td_list));
980 while (!list_empty (&stream->free_list)) {
981 struct list_head *entry;
983 entry = stream->free_list.next;
984 list_del (entry);
986 /* knows about ITD vs SITD */
987 if (stream->highspeed) {
988 struct ehci_itd *itd;
990 itd = list_entry (entry, struct ehci_itd,
991 itd_list);
992 dma_pool_free (ehci->itd_pool, itd,
993 itd->itd_dma);
994 } else {
995 struct ehci_sitd *sitd;
997 sitd = list_entry (entry, struct ehci_sitd,
998 sitd_list);
999 dma_pool_free (ehci->sitd_pool, sitd,
1000 sitd->sitd_dma);
1004 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1005 stream->bEndpointAddress &= 0x0f;
1006 stream->ep->hcpriv = NULL;
1008 if (stream->rescheduled) {
1009 ehci_info (ehci, "ep%d%s-iso rescheduled "
1010 "%lu times in %lu seconds\n",
1011 stream->bEndpointAddress, is_in ? "in" : "out",
1012 stream->rescheduled,
1013 ((jiffies - stream->start)/HZ)
1017 kfree(stream);
1021 static inline struct ehci_iso_stream *
1022 iso_stream_get (struct ehci_iso_stream *stream)
1024 if (likely (stream != NULL))
1025 stream->refcount++;
1026 return stream;
1029 static struct ehci_iso_stream *
1030 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1032 unsigned epnum;
1033 struct ehci_iso_stream *stream;
1034 struct usb_host_endpoint *ep;
1035 unsigned long flags;
1037 epnum = usb_pipeendpoint (urb->pipe);
1038 if (usb_pipein(urb->pipe))
1039 ep = urb->dev->ep_in[epnum];
1040 else
1041 ep = urb->dev->ep_out[epnum];
1043 spin_lock_irqsave (&ehci->lock, flags);
1044 stream = ep->hcpriv;
1046 if (unlikely (stream == NULL)) {
1047 stream = iso_stream_alloc(GFP_ATOMIC);
1048 if (likely (stream != NULL)) {
1049 /* dev->ep owns the initial refcount */
1050 ep->hcpriv = stream;
1051 stream->ep = ep;
1052 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1053 urb->interval);
1056 /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1057 } else if (unlikely (stream->hw_info1 != 0)) {
1058 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1059 urb->dev->devpath, epnum,
1060 usb_pipein(urb->pipe) ? "in" : "out");
1061 stream = NULL;
1064 /* caller guarantees an eventual matching iso_stream_put */
1065 stream = iso_stream_get (stream);
1067 spin_unlock_irqrestore (&ehci->lock, flags);
1068 return stream;
1071 /*-------------------------------------------------------------------------*/
1073 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1075 static struct ehci_iso_sched *
1076 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1078 struct ehci_iso_sched *iso_sched;
1079 int size = sizeof *iso_sched;
1081 size += packets * sizeof (struct ehci_iso_packet);
1082 iso_sched = kzalloc(size, mem_flags);
1083 if (likely (iso_sched != NULL)) {
1084 INIT_LIST_HEAD (&iso_sched->td_list);
1086 return iso_sched;
1089 static inline void
1090 itd_sched_init(
1091 struct ehci_hcd *ehci,
1092 struct ehci_iso_sched *iso_sched,
1093 struct ehci_iso_stream *stream,
1094 struct urb *urb
1097 unsigned i;
1098 dma_addr_t dma = urb->transfer_dma;
1100 /* how many uframes are needed for these transfers */
1101 iso_sched->span = urb->number_of_packets * stream->interval;
1103 /* figure out per-uframe itd fields that we'll need later
1104 * when we fit new itds into the schedule.
1106 for (i = 0; i < urb->number_of_packets; i++) {
1107 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1108 unsigned length;
1109 dma_addr_t buf;
1110 u32 trans;
1112 length = urb->iso_frame_desc [i].length;
1113 buf = dma + urb->iso_frame_desc [i].offset;
1115 trans = EHCI_ISOC_ACTIVE;
1116 trans |= buf & 0x0fff;
1117 if (unlikely (((i + 1) == urb->number_of_packets))
1118 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1119 trans |= EHCI_ITD_IOC;
1120 trans |= length << 16;
1121 uframe->transaction = cpu_to_hc32(ehci, trans);
1123 /* might need to cross a buffer page within a uframe */
1124 uframe->bufp = (buf & ~(u64)0x0fff);
1125 buf += length;
1126 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1127 uframe->cross = 1;
1131 static void
1132 iso_sched_free (
1133 struct ehci_iso_stream *stream,
1134 struct ehci_iso_sched *iso_sched
1137 if (!iso_sched)
1138 return;
1139 // caller must hold ehci->lock!
1140 list_splice (&iso_sched->td_list, &stream->free_list);
1141 kfree (iso_sched);
1144 static int
1145 itd_urb_transaction (
1146 struct ehci_iso_stream *stream,
1147 struct ehci_hcd *ehci,
1148 struct urb *urb,
1149 gfp_t mem_flags
1152 struct ehci_itd *itd;
1153 dma_addr_t itd_dma;
1154 int i;
1155 unsigned num_itds;
1156 struct ehci_iso_sched *sched;
1157 unsigned long flags;
1159 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1160 if (unlikely (sched == NULL))
1161 return -ENOMEM;
1163 itd_sched_init(ehci, sched, stream, urb);
1165 if (urb->interval < 8)
1166 num_itds = 1 + (sched->span + 7) / 8;
1167 else
1168 num_itds = urb->number_of_packets;
1170 /* allocate/init ITDs */
1171 spin_lock_irqsave (&ehci->lock, flags);
1172 for (i = 0; i < num_itds; i++) {
1174 /* free_list.next might be cache-hot ... but maybe
1175 * the HC caches it too. avoid that issue for now.
1178 /* prefer previously-allocated itds */
1179 if (likely (!list_empty(&stream->free_list))) {
1180 itd = list_entry (stream->free_list.prev,
1181 struct ehci_itd, itd_list);
1182 list_del (&itd->itd_list);
1183 itd_dma = itd->itd_dma;
1184 } else
1185 itd = NULL;
1187 if (!itd) {
1188 spin_unlock_irqrestore (&ehci->lock, flags);
1189 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1190 &itd_dma);
1191 spin_lock_irqsave (&ehci->lock, flags);
1194 if (unlikely (NULL == itd)) {
1195 iso_sched_free (stream, sched);
1196 spin_unlock_irqrestore (&ehci->lock, flags);
1197 return -ENOMEM;
1199 memset (itd, 0, sizeof *itd);
1200 itd->itd_dma = itd_dma;
1201 list_add (&itd->itd_list, &sched->td_list);
1203 spin_unlock_irqrestore (&ehci->lock, flags);
1205 /* temporarily store schedule info in hcpriv */
1206 urb->hcpriv = sched;
1207 urb->error_count = 0;
1208 return 0;
1211 /*-------------------------------------------------------------------------*/
1213 static inline int
1214 itd_slot_ok (
1215 struct ehci_hcd *ehci,
1216 u32 mod,
1217 u32 uframe,
1218 u8 usecs,
1219 u32 period
1222 uframe %= period;
1223 do {
1224 /* can't commit more than 80% periodic == 100 usec */
1225 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1226 > (100 - usecs))
1227 return 0;
1229 /* we know urb->interval is 2^N uframes */
1230 uframe += period;
1231 } while (uframe < mod);
1232 return 1;
1235 static inline int
1236 sitd_slot_ok (
1237 struct ehci_hcd *ehci,
1238 u32 mod,
1239 struct ehci_iso_stream *stream,
1240 u32 uframe,
1241 struct ehci_iso_sched *sched,
1242 u32 period_uframes
1245 u32 mask, tmp;
1246 u32 frame, uf;
1248 mask = stream->raw_mask << (uframe & 7);
1250 /* for IN, don't wrap CSPLIT into the next frame */
1251 if (mask & ~0xffff)
1252 return 0;
1254 /* this multi-pass logic is simple, but performance may
1255 * suffer when the schedule data isn't cached.
1258 /* check bandwidth */
1259 uframe %= period_uframes;
1260 do {
1261 u32 max_used;
1263 frame = uframe >> 3;
1264 uf = uframe & 7;
1266 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1267 /* The tt's fullspeed bus bandwidth must be available.
1268 * tt_available scheduling guarantees 10+% for control/bulk.
1270 if (!tt_available (ehci, period_uframes << 3,
1271 stream->udev, frame, uf, stream->tt_usecs))
1272 return 0;
1273 #else
1274 /* tt must be idle for start(s), any gap, and csplit.
1275 * assume scheduling slop leaves 10+% for control/bulk.
1277 if (!tt_no_collision (ehci, period_uframes << 3,
1278 stream->udev, frame, mask))
1279 return 0;
1280 #endif
1282 /* check starts (OUT uses more than one) */
1283 max_used = 100 - stream->usecs;
1284 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1285 if (periodic_usecs (ehci, frame, uf) > max_used)
1286 return 0;
1289 /* for IN, check CSPLIT */
1290 if (stream->c_usecs) {
1291 uf = uframe & 7;
1292 max_used = 100 - stream->c_usecs;
1293 do {
1294 tmp = 1 << uf;
1295 tmp <<= 8;
1296 if ((stream->raw_mask & tmp) == 0)
1297 continue;
1298 if (periodic_usecs (ehci, frame, uf)
1299 > max_used)
1300 return 0;
1301 } while (++uf < 8);
1304 /* we know urb->interval is 2^N uframes */
1305 uframe += period_uframes;
1306 } while (uframe < mod);
1308 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1309 return 1;
1313 * This scheduler plans almost as far into the future as it has actual
1314 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1315 * "as small as possible" to be cache-friendlier.) That limits the size
1316 * transfers you can stream reliably; avoid more than 64 msec per urb.
1317 * Also avoid queue depths of less than ehci's worst irq latency (affected
1318 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1319 * and other factors); or more than about 230 msec total (for portability,
1320 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1323 #define SCHEDULE_SLOP 10 /* frames */
1325 static int
1326 iso_stream_schedule (
1327 struct ehci_hcd *ehci,
1328 struct urb *urb,
1329 struct ehci_iso_stream *stream
1332 u32 now, start, max, period;
1333 int status;
1334 unsigned mod = ehci->periodic_size << 3;
1335 struct ehci_iso_sched *sched = urb->hcpriv;
1337 if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1338 ehci_dbg (ehci, "iso request %p too long\n", urb);
1339 status = -EFBIG;
1340 goto fail;
1343 if ((stream->depth + sched->span) > mod) {
1344 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1345 urb, stream->depth, sched->span, mod);
1346 status = -EFBIG;
1347 goto fail;
1350 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1352 /* when's the last uframe this urb could start? */
1353 max = now + mod;
1355 /* typical case: reuse current schedule. stream is still active,
1356 * and no gaps from host falling behind (irq delays etc)
1358 if (likely (!list_empty (&stream->td_list))) {
1359 start = stream->next_uframe;
1360 if (start < now)
1361 start += mod;
1362 if (likely ((start + sched->span) < max))
1363 goto ready;
1364 /* else fell behind; someday, try to reschedule */
1365 status = -EL2NSYNC;
1366 goto fail;
1369 /* need to schedule; when's the next (u)frame we could start?
1370 * this is bigger than ehci->i_thresh allows; scheduling itself
1371 * isn't free, the slop should handle reasonably slow cpus. it
1372 * can also help high bandwidth if the dma and irq loads don't
1373 * jump until after the queue is primed.
1375 start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1376 start %= mod;
1377 stream->next_uframe = start;
1379 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1381 period = urb->interval;
1382 if (!stream->highspeed)
1383 period <<= 3;
1385 /* find a uframe slot with enough bandwidth */
1386 for (; start < (stream->next_uframe + period); start++) {
1387 int enough_space;
1389 /* check schedule: enough space? */
1390 if (stream->highspeed)
1391 enough_space = itd_slot_ok (ehci, mod, start,
1392 stream->usecs, period);
1393 else {
1394 if ((start % 8) >= 6)
1395 continue;
1396 enough_space = sitd_slot_ok (ehci, mod, stream,
1397 start, sched, period);
1400 /* schedule it here if there's enough bandwidth */
1401 if (enough_space) {
1402 stream->next_uframe = start % mod;
1403 goto ready;
1407 /* no room in the schedule */
1408 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1409 list_empty (&stream->td_list) ? "" : "re",
1410 urb, now, max);
1411 status = -ENOSPC;
1413 fail:
1414 iso_sched_free (stream, sched);
1415 urb->hcpriv = NULL;
1416 return status;
1418 ready:
1419 /* report high speed start in uframes; full speed, in frames */
1420 urb->start_frame = stream->next_uframe;
1421 if (!stream->highspeed)
1422 urb->start_frame >>= 3;
1423 return 0;
1426 /*-------------------------------------------------------------------------*/
1428 static inline void
1429 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1430 struct ehci_itd *itd)
1432 int i;
1434 /* it's been recently zeroed */
1435 itd->hw_next = EHCI_LIST_END(ehci);
1436 itd->hw_bufp [0] = stream->buf0;
1437 itd->hw_bufp [1] = stream->buf1;
1438 itd->hw_bufp [2] = stream->buf2;
1440 for (i = 0; i < 8; i++)
1441 itd->index[i] = -1;
1443 /* All other fields are filled when scheduling */
1446 static inline void
1447 itd_patch(
1448 struct ehci_hcd *ehci,
1449 struct ehci_itd *itd,
1450 struct ehci_iso_sched *iso_sched,
1451 unsigned index,
1452 u16 uframe
1455 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1456 unsigned pg = itd->pg;
1458 // BUG_ON (pg == 6 && uf->cross);
1460 uframe &= 0x07;
1461 itd->index [uframe] = index;
1463 itd->hw_transaction[uframe] = uf->transaction;
1464 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1465 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1466 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1468 /* iso_frame_desc[].offset must be strictly increasing */
1469 if (unlikely (uf->cross)) {
1470 u64 bufp = uf->bufp + 4096;
1472 itd->pg = ++pg;
1473 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1474 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1478 static inline void
1479 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1481 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1482 itd->itd_next = ehci->pshadow [frame];
1483 itd->hw_next = ehci->periodic [frame];
1484 ehci->pshadow [frame].itd = itd;
1485 itd->frame = frame;
1486 wmb ();
1487 ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1490 /* fit urb's itds into the selected schedule slot; activate as needed */
1491 static int
1492 itd_link_urb (
1493 struct ehci_hcd *ehci,
1494 struct urb *urb,
1495 unsigned mod,
1496 struct ehci_iso_stream *stream
1499 int packet;
1500 unsigned next_uframe, uframe, frame;
1501 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1502 struct ehci_itd *itd;
1504 next_uframe = stream->next_uframe % mod;
1506 if (unlikely (list_empty(&stream->td_list))) {
1507 ehci_to_hcd(ehci)->self.bandwidth_allocated
1508 += stream->bandwidth;
1509 ehci_vdbg (ehci,
1510 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1511 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1512 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1513 urb->interval,
1514 next_uframe >> 3, next_uframe & 0x7);
1515 stream->start = jiffies;
1517 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1519 /* fill iTDs uframe by uframe */
1520 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1521 if (itd == NULL) {
1522 /* ASSERT: we have all necessary itds */
1523 // BUG_ON (list_empty (&iso_sched->td_list));
1525 /* ASSERT: no itds for this endpoint in this uframe */
1527 itd = list_entry (iso_sched->td_list.next,
1528 struct ehci_itd, itd_list);
1529 list_move_tail (&itd->itd_list, &stream->td_list);
1530 itd->stream = iso_stream_get (stream);
1531 itd->urb = usb_get_urb (urb);
1532 itd_init (ehci, stream, itd);
1535 uframe = next_uframe & 0x07;
1536 frame = next_uframe >> 3;
1538 itd_patch(ehci, itd, iso_sched, packet, uframe);
1540 next_uframe += stream->interval;
1541 stream->depth += stream->interval;
1542 next_uframe %= mod;
1543 packet++;
1545 /* link completed itds into the schedule */
1546 if (((next_uframe >> 3) != frame)
1547 || packet == urb->number_of_packets) {
1548 itd_link (ehci, frame % ehci->periodic_size, itd);
1549 itd = NULL;
1552 stream->next_uframe = next_uframe;
1554 /* don't need that schedule data any more */
1555 iso_sched_free (stream, iso_sched);
1556 urb->hcpriv = NULL;
1558 timer_action (ehci, TIMER_IO_WATCHDOG);
1559 if (unlikely (!ehci->periodic_sched++))
1560 return enable_periodic (ehci);
1561 return 0;
1564 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1566 /* Process and recycle a completed ITD. Return true iff its urb completed,
1567 * and hence its completion callback probably added things to the hardware
1568 * schedule.
1570 * Note that we carefully avoid recycling this descriptor until after any
1571 * completion callback runs, so that it won't be reused quickly. That is,
1572 * assuming (a) no more than two urbs per frame on this endpoint, and also
1573 * (b) only this endpoint's completions submit URBs. It seems some silicon
1574 * corrupts things if you reuse completed descriptors very quickly...
1576 static unsigned
1577 itd_complete (
1578 struct ehci_hcd *ehci,
1579 struct ehci_itd *itd
1581 struct urb *urb = itd->urb;
1582 struct usb_iso_packet_descriptor *desc;
1583 u32 t;
1584 unsigned uframe;
1585 int urb_index = -1;
1586 struct ehci_iso_stream *stream = itd->stream;
1587 struct usb_device *dev;
1588 unsigned retval = false;
1590 /* for each uframe with a packet */
1591 for (uframe = 0; uframe < 8; uframe++) {
1592 if (likely (itd->index[uframe] == -1))
1593 continue;
1594 urb_index = itd->index[uframe];
1595 desc = &urb->iso_frame_desc [urb_index];
1597 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1598 itd->hw_transaction [uframe] = 0;
1599 stream->depth -= stream->interval;
1601 /* report transfer status */
1602 if (unlikely (t & ISO_ERRS)) {
1603 urb->error_count++;
1604 if (t & EHCI_ISOC_BUF_ERR)
1605 desc->status = usb_pipein (urb->pipe)
1606 ? -ENOSR /* hc couldn't read */
1607 : -ECOMM; /* hc couldn't write */
1608 else if (t & EHCI_ISOC_BABBLE)
1609 desc->status = -EOVERFLOW;
1610 else /* (t & EHCI_ISOC_XACTERR) */
1611 desc->status = -EPROTO;
1613 /* HC need not update length with this error */
1614 if (!(t & EHCI_ISOC_BABBLE))
1615 desc->actual_length = EHCI_ITD_LENGTH (t);
1616 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1617 desc->status = 0;
1618 desc->actual_length = EHCI_ITD_LENGTH (t);
1622 /* handle completion now? */
1623 if (likely ((urb_index + 1) != urb->number_of_packets))
1624 goto done;
1626 /* ASSERT: it's really the last itd for this urb
1627 list_for_each_entry (itd, &stream->td_list, itd_list)
1628 BUG_ON (itd->urb == urb);
1631 /* give urb back to the driver; completion often (re)submits */
1632 dev = urb->dev;
1633 ehci_urb_done(ehci, urb, 0);
1634 retval = true;
1635 urb = NULL;
1636 ehci->periodic_sched--;
1637 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1639 if (unlikely (list_empty (&stream->td_list))) {
1640 ehci_to_hcd(ehci)->self.bandwidth_allocated
1641 -= stream->bandwidth;
1642 ehci_vdbg (ehci,
1643 "deschedule devp %s ep%d%s-iso\n",
1644 dev->devpath, stream->bEndpointAddress & 0x0f,
1645 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1647 iso_stream_put (ehci, stream);
1648 /* OK to recycle this ITD now that its completion callback ran. */
1649 done:
1650 usb_put_urb(urb);
1651 itd->urb = NULL;
1652 itd->stream = NULL;
1653 list_move(&itd->itd_list, &stream->free_list);
1654 iso_stream_put(ehci, stream);
1656 return retval;
1659 /*-------------------------------------------------------------------------*/
1661 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1662 gfp_t mem_flags)
1664 int status = -EINVAL;
1665 unsigned long flags;
1666 struct ehci_iso_stream *stream;
1668 /* Get iso_stream head */
1669 stream = iso_stream_find (ehci, urb);
1670 if (unlikely (stream == NULL)) {
1671 ehci_dbg (ehci, "can't get iso stream\n");
1672 return -ENOMEM;
1674 if (unlikely (urb->interval != stream->interval)) {
1675 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1676 stream->interval, urb->interval);
1677 goto done;
1680 #ifdef EHCI_URB_TRACE
1681 ehci_dbg (ehci,
1682 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1683 __FUNCTION__, urb->dev->devpath, urb,
1684 usb_pipeendpoint (urb->pipe),
1685 usb_pipein (urb->pipe) ? "in" : "out",
1686 urb->transfer_buffer_length,
1687 urb->number_of_packets, urb->interval,
1688 stream);
1689 #endif
1691 /* allocate ITDs w/o locking anything */
1692 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1693 if (unlikely (status < 0)) {
1694 ehci_dbg (ehci, "can't init itds\n");
1695 goto done;
1698 /* schedule ... need to lock */
1699 spin_lock_irqsave (&ehci->lock, flags);
1700 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1701 &ehci_to_hcd(ehci)->flags))) {
1702 status = -ESHUTDOWN;
1703 goto done_not_linked;
1705 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1706 if (unlikely(status))
1707 goto done_not_linked;
1708 status = iso_stream_schedule(ehci, urb, stream);
1709 if (likely (status == 0))
1710 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1711 else
1712 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1713 done_not_linked:
1714 spin_unlock_irqrestore (&ehci->lock, flags);
1716 done:
1717 if (unlikely (status < 0))
1718 iso_stream_put (ehci, stream);
1719 return status;
1722 /*-------------------------------------------------------------------------*/
1725 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1726 * TTs in USB 2.0 hubs. These need microframe scheduling.
1729 static inline void
1730 sitd_sched_init(
1731 struct ehci_hcd *ehci,
1732 struct ehci_iso_sched *iso_sched,
1733 struct ehci_iso_stream *stream,
1734 struct urb *urb
1737 unsigned i;
1738 dma_addr_t dma = urb->transfer_dma;
1740 /* how many frames are needed for these transfers */
1741 iso_sched->span = urb->number_of_packets * stream->interval;
1743 /* figure out per-frame sitd fields that we'll need later
1744 * when we fit new sitds into the schedule.
1746 for (i = 0; i < urb->number_of_packets; i++) {
1747 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1748 unsigned length;
1749 dma_addr_t buf;
1750 u32 trans;
1752 length = urb->iso_frame_desc [i].length & 0x03ff;
1753 buf = dma + urb->iso_frame_desc [i].offset;
1755 trans = SITD_STS_ACTIVE;
1756 if (((i + 1) == urb->number_of_packets)
1757 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1758 trans |= SITD_IOC;
1759 trans |= length << 16;
1760 packet->transaction = cpu_to_hc32(ehci, trans);
1762 /* might need to cross a buffer page within a td */
1763 packet->bufp = buf;
1764 packet->buf1 = (buf + length) & ~0x0fff;
1765 if (packet->buf1 != (buf & ~(u64)0x0fff))
1766 packet->cross = 1;
1768 /* OUT uses multiple start-splits */
1769 if (stream->bEndpointAddress & USB_DIR_IN)
1770 continue;
1771 length = (length + 187) / 188;
1772 if (length > 1) /* BEGIN vs ALL */
1773 length |= 1 << 3;
1774 packet->buf1 |= length;
1778 static int
1779 sitd_urb_transaction (
1780 struct ehci_iso_stream *stream,
1781 struct ehci_hcd *ehci,
1782 struct urb *urb,
1783 gfp_t mem_flags
1786 struct ehci_sitd *sitd;
1787 dma_addr_t sitd_dma;
1788 int i;
1789 struct ehci_iso_sched *iso_sched;
1790 unsigned long flags;
1792 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1793 if (iso_sched == NULL)
1794 return -ENOMEM;
1796 sitd_sched_init(ehci, iso_sched, stream, urb);
1798 /* allocate/init sITDs */
1799 spin_lock_irqsave (&ehci->lock, flags);
1800 for (i = 0; i < urb->number_of_packets; i++) {
1802 /* NOTE: for now, we don't try to handle wraparound cases
1803 * for IN (using sitd->hw_backpointer, like a FSTN), which
1804 * means we never need two sitds for full speed packets.
1807 /* free_list.next might be cache-hot ... but maybe
1808 * the HC caches it too. avoid that issue for now.
1811 /* prefer previously-allocated sitds */
1812 if (!list_empty(&stream->free_list)) {
1813 sitd = list_entry (stream->free_list.prev,
1814 struct ehci_sitd, sitd_list);
1815 list_del (&sitd->sitd_list);
1816 sitd_dma = sitd->sitd_dma;
1817 } else
1818 sitd = NULL;
1820 if (!sitd) {
1821 spin_unlock_irqrestore (&ehci->lock, flags);
1822 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1823 &sitd_dma);
1824 spin_lock_irqsave (&ehci->lock, flags);
1827 if (!sitd) {
1828 iso_sched_free (stream, iso_sched);
1829 spin_unlock_irqrestore (&ehci->lock, flags);
1830 return -ENOMEM;
1832 memset (sitd, 0, sizeof *sitd);
1833 sitd->sitd_dma = sitd_dma;
1834 list_add (&sitd->sitd_list, &iso_sched->td_list);
1837 /* temporarily store schedule info in hcpriv */
1838 urb->hcpriv = iso_sched;
1839 urb->error_count = 0;
1841 spin_unlock_irqrestore (&ehci->lock, flags);
1842 return 0;
1845 /*-------------------------------------------------------------------------*/
1847 static inline void
1848 sitd_patch(
1849 struct ehci_hcd *ehci,
1850 struct ehci_iso_stream *stream,
1851 struct ehci_sitd *sitd,
1852 struct ehci_iso_sched *iso_sched,
1853 unsigned index
1856 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1857 u64 bufp = uf->bufp;
1859 sitd->hw_next = EHCI_LIST_END(ehci);
1860 sitd->hw_fullspeed_ep = stream->address;
1861 sitd->hw_uframe = stream->splits;
1862 sitd->hw_results = uf->transaction;
1863 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1865 bufp = uf->bufp;
1866 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1867 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1869 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1870 if (uf->cross)
1871 bufp += 4096;
1872 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1873 sitd->index = index;
1876 static inline void
1877 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1879 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1880 sitd->sitd_next = ehci->pshadow [frame];
1881 sitd->hw_next = ehci->periodic [frame];
1882 ehci->pshadow [frame].sitd = sitd;
1883 sitd->frame = frame;
1884 wmb ();
1885 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1888 /* fit urb's sitds into the selected schedule slot; activate as needed */
1889 static int
1890 sitd_link_urb (
1891 struct ehci_hcd *ehci,
1892 struct urb *urb,
1893 unsigned mod,
1894 struct ehci_iso_stream *stream
1897 int packet;
1898 unsigned next_uframe;
1899 struct ehci_iso_sched *sched = urb->hcpriv;
1900 struct ehci_sitd *sitd;
1902 next_uframe = stream->next_uframe;
1904 if (list_empty(&stream->td_list)) {
1905 /* usbfs ignores TT bandwidth */
1906 ehci_to_hcd(ehci)->self.bandwidth_allocated
1907 += stream->bandwidth;
1908 ehci_vdbg (ehci,
1909 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1910 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1911 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1912 (next_uframe >> 3) % ehci->periodic_size,
1913 stream->interval, hc32_to_cpu(ehci, stream->splits));
1914 stream->start = jiffies;
1916 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1918 /* fill sITDs frame by frame */
1919 for (packet = 0, sitd = NULL;
1920 packet < urb->number_of_packets;
1921 packet++) {
1923 /* ASSERT: we have all necessary sitds */
1924 BUG_ON (list_empty (&sched->td_list));
1926 /* ASSERT: no itds for this endpoint in this frame */
1928 sitd = list_entry (sched->td_list.next,
1929 struct ehci_sitd, sitd_list);
1930 list_move_tail (&sitd->sitd_list, &stream->td_list);
1931 sitd->stream = iso_stream_get (stream);
1932 sitd->urb = usb_get_urb (urb);
1934 sitd_patch(ehci, stream, sitd, sched, packet);
1935 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1936 sitd);
1938 next_uframe += stream->interval << 3;
1939 stream->depth += stream->interval << 3;
1941 stream->next_uframe = next_uframe % mod;
1943 /* don't need that schedule data any more */
1944 iso_sched_free (stream, sched);
1945 urb->hcpriv = NULL;
1947 timer_action (ehci, TIMER_IO_WATCHDOG);
1948 if (!ehci->periodic_sched++)
1949 return enable_periodic (ehci);
1950 return 0;
1953 /*-------------------------------------------------------------------------*/
1955 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1956 | SITD_STS_XACT | SITD_STS_MMF)
1958 /* Process and recycle a completed SITD. Return true iff its urb completed,
1959 * and hence its completion callback probably added things to the hardware
1960 * schedule.
1962 * Note that we carefully avoid recycling this descriptor until after any
1963 * completion callback runs, so that it won't be reused quickly. That is,
1964 * assuming (a) no more than two urbs per frame on this endpoint, and also
1965 * (b) only this endpoint's completions submit URBs. It seems some silicon
1966 * corrupts things if you reuse completed descriptors very quickly...
1968 static unsigned
1969 sitd_complete (
1970 struct ehci_hcd *ehci,
1971 struct ehci_sitd *sitd
1973 struct urb *urb = sitd->urb;
1974 struct usb_iso_packet_descriptor *desc;
1975 u32 t;
1976 int urb_index = -1;
1977 struct ehci_iso_stream *stream = sitd->stream;
1978 struct usb_device *dev;
1979 unsigned retval = false;
1981 urb_index = sitd->index;
1982 desc = &urb->iso_frame_desc [urb_index];
1983 t = hc32_to_cpup(ehci, &sitd->hw_results);
1985 /* report transfer status */
1986 if (t & SITD_ERRS) {
1987 urb->error_count++;
1988 if (t & SITD_STS_DBE)
1989 desc->status = usb_pipein (urb->pipe)
1990 ? -ENOSR /* hc couldn't read */
1991 : -ECOMM; /* hc couldn't write */
1992 else if (t & SITD_STS_BABBLE)
1993 desc->status = -EOVERFLOW;
1994 else /* XACT, MMF, etc */
1995 desc->status = -EPROTO;
1996 } else {
1997 desc->status = 0;
1998 desc->actual_length = desc->length - SITD_LENGTH (t);
2000 stream->depth -= stream->interval << 3;
2002 /* handle completion now? */
2003 if ((urb_index + 1) != urb->number_of_packets)
2004 goto done;
2006 /* ASSERT: it's really the last sitd for this urb
2007 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2008 BUG_ON (sitd->urb == urb);
2011 /* give urb back to the driver; completion often (re)submits */
2012 dev = urb->dev;
2013 ehci_urb_done(ehci, urb, 0);
2014 retval = true;
2015 urb = NULL;
2016 ehci->periodic_sched--;
2017 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2019 if (list_empty (&stream->td_list)) {
2020 ehci_to_hcd(ehci)->self.bandwidth_allocated
2021 -= stream->bandwidth;
2022 ehci_vdbg (ehci,
2023 "deschedule devp %s ep%d%s-iso\n",
2024 dev->devpath, stream->bEndpointAddress & 0x0f,
2025 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2027 iso_stream_put (ehci, stream);
2028 /* OK to recycle this SITD now that its completion callback ran. */
2029 done:
2030 usb_put_urb(urb);
2031 sitd->urb = NULL;
2032 sitd->stream = NULL;
2033 list_move(&sitd->sitd_list, &stream->free_list);
2034 iso_stream_put(ehci, stream);
2036 return retval;
2040 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2041 gfp_t mem_flags)
2043 int status = -EINVAL;
2044 unsigned long flags;
2045 struct ehci_iso_stream *stream;
2047 /* Get iso_stream head */
2048 stream = iso_stream_find (ehci, urb);
2049 if (stream == NULL) {
2050 ehci_dbg (ehci, "can't get iso stream\n");
2051 return -ENOMEM;
2053 if (urb->interval != stream->interval) {
2054 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2055 stream->interval, urb->interval);
2056 goto done;
2059 #ifdef EHCI_URB_TRACE
2060 ehci_dbg (ehci,
2061 "submit %p dev%s ep%d%s-iso len %d\n",
2062 urb, urb->dev->devpath,
2063 usb_pipeendpoint (urb->pipe),
2064 usb_pipein (urb->pipe) ? "in" : "out",
2065 urb->transfer_buffer_length);
2066 #endif
2068 /* allocate SITDs */
2069 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2070 if (status < 0) {
2071 ehci_dbg (ehci, "can't init sitds\n");
2072 goto done;
2075 /* schedule ... need to lock */
2076 spin_lock_irqsave (&ehci->lock, flags);
2077 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2078 &ehci_to_hcd(ehci)->flags))) {
2079 status = -ESHUTDOWN;
2080 goto done_not_linked;
2082 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2083 if (unlikely(status))
2084 goto done_not_linked;
2085 status = iso_stream_schedule(ehci, urb, stream);
2086 if (status == 0)
2087 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2088 else
2089 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2090 done_not_linked:
2091 spin_unlock_irqrestore (&ehci->lock, flags);
2093 done:
2094 if (status < 0)
2095 iso_stream_put (ehci, stream);
2096 return status;
2099 /*-------------------------------------------------------------------------*/
2101 static void
2102 scan_periodic (struct ehci_hcd *ehci)
2104 unsigned frame, clock, now_uframe, mod;
2105 unsigned modified;
2107 mod = ehci->periodic_size << 3;
2110 * When running, scan from last scan point up to "now"
2111 * else clean up by scanning everything that's left.
2112 * Touches as few pages as possible: cache-friendly.
2114 now_uframe = ehci->next_uframe;
2115 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2116 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2117 else
2118 clock = now_uframe + mod - 1;
2119 clock %= mod;
2121 for (;;) {
2122 union ehci_shadow q, *q_p;
2123 __hc32 type, *hw_p;
2124 unsigned incomplete = false;
2126 frame = now_uframe >> 3;
2128 restart:
2129 /* scan each element in frame's queue for completions */
2130 q_p = &ehci->pshadow [frame];
2131 hw_p = &ehci->periodic [frame];
2132 q.ptr = q_p->ptr;
2133 type = Q_NEXT_TYPE(ehci, *hw_p);
2134 modified = 0;
2136 while (q.ptr != NULL) {
2137 unsigned uf;
2138 union ehci_shadow temp;
2139 int live;
2141 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2142 switch (hc32_to_cpu(ehci, type)) {
2143 case Q_TYPE_QH:
2144 /* handle any completions */
2145 temp.qh = qh_get (q.qh);
2146 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2147 q = q.qh->qh_next;
2148 modified = qh_completions (ehci, temp.qh);
2149 if (unlikely (list_empty (&temp.qh->qtd_list)))
2150 intr_deschedule (ehci, temp.qh);
2151 qh_put (temp.qh);
2152 break;
2153 case Q_TYPE_FSTN:
2154 /* for "save place" FSTNs, look at QH entries
2155 * in the previous frame for completions.
2157 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2158 dbg ("ignoring completions from FSTNs");
2160 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2161 q = q.fstn->fstn_next;
2162 break;
2163 case Q_TYPE_ITD:
2164 /* If this ITD is still active, leave it for
2165 * later processing ... check the next entry.
2167 rmb ();
2168 for (uf = 0; uf < 8 && live; uf++) {
2169 if (0 == (q.itd->hw_transaction [uf]
2170 & ITD_ACTIVE(ehci)))
2171 continue;
2172 incomplete = true;
2173 q_p = &q.itd->itd_next;
2174 hw_p = &q.itd->hw_next;
2175 type = Q_NEXT_TYPE(ehci,
2176 q.itd->hw_next);
2177 q = *q_p;
2178 break;
2180 if (uf < 8 && live)
2181 break;
2183 /* Take finished ITDs out of the schedule
2184 * and process them: recycle, maybe report
2185 * URB completion. HC won't cache the
2186 * pointer for much longer, if at all.
2188 *q_p = q.itd->itd_next;
2189 *hw_p = q.itd->hw_next;
2190 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2191 wmb();
2192 modified = itd_complete (ehci, q.itd);
2193 q = *q_p;
2194 break;
2195 case Q_TYPE_SITD:
2196 /* If this SITD is still active, leave it for
2197 * later processing ... check the next entry.
2199 if ((q.sitd->hw_results & SITD_ACTIVE(ehci))
2200 && live) {
2201 incomplete = true;
2202 q_p = &q.sitd->sitd_next;
2203 hw_p = &q.sitd->hw_next;
2204 type = Q_NEXT_TYPE(ehci,
2205 q.sitd->hw_next);
2206 q = *q_p;
2207 break;
2210 /* Take finished SITDs out of the schedule
2211 * and process them: recycle, maybe report
2212 * URB completion.
2214 *q_p = q.sitd->sitd_next;
2215 *hw_p = q.sitd->hw_next;
2216 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2217 wmb();
2218 modified = sitd_complete (ehci, q.sitd);
2219 q = *q_p;
2220 break;
2221 default:
2222 dbg ("corrupt type %d frame %d shadow %p",
2223 type, frame, q.ptr);
2224 // BUG ();
2225 q.ptr = NULL;
2228 /* assume completion callbacks modify the queue */
2229 if (unlikely (modified)) {
2230 if (likely(ehci->periodic_sched > 0))
2231 goto restart;
2232 /* maybe we can short-circuit this scan! */
2233 disable_periodic(ehci);
2234 now_uframe = clock;
2235 break;
2239 /* If we can tell we caught up to the hardware, stop now.
2240 * We can't advance our scan without collecting the ISO
2241 * transfers that are still pending in this frame.
2243 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2244 ehci->next_uframe = now_uframe;
2245 break;
2248 // FIXME: this assumes we won't get lapped when
2249 // latencies climb; that should be rare, but...
2250 // detect it, and just go all the way around.
2251 // FLR might help detect this case, so long as latencies
2252 // don't exceed periodic_size msec (default 1.024 sec).
2254 // FIXME: likewise assumes HC doesn't halt mid-scan
2256 if (now_uframe == clock) {
2257 unsigned now;
2259 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2260 || ehci->periodic_sched == 0)
2261 break;
2262 ehci->next_uframe = now_uframe;
2263 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2264 if (now_uframe == now)
2265 break;
2267 /* rescan the rest of this frame, then ... */
2268 clock = now;
2269 } else {
2270 now_uframe++;
2271 now_uframe %= mod;