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ARM: integrator: use new init_early for clock tree init
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-integrator / integrator_cp.c
blobe6700aab849a014eb3fc3a6cbb48969db1a7801f
1 /*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/sysdev.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
22 #include <linux/io.h>
23 #include <linux/gfp.h>
24 #include <linux/clkdev.h>
25
26 #include <mach/hardware.h>
27 #include <mach/platform.h>
28 #include <asm/irq.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware/arm_timer.h>
32 #include <asm/hardware/icst.h>
33
34 #include <mach/cm.h>
35 #include <mach/lm.h>
36
37 #include <asm/mach/arch.h>
38 #include <asm/mach/flash.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/time.h>
42
43 #include <asm/hardware/timer-sp.h>
44
45 #include <plat/clcd.h>
46
47 #include "common.h"
48
49 #define INTCP_PA_FLASH_BASE 0x24000000
50 #define INTCP_FLASH_SIZE SZ_32M
51
52 #define INTCP_PA_CLCD_BASE 0xc0000000
53
54 #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
55 #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
56 #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
57
58 #define INTCP_ETH_SIZE 0x10
59
60 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
61 #define INTCP_FLASHPROG 0x04
62 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
63 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
64
65 /*
66 * Logical Physical
67 * f1000000 10000000 Core module registers
68 * f1100000 11000000 System controller registers
69 * f1200000 12000000 EBI registers
70 * f1300000 13000000 Counter/Timer
71 * f1400000 14000000 Interrupt controller
72 * f1600000 16000000 UART 0
73 * f1700000 17000000 UART 1
74 * f1a00000 1a000000 Debug LEDs
75 * fc900000 c9000000 GPIO
76 * fca00000 ca000000 SIC
77 * fcb00000 cb000000 CP system control
78 */
79
80 static struct map_desc intcp_io_desc[] __initdata = {
81 {
82 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
83 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
84 .length = SZ_4K,
85 .type = MT_DEVICE
86 }, {
87 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
88 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
89 .length = SZ_4K,
90 .type = MT_DEVICE
91 }, {
92 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
93 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
94 .length = SZ_4K,
95 .type = MT_DEVICE
96 }, {
97 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
98 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
99 .length = SZ_4K,
100 .type = MT_DEVICE
101 }, {
102 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
103 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
104 .length = SZ_4K,
105 .type = MT_DEVICE
106 }, {
107 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
108 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
109 .length = SZ_4K,
110 .type = MT_DEVICE
111 }, {
112 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
113 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
114 .length = SZ_4K,
115 .type = MT_DEVICE
116 }, {
117 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
118 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
119 .length = SZ_4K,
120 .type = MT_DEVICE
121 }, {
122 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
123 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
124 .length = SZ_4K,
125 .type = MT_DEVICE
126 }, {
127 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
128 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
129 .length = SZ_4K,
130 .type = MT_DEVICE
131 }, {
132 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
133 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 }
137 };
138
139 static void __init intcp_map_io(void)
140 {
141 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
142 }
143
144 #define cic_writel __raw_writel
145 #define cic_readl __raw_readl
146 #define pic_writel __raw_writel
147 #define pic_readl __raw_readl
148 #define sic_writel __raw_writel
149 #define sic_readl __raw_readl
150
151 static void cic_mask_irq(struct irq_data *d)
152 {
153 unsigned int irq = d->irq - IRQ_CIC_START;
154 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
155 }
156
157 static void cic_unmask_irq(struct irq_data *d)
158 {
159 unsigned int irq = d->irq - IRQ_CIC_START;
160 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
161 }
162
163 static struct irq_chip cic_chip = {
164 .name = "CIC",
165 .irq_ack = cic_mask_irq,
166 .irq_mask = cic_mask_irq,
167 .irq_unmask = cic_unmask_irq,
168 };
169
170 static void pic_mask_irq(struct irq_data *d)
171 {
172 unsigned int irq = d->irq - IRQ_PIC_START;
173 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
174 }
175
176 static void pic_unmask_irq(struct irq_data *d)
177 {
178 unsigned int irq = d->irq - IRQ_PIC_START;
179 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
180 }
181
182 static struct irq_chip pic_chip = {
183 .name = "PIC",
184 .irq_ack = pic_mask_irq,
185 .irq_mask = pic_mask_irq,
186 .irq_unmask = pic_unmask_irq,
187 };
188
189 static void sic_mask_irq(struct irq_data *d)
190 {
191 unsigned int irq = d->irq - IRQ_SIC_START;
192 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
193 }
194
195 static void sic_unmask_irq(struct irq_data *d)
196 {
197 unsigned int irq = d->irq - IRQ_SIC_START;
198 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
199 }
200
201 static struct irq_chip sic_chip = {
202 .name = "SIC",
203 .irq_ack = sic_mask_irq,
204 .irq_mask = sic_mask_irq,
205 .irq_unmask = sic_unmask_irq,
206 };
207
208 static void
209 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
210 {
211 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
212
213 if (status == 0) {
214 do_bad_IRQ(irq, desc);
215 return;
216 }
217
218 do {
219 irq = ffs(status) - 1;
220 status &= ~(1 << irq);
221
222 irq += IRQ_SIC_START;
223
224 generic_handle_irq(irq);
225 } while (status);
226 }
227
228 static void __init intcp_init_irq(void)
229 {
230 unsigned int i;
231
232 /*
233 * Disable all interrupt sources
234 */
235 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
236 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
237
238 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
239 if (i == 11)
240 i = 22;
241 if (i == 29)
242 break;
243 set_irq_chip(i, &pic_chip);
244 set_irq_handler(i, handle_level_irq);
245 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
246 }
247
248 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
249 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
250
251 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
252 set_irq_chip(i, &cic_chip);
253 set_irq_handler(i, handle_level_irq);
254 set_irq_flags(i, IRQF_VALID);
255 }
256
257 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
258 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
259
260 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
261 set_irq_chip(i, &sic_chip);
262 set_irq_handler(i, handle_level_irq);
263 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
264 }
265
266 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
267 }
268
269 /*
270 * Clock handling
271 */
272 #define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
273 #define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
274
275 static const struct icst_params cp_auxvco_params = {
276 .ref = 24000000,
277 .vco_max = ICST525_VCO_MAX_5V,
278 .vco_min = ICST525_VCO_MIN,
279 .vd_min = 8,
280 .vd_max = 263,
281 .rd_min = 3,
282 .rd_max = 65,
283 .s2div = icst525_s2div,
284 .idx2s = icst525_idx2s,
285 };
286
287 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
288 {
289 u32 val;
290
291 val = readl(clk->vcoreg) & ~0x7ffff;
292 val |= vco.v | (vco.r << 9) | (vco.s << 16);
293
294 writel(0xa05f, CM_LOCK);
295 writel(val, clk->vcoreg);
296 writel(0, CM_LOCK);
297 }
298
299 static const struct clk_ops cp_auxclk_ops = {
300 .round = icst_clk_round,
301 .set = icst_clk_set,
302 .setvco = cp_auxvco_set,
303 };
304
305 static struct clk cp_auxclk = {
306 .ops = &cp_auxclk_ops,
307 .params = &cp_auxvco_params,
308 .vcoreg = CM_AUXOSC,
309 };
310
311 static struct clk_lookup cp_lookups[] = {
312 { /* CLCD */
313 .dev_id = "mb:c0",
314 .clk = &cp_auxclk,
315 },
316 };
317
318 /*
319 * Flash handling.
320 */
321 static int intcp_flash_init(void)
322 {
323 u32 val;
324
325 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
326 val |= CINTEGRATOR_FLASHPROG_FLWREN;
327 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
328
329 return 0;
330 }
331
332 static void intcp_flash_exit(void)
333 {
334 u32 val;
335
336 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
337 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
338 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
339 }
340
341 static void intcp_flash_set_vpp(int on)
342 {
343 u32 val;
344
345 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
346 if (on)
347 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
348 else
349 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
350 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
351 }
352
353 static struct flash_platform_data intcp_flash_data = {
354 .map_name = "cfi_probe",
355 .width = 4,
356 .init = intcp_flash_init,
357 .exit = intcp_flash_exit,
358 .set_vpp = intcp_flash_set_vpp,
359 };
360
361 static struct resource intcp_flash_resource = {
362 .start = INTCP_PA_FLASH_BASE,
363 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
364 .flags = IORESOURCE_MEM,
365 };
366
367 static struct platform_device intcp_flash_device = {
368 .name = "armflash",
369 .id = 0,
370 .dev = {
371 .platform_data = &intcp_flash_data,
372 },
373 .num_resources = 1,
374 .resource = &intcp_flash_resource,
375 };
376
377 static struct resource smc91x_resources[] = {
378 [0] = {
379 .start = INTEGRATOR_CP_ETH_BASE,
380 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = {
384 .start = IRQ_CP_ETHINT,
385 .end = IRQ_CP_ETHINT,
386 .flags = IORESOURCE_IRQ,
387 },
388 };
389
390 static struct platform_device smc91x_device = {
391 .name = "smc91x",
392 .id = 0,
393 .num_resources = ARRAY_SIZE(smc91x_resources),
394 .resource = smc91x_resources,
395 };
396
397 static struct platform_device *intcp_devs[] __initdata = {
398 &intcp_flash_device,
399 &smc91x_device,
400 };
401
402 /*
403 * It seems that the card insertion interrupt remains active after
404 * we've acknowledged it. We therefore ignore the interrupt, and
405 * rely on reading it from the SIC. This also means that we must
406 * clear the latched interrupt.
407 */
408 static unsigned int mmc_status(struct device *dev)
409 {
410 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
411 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
412
413 return status & 8;
414 }
415
416 static struct mmci_platform_data mmc_data = {
417 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
418 .status = mmc_status,
419 .gpio_wp = -1,
420 .gpio_cd = -1,
421 };
422
423 static struct amba_device mmc_device = {
424 .dev = {
425 .init_name = "mb:1c",
426 .platform_data = &mmc_data,
427 },
428 .res = {
429 .start = INTEGRATOR_CP_MMC_BASE,
430 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
431 .flags = IORESOURCE_MEM,
432 },
433 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
434 .periphid = 0,
435 };
436
437 static struct amba_device aaci_device = {
438 .dev = {
439 .init_name = "mb:1d",
440 },
441 .res = {
442 .start = INTEGRATOR_CP_AACI_BASE,
443 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 .irq = { IRQ_CP_AACIINT, NO_IRQ },
447 .periphid = 0,
448 };
449
450
451 /*
452 * CLCD support
453 */
454 /*
455 * Ensure VGA is selected.
456 */
457 static void cp_clcd_enable(struct clcd_fb *fb)
458 {
459 struct fb_var_screeninfo *var = &fb->fb.var;
460 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
461
462 if (var->bits_per_pixel <= 8 ||
463 (var->bits_per_pixel == 16 && var->green.length == 5))
464 /* Pseudocolor, RGB555, BGR555 */
465 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
466 else if (fb->fb.var.bits_per_pixel <= 16)
467 /* truecolor RGB565 */
468 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
469 else
470 val = 0; /* no idea for this, don't trust the docs */
471
472 cm_control(CM_CTRL_LCDMUXSEL_MASK|
473 CM_CTRL_LCDEN0|
474 CM_CTRL_LCDEN1|
475 CM_CTRL_STATIC1|
476 CM_CTRL_STATIC2|
477 CM_CTRL_STATIC|
478 CM_CTRL_n24BITEN, val);
479 }
480
481 static int cp_clcd_setup(struct clcd_fb *fb)
482 {
483 fb->panel = versatile_clcd_get_panel("VGA");
484 if (!fb->panel)
485 return -EINVAL;
486
487 return versatile_clcd_setup_dma(fb, SZ_1M);
488 }
489
490 static struct clcd_board clcd_data = {
491 .name = "Integrator/CP",
492 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
493 .check = clcdfb_check,
494 .decode = clcdfb_decode,
495 .enable = cp_clcd_enable,
496 .setup = cp_clcd_setup,
497 .mmap = versatile_clcd_mmap_dma,
498 .remove = versatile_clcd_remove_dma,
499 };
500
501 static struct amba_device clcd_device = {
502 .dev = {
503 .init_name = "mb:c0",
504 .coherent_dma_mask = ~0,
505 .platform_data = &clcd_data,
506 },
507 .res = {
508 .start = INTCP_PA_CLCD_BASE,
509 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 .dma_mask = ~0,
513 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
514 .periphid = 0,
515 };
516
517 static struct amba_device *amba_devs[] __initdata = {
518 &mmc_device,
519 &aaci_device,
520 &clcd_device,
521 };
522
523 static void __init intcp_init_early(void)
524 {
525 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
526
527 integrator_init_early();
528 }
529
530 static void __init intcp_init(void)
531 {
532 int i;
533
534 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
535
536 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
537 struct amba_device *d = amba_devs[i];
538 amba_device_register(d, &iomem_resource);
539 }
540 }
541
542 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
543 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
544 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
545
546 static void __init intcp_timer_init(void)
547 {
548 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
549 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
550 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
551
552 sp804_clocksource_init(TIMER2_VA_BASE);
553 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
554 }
555
556 static struct sys_timer cp_timer = {
557 .init = intcp_timer_init,
558 };
559
560 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
561 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
562 .boot_params = 0x00000100,
563 .reserve = integrator_reserve,
564 .map_io = intcp_map_io,
565 .init_early = intcp_init_early,
566 .init_irq = intcp_init_irq,
567 .timer = &cp_timer,
568 .init_machine = intcp_init,
569 MACHINE_END
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