arch/x86/kernel/amd_iommu.c

   1 /*
   2  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #include <linux/pci.h>
  21 #include <linux/gfp.h>
  22 #include <linux/bitops.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/iommu-helper.h>
  25 #include <asm/proto.h>
  26 #include <asm/gart.h>
  27 #include <asm/amd_iommu_types.h>
  28 #include <asm/amd_iommu.h>
  29
  30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
  31
  32 #define to_pages(addr, size) \
  33          (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
  34
  35 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
  36
  37 struct command {
  38         u32 data[4];
  39 };
  40
  41 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
  42                              struct unity_map_entry *e);
  43
  44 static int iommu_has_npcache(struct amd_iommu *iommu)
  45 {
  46         return iommu->cap & IOMMU_CAP_NPCACHE;
  47 }
  48
  49 static int __iommu_queue_command(struct amd_iommu *iommu, struct command *cmd)
  50 {
  51         u32 tail, head;
  52         u8 *target;
  53
  54         tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
  55         target = (iommu->cmd_buf + tail);
  56         memcpy_toio(target, cmd, sizeof(*cmd));
  57         tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
  58         head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
  59         if (tail == head)
  60                 return -ENOMEM;
  61         writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
  62
  63         return 0;
  64 }
  65
  66 static int iommu_queue_command(struct amd_iommu *iommu, struct command *cmd)
  67 {
  68         unsigned long flags;
  69         int ret;
  70
  71         spin_lock_irqsave(&iommu->lock, flags);
  72         ret = __iommu_queue_command(iommu, cmd);
  73         spin_unlock_irqrestore(&iommu->lock, flags);
  74
  75         return ret;
  76 }
  77
  78 static int iommu_completion_wait(struct amd_iommu *iommu)
  79 {
  80         int ret;
  81         struct command cmd;
  82         volatile u64 ready = 0;
  83         unsigned long ready_phys = virt_to_phys(&ready);
  84
  85         memset(&cmd, 0, sizeof(cmd));
  86         cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK;
  87         cmd.data[1] = HIGH_U32(ready_phys);
  88         cmd.data[2] = 1; /* value written to 'ready' */
  89         CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
  90
  91         iommu->need_sync = 0;
  92
  93         ret = iommu_queue_command(iommu, &cmd);
  94
  95         if (ret)
  96                 return ret;
  97
  98         while (!ready)
  99                 cpu_relax();
 100
 101         return 0;
 102 }
 103
 104 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
 105 {
 106         struct command cmd;
 107
 108         BUG_ON(iommu == NULL);
 109
 110         memset(&cmd, 0, sizeof(cmd));
 111         CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
 112         cmd.data[0] = devid;
 113
 114         iommu->need_sync = 1;
 115
 116         return iommu_queue_command(iommu, &cmd);
 117 }
 118
 119 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
 120                 u64 address, u16 domid, int pde, int s)
 121 {
 122         struct command cmd;
 123
 124         memset(&cmd, 0, sizeof(cmd));
 125         address &= PAGE_MASK;
 126         CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
 127         cmd.data[1] |= domid;
 128         cmd.data[2] = LOW_U32(address);
 129         cmd.data[3] = HIGH_U32(address);
 130         if (s)
 131                 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
 132         if (pde)
 133                 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
 134
 135         iommu->need_sync = 1;
 136
 137         return iommu_queue_command(iommu, &cmd);
 138 }
 139
 140 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
 141                 u64 address, size_t size)
 142 {
 143         int i;
 144         unsigned pages = to_pages(address, size);
 145
 146         address &= PAGE_MASK;
 147
 148         for (i = 0; i < pages; ++i) {
 149                 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 0);
 150                 address += PAGE_SIZE;
 151         }
 152
 153         return 0;
 154 }
 155
 156 static int iommu_map(struct protection_domain *dom,
 157                      unsigned long bus_addr,
 158                      unsigned long phys_addr,
 159                      int prot)
 160 {
 161         u64 __pte, *pte, *page;
 162
 163         bus_addr  = PAGE_ALIGN(bus_addr);
 164         phys_addr = PAGE_ALIGN(bus_addr);
 165
 166         /* only support 512GB address spaces for now */
 167         if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
 168                 return -EINVAL;
 169
 170         pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
 171
 172         if (!IOMMU_PTE_PRESENT(*pte)) {
 173                 page = (u64 *)get_zeroed_page(GFP_KERNEL);
 174                 if (!page)
 175                         return -ENOMEM;
 176                 *pte = IOMMU_L2_PDE(virt_to_phys(page));
 177         }
 178
 179         pte = IOMMU_PTE_PAGE(*pte);
 180         pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
 181
 182         if (!IOMMU_PTE_PRESENT(*pte)) {
 183                 page = (u64 *)get_zeroed_page(GFP_KERNEL);
 184                 if (!page)
 185                         return -ENOMEM;
 186                 *pte = IOMMU_L1_PDE(virt_to_phys(page));
 187         }
 188
 189         pte = IOMMU_PTE_PAGE(*pte);
 190         pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
 191
 192         if (IOMMU_PTE_PRESENT(*pte))
 193                 return -EBUSY;
 194
 195         __pte = phys_addr | IOMMU_PTE_P;
 196         if (prot & IOMMU_PROT_IR)
 197                 __pte |= IOMMU_PTE_IR;
 198         if (prot & IOMMU_PROT_IW)
 199                 __pte |= IOMMU_PTE_IW;
 200
 201         *pte = __pte;
 202
 203         return 0;
 204 }
 205
 206 static int iommu_for_unity_map(struct amd_iommu *iommu,
 207                                struct unity_map_entry *entry)
 208 {
 209         u16 bdf, i;
 210
 211         for (i = entry->devid_start; i <= entry->devid_end; ++i) {
 212                 bdf = amd_iommu_alias_table[i];
 213                 if (amd_iommu_rlookup_table[bdf] == iommu)
 214                         return 1;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
 221 {
 222         struct unity_map_entry *entry;
 223         int ret;
 224
 225         list_for_each_entry(entry, &amd_iommu_unity_map, list) {
 226                 if (!iommu_for_unity_map(iommu, entry))
 227                         continue;
 228                 ret = dma_ops_unity_map(iommu->default_dom, entry);
 229                 if (ret)
 230                         return ret;
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
 237                              struct unity_map_entry *e)
 238 {
 239         u64 addr;
 240         int ret;
 241
 242         for (addr = e->address_start; addr < e->address_end;
 243              addr += PAGE_SIZE) {
 244                 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
 245                 if (ret)
 246                         return ret;
 247                 /*
 248                  * if unity mapping is in aperture range mark the page
 249                  * as allocated in the aperture
 250                  */
 251                 if (addr < dma_dom->aperture_size)
 252                         __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
 259                                           u16 devid)
 260 {
 261         struct unity_map_entry *e;
 262         int ret;
 263
 264         list_for_each_entry(e, &amd_iommu_unity_map, list) {
 265                 if (!(devid >= e->devid_start && devid <= e->devid_end))
 266                         continue;
 267                 ret = dma_ops_unity_map(dma_dom, e);
 268                 if (ret)
 269                         return ret;
 270         }
 271
 272         return 0;
 273 }
 274
 275 static unsigned long dma_mask_to_pages(unsigned long mask)
 276 {
 277         return (mask >> PAGE_SHIFT) +
 278                 (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
 279 }
 280
 281 static unsigned long dma_ops_alloc_addresses(struct device *dev,
 282                                              struct dma_ops_domain *dom,
 283                                              unsigned int pages)
 284 {
 285         unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
 286         unsigned long address;
 287         unsigned long size = dom->aperture_size >> PAGE_SHIFT;
 288         unsigned long boundary_size;
 289
 290         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 291                         PAGE_SIZE) >> PAGE_SHIFT;
 292         limit = limit < size ? limit : size;
 293
 294         if (dom->next_bit >= limit)
 295                 dom->next_bit = 0;
 296
 297         address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
 298                         0 , boundary_size, 0);
 299         if (address == -1)
 300                 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
 301                                 0, boundary_size, 0);
 302
 303         if (likely(address != -1)) {
 304                 set_bit_string(dom->bitmap, address, pages);
 305                 dom->next_bit = address + pages;
 306                 address <<= PAGE_SHIFT;
 307         } else
 308                 address = bad_dma_address;
 309
 310         WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
 311
 312         return address;
 313 }
 314
 315 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
 316                                    unsigned long address,
 317                                    unsigned int pages)
 318 {
 319         address >>= PAGE_SHIFT;
 320         iommu_area_free(dom->bitmap, address, pages);
 321 }
 322
 323 static u16 domain_id_alloc(void)
 324 {
 325         unsigned long flags;
 326         int id;
 327
 328         write_lock_irqsave(&amd_iommu_devtable_lock, flags);
 329         id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
 330         BUG_ON(id == 0);
 331         if (id > 0 && id < MAX_DOMAIN_ID)
 332                 __set_bit(id, amd_iommu_pd_alloc_bitmap);
 333         else
 334                 id = 0;
 335         write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
 336
 337         return id;
 338 }
 339
 340 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
 341                                       unsigned long start_page,
 342                                       unsigned int pages)
 343 {
 344         unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
 345
 346         if (start_page + pages > last_page)
 347                 pages = last_page - start_page;
 348
 349         set_bit_string(dom->bitmap, start_page, pages);
 350 }
 351
 352 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
 353 {
 354         int i, j;
 355         u64 *p1, *p2, *p3;
 356
 357         p1 = dma_dom->domain.pt_root;
 358
 359         if (!p1)
 360                 return;
 361
 362         for (i = 0; i < 512; ++i) {
 363                 if (!IOMMU_PTE_PRESENT(p1[i]))
 364                         continue;
 365
 366                 p2 = IOMMU_PTE_PAGE(p1[i]);
 367                 for (j = 0; j < 512; ++i) {
 368                         if (!IOMMU_PTE_PRESENT(p2[j]))
 369                                 continue;
 370                         p3 = IOMMU_PTE_PAGE(p2[j]);
 371                         free_page((unsigned long)p3);
 372                 }
 373
 374                 free_page((unsigned long)p2);
 375         }
 376
 377         free_page((unsigned long)p1);
 378 }
 379
 380 static void dma_ops_domain_free(struct dma_ops_domain *dom)
 381 {
 382         if (!dom)
 383                 return;
 384
 385         dma_ops_free_pagetable(dom);
 386
 387         kfree(dom->pte_pages);
 388
 389         kfree(dom->bitmap);
 390
 391         kfree(dom);
 392 }
 393
 394 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
 395                                                    unsigned order)
 396 {
 397         struct dma_ops_domain *dma_dom;
 398         unsigned i, num_pte_pages;
 399         u64 *l2_pde;
 400         u64 address;
 401
 402         /*
 403          * Currently the DMA aperture must be between 32 MB and 1GB in size
 404          */
 405         if ((order < 25) || (order > 30))
 406                 return NULL;
 407
 408         dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
 409         if (!dma_dom)
 410                 return NULL;
 411
 412         spin_lock_init(&dma_dom->domain.lock);
 413
 414         dma_dom->domain.id = domain_id_alloc();
 415         if (dma_dom->domain.id == 0)
 416                 goto free_dma_dom;
 417         dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
 418         dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
 419         dma_dom->domain.priv = dma_dom;
 420         if (!dma_dom->domain.pt_root)
 421                 goto free_dma_dom;
 422         dma_dom->aperture_size = (1ULL << order);
 423         dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
 424                                   GFP_KERNEL);
 425         if (!dma_dom->bitmap)
 426                 goto free_dma_dom;
 427         /*
 428          * mark the first page as allocated so we never return 0 as
 429          * a valid dma-address. So we can use 0 as error value
 430          */
 431         dma_dom->bitmap[0] = 1;
 432         dma_dom->next_bit = 0;
 433
 434         if (iommu->exclusion_start &&
 435             iommu->exclusion_start < dma_dom->aperture_size) {
 436                 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
 437                 int pages = to_pages(iommu->exclusion_start,
 438                                 iommu->exclusion_length);
 439                 dma_ops_reserve_addresses(dma_dom, startpage, pages);
 440         }
 441
 442         num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
 443         dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
 444                         GFP_KERNEL);
 445         if (!dma_dom->pte_pages)
 446                 goto free_dma_dom;
 447
 448         l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
 449         if (l2_pde == NULL)
 450                 goto free_dma_dom;
 451
 452         dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
 453
 454         for (i = 0; i < num_pte_pages; ++i) {
 455                 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
 456                 if (!dma_dom->pte_pages[i])
 457                         goto free_dma_dom;
 458                 address = virt_to_phys(dma_dom->pte_pages[i]);
 459                 l2_pde[i] = IOMMU_L1_PDE(address);
 460         }
 461
 462         return dma_dom;
 463
 464 free_dma_dom:
 465         dma_ops_domain_free(dma_dom);
 466
 467         return NULL;
 468 }
 469
 470 static struct protection_domain *domain_for_device(u16 devid)
 471 {
 472         struct protection_domain *dom;
 473         unsigned long flags;
 474
 475         read_lock_irqsave(&amd_iommu_devtable_lock, flags);
 476         dom = amd_iommu_pd_table[devid];
 477         read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
 478
 479         return dom;
 480 }
 481
 482 static void set_device_domain(struct amd_iommu *iommu,
 483                               struct protection_domain *domain,
 484                               u16 devid)
 485 {
 486         unsigned long flags;
 487
 488         u64 pte_root = virt_to_phys(domain->pt_root);
 489
 490         pte_root |= (domain->mode & 0x07) << 9;
 491         pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
 492
 493         write_lock_irqsave(&amd_iommu_devtable_lock, flags);
 494         amd_iommu_dev_table[devid].data[0] = pte_root;
 495         amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
 496         amd_iommu_dev_table[devid].data[2] = domain->id;
 497
 498         amd_iommu_pd_table[devid] = domain;
 499         write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
 500
 501         iommu_queue_inv_dev_entry(iommu, devid);
 502
 503         iommu->need_sync = 1;
 504 }
 505
 506 static int get_device_resources(struct device *dev,
 507                                 struct amd_iommu **iommu,
 508                                 struct protection_domain **domain,
 509                                 u16 *bdf)
 510 {
 511         struct dma_ops_domain *dma_dom;
 512         struct pci_dev *pcidev;
 513         u16 _bdf;
 514
 515         BUG_ON(!dev || dev->bus != &pci_bus_type || !dev->dma_mask);
 516
 517         pcidev = to_pci_dev(dev);
 518         _bdf = (pcidev->bus->number << 8) | pcidev->devfn;
 519
 520         if (_bdf >= amd_iommu_last_bdf) {
 521                 *iommu = NULL;
 522                 *domain = NULL;
 523                 *bdf = 0xffff;
 524                 return 0;
 525         }
 526
 527         *bdf = amd_iommu_alias_table[_bdf];
 528
 529         *iommu = amd_iommu_rlookup_table[*bdf];
 530         if (*iommu == NULL)
 531                 return 0;
 532         dma_dom = (*iommu)->default_dom;
 533         *domain = domain_for_device(*bdf);
 534         if (*domain == NULL) {
 535                 *domain = &dma_dom->domain;
 536                 set_device_domain(*iommu, *domain, *bdf);
 537                 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
 538                                 "device ", (*domain)->id);
 539                 print_devid(_bdf, 1);
 540         }
 541
 542         return 1;
 543 }
 544
 545 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
 546                                      struct dma_ops_domain *dom,
 547                                      unsigned long address,
 548                                      phys_addr_t paddr,
 549                                      int direction)
 550 {
 551         u64 *pte, __pte;
 552
 553         WARN_ON(address > dom->aperture_size);
 554
 555         paddr &= PAGE_MASK;
 556
 557         pte  = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
 558         pte += IOMMU_PTE_L0_INDEX(address);
 559
 560         __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
 561
 562         if (direction == DMA_TO_DEVICE)
 563                 __pte |= IOMMU_PTE_IR;
 564         else if (direction == DMA_FROM_DEVICE)
 565                 __pte |= IOMMU_PTE_IW;
 566         else if (direction == DMA_BIDIRECTIONAL)
 567                 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
 568
 569         WARN_ON(*pte);
 570
 571         *pte = __pte;
 572
 573         return (dma_addr_t)address;
 574 }
 575
 576 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
 577                                  struct dma_ops_domain *dom,
 578                                  unsigned long address)
 579 {
 580         u64 *pte;
 581
 582         if (address >= dom->aperture_size)
 583                 return;
 584
 585         WARN_ON(address & 0xfffULL || address > dom->aperture_size);
 586
 587         pte  = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
 588         pte += IOMMU_PTE_L0_INDEX(address);
 589
 590         WARN_ON(!*pte);
 591
 592         *pte = 0ULL;
 593 }
 594
 595 static dma_addr_t __map_single(struct device *dev,
 596                                struct amd_iommu *iommu,
 597                                struct dma_ops_domain *dma_dom,
 598                                phys_addr_t paddr,
 599                                size_t size,
 600                                int dir)
 601 {
 602         dma_addr_t offset = paddr & ~PAGE_MASK;
 603         dma_addr_t address, start;
 604         unsigned int pages;
 605         int i;
 606
 607         pages = to_pages(paddr, size);
 608         paddr &= PAGE_MASK;
 609
 610         address = dma_ops_alloc_addresses(dev, dma_dom, pages);
 611         if (unlikely(address == bad_dma_address))
 612                 goto out;
 613
 614         start = address;
 615         for (i = 0; i < pages; ++i) {
 616                 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
 617                 paddr += PAGE_SIZE;
 618                 start += PAGE_SIZE;
 619         }
 620         address += offset;
 621
 622 out:
 623         return address;
 624 }
 625
 626 static void __unmap_single(struct amd_iommu *iommu,
 627                            struct dma_ops_domain *dma_dom,
 628                            dma_addr_t dma_addr,
 629                            size_t size,
 630                            int dir)
 631 {
 632         dma_addr_t i, start;
 633         unsigned int pages;
 634
 635         if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
 636                 return;
 637
 638         pages = to_pages(dma_addr, size);
 639         dma_addr &= PAGE_MASK;
 640         start = dma_addr;
 641
 642         for (i = 0; i < pages; ++i) {
 643                 dma_ops_domain_unmap(iommu, dma_dom, start);
 644                 start += PAGE_SIZE;
 645         }
 646
 647         dma_ops_free_addresses(dma_dom, dma_addr, pages);
 648 }
 649
 650 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
 651                              size_t size, int dir)
 652 {
 653         unsigned long flags;
 654         struct amd_iommu *iommu;
 655         struct protection_domain *domain;
 656         u16 devid;
 657         dma_addr_t addr;
 658
 659         get_device_resources(dev, &iommu, &domain, &devid);
 660
 661         if (iommu == NULL || domain == NULL)
 662                 return (dma_addr_t)paddr;
 663
 664         spin_lock_irqsave(&domain->lock, flags);
 665         addr = __map_single(dev, iommu, domain->priv, paddr, size, dir);
 666         if (addr == bad_dma_address)
 667                 goto out;
 668
 669         if (iommu_has_npcache(iommu))
 670                 iommu_flush_pages(iommu, domain->id, addr, size);
 671
 672         if (iommu->need_sync)
 673                 iommu_completion_wait(iommu);
 674
 675 out:
 676         spin_unlock_irqrestore(&domain->lock, flags);
 677
 678         return addr;
 679 }
 680
 681 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
 682                          size_t size, int dir)
 683 {
 684         unsigned long flags;
 685         struct amd_iommu *iommu;
 686         struct protection_domain *domain;
 687         u16 devid;
 688
 689         if (!get_device_resources(dev, &iommu, &domain, &devid))
 690                 return;
 691
 692         spin_lock_irqsave(&domain->lock, flags);
 693
 694         __unmap_single(iommu, domain->priv, dma_addr, size, dir);
 695
 696         iommu_flush_pages(iommu, domain->id, dma_addr, size);
 697
 698         if (iommu->need_sync)
 699                 iommu_completion_wait(iommu);
 700
 701         spin_unlock_irqrestore(&domain->lock, flags);
 702 }
 703
 704 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
 705                            int nelems, int dir)
 706 {
 707         struct scatterlist *s;
 708         int i;
 709
 710         for_each_sg(sglist, s, nelems, i) {
 711                 s->dma_address = (dma_addr_t)sg_phys(s);
 712                 s->dma_length  = s->length;
 713         }
 714
 715         return nelems;
 716 }
 717
 718 static int map_sg(struct device *dev, struct scatterlist *sglist,
 719                   int nelems, int dir)
 720 {
 721         unsigned long flags;
 722         struct amd_iommu *iommu;
 723         struct protection_domain *domain;
 724         u16 devid;
 725         int i;
 726         struct scatterlist *s;
 727         phys_addr_t paddr;
 728         int mapped_elems = 0;
 729
 730         get_device_resources(dev, &iommu, &domain, &devid);
 731
 732         if (!iommu || !domain)
 733                 return map_sg_no_iommu(dev, sglist, nelems, dir);
 734
 735         spin_lock_irqsave(&domain->lock, flags);
 736
 737         for_each_sg(sglist, s, nelems, i) {
 738                 paddr = sg_phys(s);
 739
 740                 s->dma_address = __map_single(dev, iommu, domain->priv,
 741                                               paddr, s->length, dir);
 742
 743                 if (s->dma_address) {
 744                         s->dma_length = s->length;
 745                         mapped_elems++;
 746                 } else
 747                         goto unmap;
 748                 if (iommu_has_npcache(iommu))
 749                         iommu_flush_pages(iommu, domain->id, s->dma_address,
 750                                           s->dma_length);
 751         }
 752
 753         if (iommu->need_sync)
 754                 iommu_completion_wait(iommu);
 755
 756 out:
 757         spin_unlock_irqrestore(&domain->lock, flags);
 758
 759         return mapped_elems;
 760 unmap:
 761         for_each_sg(sglist, s, mapped_elems, i) {
 762                 if (s->dma_address)
 763                         __unmap_single(iommu, domain->priv, s->dma_address,
 764                                        s->dma_length, dir);
 765                 s->dma_address = s->dma_length = 0;
 766         }
 767
 768         mapped_elems = 0;
 769
 770         goto out;
 771 }
 772
 773 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
 774                      int nelems, int dir)
 775 {
 776         unsigned long flags;
 777         struct amd_iommu *iommu;
 778         struct protection_domain *domain;
 779         struct scatterlist *s;
 780         u16 devid;
 781         int i;
 782
 783         if (!get_device_resources(dev, &iommu, &domain, &devid))
 784                 return;
 785
 786         spin_lock_irqsave(&domain->lock, flags);
 787
 788         for_each_sg(sglist, s, nelems, i) {
 789                 __unmap_single(iommu, domain->priv, s->dma_address,
 790                                s->dma_length, dir);
 791                 iommu_flush_pages(iommu, domain->id, s->dma_address,
 792                                   s->dma_length);
 793                 s->dma_address = s->dma_length = 0;
 794         }
 795
 796         if (iommu->need_sync)
 797                 iommu_completion_wait(iommu);
 798
 799         spin_unlock_irqrestore(&domain->lock, flags);
 800 }
 801
 802 static void *alloc_coherent(struct device *dev, size_t size,
 803                             dma_addr_t *dma_addr, gfp_t flag)
 804 {
 805         unsigned long flags;
 806         void *virt_addr;
 807         struct amd_iommu *iommu;
 808         struct protection_domain *domain;
 809         u16 devid;
 810         phys_addr_t paddr;
 811
 812         virt_addr = (void *)__get_free_pages(flag, get_order(size));
 813         if (!virt_addr)
 814                 return 0;
 815
 816         memset(virt_addr, 0, size);
 817         paddr = virt_to_phys(virt_addr);
 818
 819         get_device_resources(dev, &iommu, &domain, &devid);
 820
 821         if (!iommu || !domain) {
 822                 *dma_addr = (dma_addr_t)paddr;
 823                 return virt_addr;
 824         }
 825
 826         spin_lock_irqsave(&domain->lock, flags);
 827
 828         *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
 829                                  size, DMA_BIDIRECTIONAL);
 830
 831         if (*dma_addr == bad_dma_address) {
 832                 free_pages((unsigned long)virt_addr, get_order(size));
 833                 virt_addr = NULL;
 834                 goto out;
 835         }
 836
 837         if (iommu_has_npcache(iommu))
 838                 iommu_flush_pages(iommu, domain->id, *dma_addr, size);
 839
 840         if (iommu->need_sync)
 841                 iommu_completion_wait(iommu);
 842
 843 out:
 844         spin_unlock_irqrestore(&domain->lock, flags);
 845
 846         return virt_addr;
 847 }
 848
 849 static void free_coherent(struct device *dev, size_t size,
 850                           void *virt_addr, dma_addr_t dma_addr)
 851 {
 852         unsigned long flags;
 853         struct amd_iommu *iommu;
 854         struct protection_domain *domain;
 855         u16 devid;
 856
 857         get_device_resources(dev, &iommu, &domain, &devid);
 858
 859         if (!iommu || !domain)
 860                 goto free_mem;
 861
 862         spin_lock_irqsave(&domain->lock, flags);
 863
 864         __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
 865         iommu_flush_pages(iommu, domain->id, dma_addr, size);
 866
 867         if (iommu->need_sync)
 868                 iommu_completion_wait(iommu);
 869
 870         spin_unlock_irqrestore(&domain->lock, flags);
 871
 872 free_mem:
 873         free_pages((unsigned long)virt_addr, get_order(size));
 874 }
 875
 876 /*
 877  * If the driver core informs the DMA layer if a driver grabs a device
 878  * we don't need to preallocate the protection domains anymore.
 879  * For now we have to.
 880  */
 881 void prealloc_protection_domains(void)
 882 {
 883         struct pci_dev *dev = NULL;
 884         struct dma_ops_domain *dma_dom;
 885         struct amd_iommu *iommu;
 886         int order = amd_iommu_aperture_order;
 887         u16 devid;
 888
 889         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
 890                 devid = (dev->bus->number << 8) | dev->devfn;
 891                 if (devid >= amd_iommu_last_bdf)
 892                         continue;
 893                 devid = amd_iommu_alias_table[devid];
 894                 if (domain_for_device(devid))
 895                         continue;
 896                 iommu = amd_iommu_rlookup_table[devid];
 897                 if (!iommu)
 898                         continue;
 899                 dma_dom = dma_ops_domain_alloc(iommu, order);
 900                 if (!dma_dom)
 901                         continue;
 902                 init_unity_mappings_for_device(dma_dom, devid);
 903                 set_device_domain(iommu, &dma_dom->domain, devid);
 904                 printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
 905                        dma_dom->domain.id);
 906                 print_devid(devid, 1);
 907         }
 908 }
 909
 910 static struct dma_mapping_ops amd_iommu_dma_ops = {
 911         .alloc_coherent = alloc_coherent,
 912         .free_coherent = free_coherent,
 913         .map_single = map_single,
 914         .unmap_single = unmap_single,
 915         .map_sg = map_sg,
 916         .unmap_sg = unmap_sg,
 917 };
 918
 919 int __init amd_iommu_init_dma_ops(void)
 920 {
 921         struct amd_iommu *iommu;
 922         int order = amd_iommu_aperture_order;
 923         int ret;
 924
 925         list_for_each_entry(iommu, &amd_iommu_list, list) {
 926                 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
 927                 if (iommu->default_dom == NULL)
 928                         return -ENOMEM;
 929                 ret = iommu_init_unity_mappings(iommu);
 930                 if (ret)
 931                         goto free_domains;
 932         }
 933
 934         if (amd_iommu_isolate)
 935                 prealloc_protection_domains();
 936
 937         iommu_detected = 1;
 938         force_iommu = 1;
 939         bad_dma_address = 0;
 940         gart_iommu_aperture_disabled = 1;
 941         gart_iommu_aperture = 0;
 942
 943         dma_ops = &amd_iommu_dma_ops;
 944
 945         return 0;
 946
 947 free_domains:
 948
 949         list_for_each_entry(iommu, &amd_iommu_list, list) {
 950                 if (iommu->default_dom)
 951                         dma_ops_domain_free(iommu->default_dom);
 952         }
 953
 954         return ret;
 955 }