arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/omapfb.h>
  23
  24 #include <asm/tlb.h>
  25 #include <asm/cacheflush.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <plat/sram.h>
  30 #include <plat/board.h>
  31 #include <plat/cpu.h>
  32 #include <plat/vram.h>
  33
  34 #include "sram.h"
  35 #include "fb.h"
  36 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  37 # include "../mach-omap2/prm.h"
  38 # include "../mach-omap2/cm.h"
  39 # include "../mach-omap2/sdrc.h"
  40 #endif
  41
  42 #define OMAP1_SRAM_PA           0x20000000
  43 #define OMAP1_SRAM_VA           VMALLOC_END
  44 #define OMAP2_SRAM_PA           0x40200000
  45 #define OMAP2_SRAM_PUB_PA       0x4020f800
  46 #define OMAP2_SRAM_VA           0xfe400000
  47 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  48 #define OMAP3_SRAM_PA           0x40200000
  49 #define OMAP3_SRAM_VA           0xfe400000
  50 #define OMAP3_SRAM_PUB_PA       0x40208000
  51 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  52 #define OMAP4_SRAM_PA           0x40300000
  53 #define OMAP4_SRAM_VA           0xfe400000
  54 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  55 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
  56
  57 #if defined(CONFIG_ARCH_OMAP2PLUS)
  58 #define SRAM_BOOTLOADER_SZ      0x00
  59 #else
  60 #define SRAM_BOOTLOADER_SZ      0x80
  61 #endif
  62
  63 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  64 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  65 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  66
  67 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  68 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  69 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  70 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  71 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  72
  73 #define GP_DEVICE               0x300
  74
  75 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  76
  77 static unsigned long omap_sram_start;
  78 static unsigned long omap_sram_base;
  79 static unsigned long omap_sram_size;
  80 static unsigned long omap_sram_ceil;
  81
  82 /*
  83  * Depending on the target RAMFS firewall setup, the public usable amount of
  84  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  85  * device allows ARM11 but not other initiators for full size. This
  86  * functionality seems ok until some nice security API happens.
  87  */
  88 static int is_sram_locked(void)
  89 {
  90         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  91                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  92                 if (cpu_is_omap242x()) {
  93                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  94                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  95                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  96                 }
  97                 if (cpu_is_omap34xx()) {
  98                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  99                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 100                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 101                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 102                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 103                 }
 104                 return 0;
 105         } else
 106                 return 1; /* assume locked with no PPA or security driver */
 107 }
 108
 109 /*
 110  * The amount of SRAM depends on the core type.
 111  * Note that we cannot try to test for SRAM here because writes
 112  * to secure SRAM will hang the system. Also the SRAM is not
 113  * yet mapped at this point.
 114  */
 115 static void __init omap_detect_sram(void)
 116 {
 117         unsigned long reserved;
 118
 119         if (cpu_class_is_omap2()) {
 120                 if (is_sram_locked()) {
 121                         if (cpu_is_omap34xx()) {
 122                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 123                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 124                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 125                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 126                                         omap_sram_size = 0x7000; /* 28K */
 127                                 } else {
 128                                         omap_sram_size = 0x8000; /* 32K */
 129                                 }
 130                         } else if (cpu_is_omap44xx()) {
 131                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
 132                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 133                                 omap_sram_size = 0xa000; /* 40K */
 134                         } else {
 135                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 136                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 137                                 omap_sram_size = 0x800; /* 2K */
 138                         }
 139                 } else {
 140                         if (cpu_is_omap34xx()) {
 141                                 omap_sram_base = OMAP3_SRAM_VA;
 142                                 omap_sram_start = OMAP3_SRAM_PA;
 143                                 omap_sram_size = 0x10000; /* 64K */
 144                         } else if (cpu_is_omap44xx()) {
 145                                 omap_sram_base = OMAP4_SRAM_VA;
 146                                 omap_sram_start = OMAP4_SRAM_PA;
 147                                 omap_sram_size = 0xe000; /* 56K */
 148                         } else {
 149                                 omap_sram_base = OMAP2_SRAM_VA;
 150                                 omap_sram_start = OMAP2_SRAM_PA;
 151                                 if (cpu_is_omap242x())
 152                                         omap_sram_size = 0xa0000; /* 640K */
 153                                 else if (cpu_is_omap243x())
 154                                         omap_sram_size = 0x10000; /* 64K */
 155                         }
 156                 }
 157         } else {
 158                 omap_sram_base = OMAP1_SRAM_VA;
 159                 omap_sram_start = OMAP1_SRAM_PA;
 160
 161                 if (cpu_is_omap7xx())
 162                         omap_sram_size = 0x32000;       /* 200K */
 163                 else if (cpu_is_omap15xx())
 164                         omap_sram_size = 0x30000;       /* 192K */
 165                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 166                      cpu_is_omap1710())
 167                         omap_sram_size = 0x4000;        /* 16K */
 168                 else if (cpu_is_omap1611())
 169                         omap_sram_size = SZ_256K;
 170                 else {
 171                         printk(KERN_ERR "Could not detect SRAM size\n");
 172                         omap_sram_size = 0x4000;
 173                 }
 174         }
 175         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 176                                        omap_sram_size,
 177                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 178                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 179         omap_sram_size -= reserved;
 180
 181         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
 182                         omap_sram_size,
 183                         omap_sram_start + SRAM_BOOTLOADER_SZ,
 184                         omap_sram_size - SRAM_BOOTLOADER_SZ);
 185         omap_sram_size -= reserved;
 186
 187         omap_sram_ceil = omap_sram_base + omap_sram_size;
 188 }
 189
 190 static struct map_desc omap_sram_io_desc[] __initdata = {
 191         {       /* .length gets filled in at runtime */
 192                 .virtual        = OMAP1_SRAM_VA,
 193                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 194                 .type           = MT_MEMORY
 195         }
 196 };
 197
 198 /*
 199  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 200  */
 201 static void __init omap_map_sram(void)
 202 {
 203         unsigned long base;
 204
 205         if (omap_sram_size == 0)
 206                 return;
 207
 208         if (cpu_is_omap34xx()) {
 209                 /*
 210                  * SRAM must be marked as non-cached on OMAP3 since the
 211                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 212                  * SDRAM controller disabled, and if it is marked cached,
 213                  * the ARM may attempt to write cache lines back to SDRAM
 214                  * which will cause the system to hang.
 215                  */
 216                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 217         }
 218
 219         omap_sram_io_desc[0].virtual = omap_sram_base;
 220         base = omap_sram_start;
 221         base = ROUND_DOWN(base, PAGE_SIZE);
 222         omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 223         omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
 224         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 225
 226         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 227         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 228         omap_sram_io_desc[0].virtual,
 229                omap_sram_io_desc[0].length);
 230
 231         /*
 232          * Normally devicemaps_init() would flush caches and tlb after
 233          * mdesc->map_io(), but since we're called from map_io(), we
 234          * must do it here.
 235          */
 236         local_flush_tlb_all();
 237         flush_cache_all();
 238
 239         /*
 240          * Looks like we need to preserve some bootloader code at the
 241          * beginning of SRAM for jumping to flash for reboot to work...
 242          */
 243         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 244                omap_sram_size - SRAM_BOOTLOADER_SZ);
 245 }
 246
 247 void * omap_sram_push(void * start, unsigned long size)
 248 {
 249         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 250                 printk(KERN_ERR "Not enough space in SRAM\n");
 251                 return NULL;
 252         }
 253
 254         omap_sram_ceil -= size;
 255         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 256         memcpy((void *)omap_sram_ceil, start, size);
 257         flush_icache_range((unsigned long)omap_sram_ceil,
 258                 (unsigned long)(omap_sram_ceil + size));
 259
 260         return (void *)omap_sram_ceil;
 261 }
 262
 263 #ifdef CONFIG_ARCH_OMAP1
 264
 265 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 266
 267 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 268 {
 269         BUG_ON(!_omap_sram_reprogram_clock);
 270         _omap_sram_reprogram_clock(dpllctl, ckctl);
 271 }
 272
 273 int __init omap1_sram_init(void)
 274 {
 275         _omap_sram_reprogram_clock =
 276                         omap_sram_push(omap1_sram_reprogram_clock,
 277                                         omap1_sram_reprogram_clock_sz);
 278
 279         return 0;
 280 }
 281
 282 #else
 283 #define omap1_sram_init()       do {} while (0)
 284 #endif
 285
 286 #if defined(CONFIG_ARCH_OMAP2)
 287
 288 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 289                               u32 base_cs, u32 force_unlock);
 290
 291 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 292                    u32 base_cs, u32 force_unlock)
 293 {
 294         BUG_ON(!_omap2_sram_ddr_init);
 295         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 296                              base_cs, force_unlock);
 297 }
 298
 299 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 300                                           u32 mem_type);
 301
 302 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 303 {
 304         BUG_ON(!_omap2_sram_reprogram_sdrc);
 305         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 306 }
 307
 308 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 309
 310 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 311 {
 312         BUG_ON(!_omap2_set_prcm);
 313         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 314 }
 315 #endif
 316
 317 #ifdef CONFIG_ARCH_OMAP2420
 318 static int __init omap242x_sram_init(void)
 319 {
 320         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 321                                         omap242x_sram_ddr_init_sz);
 322
 323         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 324                                             omap242x_sram_reprogram_sdrc_sz);
 325
 326         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 327                                          omap242x_sram_set_prcm_sz);
 328
 329         return 0;
 330 }
 331 #else
 332 static inline int omap242x_sram_init(void)
 333 {
 334         return 0;
 335 }
 336 #endif
 337
 338 #ifdef CONFIG_ARCH_OMAP2430
 339 static int __init omap243x_sram_init(void)
 340 {
 341         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 342                                         omap243x_sram_ddr_init_sz);
 343
 344         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 345                                             omap243x_sram_reprogram_sdrc_sz);
 346
 347         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 348                                          omap243x_sram_set_prcm_sz);
 349
 350         return 0;
 351 }
 352 #else
 353 static inline int omap243x_sram_init(void)
 354 {
 355         return 0;
 356 }
 357 #endif
 358
 359 #ifdef CONFIG_ARCH_OMAP3
 360
 361 static u32 (*_omap3_sram_configure_core_dpll)(
 362                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 363                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 364                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 365                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 366                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 367
 368 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 369                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 370                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 371                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 372                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 373 {
 374         BUG_ON(!_omap3_sram_configure_core_dpll);
 375         return _omap3_sram_configure_core_dpll(
 376                         m2, unlock_dll, f, inc,
 377                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 378                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 379                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 380                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 381 }
 382
 383 #ifdef CONFIG_PM
 384 void omap3_sram_restore_context(void)
 385 {
 386         omap_sram_ceil = omap_sram_base + omap_sram_size;
 387
 388         _omap3_sram_configure_core_dpll =
 389                 omap_sram_push(omap3_sram_configure_core_dpll,
 390                                omap3_sram_configure_core_dpll_sz);
 391         omap_push_sram_idle();
 392 }
 393 #endif /* CONFIG_PM */
 394
 395 static int __init omap34xx_sram_init(void)
 396 {
 397         _omap3_sram_configure_core_dpll =
 398                 omap_sram_push(omap3_sram_configure_core_dpll,
 399                                omap3_sram_configure_core_dpll_sz);
 400         omap_push_sram_idle();
 401         return 0;
 402 }
 403 #else
 404 static inline int omap34xx_sram_init(void)
 405 {
 406         return 0;
 407 }
 408 #endif
 409
 410 #ifdef CONFIG_ARCH_OMAP4
 411 static int __init omap44xx_sram_init(void)
 412 {
 413         printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
 414
 415         return -ENODEV;
 416 }
 417 #else
 418 static inline int omap44xx_sram_init(void)
 419 {
 420         return 0;
 421 }
 422 #endif
 423
 424 int __init omap_sram_init(void)
 425 {
 426         omap_detect_sram();
 427         omap_map_sram();
 428
 429         if (!(cpu_class_is_omap2()))
 430                 omap1_sram_init();
 431         else if (cpu_is_omap242x())
 432                 omap242x_sram_init();
 433         else if (cpu_is_omap2430())
 434                 omap243x_sram_init();
 435         else if (cpu_is_omap34xx())
 436                 omap34xx_sram_init();
 437         else if (cpu_is_omap44xx())
 438                 omap44xx_sram_init();
 439
 440         return 0;
 441 }