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gma500: Fix DPU build
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / gma500 / mdfld_dsi_pkg_sender.c
blob9b96a5c9abcdf77816f76ce6aac58b3c0967a697
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jackie Li<yaodong.li@intel.com>
25 */
26
27 #include <linux/freezer.h>
28
29 #include "mdfld_dsi_output.h"
30 #include "mdfld_dsi_pkg_sender.h"
31 #include "mdfld_dsi_dbi.h"
32 #include "mdfld_dsi_dpi.h"
33
34 #define MDFLD_DSI_DBI_FIFO_TIMEOUT 100
35 #define MDFLD_DSI_MAX_RETURN_PACKET_SIZE 512
36 #define MDFLD_DSI_READ_MAX_COUNT 5000
37
38 static const char * const dsi_errors[] = {
39 "RX SOT Error",
40 "RX SOT Sync Error",
41 "RX EOT Sync Error",
42 "RX Escape Mode Entry Error",
43 "RX LP TX Sync Error",
44 "RX HS Receive Timeout Error",
45 "RX False Control Error",
46 "RX ECC Single Bit Error",
47 "RX ECC Multibit Error",
48 "RX Checksum Error",
49 "RX DSI Data Type Not Recognised",
50 "RX DSI VC ID Invalid",
51 "TX False Control Error",
52 "TX ECC Single Bit Error",
53 "TX ECC Multibit Error",
54 "TX Checksum Error",
55 "TX DSI Data Type Not Recognised",
56 "TX DSI VC ID invalid",
57 "High Contention",
58 "Low contention",
59 "DPI FIFO Under run",
60 "HS TX Timeout",
61 "LP RX Timeout",
62 "Turn Around ACK Timeout",
63 "ACK With No Error",
64 "RX Invalid TX Length",
65 "RX Prot Violation",
66 "HS Generic Write FIFO Full",
67 "LP Generic Write FIFO Full",
68 "Generic Read Data Avail",
69 "Special Packet Sent",
70 "Tearing Effect",
71 };
72
73 static int wait_for_gen_fifo_empty(struct mdfld_dsi_pkg_sender *sender,
74 u32 mask)
75 {
76 struct drm_device *dev = sender->dev;
77 u32 gen_fifo_stat_reg = sender->mipi_gen_fifo_stat_reg;
78 int retry = 0xffff;
79
80 while (retry--) {
81 if ((mask & REG_READ(gen_fifo_stat_reg)) == mask)
82 return 0;
83 udelay(100);
84 }
85 dev_err(dev->dev, "fifo is NOT empty 0x%08x\n",
86 REG_READ(gen_fifo_stat_reg));
87 return -EIO;
88 }
89
90 static int wait_for_all_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
91 {
92 return wait_for_gen_fifo_empty(sender, (1 << 2) | (1 << 10) | (1 << 18)
93 | (1 << 26) | (1 << 27) | (1 << 28));
94 }
95
96 static int wait_for_lp_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
97 {
98 return wait_for_gen_fifo_empty(sender, (1 << 10) | (1 << 26));
99 }
100
101 static int wait_for_hs_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
102 {
103 return wait_for_gen_fifo_empty(sender, (1 << 2) | (1 << 18));
104 }
105
106 static int wait_for_dbi_fifo_empty(struct mdfld_dsi_pkg_sender *sender)
107 {
108 return wait_for_gen_fifo_empty(sender, (1 << 27));
109 }
110
111 static int handle_dsi_error(struct mdfld_dsi_pkg_sender *sender, u32 mask)
112 {
113 u32 intr_stat_reg = sender->mipi_intr_stat_reg;
114 struct drm_device *dev = sender->dev;
115
116 switch (mask) {
117 case (1 << 0):
118 case (1 << 1):
119 case (1 << 2):
120 case (1 << 3):
121 case (1 << 4):
122 case (1 << 5):
123 case (1 << 6):
124 case (1 << 7):
125 case (1 << 8):
126 case (1 << 9):
127 case (1 << 10):
128 case (1 << 11):
129 case (1 << 12):
130 case (1 << 13):
131 break;
132 case (1 << 14):
133 /*wait for all fifo empty*/
134 /*wait_for_all_fifos_empty(sender)*/;
135 break;
136 case (1 << 15):
137 break;
138 case (1 << 16):
139 break;
140 case (1 << 17):
141 break;
142 case (1 << 18):
143 case (1 << 19):
144 /*wait for contention recovery time*/
145 /*mdelay(10);*/
146 /*wait for all fifo empty*/
147 if (0)
148 wait_for_all_fifos_empty(sender);
149 break;
150 case (1 << 20):
151 break;
152 case (1 << 21):
153 /*wait for all fifo empty*/
154 /*wait_for_all_fifos_empty(sender);*/
155 break;
156 case (1 << 22):
157 break;
158 case (1 << 23):
159 case (1 << 24):
160 case (1 << 25):
161 case (1 << 26):
162 case (1 << 27):
163 /* HS Gen fifo full */
164 REG_WRITE(intr_stat_reg, mask);
165 wait_for_hs_fifos_empty(sender);
166 break;
167 case (1 << 28):
168 /* LP Gen fifo full\n */
169 REG_WRITE(intr_stat_reg, mask);
170 wait_for_lp_fifos_empty(sender);
171 break;
172 case (1 << 29):
173 case (1 << 30):
174 case (1 << 31):
175 break;
176 }
177
178 if (mask & REG_READ(intr_stat_reg))
179 dev_warn(dev->dev, "Cannot clean interrupt 0x%08x\n", mask);
180
181 return 0;
182 }
183
184 static int dsi_error_handler(struct mdfld_dsi_pkg_sender *sender)
185 {
186 struct drm_device *dev = sender->dev;
187 u32 intr_stat_reg = sender->mipi_intr_stat_reg;
188 u32 mask;
189 u32 intr_stat;
190 int i;
191 int err = 0;
192
193 intr_stat = REG_READ(intr_stat_reg);
194
195 for (i = 0; i < 32; i++) {
196 mask = (0x00000001UL) << i;
197 if (intr_stat & mask) {
198 dev_dbg(dev->dev, "[DSI]: %s\n", dsi_errors[i]);
199 err = handle_dsi_error(sender, mask);
200 if (err)
201 dev_err(dev->dev, "Cannot handle error\n");
202 }
203 }
204 return err;
205 }
206
207 static inline int dbi_cmd_sent(struct mdfld_dsi_pkg_sender *sender)
208 {
209 struct drm_device *dev = sender->dev;
210 u32 retry = 0xffff;
211 u32 dbi_cmd_addr_reg = sender->mipi_cmd_addr_reg;
212
213 /* Query the command execution status */
214 while (retry--) {
215 if (!(REG_READ(dbi_cmd_addr_reg) & (1 << 0)))
216 break;
217 }
218
219 if (!retry) {
220 dev_err(dev->dev, "Timeout waiting for DBI Command status\n");
221 return -EAGAIN;
222 }
223 return 0;
224 }
225
226 /*
227 * NOTE: this interface is abandoned expect for write_mem_start DCS
228 * other DCS are sent via generic pkg interfaces
229 */
230 static int send_dcs_pkg(struct mdfld_dsi_pkg_sender *sender,
231 struct mdfld_dsi_pkg *pkg)
232 {
233 struct drm_device *dev = sender->dev;
234 struct mdfld_dsi_dcs_pkg *dcs_pkg = &pkg->pkg.dcs_pkg;
235 u32 dbi_cmd_len_reg = sender->mipi_cmd_len_reg;
236 u32 dbi_cmd_addr_reg = sender->mipi_cmd_addr_reg;
237 u32 cb_phy = sender->dbi_cb_phy;
238 u32 index = 0;
239 u8 *cb = (u8 *)sender->dbi_cb_addr;
240 int i;
241 int ret;
242
243 if (!sender->dbi_pkg_support) {
244 dev_err(dev->dev, "Trying to send DCS on a non DBI output, abort!\n");
245 return -ENOTSUPP;
246 }
247
248 /*wait for DBI fifo empty*/
249 wait_for_dbi_fifo_empty(sender);
250
251 *(cb + (index++)) = dcs_pkg->cmd;
252 if (dcs_pkg->param_num) {
253 for (i = 0; i < dcs_pkg->param_num; i++)
254 *(cb + (index++)) = *(dcs_pkg->param + i);
255 }
256
257 REG_WRITE(dbi_cmd_len_reg, (1 + dcs_pkg->param_num));
258 REG_WRITE(dbi_cmd_addr_reg,
259 (cb_phy << CMD_MEM_ADDR_OFFSET)
260 | (1 << 0)
261 | ((dcs_pkg->data_src == CMD_DATA_SRC_PIPE) ? (1 << 1) : 0));
262
263 ret = dbi_cmd_sent(sender);
264 if (ret) {
265 dev_err(dev->dev, "command 0x%x not complete\n", dcs_pkg->cmd);
266 return -EAGAIN;
267 }
268 return 0;
269 }
270
271 static int __send_short_pkg(struct mdfld_dsi_pkg_sender *sender,
272 struct mdfld_dsi_pkg *pkg)
273 {
274 struct drm_device *dev = sender->dev;
275 u32 hs_gen_ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
276 u32 lp_gen_ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
277 u32 gen_ctrl_val = 0;
278 struct mdfld_dsi_gen_short_pkg *short_pkg = &pkg->pkg.short_pkg;
279
280 gen_ctrl_val |= short_pkg->cmd << MCS_COMMANDS_POS;
281 gen_ctrl_val |= 0 << DCS_CHANNEL_NUMBER_POS;
282 gen_ctrl_val |= pkg->pkg_type;
283 gen_ctrl_val |= short_pkg->param << MCS_PARAMETER_POS;
284
285 if (pkg->transmission_type == MDFLD_DSI_HS_TRANSMISSION) {
286 /* wait for hs fifo empty */
287 /* wait_for_hs_fifos_empty(sender); */
288 /* Send pkg */
289 REG_WRITE(hs_gen_ctrl_reg, gen_ctrl_val);
290 } else if (pkg->transmission_type == MDFLD_DSI_LP_TRANSMISSION) {
291 /* wait_for_lp_fifos_empty(sender); */
292 /* Send pkg*/
293 REG_WRITE(lp_gen_ctrl_reg, gen_ctrl_val);
294 } else {
295 dev_err(dev->dev, "Unknown transmission type %d\n",
296 pkg->transmission_type);
297 return -EINVAL;
298 }
299
300 return 0;
301 }
302
303 static int __send_long_pkg(struct mdfld_dsi_pkg_sender *sender,
304 struct mdfld_dsi_pkg *pkg)
305 {
306 struct drm_device *dev = sender->dev;
307 u32 hs_gen_ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
308 u32 hs_gen_data_reg = sender->mipi_hs_gen_data_reg;
309 u32 lp_gen_ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
310 u32 lp_gen_data_reg = sender->mipi_lp_gen_data_reg;
311 u32 gen_ctrl_val = 0;
312 u32 *dp;
313 int i;
314 struct mdfld_dsi_gen_long_pkg *long_pkg = &pkg->pkg.long_pkg;
315
316 dp = long_pkg->data;
317
318 /*
319 * Set up word count for long pkg
320 * FIXME: double check word count field.
321 * currently, using the byte counts of the payload as the word count.
322 * ------------------------------------------------------------
323 * | DI | WC | ECC| PAYLOAD |CHECKSUM|
324 * ------------------------------------------------------------
325 */
326 gen_ctrl_val |= (long_pkg->len << 2) << WORD_COUNTS_POS;
327 gen_ctrl_val |= 0 << DCS_CHANNEL_NUMBER_POS;
328 gen_ctrl_val |= pkg->pkg_type;
329
330 if (pkg->transmission_type == MDFLD_DSI_HS_TRANSMISSION) {
331 /* Wait for hs ctrl and data fifos to be empty */
332 /* wait_for_hs_fifos_empty(sender); */
333 for (i = 0; i < long_pkg->len; i++)
334 REG_WRITE(hs_gen_data_reg, *(dp + i));
335 REG_WRITE(hs_gen_ctrl_reg, gen_ctrl_val);
336 } else if (pkg->transmission_type == MDFLD_DSI_LP_TRANSMISSION) {
337 /* wait_for_lp_fifos_empty(sender); */
338 for (i = 0; i < long_pkg->len; i++)
339 REG_WRITE(lp_gen_data_reg, *(dp + i));
340 REG_WRITE(lp_gen_ctrl_reg, gen_ctrl_val);
341 } else {
342 dev_err(dev->dev, "Unknown transmission type %d\n",
343 pkg->transmission_type);
344 return -EINVAL;
345 }
346
347 return 0;
348
349 }
350
351 static int send_mcs_short_pkg(struct mdfld_dsi_pkg_sender *sender,
352 struct mdfld_dsi_pkg *pkg)
353 {
354 return __send_short_pkg(sender, pkg);
355 }
356
357 static int send_mcs_long_pkg(struct mdfld_dsi_pkg_sender *sender,
358 struct mdfld_dsi_pkg *pkg)
359 {
360 return __send_long_pkg(sender, pkg);
361 }
362
363 static int send_gen_short_pkg(struct mdfld_dsi_pkg_sender *sender,
364 struct mdfld_dsi_pkg *pkg)
365 {
366 return __send_short_pkg(sender, pkg);
367 }
368
369 static int send_gen_long_pkg(struct mdfld_dsi_pkg_sender *sender,
370 struct mdfld_dsi_pkg *pkg)
371 {
372 return __send_long_pkg(sender, pkg);
373 }
374
375 static int send_pkg_prepare(struct mdfld_dsi_pkg_sender *sender,
376 struct mdfld_dsi_pkg *pkg)
377 {
378 u8 cmd;
379 u8 *data;
380
381 switch (pkg->pkg_type) {
382 case MDFLD_DSI_PKG_DCS:
383 cmd = pkg->pkg.dcs_pkg.cmd;
384 break;
385 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_0:
386 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_1:
387 cmd = pkg->pkg.short_pkg.cmd;
388 break;
389 case MDFLD_DSI_PKG_MCS_LONG_WRITE:
390 data = (u8 *)pkg->pkg.long_pkg.data;
391 cmd = *data;
392 break;
393 default:
394 return 0;
395 }
396
397 /* This prevents other package sending while doing msleep */
398 sender->status = MDFLD_DSI_PKG_SENDER_BUSY;
399
400 /* Check panel mode v.s. sending command */
401 if ((sender->panel_mode & MDFLD_DSI_PANEL_MODE_SLEEP) &&
402 cmd != exit_sleep_mode) {
403 dev_err(sender->dev->dev,
404 "sending 0x%x when panel sleep in\n", cmd);
405 sender->status = MDFLD_DSI_PKG_SENDER_FREE;
406 return -EINVAL;
407 }
408
409 /* Wait for 120 milliseconds in case exit_sleep_mode just be sent */
410 if (cmd == DCS_ENTER_SLEEP_MODE) {
411 /*TODO: replace it with msleep later*/
412 mdelay(120);
413 }
414 return 0;
415 }
416
417 static int send_pkg_done(struct mdfld_dsi_pkg_sender *sender,
418 struct mdfld_dsi_pkg *pkg)
419 {
420 u8 cmd;
421 u8 *data;
422
423 switch (pkg->pkg_type) {
424 case MDFLD_DSI_PKG_DCS:
425 cmd = pkg->pkg.dcs_pkg.cmd;
426 break;
427 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_0:
428 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_1:
429 cmd = pkg->pkg.short_pkg.cmd;
430 break;
431 case MDFLD_DSI_PKG_MCS_LONG_WRITE:
432 data = (u8 *)pkg->pkg.long_pkg.data;
433 cmd = *data;
434 break;
435 default:
436 return 0;
437 }
438
439 /* Update panel status */
440 if (cmd == DCS_ENTER_SLEEP_MODE) {
441 sender->panel_mode |= MDFLD_DSI_PANEL_MODE_SLEEP;
442 /*TODO: replace it with msleep later*/
443 mdelay(120);
444 } else if (cmd == DCS_EXIT_SLEEP_MODE) {
445 sender->panel_mode &= ~MDFLD_DSI_PANEL_MODE_SLEEP;
446 /*TODO: replace it with msleep later*/
447 mdelay(120);
448 } else if (unlikely(cmd == DCS_SOFT_RESET)) {
449 /*TODO: replace it with msleep later*/
450 mdelay(5);
451 }
452 sender->status = MDFLD_DSI_PKG_SENDER_FREE;
453 return 0;
454
455 }
456
457 static int do_send_pkg(struct mdfld_dsi_pkg_sender *sender,
458 struct mdfld_dsi_pkg *pkg)
459 {
460 int ret;
461
462 if (sender->status == MDFLD_DSI_PKG_SENDER_BUSY) {
463 dev_err(sender->dev->dev, "sender is busy\n");
464 return -EAGAIN;
465 }
466
467 ret = send_pkg_prepare(sender, pkg);
468 if (ret) {
469 dev_err(sender->dev->dev, "send_pkg_prepare error\n");
470 return ret;
471 }
472
473 switch (pkg->pkg_type) {
474 case MDFLD_DSI_PKG_DCS:
475 ret = send_dcs_pkg(sender, pkg);
476 break;
477 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_0:
478 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_1:
479 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_2:
480 case MDFLD_DSI_PKG_GEN_READ_0:
481 case MDFLD_DSI_PKG_GEN_READ_1:
482 case MDFLD_DSI_PKG_GEN_READ_2:
483 ret = send_gen_short_pkg(sender, pkg);
484 break;
485 case MDFLD_DSI_PKG_GEN_LONG_WRITE:
486 ret = send_gen_long_pkg(sender, pkg);
487 break;
488 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_0:
489 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_1:
490 case MDFLD_DSI_PKG_MCS_READ:
491 ret = send_mcs_short_pkg(sender, pkg);
492 break;
493 case MDFLD_DSI_PKG_MCS_LONG_WRITE:
494 ret = send_mcs_long_pkg(sender, pkg);
495 break;
496 default:
497 dev_err(sender->dev->dev, "Invalid pkg type 0x%x\n",
498 pkg->pkg_type);
499 ret = -EINVAL;
500 }
501 send_pkg_done(sender, pkg);
502 return ret;
503 }
504
505 static int send_pkg(struct mdfld_dsi_pkg_sender *sender,
506 struct mdfld_dsi_pkg *pkg)
507 {
508 int err ;
509
510 /* Handle DSI error */
511 err = dsi_error_handler(sender);
512 if (err) {
513 dev_err(sender->dev->dev, "Error handling failed\n");
514 err = -EAGAIN;
515 goto send_pkg_err;
516 }
517
518 /* Send pkg */
519 err = do_send_pkg(sender, pkg);
520 if (err) {
521 dev_err(sender->dev->dev, "sent pkg failed\n");
522 err = -EAGAIN;
523 goto send_pkg_err;
524 }
525
526 /* FIXME: should I query complete and fifo empty here? */
527 send_pkg_err:
528 return err;
529 }
530
531 static struct mdfld_dsi_pkg *pkg_sender_get_pkg_locked(
532 struct mdfld_dsi_pkg_sender *sender)
533 {
534 struct mdfld_dsi_pkg *pkg;
535
536 if (list_empty(&sender->free_list)) {
537 dev_err(sender->dev->dev, "No free pkg left\n");
538 return NULL;
539 }
540 pkg = list_first_entry(&sender->free_list, struct mdfld_dsi_pkg, entry);
541 /* Detach from free list */
542 list_del_init(&pkg->entry);
543 return pkg;
544 }
545
546 static void pkg_sender_put_pkg_locked(struct mdfld_dsi_pkg_sender *sender,
547 struct mdfld_dsi_pkg *pkg)
548 {
549 memset(pkg, 0, sizeof(struct mdfld_dsi_pkg));
550 INIT_LIST_HEAD(&pkg->entry);
551 list_add_tail(&pkg->entry, &sender->free_list);
552 }
553
554 static int mdfld_dbi_cb_init(struct mdfld_dsi_pkg_sender *sender,
555 struct psb_gtt *pg, int pipe)
556 {
557 unsigned long phys;
558 void *virt_addr = NULL;
559
560 switch (pipe) {
561 case 0:
562 /* FIXME: Doesn't this collide with stolen space ? */
563 phys = pg->gtt_phys_start - 0x1000;
564 break;
565 case 2:
566 phys = pg->gtt_phys_start - 0x800;
567 break;
568 default:
569 dev_err(sender->dev->dev, "Unsupported channel %d\n", pipe);
570 return -EINVAL;
571 }
572
573 virt_addr = ioremap_nocache(phys, 0x800);
574 if (!virt_addr) {
575 dev_err(sender->dev->dev, "Map DBI command buffer error\n");
576 return -ENOMEM;
577 }
578 sender->dbi_cb_phy = phys;
579 sender->dbi_cb_addr = virt_addr;
580 return 0;
581 }
582
583 static void mdfld_dbi_cb_destroy(struct mdfld_dsi_pkg_sender *sender)
584 {
585 if (sender && sender->dbi_cb_addr)
586 iounmap(sender->dbi_cb_addr);
587 }
588
589 static void pkg_sender_queue_pkg(struct mdfld_dsi_pkg_sender *sender,
590 struct mdfld_dsi_pkg *pkg,
591 int delay)
592 {
593 unsigned long flags;
594
595 spin_lock_irqsave(&sender->lock, flags);
596
597 if (!delay) {
598 send_pkg(sender, pkg);
599 pkg_sender_put_pkg_locked(sender, pkg);
600 } else {
601 /* Queue it */
602 list_add_tail(&pkg->entry, &sender->pkg_list);
603 }
604 spin_unlock_irqrestore(&sender->lock, flags);
605 }
606
607 static void process_pkg_list(struct mdfld_dsi_pkg_sender *sender)
608 {
609 struct mdfld_dsi_pkg *pkg;
610 unsigned long flags;
611
612 spin_lock_irqsave(&sender->lock, flags);
613
614 while (!list_empty(&sender->pkg_list)) {
615 pkg = list_first_entry(&sender->pkg_list,
616 struct mdfld_dsi_pkg, entry);
617 send_pkg(sender, pkg);
618 list_del_init(&pkg->entry);
619 pkg_sender_put_pkg_locked(sender, pkg);
620 }
621
622 spin_unlock_irqrestore(&sender->lock, flags);
623 }
624
625 static int mdfld_dsi_send_mcs_long(struct mdfld_dsi_pkg_sender *sender,
626 u32 *data, u32 len, u8 transmission, int delay)
627 {
628 struct mdfld_dsi_pkg *pkg;
629 unsigned long flags;
630
631 spin_lock_irqsave(&sender->lock, flags);
632 pkg = pkg_sender_get_pkg_locked(sender);
633 spin_unlock_irqrestore(&sender->lock, flags);
634
635 if (!pkg) {
636 dev_err(sender->dev->dev, "No memory\n");
637 return -ENOMEM;
638 }
639 pkg->pkg_type = MDFLD_DSI_PKG_MCS_LONG_WRITE;
640 pkg->transmission_type = transmission;
641 pkg->pkg.long_pkg.data = data;
642 pkg->pkg.long_pkg.len = len;
643 INIT_LIST_HEAD(&pkg->entry);
644
645 pkg_sender_queue_pkg(sender, pkg, delay);
646 return 0;
647 }
648
649 static int mdfld_dsi_send_mcs_short(struct mdfld_dsi_pkg_sender *sender,
650 u8 cmd, u8 param, u8 param_num,
651 u8 transmission,
652 int delay)
653 {
654 struct mdfld_dsi_pkg *pkg;
655 unsigned long flags;
656
657 spin_lock_irqsave(&sender->lock, flags);
658 pkg = pkg_sender_get_pkg_locked(sender);
659 spin_unlock_irqrestore(&sender->lock, flags);
660
661 if (!pkg) {
662 dev_err(sender->dev->dev, "No memory\n");
663 return -ENOMEM;
664 }
665
666 if (param_num) {
667 pkg->pkg_type = MDFLD_DSI_PKG_MCS_SHORT_WRITE_1;
668 pkg->pkg.short_pkg.param = param;
669 } else {
670 pkg->pkg_type = MDFLD_DSI_PKG_MCS_SHORT_WRITE_0;
671 pkg->pkg.short_pkg.param = 0;
672 }
673 pkg->transmission_type = transmission;
674 pkg->pkg.short_pkg.cmd = cmd;
675 INIT_LIST_HEAD(&pkg->entry);
676
677 pkg_sender_queue_pkg(sender, pkg, delay);
678 return 0;
679 }
680
681 static int mdfld_dsi_send_gen_short(struct mdfld_dsi_pkg_sender *sender,
682 u8 param0, u8 param1, u8 param_num,
683 u8 transmission,
684 int delay)
685 {
686 struct mdfld_dsi_pkg *pkg;
687 unsigned long flags;
688
689 spin_lock_irqsave(&sender->lock, flags);
690 pkg = pkg_sender_get_pkg_locked(sender);
691 spin_unlock_irqrestore(&sender->lock, flags);
692
693 if (!pkg) {
694 dev_err(sender->dev->dev, "No pkg memory\n");
695 return -ENOMEM;
696 }
697
698 switch (param_num) {
699 case 0:
700 pkg->pkg_type = MDFLD_DSI_PKG_GEN_SHORT_WRITE_0;
701 pkg->pkg.short_pkg.cmd = 0;
702 pkg->pkg.short_pkg.param = 0;
703 break;
704 case 1:
705 pkg->pkg_type = MDFLD_DSI_PKG_GEN_SHORT_WRITE_1;
706 pkg->pkg.short_pkg.cmd = param0;
707 pkg->pkg.short_pkg.param = 0;
708 break;
709 case 2:
710 pkg->pkg_type = MDFLD_DSI_PKG_GEN_SHORT_WRITE_2;
711 pkg->pkg.short_pkg.cmd = param0;
712 pkg->pkg.short_pkg.param = param1;
713 break;
714 }
715
716 pkg->transmission_type = transmission;
717 INIT_LIST_HEAD(&pkg->entry);
718
719 pkg_sender_queue_pkg(sender, pkg, delay);
720 return 0;
721 }
722
723 static int mdfld_dsi_send_gen_long(struct mdfld_dsi_pkg_sender *sender,
724 u32 *data, u32 len, u8 transmission, int delay)
725 {
726 struct mdfld_dsi_pkg *pkg;
727 unsigned long flags;
728
729 spin_lock_irqsave(&sender->lock, flags);
730 pkg = pkg_sender_get_pkg_locked(sender);
731 spin_unlock_irqrestore(&sender->lock, flags);
732
733 if (!pkg) {
734 dev_err(sender->dev->dev, "No pkg memory\n");
735 return -ENOMEM;
736 }
737
738 pkg->pkg_type = MDFLD_DSI_PKG_GEN_LONG_WRITE;
739 pkg->transmission_type = transmission;
740 pkg->pkg.long_pkg.data = data;
741 pkg->pkg.long_pkg.len = len;
742
743 INIT_LIST_HEAD(&pkg->entry);
744
745 pkg_sender_queue_pkg(sender, pkg, delay);
746
747 return 0;
748 }
749
750 static int __read_panel_data(struct mdfld_dsi_pkg_sender *sender,
751 struct mdfld_dsi_pkg *pkg,
752 u32 *data,
753 u16 len)
754 {
755 unsigned long flags;
756 struct drm_device *dev = sender->dev;
757 int i;
758 u32 gen_data_reg;
759 int retry = MDFLD_DSI_READ_MAX_COUNT;
760 u8 transmission = pkg->transmission_type;
761
762 /*
763 * do reading.
764 * 0) send out generic read request
765 * 1) polling read data avail interrupt
766 * 2) read data
767 */
768 spin_lock_irqsave(&sender->lock, flags);
769
770 REG_WRITE(sender->mipi_intr_stat_reg, 1 << 29);
771
772 if ((REG_READ(sender->mipi_intr_stat_reg) & (1 << 29)))
773 DRM_ERROR("Can NOT clean read data valid interrupt\n");
774
775 /*send out read request*/
776 send_pkg(sender, pkg);
777
778 pkg_sender_put_pkg_locked(sender, pkg);
779
780 /*polling read data avail interrupt*/
781 while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & (1 << 29))) {
782 udelay(100);
783 retry--;
784 }
785
786 if (!retry) {
787 spin_unlock_irqrestore(&sender->lock, flags);
788 return -ETIMEDOUT;
789 }
790
791 REG_WRITE(sender->mipi_intr_stat_reg, (1 << 29));
792
793 /*read data*/
794 if (transmission == MDFLD_DSI_HS_TRANSMISSION)
795 gen_data_reg = sender->mipi_hs_gen_data_reg;
796 else if (transmission == MDFLD_DSI_LP_TRANSMISSION)
797 gen_data_reg = sender->mipi_lp_gen_data_reg;
798 else {
799 DRM_ERROR("Unknown transmission");
800 spin_unlock_irqrestore(&sender->lock, flags);
801 return -EINVAL;
802 }
803
804 for (i=0; i<len; i++)
805 *(data + i) = REG_READ(gen_data_reg);
806
807 spin_unlock_irqrestore(&sender->lock, flags);
808
809 return 0;
810 }
811
812 static int mdfld_dsi_read_gen(struct mdfld_dsi_pkg_sender *sender,
813 u8 param0,
814 u8 param1,
815 u8 param_num,
816 u32 *data,
817 u16 len,
818 u8 transmission)
819 {
820 struct mdfld_dsi_pkg *pkg;
821 unsigned long flags;
822
823 spin_lock_irqsave(&sender->lock, flags);
824
825 pkg = pkg_sender_get_pkg_locked(sender);
826
827 spin_unlock_irqrestore(&sender->lock,flags);
828
829 if (!pkg) {
830 dev_err(sender->dev->dev, "No pkg memory\n");
831 return -ENOMEM;
832 }
833
834 switch (param_num) {
835 case 0:
836 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_0;
837 pkg->pkg.short_pkg.cmd = 0;
838 pkg->pkg.short_pkg.param = 0;
839 break;
840 case 1:
841 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_1;
842 pkg->pkg.short_pkg.cmd = param0;
843 pkg->pkg.short_pkg.param = 0;
844 break;
845 case 2:
846 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_2;
847 pkg->pkg.short_pkg.cmd = param0;
848 pkg->pkg.short_pkg.param = param1;
849 break;
850 }
851
852 pkg->transmission_type = transmission;
853
854 INIT_LIST_HEAD(&pkg->entry);
855
856 return __read_panel_data(sender, pkg, data, len);
857 }
858
859 static int mdfld_dsi_read_mcs(struct mdfld_dsi_pkg_sender *sender,
860 u8 cmd,
861 u32 *data,
862 u16 len,
863 u8 transmission)
864 {
865 struct mdfld_dsi_pkg *pkg;
866 unsigned long flags;
867
868 spin_lock_irqsave(&sender->lock, flags);
869
870 pkg = pkg_sender_get_pkg_locked(sender);
871
872 spin_unlock_irqrestore(&sender->lock, flags);
873
874 if (!pkg) {
875 dev_err(sender->dev->dev, "No pkg memory\n");
876 return -ENOMEM;
877 }
878
879 pkg->pkg_type = MDFLD_DSI_PKG_MCS_READ;
880 pkg->pkg.short_pkg.cmd = cmd;
881 pkg->pkg.short_pkg.param = 0;
882
883 pkg->transmission_type = transmission;
884
885 INIT_LIST_HEAD(&pkg->entry);
886
887 return __read_panel_data(sender, pkg, data, len);
888 }
889
890 void dsi_controller_dbi_init(struct mdfld_dsi_config * dsi_config, int pipe)
891 {
892 struct drm_device * dev = dsi_config->dev;
893 u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
894 int lane_count = dsi_config->lane_count;
895 u32 val = 0;
896
897 /*un-ready device*/
898 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
899
900 /*init dsi adapter before kicking off*/
901 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
902
903 /*TODO: figure out how to setup these registers*/
904 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
905 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), 0x000a0014);
906 REG_WRITE((MIPIA_DBI_BW_CTRL_REG + reg_offset), 0x00000400);
907 REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000001);
908 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000);
909
910 /*enable all interrupts*/
911 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
912 /*max value: 20 clock cycles of txclkesc*/
913 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f);
914 /*min 21 txclkesc, max: ffffh*/
915 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff);
916 /*min: 7d0 max: 4e20*/
917 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0);
918
919 /*set up max return packet size*/
920 REG_WRITE((MIPIA_MAX_RETURN_PACK_SIZE_REG + reg_offset),
921 MDFLD_DSI_MAX_RETURN_PACKET_SIZE);
922
923 /*set up func_prg*/
924 val |= lane_count;
925 val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET);
926 val |= DSI_DBI_COLOR_FORMAT_OPTION2;
927 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
928
929 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff);
930 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff);
931
932 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
933 REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000000);
934 REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
935 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
936 }
937
938 void dsi_controller_dpi_init(struct mdfld_dsi_config * dsi_config, int pipe)
939 {
940 struct drm_device * dev = dsi_config->dev;
941 u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
942 int lane_count = dsi_config->lane_count;
943 struct mdfld_dsi_dpi_timing dpi_timing;
944 struct drm_display_mode * mode = dsi_config->mode;
945 u32 val = 0;
946
947 /*un-ready device*/
948 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
949
950 /*init dsi adapter before kicking off*/
951 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
952
953 /*enable all interrupts*/
954 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
955
956 /*set up func_prg*/
957 val |= lane_count;
958 val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET;
959
960 switch(dsi_config->bpp) {
961 case 16:
962 val |= DSI_DPI_COLOR_FORMAT_RGB565;
963 break;
964 case 18:
965 val |= DSI_DPI_COLOR_FORMAT_RGB666;
966 break;
967 case 24:
968 val |= DSI_DPI_COLOR_FORMAT_RGB888;
969 break;
970 default:
971 DRM_ERROR("unsupported color format, bpp = %d\n", dsi_config->bpp);
972 }
973
974 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
975
976 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset),
977 (mode->vtotal * mode->htotal * dsi_config->bpp / (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK);
978 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff & DSI_LP_RX_TIMEOUT_MASK);
979
980 /*max value: 20 clock cycles of txclkesc*/
981 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x14 & DSI_TURN_AROUND_TIMEOUT_MASK);
982
983 /*min 21 txclkesc, max: ffffh*/
984 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0xffff & DSI_RESET_TIMER_MASK);
985
986 REG_WRITE((MIPIA_DPI_RESOLUTION_REG + reg_offset), mode->vdisplay << 16 | mode->hdisplay);
987
988 /*set DPI timing registers*/
989 mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing, dsi_config->lane_count, dsi_config->bpp);
990
991 REG_WRITE((MIPIA_HSYNC_COUNT_REG + reg_offset), dpi_timing.hsync_count & DSI_DPI_TIMING_MASK);
992 REG_WRITE((MIPIA_HBP_COUNT_REG + reg_offset), dpi_timing.hbp_count & DSI_DPI_TIMING_MASK);
993 REG_WRITE((MIPIA_HFP_COUNT_REG + reg_offset), dpi_timing.hfp_count & DSI_DPI_TIMING_MASK);
994 REG_WRITE((MIPIA_HACTIVE_COUNT_REG + reg_offset), dpi_timing.hactive_count & DSI_DPI_TIMING_MASK);
995 REG_WRITE((MIPIA_VSYNC_COUNT_REG + reg_offset), dpi_timing.vsync_count & DSI_DPI_TIMING_MASK);
996 REG_WRITE((MIPIA_VBP_COUNT_REG + reg_offset), dpi_timing.vbp_count & DSI_DPI_TIMING_MASK);
997 REG_WRITE((MIPIA_VFP_COUNT_REG + reg_offset), dpi_timing.vfp_count & DSI_DPI_TIMING_MASK);
998
999 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
1000
1001 /*min: 7d0 max: 4e20*/
1002 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x000007d0);
1003
1004 /*set up video mode*/
1005 val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE;
1006 REG_WRITE((MIPIA_VIDEO_MODE_FORMAT_REG + reg_offset), val);
1007
1008 REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000000);
1009
1010 REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
1011
1012 /*TODO: figure out how to setup these registers*/
1013 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
1014
1015 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), (0xa << 16) | 0x14);
1016
1017 /*set device ready*/
1018 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
1019 }
1020
1021 static void dsi_controller_init(struct mdfld_dsi_config * dsi_config, int pipe)
1022 {
1023 if (!dsi_config || ((pipe != 0) && (pipe != 2))) {
1024 DRM_ERROR("Invalid parameters\n");
1025 return;
1026 }
1027
1028 if (dsi_config->type == MDFLD_DSI_ENCODER_DPI)
1029 dsi_controller_dpi_init(dsi_config, pipe);
1030 else if (dsi_config->type == MDFLD_DSI_ENCODER_DBI)
1031 dsi_controller_dbi_init(dsi_config, pipe);
1032 else
1033 DRM_ERROR("Bad DSI encoder type\n");
1034 }
1035
1036 void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender)
1037 {
1038 process_pkg_list(sender);
1039 }
1040
1041 int mdfld_dsi_send_dcs(struct mdfld_dsi_pkg_sender *sender,
1042 u8 dcs, u8 *param, u32 param_num, u8 data_src,
1043 int delay)
1044 {
1045 struct mdfld_dsi_pkg *pkg;
1046 u32 cb_phy = sender->dbi_cb_phy;
1047 struct drm_device *dev = sender->dev;
1048 u32 index = 0;
1049 u8 *cb = (u8 *)sender->dbi_cb_addr;
1050 unsigned long flags;
1051 int retry;
1052 u8 *dst = NULL;
1053 u32 len;
1054
1055 if (!sender) {
1056 WARN_ON(1);
1057 return -EINVAL;
1058 }
1059
1060 if (!sender->dbi_pkg_support) {
1061 dev_err(dev->dev, "No DBI pkg sending on this sender\n");
1062 return -ENOTSUPP;
1063 }
1064
1065 if (param_num > MDFLD_MAX_DCS_PARAM) {
1066 dev_err(dev->dev, "Sender only supports up to %d DCS params\n",
1067 MDFLD_MAX_DCS_PARAM);
1068 return -EINVAL;
1069 }
1070
1071 /*
1072 * If dcs is write_mem_start, send it directly using DSI adapter
1073 * interface
1074 */
1075 if (dcs == DCS_WRITE_MEM_START) {
1076 if (!spin_trylock(&sender->lock))
1077 return -EAGAIN;
1078
1079 /*
1080 * query whether DBI FIFO is empty,
1081 * if not wait it becoming empty
1082 */
1083 retry = MDFLD_DSI_DBI_FIFO_TIMEOUT;
1084 while (retry &&
1085 !(REG_READ(sender->mipi_gen_fifo_stat_reg) & (1 << 27))) {
1086 udelay(500);
1087 retry--;
1088 }
1089
1090 /* If DBI FIFO timeout, drop this frame */
1091 if (!retry) {
1092 spin_unlock(&sender->lock);
1093 return 0;
1094 }
1095
1096 *(cb + (index++)) = write_mem_start;
1097
1098 REG_WRITE(sender->mipi_cmd_len_reg, 1);
1099 REG_WRITE(sender->mipi_cmd_addr_reg,
1100 cb_phy | (1 << 0) | (1 << 1));
1101
1102 retry = MDFLD_DSI_DBI_FIFO_TIMEOUT;
1103 while (retry &&
1104 (REG_READ(sender->mipi_cmd_addr_reg) & (1 << 0))) {
1105 udelay(1);
1106 retry--;
1107 }
1108
1109 spin_unlock(&sender->lock);
1110 return 0;
1111 }
1112
1113 /* Get a free pkg */
1114 spin_lock_irqsave(&sender->lock, flags);
1115 pkg = pkg_sender_get_pkg_locked(sender);
1116 spin_unlock_irqrestore(&sender->lock, flags);
1117
1118 if (!pkg) {
1119 dev_err(dev->dev, "No packages memory\n");
1120 return -ENOMEM;
1121 }
1122
1123 dst = pkg->pkg.dcs_pkg.param;
1124 memcpy(dst, param, param_num);
1125
1126 pkg->pkg_type = MDFLD_DSI_PKG_DCS;
1127 pkg->transmission_type = MDFLD_DSI_DCS;
1128 pkg->pkg.dcs_pkg.cmd = dcs;
1129 pkg->pkg.dcs_pkg.param_num = param_num;
1130 pkg->pkg.dcs_pkg.data_src = data_src;
1131
1132 INIT_LIST_HEAD(&pkg->entry);
1133
1134 if (param_num == 0)
1135 return mdfld_dsi_send_mcs_short_hs(sender, dcs, 0, 0, delay);
1136 else if (param_num == 1)
1137 return mdfld_dsi_send_mcs_short_hs(sender, dcs,
1138 param[0], 1, delay);
1139 else if (param_num > 1) {
1140 len = (param_num + 1) / 4;
1141 if ((param_num + 1) % 4)
1142 len++;
1143 return mdfld_dsi_send_mcs_long_hs(sender,
1144 (u32 *)&pkg->pkg.dcs_pkg, len, delay);
1145 }
1146 return 0;
1147 }
1148
1149 int mdfld_dsi_send_mcs_short_hs(struct mdfld_dsi_pkg_sender *sender,
1150 u8 cmd, u8 param, u8 param_num, int delay)
1151 {
1152 if (!sender) {
1153 WARN_ON(1);
1154 return -EINVAL;
1155 }
1156 return mdfld_dsi_send_mcs_short(sender, cmd, param, param_num,
1157 MDFLD_DSI_HS_TRANSMISSION, delay);
1158 }
1159
1160 int mdfld_dsi_send_mcs_short_lp(struct mdfld_dsi_pkg_sender *sender,
1161 u8 cmd, u8 param, u8 param_num, int delay)
1162 {
1163 if (!sender) {
1164 WARN_ON(1);
1165 return -EINVAL;
1166 }
1167 return mdfld_dsi_send_mcs_short(sender, cmd, param, param_num,
1168 MDFLD_DSI_LP_TRANSMISSION, delay);
1169 }
1170
1171 int mdfld_dsi_send_mcs_long_hs(struct mdfld_dsi_pkg_sender *sender,
1172 u32 *data,
1173 u32 len,
1174 int delay)
1175 {
1176 if (!sender || !data || !len) {
1177 DRM_ERROR("Invalid parameters\n");
1178 return -EINVAL;
1179 }
1180 return mdfld_dsi_send_mcs_long(sender, data, len,
1181 MDFLD_DSI_HS_TRANSMISSION, delay);
1182 }
1183
1184 int mdfld_dsi_send_mcs_long_lp(struct mdfld_dsi_pkg_sender *sender,
1185 u32 *data,
1186 u32 len,
1187 int delay)
1188 {
1189 if (!sender || !data || !len) {
1190 WARN_ON(1);
1191 return -EINVAL;
1192 }
1193 return mdfld_dsi_send_mcs_long(sender, data, len,
1194 MDFLD_DSI_LP_TRANSMISSION, delay);
1195 }
1196
1197 int mdfld_dsi_send_gen_short_hs(struct mdfld_dsi_pkg_sender *sender,
1198 u8 param0, u8 param1, u8 param_num, int delay)
1199 {
1200 if (!sender) {
1201 WARN_ON(1);
1202 return -EINVAL;
1203 }
1204 return mdfld_dsi_send_gen_short(sender, param0, param1, param_num,
1205 MDFLD_DSI_HS_TRANSMISSION, delay);
1206 }
1207
1208 int mdfld_dsi_send_gen_short_lp(struct mdfld_dsi_pkg_sender *sender,
1209 u8 param0, u8 param1, u8 param_num, int delay)
1210 {
1211 if (!sender || param_num < 0 || param_num > 2) {
1212 WARN_ON(1);
1213 return -EINVAL;
1214 }
1215 return mdfld_dsi_send_gen_short(sender, param0, param1, param_num,
1216 MDFLD_DSI_LP_TRANSMISSION, delay);
1217 }
1218
1219 int mdfld_dsi_send_gen_long_hs(struct mdfld_dsi_pkg_sender *sender,
1220 u32 *data,
1221 u32 len,
1222 int delay)
1223 {
1224 if (!sender || !data || !len) {
1225 WARN_ON(1);
1226 return -EINVAL;
1227 }
1228 return mdfld_dsi_send_gen_long(sender, data, len,
1229 MDFLD_DSI_HS_TRANSMISSION, delay);
1230 }
1231
1232 int mdfld_dsi_send_gen_long_lp(struct mdfld_dsi_pkg_sender *sender,
1233 u32 *data,
1234 u32 len,
1235 int delay)
1236 {
1237 if (!sender || !data || !len) {
1238 WARN_ON(1);
1239 return -EINVAL;
1240 }
1241 return mdfld_dsi_send_gen_long(sender, data, len,
1242 MDFLD_DSI_LP_TRANSMISSION, delay);
1243 }
1244
1245 int mdfld_dsi_read_gen_hs(struct mdfld_dsi_pkg_sender *sender,
1246 u8 param0,
1247 u8 param1,
1248 u8 param_num,
1249 u32 *data,
1250 u16 len)
1251 {
1252 if (!sender || !data || param_num < 0 || param_num > 2
1253 || !data || !len) {
1254 DRM_ERROR("Invalid parameters\n");
1255 return -EINVAL;
1256 }
1257
1258 return mdfld_dsi_read_gen(sender, param0, param1, param_num,
1259 data, len, MDFLD_DSI_HS_TRANSMISSION);
1260
1261 }
1262
1263 int mdfld_dsi_read_gen_lp(struct mdfld_dsi_pkg_sender *sender,
1264 u8 param0,
1265 u8 param1,
1266 u8 param_num,
1267 u32 *data,
1268 u16 len)
1269 {
1270 if (!sender || !data || param_num < 0 || param_num > 2
1271 || !data || !len) {
1272 DRM_ERROR("Invalid parameters\n");
1273 return -EINVAL;
1274 }
1275
1276 return mdfld_dsi_read_gen(sender, param0, param1, param_num,
1277 data, len, MDFLD_DSI_LP_TRANSMISSION);
1278 }
1279
1280 int mdfld_dsi_read_mcs_hs(struct mdfld_dsi_pkg_sender *sender,
1281 u8 cmd,
1282 u32 *data,
1283 u16 len)
1284 {
1285 if (!sender || !data || !len) {
1286 DRM_ERROR("Invalid parameters\n");
1287 return -EINVAL;
1288 }
1289
1290 return mdfld_dsi_read_mcs(sender, cmd, data, len,
1291 MDFLD_DSI_HS_TRANSMISSION);
1292 }
1293
1294 int mdfld_dsi_read_mcs_lp(struct mdfld_dsi_pkg_sender *sender,
1295 u8 cmd,
1296 u32 *data,
1297 u16 len)
1298 {
1299 if (!sender || !data || !len) {
1300 WARN_ON(1);
1301 return -EINVAL;
1302 }
1303
1304 return mdfld_dsi_read_mcs(sender, cmd, data, len,
1305 MDFLD_DSI_LP_TRANSMISSION);
1306 }
1307
1308 int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
1309 int pipe)
1310 {
1311 int ret;
1312 struct mdfld_dsi_pkg_sender *pkg_sender;
1313 struct mdfld_dsi_config *dsi_config =
1314 mdfld_dsi_get_config(dsi_connector);
1315 struct drm_device *dev = dsi_config->dev;
1316 struct drm_psb_private *dev_priv = dev->dev_private;
1317 struct psb_gtt *pg = &dev_priv->gtt;
1318 int i;
1319 struct mdfld_dsi_pkg *pkg, *tmp;
1320 u32 mipi_val = 0;
1321
1322 if (!dsi_connector) {
1323 WARN_ON(1);
1324 return -EINVAL;
1325 }
1326
1327 pkg_sender = dsi_connector->pkg_sender;
1328
1329 if (!pkg_sender || IS_ERR(pkg_sender)) {
1330 pkg_sender = kzalloc(sizeof(struct mdfld_dsi_pkg_sender),
1331 GFP_KERNEL);
1332 if (!pkg_sender) {
1333 dev_err(dev->dev, "Create DSI pkg sender failed\n");
1334 return -ENOMEM;
1335 }
1336
1337 dsi_connector->pkg_sender = (void *)pkg_sender;
1338 }
1339
1340 pkg_sender->dev = dev;
1341 pkg_sender->dsi_connector = dsi_connector;
1342 pkg_sender->pipe = pipe;
1343 pkg_sender->pkg_num = 0;
1344 pkg_sender->panel_mode = 0;
1345 pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE;
1346
1347 /* Init dbi command buffer*/
1348
1349 if (dsi_config->type == MDFLD_DSI_ENCODER_DBI) {
1350 pkg_sender->dbi_pkg_support = 1;
1351 ret = mdfld_dbi_cb_init(pkg_sender, pg, pipe);
1352 if (ret) {
1353 dev_err(dev->dev, "DBI command buffer map failed\n");
1354 goto mapping_err;
1355 }
1356 }
1357
1358 /* Init regs */
1359 if (pipe == 0) {
1360 pkg_sender->dpll_reg = MRST_DPLL_A;
1361 pkg_sender->dspcntr_reg = DSPACNTR;
1362 pkg_sender->pipeconf_reg = PIPEACONF;
1363 pkg_sender->dsplinoff_reg = DSPALINOFF;
1364 pkg_sender->dspsurf_reg = DSPASURF;
1365 pkg_sender->pipestat_reg = PIPEASTAT;
1366
1367 pkg_sender->mipi_intr_stat_reg = MIPIA_INTR_STAT_REG;
1368 pkg_sender->mipi_lp_gen_data_reg = MIPIA_LP_GEN_DATA_REG;
1369 pkg_sender->mipi_hs_gen_data_reg = MIPIA_HS_GEN_DATA_REG;
1370 pkg_sender->mipi_lp_gen_ctrl_reg = MIPIA_LP_GEN_CTRL_REG;
1371 pkg_sender->mipi_hs_gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
1372 pkg_sender->mipi_gen_fifo_stat_reg = MIPIA_GEN_FIFO_STAT_REG;
1373 pkg_sender->mipi_data_addr_reg = MIPIA_DATA_ADD_REG;
1374 pkg_sender->mipi_data_len_reg = MIPIA_DATA_LEN_REG;
1375 pkg_sender->mipi_cmd_addr_reg = MIPIA_CMD_ADD_REG;
1376 pkg_sender->mipi_cmd_len_reg = MIPIA_CMD_LEN_REG;
1377 } else if (pipe == 2) {
1378 pkg_sender->dpll_reg = MRST_DPLL_A;
1379 pkg_sender->dspcntr_reg = DSPCCNTR;
1380 pkg_sender->pipeconf_reg = PIPECCONF;
1381 pkg_sender->dsplinoff_reg = DSPCLINOFF;
1382 pkg_sender->dspsurf_reg = DSPCSURF;
1383 pkg_sender->pipestat_reg = PIPECSTAT;
1384
1385 pkg_sender->mipi_intr_stat_reg =
1386 MIPIA_INTR_STAT_REG + MIPIC_REG_OFFSET;
1387 pkg_sender->mipi_lp_gen_data_reg =
1388 MIPIA_LP_GEN_DATA_REG + MIPIC_REG_OFFSET;
1389 pkg_sender->mipi_hs_gen_data_reg =
1390 MIPIA_HS_GEN_DATA_REG + MIPIC_REG_OFFSET;
1391 pkg_sender->mipi_lp_gen_ctrl_reg =
1392 MIPIA_LP_GEN_CTRL_REG + MIPIC_REG_OFFSET;
1393 pkg_sender->mipi_hs_gen_ctrl_reg =
1394 MIPIA_HS_GEN_CTRL_REG + MIPIC_REG_OFFSET;
1395 pkg_sender->mipi_gen_fifo_stat_reg =
1396 MIPIA_GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET;
1397 pkg_sender->mipi_data_addr_reg =
1398 MIPIA_DATA_ADD_REG + MIPIC_REG_OFFSET;
1399 pkg_sender->mipi_data_len_reg =
1400 MIPIA_DATA_LEN_REG + MIPIC_REG_OFFSET;
1401 pkg_sender->mipi_cmd_addr_reg =
1402 MIPIA_CMD_ADD_REG + MIPIC_REG_OFFSET;
1403 pkg_sender->mipi_cmd_len_reg =
1404 MIPIA_CMD_LEN_REG + MIPIC_REG_OFFSET;
1405 }
1406
1407 /* Init pkg list */
1408 INIT_LIST_HEAD(&pkg_sender->pkg_list);
1409 INIT_LIST_HEAD(&pkg_sender->free_list);
1410
1411 spin_lock_init(&pkg_sender->lock);
1412
1413 /* Allocate free pkg pool */
1414 for (i = 0; i < MDFLD_MAX_PKG_NUM; i++) {
1415 pkg = kzalloc(sizeof(struct mdfld_dsi_pkg), GFP_KERNEL);
1416 if (!pkg) {
1417 dev_err(dev->dev, "Out of memory allocating pkg pool");
1418 ret = -ENOMEM;
1419 goto pkg_alloc_err;
1420 }
1421 INIT_LIST_HEAD(&pkg->entry);
1422 list_add_tail(&pkg->entry, &pkg_sender->free_list);
1423 }
1424
1425 /*
1426 * For video mode, don't enable DPI timing output here,
1427 * will init the DPI timing output during mode setting.
1428 */
1429 if (dsi_config->type == MDFLD_DSI_ENCODER_DPI)
1430 mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
1431 else if (dsi_config->type == MDFLD_DSI_ENCODER_DBI)
1432 mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX
1433 | TE_TRIGGER_GPIO_PIN;
1434 else
1435 DRM_ERROR("Bad DSI encoder type\n");
1436
1437 if (pipe == 0) {
1438 mipi_val |= 0x2;
1439 REG_WRITE(MIPI, mipi_val);
1440 REG_READ(MIPI);
1441 } else if (pipe == 2) {
1442 REG_WRITE(MIPI_C, mipi_val);
1443 REG_READ(MIPI_C);
1444 }
1445
1446 /*do dsi controller init*/
1447 dsi_controller_init(dsi_config, pipe);
1448
1449 return 0;
1450
1451 pkg_alloc_err:
1452 list_for_each_entry_safe(pkg, tmp, &pkg_sender->free_list, entry) {
1453 list_del(&pkg->entry);
1454 kfree(pkg);
1455 }
1456
1457 /* Free mapped command buffer */
1458 mdfld_dbi_cb_destroy(pkg_sender);
1459 mapping_err:
1460 kfree(pkg_sender);
1461 dsi_connector->pkg_sender = NULL;
1462 return ret;
1463 }
1464
1465 void mdfld_dsi_pkg_sender_destroy(struct mdfld_dsi_pkg_sender *sender)
1466 {
1467 struct mdfld_dsi_pkg *pkg, *tmp;
1468
1469 if (!sender || IS_ERR(sender))
1470 return;
1471
1472 /* Free pkg pool */
1473 list_for_each_entry_safe(pkg, tmp, &sender->free_list, entry) {
1474 list_del(&pkg->entry);
1475 kfree(pkg);
1476 }
1477 /* Free pkg list */
1478 list_for_each_entry_safe(pkg, tmp, &sender->pkg_list, entry) {
1479 list_del(&pkg->entry);
1480 kfree(pkg);
1481 }
1482 mdfld_dbi_cb_destroy(sender); /* free mapped command buffer */
1483 kfree(sender);
1484 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree