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net: sh_eth: remove almost #ifdef of SH7763
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sh_eth.c
blob6734311e56e45ab28c182866a8f7a8a42922653f
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
32 #include <linux/io.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
37
38 #include "sh_eth.h"
39
40 #define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device *ndev)
50 {
51 struct sh_eth_private *mdp = netdev_priv(ndev);
52
53 if (mdp->duplex) /* Full */
54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
55 else /* Half */
56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
57 }
58
59 static void sh_eth_set_rate(struct net_device *ndev)
60 {
61 struct sh_eth_private *mdp = netdev_priv(ndev);
62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
66 break;
67 case 100:/* 100BASE */
68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
69 break;
70 default:
71 break;
72 }
73 }
74
75 /* SH7724 */
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
95 };
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_RESET_DEFAULT 1
98 static void sh_eth_set_duplex(struct net_device *ndev)
99 {
100 struct sh_eth_private *mdp = netdev_priv(ndev);
101
102 if (mdp->duplex) /* Full */
103 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
104 else /* Half */
105 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
106 }
107
108 static void sh_eth_set_rate(struct net_device *ndev)
109 {
110 struct sh_eth_private *mdp = netdev_priv(ndev);
111
112 switch (mdp->speed) {
113 case 10: /* 10BASE */
114 sh_eth_write(ndev, 0, RTRATE);
115 break;
116 case 100:/* 100BASE */
117 sh_eth_write(ndev, 1, RTRATE);
118 break;
119 default:
120 break;
121 }
122 }
123
124 /* SH7757 */
125 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
126 .set_duplex = sh_eth_set_duplex,
127 .set_rate = sh_eth_set_rate,
128
129 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
130 .rmcr_value = 0x00000001,
131
132 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
133 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
134 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
135 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
136
137 .apr = 1,
138 .mpr = 1,
139 .tpauser = 1,
140 .hw_swap = 1,
141 .no_ade = 1,
142 };
143
144 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
145 #define SH_ETH_HAS_TSU 1
146 static void sh_eth_chip_reset(struct net_device *ndev)
147 {
148 struct sh_eth_private *mdp = netdev_priv(ndev);
149
150 /* reset device */
151 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
152 mdelay(1);
153 }
154
155 static void sh_eth_reset(struct net_device *ndev)
156 {
157 int cnt = 100;
158
159 sh_eth_write(ndev, EDSR_ENALL, EDSR);
160 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
161 while (cnt > 0) {
162 if (!(sh_eth_read(ndev, EDMR) & 0x3))
163 break;
164 mdelay(1);
165 cnt--;
166 }
167 if (cnt == 0)
168 printk(KERN_ERR "Device reset fail\n");
169
170 /* Table Init */
171 sh_eth_write(ndev, 0x0, TDLAR);
172 sh_eth_write(ndev, 0x0, TDFAR);
173 sh_eth_write(ndev, 0x0, TDFXR);
174 sh_eth_write(ndev, 0x0, TDFFR);
175 sh_eth_write(ndev, 0x0, RDLAR);
176 sh_eth_write(ndev, 0x0, RDFAR);
177 sh_eth_write(ndev, 0x0, RDFXR);
178 sh_eth_write(ndev, 0x0, RDFFR);
179 }
180
181 static void sh_eth_set_duplex(struct net_device *ndev)
182 {
183 struct sh_eth_private *mdp = netdev_priv(ndev);
184
185 if (mdp->duplex) /* Full */
186 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
187 else /* Half */
188 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
189 }
190
191 static void sh_eth_set_rate(struct net_device *ndev)
192 {
193 struct sh_eth_private *mdp = netdev_priv(ndev);
194
195 switch (mdp->speed) {
196 case 10: /* 10BASE */
197 sh_eth_write(ndev, GECMR_10, GECMR);
198 break;
199 case 100:/* 100BASE */
200 sh_eth_write(ndev, GECMR_100, GECMR);
201 break;
202 case 1000: /* 1000BASE */
203 sh_eth_write(ndev, GECMR_1000, GECMR);
204 break;
205 default:
206 break;
207 }
208 }
209
210 /* sh7763 */
211 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
212 .chip_reset = sh_eth_chip_reset,
213 .set_duplex = sh_eth_set_duplex,
214 .set_rate = sh_eth_set_rate,
215
216 .ecsr_value = ECSR_ICD | ECSR_MPD,
217 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
218 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
219
220 .tx_check = EESR_TC1 | EESR_FTC,
221 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
222 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
223 EESR_ECI,
224 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
225 EESR_TFE,
226
227 .apr = 1,
228 .mpr = 1,
229 .tpauser = 1,
230 .bculr = 1,
231 .hw_swap = 1,
232 .no_trimd = 1,
233 .no_ade = 1,
234 .tsu = 1,
235 };
236
237 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
238 #define SH_ETH_RESET_DEFAULT 1
239 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
240 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
241
242 .apr = 1,
243 .mpr = 1,
244 .tpauser = 1,
245 .hw_swap = 1,
246 };
247 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
248 #define SH_ETH_RESET_DEFAULT 1
249 #define SH_ETH_HAS_TSU 1
250 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
251 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
252 .tsu = 1,
253 };
254 #endif
255
256 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
257 {
258 if (!cd->ecsr_value)
259 cd->ecsr_value = DEFAULT_ECSR_INIT;
260
261 if (!cd->ecsipr_value)
262 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
263
264 if (!cd->fcftr_value)
265 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
266 DEFAULT_FIFO_F_D_RFD;
267
268 if (!cd->fdr_value)
269 cd->fdr_value = DEFAULT_FDR_INIT;
270
271 if (!cd->rmcr_value)
272 cd->rmcr_value = DEFAULT_RMCR_VALUE;
273
274 if (!cd->tx_check)
275 cd->tx_check = DEFAULT_TX_CHECK;
276
277 if (!cd->eesr_err_check)
278 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
279
280 if (!cd->tx_error_check)
281 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
282 }
283
284 #if defined(SH_ETH_RESET_DEFAULT)
285 /* Chip Reset */
286 static void sh_eth_reset(struct net_device *ndev)
287 {
288 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
289 mdelay(3);
290 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
291 }
292 #endif
293
294 #if defined(CONFIG_CPU_SH4)
295 static void sh_eth_set_receive_align(struct sk_buff *skb)
296 {
297 int reserve;
298
299 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
300 if (reserve)
301 skb_reserve(skb, reserve);
302 }
303 #else
304 static void sh_eth_set_receive_align(struct sk_buff *skb)
305 {
306 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
307 }
308 #endif
309
310
311 /* CPU <-> EDMAC endian convert */
312 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
313 {
314 switch (mdp->edmac_endian) {
315 case EDMAC_LITTLE_ENDIAN:
316 return cpu_to_le32(x);
317 case EDMAC_BIG_ENDIAN:
318 return cpu_to_be32(x);
319 }
320 return x;
321 }
322
323 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
324 {
325 switch (mdp->edmac_endian) {
326 case EDMAC_LITTLE_ENDIAN:
327 return le32_to_cpu(x);
328 case EDMAC_BIG_ENDIAN:
329 return be32_to_cpu(x);
330 }
331 return x;
332 }
333
334 /*
335 * Program the hardware MAC address from dev->dev_addr.
336 */
337 static void update_mac_address(struct net_device *ndev)
338 {
339 sh_eth_write(ndev,
340 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
341 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
342 sh_eth_write(ndev,
343 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
344 }
345
346 /*
347 * Get MAC address from SuperH MAC address register
348 *
349 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
350 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
351 * When you want use this device, you must set MAC address in bootloader.
352 *
353 */
354 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
355 {
356 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
357 memcpy(ndev->dev_addr, mac, 6);
358 } else {
359 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
360 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
361 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
362 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
363 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
364 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
365 }
366 }
367
368 static int sh_eth_is_gether(struct sh_eth_private *mdp)
369 {
370 if (mdp->reg_offset == sh_eth_offset_gigabit)
371 return 1;
372 else
373 return 0;
374 }
375
376 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
377 {
378 if (sh_eth_is_gether(mdp))
379 return EDTRR_TRNS_GETHER;
380 else
381 return EDTRR_TRNS_ETHER;
382 }
383
384 struct bb_info {
385 struct mdiobb_ctrl ctrl;
386 u32 addr;
387 u32 mmd_msk;/* MMD */
388 u32 mdo_msk;
389 u32 mdi_msk;
390 u32 mdc_msk;
391 };
392
393 /* PHY bit set */
394 static void bb_set(u32 addr, u32 msk)
395 {
396 writel(readl(addr) | msk, addr);
397 }
398
399 /* PHY bit clear */
400 static void bb_clr(u32 addr, u32 msk)
401 {
402 writel((readl(addr) & ~msk), addr);
403 }
404
405 /* PHY bit read */
406 static int bb_read(u32 addr, u32 msk)
407 {
408 return (readl(addr) & msk) != 0;
409 }
410
411 /* Data I/O pin control */
412 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
413 {
414 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
415 if (bit)
416 bb_set(bitbang->addr, bitbang->mmd_msk);
417 else
418 bb_clr(bitbang->addr, bitbang->mmd_msk);
419 }
420
421 /* Set bit data*/
422 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
423 {
424 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
425
426 if (bit)
427 bb_set(bitbang->addr, bitbang->mdo_msk);
428 else
429 bb_clr(bitbang->addr, bitbang->mdo_msk);
430 }
431
432 /* Get bit data*/
433 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
434 {
435 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
436 return bb_read(bitbang->addr, bitbang->mdi_msk);
437 }
438
439 /* MDC pin control */
440 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
441 {
442 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
443
444 if (bit)
445 bb_set(bitbang->addr, bitbang->mdc_msk);
446 else
447 bb_clr(bitbang->addr, bitbang->mdc_msk);
448 }
449
450 /* mdio bus control struct */
451 static struct mdiobb_ops bb_ops = {
452 .owner = THIS_MODULE,
453 .set_mdc = sh_mdc_ctrl,
454 .set_mdio_dir = sh_mmd_ctrl,
455 .set_mdio_data = sh_set_mdio,
456 .get_mdio_data = sh_get_mdio,
457 };
458
459 /* free skb and descriptor buffer */
460 static void sh_eth_ring_free(struct net_device *ndev)
461 {
462 struct sh_eth_private *mdp = netdev_priv(ndev);
463 int i;
464
465 /* Free Rx skb ringbuffer */
466 if (mdp->rx_skbuff) {
467 for (i = 0; i < RX_RING_SIZE; i++) {
468 if (mdp->rx_skbuff[i])
469 dev_kfree_skb(mdp->rx_skbuff[i]);
470 }
471 }
472 kfree(mdp->rx_skbuff);
473
474 /* Free Tx skb ringbuffer */
475 if (mdp->tx_skbuff) {
476 for (i = 0; i < TX_RING_SIZE; i++) {
477 if (mdp->tx_skbuff[i])
478 dev_kfree_skb(mdp->tx_skbuff[i]);
479 }
480 }
481 kfree(mdp->tx_skbuff);
482 }
483
484 /* format skb and descriptor buffer */
485 static void sh_eth_ring_format(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488 int i;
489 struct sk_buff *skb;
490 struct sh_eth_rxdesc *rxdesc = NULL;
491 struct sh_eth_txdesc *txdesc = NULL;
492 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
493 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
494
495 mdp->cur_rx = mdp->cur_tx = 0;
496 mdp->dirty_rx = mdp->dirty_tx = 0;
497
498 memset(mdp->rx_ring, 0, rx_ringsize);
499
500 /* build Rx ring buffer */
501 for (i = 0; i < RX_RING_SIZE; i++) {
502 /* skb */
503 mdp->rx_skbuff[i] = NULL;
504 skb = dev_alloc_skb(mdp->rx_buf_sz);
505 mdp->rx_skbuff[i] = skb;
506 if (skb == NULL)
507 break;
508 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
509 DMA_FROM_DEVICE);
510 skb->dev = ndev; /* Mark as being used by this device. */
511 sh_eth_set_receive_align(skb);
512
513 /* RX descriptor */
514 rxdesc = &mdp->rx_ring[i];
515 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
516 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
517
518 /* The size of the buffer is 16 byte boundary. */
519 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
520 /* Rx descriptor address set */
521 if (i == 0) {
522 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
523 if (sh_eth_is_gether(mdp))
524 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
525 }
526 }
527
528 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
529
530 /* Mark the last entry as wrapping the ring. */
531 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
532
533 memset(mdp->tx_ring, 0, tx_ringsize);
534
535 /* build Tx ring buffer */
536 for (i = 0; i < TX_RING_SIZE; i++) {
537 mdp->tx_skbuff[i] = NULL;
538 txdesc = &mdp->tx_ring[i];
539 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
540 txdesc->buffer_length = 0;
541 if (i == 0) {
542 /* Tx descriptor address set */
543 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
544 if (sh_eth_is_gether(mdp))
545 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
546 }
547 }
548
549 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
550 }
551
552 /* Get skb and descriptor buffer */
553 static int sh_eth_ring_init(struct net_device *ndev)
554 {
555 struct sh_eth_private *mdp = netdev_priv(ndev);
556 int rx_ringsize, tx_ringsize, ret = 0;
557
558 /*
559 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
560 * card needs room to do 8 byte alignment, +2 so we can reserve
561 * the first 2 bytes, and +16 gets room for the status word from the
562 * card.
563 */
564 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
565 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
566 if (mdp->cd->rpadir)
567 mdp->rx_buf_sz += NET_IP_ALIGN;
568
569 /* Allocate RX and TX skb rings */
570 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
571 GFP_KERNEL);
572 if (!mdp->rx_skbuff) {
573 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
574 ret = -ENOMEM;
575 return ret;
576 }
577
578 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
579 GFP_KERNEL);
580 if (!mdp->tx_skbuff) {
581 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
582 ret = -ENOMEM;
583 goto skb_ring_free;
584 }
585
586 /* Allocate all Rx descriptors. */
587 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
588 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
589 GFP_KERNEL);
590
591 if (!mdp->rx_ring) {
592 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
593 rx_ringsize);
594 ret = -ENOMEM;
595 goto desc_ring_free;
596 }
597
598 mdp->dirty_rx = 0;
599
600 /* Allocate all Tx descriptors. */
601 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
602 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
603 GFP_KERNEL);
604 if (!mdp->tx_ring) {
605 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
606 tx_ringsize);
607 ret = -ENOMEM;
608 goto desc_ring_free;
609 }
610 return ret;
611
612 desc_ring_free:
613 /* free DMA buffer */
614 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
615
616 skb_ring_free:
617 /* Free Rx and Tx skb ring buffer */
618 sh_eth_ring_free(ndev);
619
620 return ret;
621 }
622
623 static int sh_eth_dev_init(struct net_device *ndev)
624 {
625 int ret = 0;
626 struct sh_eth_private *mdp = netdev_priv(ndev);
627 u_int32_t rx_int_var, tx_int_var;
628 u32 val;
629
630 /* Soft Reset */
631 sh_eth_reset(ndev);
632
633 /* Descriptor format */
634 sh_eth_ring_format(ndev);
635 if (mdp->cd->rpadir)
636 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
637
638 /* all sh_eth int mask */
639 sh_eth_write(ndev, 0, EESIPR);
640
641 #if defined(__LITTLE_ENDIAN__)
642 if (mdp->cd->hw_swap)
643 sh_eth_write(ndev, EDMR_EL, EDMR);
644 else
645 #endif
646 sh_eth_write(ndev, 0, EDMR);
647
648 /* FIFO size set */
649 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
650 sh_eth_write(ndev, 0, TFTR);
651
652 /* Frame recv control */
653 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
654
655 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
656 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
657 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
658
659 if (mdp->cd->bculr)
660 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
661
662 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
663
664 if (!mdp->cd->no_trimd)
665 sh_eth_write(ndev, 0, TRIMD);
666
667 /* Recv frame limit set register */
668 sh_eth_write(ndev, RFLR_VALUE, RFLR);
669
670 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
671 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
672
673 /* PAUSE Prohibition */
674 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
675 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
676
677 sh_eth_write(ndev, val, ECMR);
678
679 if (mdp->cd->set_rate)
680 mdp->cd->set_rate(ndev);
681
682 /* E-MAC Status Register clear */
683 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
684
685 /* E-MAC Interrupt Enable register */
686 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
687
688 /* Set MAC address */
689 update_mac_address(ndev);
690
691 /* mask reset */
692 if (mdp->cd->apr)
693 sh_eth_write(ndev, APR_AP, APR);
694 if (mdp->cd->mpr)
695 sh_eth_write(ndev, MPR_MP, MPR);
696 if (mdp->cd->tpauser)
697 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
698
699 /* Setting the Rx mode will start the Rx process. */
700 sh_eth_write(ndev, EDRRR_R, EDRRR);
701
702 netif_start_queue(ndev);
703
704 return ret;
705 }
706
707 /* free Tx skb function */
708 static int sh_eth_txfree(struct net_device *ndev)
709 {
710 struct sh_eth_private *mdp = netdev_priv(ndev);
711 struct sh_eth_txdesc *txdesc;
712 int freeNum = 0;
713 int entry = 0;
714
715 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
716 entry = mdp->dirty_tx % TX_RING_SIZE;
717 txdesc = &mdp->tx_ring[entry];
718 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
719 break;
720 /* Free the original skb. */
721 if (mdp->tx_skbuff[entry]) {
722 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
723 mdp->tx_skbuff[entry] = NULL;
724 freeNum++;
725 }
726 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
727 if (entry >= TX_RING_SIZE - 1)
728 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
729
730 mdp->stats.tx_packets++;
731 mdp->stats.tx_bytes += txdesc->buffer_length;
732 }
733 return freeNum;
734 }
735
736 /* Packet receive function */
737 static int sh_eth_rx(struct net_device *ndev)
738 {
739 struct sh_eth_private *mdp = netdev_priv(ndev);
740 struct sh_eth_rxdesc *rxdesc;
741
742 int entry = mdp->cur_rx % RX_RING_SIZE;
743 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
744 struct sk_buff *skb;
745 u16 pkt_len = 0;
746 u32 desc_status;
747
748 rxdesc = &mdp->rx_ring[entry];
749 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
750 desc_status = edmac_to_cpu(mdp, rxdesc->status);
751 pkt_len = rxdesc->frame_length;
752
753 if (--boguscnt < 0)
754 break;
755
756 if (!(desc_status & RDFEND))
757 mdp->stats.rx_length_errors++;
758
759 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
760 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
761 mdp->stats.rx_errors++;
762 if (desc_status & RD_RFS1)
763 mdp->stats.rx_crc_errors++;
764 if (desc_status & RD_RFS2)
765 mdp->stats.rx_frame_errors++;
766 if (desc_status & RD_RFS3)
767 mdp->stats.rx_length_errors++;
768 if (desc_status & RD_RFS4)
769 mdp->stats.rx_length_errors++;
770 if (desc_status & RD_RFS6)
771 mdp->stats.rx_missed_errors++;
772 if (desc_status & RD_RFS10)
773 mdp->stats.rx_over_errors++;
774 } else {
775 if (!mdp->cd->hw_swap)
776 sh_eth_soft_swap(
777 phys_to_virt(ALIGN(rxdesc->addr, 4)),
778 pkt_len + 2);
779 skb = mdp->rx_skbuff[entry];
780 mdp->rx_skbuff[entry] = NULL;
781 if (mdp->cd->rpadir)
782 skb_reserve(skb, NET_IP_ALIGN);
783 skb_put(skb, pkt_len);
784 skb->protocol = eth_type_trans(skb, ndev);
785 netif_rx(skb);
786 mdp->stats.rx_packets++;
787 mdp->stats.rx_bytes += pkt_len;
788 }
789 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
790 entry = (++mdp->cur_rx) % RX_RING_SIZE;
791 rxdesc = &mdp->rx_ring[entry];
792 }
793
794 /* Refill the Rx ring buffers. */
795 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
796 entry = mdp->dirty_rx % RX_RING_SIZE;
797 rxdesc = &mdp->rx_ring[entry];
798 /* The size of the buffer is 16 byte boundary. */
799 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
800
801 if (mdp->rx_skbuff[entry] == NULL) {
802 skb = dev_alloc_skb(mdp->rx_buf_sz);
803 mdp->rx_skbuff[entry] = skb;
804 if (skb == NULL)
805 break; /* Better luck next round. */
806 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
807 DMA_FROM_DEVICE);
808 skb->dev = ndev;
809 sh_eth_set_receive_align(skb);
810
811 skb_checksum_none_assert(skb);
812 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
813 }
814 if (entry >= RX_RING_SIZE - 1)
815 rxdesc->status |=
816 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
817 else
818 rxdesc->status |=
819 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
820 }
821
822 /* Restart Rx engine if stopped. */
823 /* If we don't need to check status, don't. -KDU */
824 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
825 sh_eth_write(ndev, EDRRR_R, EDRRR);
826
827 return 0;
828 }
829
830 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
831 {
832 /* disable tx and rx */
833 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
834 ~(ECMR_RE | ECMR_TE), ECMR);
835 }
836
837 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
838 {
839 /* enable tx and rx */
840 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
841 (ECMR_RE | ECMR_TE), ECMR);
842 }
843
844 /* error control function */
845 static void sh_eth_error(struct net_device *ndev, int intr_status)
846 {
847 struct sh_eth_private *mdp = netdev_priv(ndev);
848 u32 felic_stat;
849 u32 link_stat;
850 u32 mask;
851
852 if (intr_status & EESR_ECI) {
853 felic_stat = sh_eth_read(ndev, ECSR);
854 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
855 if (felic_stat & ECSR_ICD)
856 mdp->stats.tx_carrier_errors++;
857 if (felic_stat & ECSR_LCHNG) {
858 /* Link Changed */
859 if (mdp->cd->no_psr || mdp->no_ether_link) {
860 if (mdp->link == PHY_DOWN)
861 link_stat = 0;
862 else
863 link_stat = PHY_ST_LINK;
864 } else {
865 link_stat = (sh_eth_read(ndev, PSR));
866 if (mdp->ether_link_active_low)
867 link_stat = ~link_stat;
868 }
869 if (!(link_stat & PHY_ST_LINK))
870 sh_eth_rcv_snd_disable(ndev);
871 else {
872 /* Link Up */
873 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
874 ~DMAC_M_ECI, EESIPR);
875 /*clear int */
876 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
877 ECSR);
878 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
879 DMAC_M_ECI, EESIPR);
880 /* enable tx and rx */
881 sh_eth_rcv_snd_enable(ndev);
882 }
883 }
884 }
885
886 if (intr_status & EESR_TWB) {
887 /* Write buck end. unused write back interrupt */
888 if (intr_status & EESR_TABT) /* Transmit Abort int */
889 mdp->stats.tx_aborted_errors++;
890 if (netif_msg_tx_err(mdp))
891 dev_err(&ndev->dev, "Transmit Abort\n");
892 }
893
894 if (intr_status & EESR_RABT) {
895 /* Receive Abort int */
896 if (intr_status & EESR_RFRMER) {
897 /* Receive Frame Overflow int */
898 mdp->stats.rx_frame_errors++;
899 if (netif_msg_rx_err(mdp))
900 dev_err(&ndev->dev, "Receive Abort\n");
901 }
902 }
903
904 if (intr_status & EESR_TDE) {
905 /* Transmit Descriptor Empty int */
906 mdp->stats.tx_fifo_errors++;
907 if (netif_msg_tx_err(mdp))
908 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
909 }
910
911 if (intr_status & EESR_TFE) {
912 /* FIFO under flow */
913 mdp->stats.tx_fifo_errors++;
914 if (netif_msg_tx_err(mdp))
915 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
916 }
917
918 if (intr_status & EESR_RDE) {
919 /* Receive Descriptor Empty int */
920 mdp->stats.rx_over_errors++;
921
922 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
923 sh_eth_write(ndev, EDRRR_R, EDRRR);
924 if (netif_msg_rx_err(mdp))
925 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
926 }
927
928 if (intr_status & EESR_RFE) {
929 /* Receive FIFO Overflow int */
930 mdp->stats.rx_fifo_errors++;
931 if (netif_msg_rx_err(mdp))
932 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
933 }
934
935 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
936 /* Address Error */
937 mdp->stats.tx_fifo_errors++;
938 if (netif_msg_tx_err(mdp))
939 dev_err(&ndev->dev, "Address Error\n");
940 }
941
942 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
943 if (mdp->cd->no_ade)
944 mask &= ~EESR_ADE;
945 if (intr_status & mask) {
946 /* Tx error */
947 u32 edtrr = sh_eth_read(ndev, EDTRR);
948 /* dmesg */
949 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
950 intr_status, mdp->cur_tx);
951 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
952 mdp->dirty_tx, (u32) ndev->state, edtrr);
953 /* dirty buffer free */
954 sh_eth_txfree(ndev);
955
956 /* SH7712 BUG */
957 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
958 /* tx dma start */
959 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
960 }
961 /* wakeup */
962 netif_wake_queue(ndev);
963 }
964 }
965
966 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
967 {
968 struct net_device *ndev = netdev;
969 struct sh_eth_private *mdp = netdev_priv(ndev);
970 struct sh_eth_cpu_data *cd = mdp->cd;
971 irqreturn_t ret = IRQ_NONE;
972 u32 intr_status = 0;
973
974 spin_lock(&mdp->lock);
975
976 /* Get interrpt stat */
977 intr_status = sh_eth_read(ndev, EESR);
978 /* Clear interrupt */
979 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
980 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
981 cd->tx_check | cd->eesr_err_check)) {
982 sh_eth_write(ndev, intr_status, EESR);
983 ret = IRQ_HANDLED;
984 } else
985 goto other_irq;
986
987 if (intr_status & (EESR_FRC | /* Frame recv*/
988 EESR_RMAF | /* Multi cast address recv*/
989 EESR_RRF | /* Bit frame recv */
990 EESR_RTLF | /* Long frame recv*/
991 EESR_RTSF | /* short frame recv */
992 EESR_PRE | /* PHY-LSI recv error */
993 EESR_CERF)){ /* recv frame CRC error */
994 sh_eth_rx(ndev);
995 }
996
997 /* Tx Check */
998 if (intr_status & cd->tx_check) {
999 sh_eth_txfree(ndev);
1000 netif_wake_queue(ndev);
1001 }
1002
1003 if (intr_status & cd->eesr_err_check)
1004 sh_eth_error(ndev, intr_status);
1005
1006 other_irq:
1007 spin_unlock(&mdp->lock);
1008
1009 return ret;
1010 }
1011
1012 static void sh_eth_timer(unsigned long data)
1013 {
1014 struct net_device *ndev = (struct net_device *)data;
1015 struct sh_eth_private *mdp = netdev_priv(ndev);
1016
1017 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1018 }
1019
1020 /* PHY state control function */
1021 static void sh_eth_adjust_link(struct net_device *ndev)
1022 {
1023 struct sh_eth_private *mdp = netdev_priv(ndev);
1024 struct phy_device *phydev = mdp->phydev;
1025 int new_state = 0;
1026
1027 if (phydev->link != PHY_DOWN) {
1028 if (phydev->duplex != mdp->duplex) {
1029 new_state = 1;
1030 mdp->duplex = phydev->duplex;
1031 if (mdp->cd->set_duplex)
1032 mdp->cd->set_duplex(ndev);
1033 }
1034
1035 if (phydev->speed != mdp->speed) {
1036 new_state = 1;
1037 mdp->speed = phydev->speed;
1038 if (mdp->cd->set_rate)
1039 mdp->cd->set_rate(ndev);
1040 }
1041 if (mdp->link == PHY_DOWN) {
1042 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1043 | ECMR_DM, ECMR);
1044 new_state = 1;
1045 mdp->link = phydev->link;
1046 }
1047 } else if (mdp->link) {
1048 new_state = 1;
1049 mdp->link = PHY_DOWN;
1050 mdp->speed = 0;
1051 mdp->duplex = -1;
1052 }
1053
1054 if (new_state && netif_msg_link(mdp))
1055 phy_print_status(phydev);
1056 }
1057
1058 /* PHY init function */
1059 static int sh_eth_phy_init(struct net_device *ndev)
1060 {
1061 struct sh_eth_private *mdp = netdev_priv(ndev);
1062 char phy_id[MII_BUS_ID_SIZE + 3];
1063 struct phy_device *phydev = NULL;
1064
1065 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1066 mdp->mii_bus->id , mdp->phy_id);
1067
1068 mdp->link = PHY_DOWN;
1069 mdp->speed = 0;
1070 mdp->duplex = -1;
1071
1072 /* Try connect to PHY */
1073 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1074 0, PHY_INTERFACE_MODE_MII);
1075 if (IS_ERR(phydev)) {
1076 dev_err(&ndev->dev, "phy_connect failed\n");
1077 return PTR_ERR(phydev);
1078 }
1079
1080 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1081 phydev->addr, phydev->drv->name);
1082
1083 mdp->phydev = phydev;
1084
1085 return 0;
1086 }
1087
1088 /* PHY control start function */
1089 static int sh_eth_phy_start(struct net_device *ndev)
1090 {
1091 struct sh_eth_private *mdp = netdev_priv(ndev);
1092 int ret;
1093
1094 ret = sh_eth_phy_init(ndev);
1095 if (ret)
1096 return ret;
1097
1098 /* reset phy - this also wakes it from PDOWN */
1099 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1100 phy_start(mdp->phydev);
1101
1102 return 0;
1103 }
1104
1105 static int sh_eth_get_settings(struct net_device *ndev,
1106 struct ethtool_cmd *ecmd)
1107 {
1108 struct sh_eth_private *mdp = netdev_priv(ndev);
1109 unsigned long flags;
1110 int ret;
1111
1112 spin_lock_irqsave(&mdp->lock, flags);
1113 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1114 spin_unlock_irqrestore(&mdp->lock, flags);
1115
1116 return ret;
1117 }
1118
1119 static int sh_eth_set_settings(struct net_device *ndev,
1120 struct ethtool_cmd *ecmd)
1121 {
1122 struct sh_eth_private *mdp = netdev_priv(ndev);
1123 unsigned long flags;
1124 int ret;
1125
1126 spin_lock_irqsave(&mdp->lock, flags);
1127
1128 /* disable tx and rx */
1129 sh_eth_rcv_snd_disable(ndev);
1130
1131 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1132 if (ret)
1133 goto error_exit;
1134
1135 if (ecmd->duplex == DUPLEX_FULL)
1136 mdp->duplex = 1;
1137 else
1138 mdp->duplex = 0;
1139
1140 if (mdp->cd->set_duplex)
1141 mdp->cd->set_duplex(ndev);
1142
1143 error_exit:
1144 mdelay(1);
1145
1146 /* enable tx and rx */
1147 sh_eth_rcv_snd_enable(ndev);
1148
1149 spin_unlock_irqrestore(&mdp->lock, flags);
1150
1151 return ret;
1152 }
1153
1154 static int sh_eth_nway_reset(struct net_device *ndev)
1155 {
1156 struct sh_eth_private *mdp = netdev_priv(ndev);
1157 unsigned long flags;
1158 int ret;
1159
1160 spin_lock_irqsave(&mdp->lock, flags);
1161 ret = phy_start_aneg(mdp->phydev);
1162 spin_unlock_irqrestore(&mdp->lock, flags);
1163
1164 return ret;
1165 }
1166
1167 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1168 {
1169 struct sh_eth_private *mdp = netdev_priv(ndev);
1170 return mdp->msg_enable;
1171 }
1172
1173 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1174 {
1175 struct sh_eth_private *mdp = netdev_priv(ndev);
1176 mdp->msg_enable = value;
1177 }
1178
1179 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1180 "rx_current", "tx_current",
1181 "rx_dirty", "tx_dirty",
1182 };
1183 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1184
1185 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1186 {
1187 switch (sset) {
1188 case ETH_SS_STATS:
1189 return SH_ETH_STATS_LEN;
1190 default:
1191 return -EOPNOTSUPP;
1192 }
1193 }
1194
1195 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1196 struct ethtool_stats *stats, u64 *data)
1197 {
1198 struct sh_eth_private *mdp = netdev_priv(ndev);
1199 int i = 0;
1200
1201 /* device-specific stats */
1202 data[i++] = mdp->cur_rx;
1203 data[i++] = mdp->cur_tx;
1204 data[i++] = mdp->dirty_rx;
1205 data[i++] = mdp->dirty_tx;
1206 }
1207
1208 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1209 {
1210 switch (stringset) {
1211 case ETH_SS_STATS:
1212 memcpy(data, *sh_eth_gstrings_stats,
1213 sizeof(sh_eth_gstrings_stats));
1214 break;
1215 }
1216 }
1217
1218 static struct ethtool_ops sh_eth_ethtool_ops = {
1219 .get_settings = sh_eth_get_settings,
1220 .set_settings = sh_eth_set_settings,
1221 .nway_reset = sh_eth_nway_reset,
1222 .get_msglevel = sh_eth_get_msglevel,
1223 .set_msglevel = sh_eth_set_msglevel,
1224 .get_link = ethtool_op_get_link,
1225 .get_strings = sh_eth_get_strings,
1226 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1227 .get_sset_count = sh_eth_get_sset_count,
1228 };
1229
1230 /* network device open function */
1231 static int sh_eth_open(struct net_device *ndev)
1232 {
1233 int ret = 0;
1234 struct sh_eth_private *mdp = netdev_priv(ndev);
1235
1236 pm_runtime_get_sync(&mdp->pdev->dev);
1237
1238 ret = request_irq(ndev->irq, sh_eth_interrupt,
1239 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1240 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1241 defined(CONFIG_CPU_SUBTYPE_SH7757)
1242 IRQF_SHARED,
1243 #else
1244 0,
1245 #endif
1246 ndev->name, ndev);
1247 if (ret) {
1248 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1249 return ret;
1250 }
1251
1252 /* Descriptor set */
1253 ret = sh_eth_ring_init(ndev);
1254 if (ret)
1255 goto out_free_irq;
1256
1257 /* device init */
1258 ret = sh_eth_dev_init(ndev);
1259 if (ret)
1260 goto out_free_irq;
1261
1262 /* PHY control start*/
1263 ret = sh_eth_phy_start(ndev);
1264 if (ret)
1265 goto out_free_irq;
1266
1267 /* Set the timer to check for link beat. */
1268 init_timer(&mdp->timer);
1269 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1270 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1271
1272 return ret;
1273
1274 out_free_irq:
1275 free_irq(ndev->irq, ndev);
1276 pm_runtime_put_sync(&mdp->pdev->dev);
1277 return ret;
1278 }
1279
1280 /* Timeout function */
1281 static void sh_eth_tx_timeout(struct net_device *ndev)
1282 {
1283 struct sh_eth_private *mdp = netdev_priv(ndev);
1284 struct sh_eth_rxdesc *rxdesc;
1285 int i;
1286
1287 netif_stop_queue(ndev);
1288
1289 if (netif_msg_timer(mdp))
1290 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1291 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1292
1293 /* tx_errors count up */
1294 mdp->stats.tx_errors++;
1295
1296 /* timer off */
1297 del_timer_sync(&mdp->timer);
1298
1299 /* Free all the skbuffs in the Rx queue. */
1300 for (i = 0; i < RX_RING_SIZE; i++) {
1301 rxdesc = &mdp->rx_ring[i];
1302 rxdesc->status = 0;
1303 rxdesc->addr = 0xBADF00D0;
1304 if (mdp->rx_skbuff[i])
1305 dev_kfree_skb(mdp->rx_skbuff[i]);
1306 mdp->rx_skbuff[i] = NULL;
1307 }
1308 for (i = 0; i < TX_RING_SIZE; i++) {
1309 if (mdp->tx_skbuff[i])
1310 dev_kfree_skb(mdp->tx_skbuff[i]);
1311 mdp->tx_skbuff[i] = NULL;
1312 }
1313
1314 /* device init */
1315 sh_eth_dev_init(ndev);
1316
1317 /* timer on */
1318 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1319 add_timer(&mdp->timer);
1320 }
1321
1322 /* Packet transmit function */
1323 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1324 {
1325 struct sh_eth_private *mdp = netdev_priv(ndev);
1326 struct sh_eth_txdesc *txdesc;
1327 u32 entry;
1328 unsigned long flags;
1329
1330 spin_lock_irqsave(&mdp->lock, flags);
1331 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1332 if (!sh_eth_txfree(ndev)) {
1333 if (netif_msg_tx_queued(mdp))
1334 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1335 netif_stop_queue(ndev);
1336 spin_unlock_irqrestore(&mdp->lock, flags);
1337 return NETDEV_TX_BUSY;
1338 }
1339 }
1340 spin_unlock_irqrestore(&mdp->lock, flags);
1341
1342 entry = mdp->cur_tx % TX_RING_SIZE;
1343 mdp->tx_skbuff[entry] = skb;
1344 txdesc = &mdp->tx_ring[entry];
1345 txdesc->addr = virt_to_phys(skb->data);
1346 /* soft swap. */
1347 if (!mdp->cd->hw_swap)
1348 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1349 skb->len + 2);
1350 /* write back */
1351 __flush_purge_region(skb->data, skb->len);
1352 if (skb->len < ETHERSMALL)
1353 txdesc->buffer_length = ETHERSMALL;
1354 else
1355 txdesc->buffer_length = skb->len;
1356
1357 if (entry >= TX_RING_SIZE - 1)
1358 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1359 else
1360 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1361
1362 mdp->cur_tx++;
1363
1364 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1365 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1366
1367 return NETDEV_TX_OK;
1368 }
1369
1370 /* device close function */
1371 static int sh_eth_close(struct net_device *ndev)
1372 {
1373 struct sh_eth_private *mdp = netdev_priv(ndev);
1374 int ringsize;
1375
1376 netif_stop_queue(ndev);
1377
1378 /* Disable interrupts by clearing the interrupt mask. */
1379 sh_eth_write(ndev, 0x0000, EESIPR);
1380
1381 /* Stop the chip's Tx and Rx processes. */
1382 sh_eth_write(ndev, 0, EDTRR);
1383 sh_eth_write(ndev, 0, EDRRR);
1384
1385 /* PHY Disconnect */
1386 if (mdp->phydev) {
1387 phy_stop(mdp->phydev);
1388 phy_disconnect(mdp->phydev);
1389 }
1390
1391 free_irq(ndev->irq, ndev);
1392
1393 del_timer_sync(&mdp->timer);
1394
1395 /* Free all the skbuffs in the Rx queue. */
1396 sh_eth_ring_free(ndev);
1397
1398 /* free DMA buffer */
1399 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1400 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1401
1402 /* free DMA buffer */
1403 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1404 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1405
1406 pm_runtime_put_sync(&mdp->pdev->dev);
1407
1408 return 0;
1409 }
1410
1411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1412 {
1413 struct sh_eth_private *mdp = netdev_priv(ndev);
1414
1415 pm_runtime_get_sync(&mdp->pdev->dev);
1416
1417 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1418 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1419 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1420 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1421 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1422 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1423 if (sh_eth_is_gether(mdp)) {
1424 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1425 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1426 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1427 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1428 } else {
1429 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1430 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1431 }
1432 pm_runtime_put_sync(&mdp->pdev->dev);
1433
1434 return &mdp->stats;
1435 }
1436
1437 /* ioctl to device funciotn*/
1438 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1439 int cmd)
1440 {
1441 struct sh_eth_private *mdp = netdev_priv(ndev);
1442 struct phy_device *phydev = mdp->phydev;
1443
1444 if (!netif_running(ndev))
1445 return -EINVAL;
1446
1447 if (!phydev)
1448 return -ENODEV;
1449
1450 return phy_mii_ioctl(phydev, rq, cmd);
1451 }
1452
1453 #if defined(SH_ETH_HAS_TSU)
1454 /* Multicast reception directions set */
1455 static void sh_eth_set_multicast_list(struct net_device *ndev)
1456 {
1457 if (ndev->flags & IFF_PROMISC) {
1458 /* Set promiscuous. */
1459 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1460 ECMR_PRM, ECMR);
1461 } else {
1462 /* Normal, unicast/broadcast-only mode. */
1463 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1464 ECMR_MCT, ECMR);
1465 }
1466 }
1467 #endif /* SH_ETH_HAS_TSU */
1468
1469 /* SuperH's TSU register init function */
1470 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1471 {
1472 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1473 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1474 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1475 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1476 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1477 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1478 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1479 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1480 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1481 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1482 if (sh_eth_is_gether(mdp)) {
1483 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1484 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1485 } else {
1486 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1487 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1488 }
1489 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1490 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1491 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1492 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1493 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1494 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1495 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1496 }
1497
1498 /* MDIO bus release function */
1499 static int sh_mdio_release(struct net_device *ndev)
1500 {
1501 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1502
1503 /* unregister mdio bus */
1504 mdiobus_unregister(bus);
1505
1506 /* remove mdio bus info from net_device */
1507 dev_set_drvdata(&ndev->dev, NULL);
1508
1509 /* free interrupts memory */
1510 kfree(bus->irq);
1511
1512 /* free bitbang info */
1513 free_mdio_bitbang(bus);
1514
1515 return 0;
1516 }
1517
1518 /* MDIO bus init function */
1519 static int sh_mdio_init(struct net_device *ndev, int id)
1520 {
1521 int ret, i;
1522 struct bb_info *bitbang;
1523 struct sh_eth_private *mdp = netdev_priv(ndev);
1524
1525 /* create bit control struct for PHY */
1526 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1527 if (!bitbang) {
1528 ret = -ENOMEM;
1529 goto out;
1530 }
1531
1532 /* bitbang init */
1533 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1534 bitbang->mdi_msk = 0x08;
1535 bitbang->mdo_msk = 0x04;
1536 bitbang->mmd_msk = 0x02;/* MMD */
1537 bitbang->mdc_msk = 0x01;
1538 bitbang->ctrl.ops = &bb_ops;
1539
1540 /* MII controller setting */
1541 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1542 if (!mdp->mii_bus) {
1543 ret = -ENOMEM;
1544 goto out_free_bitbang;
1545 }
1546
1547 /* Hook up MII support for ethtool */
1548 mdp->mii_bus->name = "sh_mii";
1549 mdp->mii_bus->parent = &ndev->dev;
1550 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1551
1552 /* PHY IRQ */
1553 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1554 if (!mdp->mii_bus->irq) {
1555 ret = -ENOMEM;
1556 goto out_free_bus;
1557 }
1558
1559 for (i = 0; i < PHY_MAX_ADDR; i++)
1560 mdp->mii_bus->irq[i] = PHY_POLL;
1561
1562 /* regist mdio bus */
1563 ret = mdiobus_register(mdp->mii_bus);
1564 if (ret)
1565 goto out_free_irq;
1566
1567 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1568
1569 return 0;
1570
1571 out_free_irq:
1572 kfree(mdp->mii_bus->irq);
1573
1574 out_free_bus:
1575 free_mdio_bitbang(mdp->mii_bus);
1576
1577 out_free_bitbang:
1578 kfree(bitbang);
1579
1580 out:
1581 return ret;
1582 }
1583
1584 static const u16 *sh_eth_get_register_offset(int register_type)
1585 {
1586 const u16 *reg_offset = NULL;
1587
1588 switch (register_type) {
1589 case SH_ETH_REG_GIGABIT:
1590 reg_offset = sh_eth_offset_gigabit;
1591 break;
1592 case SH_ETH_REG_FAST_SH4:
1593 reg_offset = sh_eth_offset_fast_sh4;
1594 break;
1595 case SH_ETH_REG_FAST_SH3_SH2:
1596 reg_offset = sh_eth_offset_fast_sh3_sh2;
1597 break;
1598 default:
1599 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1600 break;
1601 }
1602
1603 return reg_offset;
1604 }
1605
1606 static const struct net_device_ops sh_eth_netdev_ops = {
1607 .ndo_open = sh_eth_open,
1608 .ndo_stop = sh_eth_close,
1609 .ndo_start_xmit = sh_eth_start_xmit,
1610 .ndo_get_stats = sh_eth_get_stats,
1611 #if defined(SH_ETH_HAS_TSU)
1612 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1613 #endif
1614 .ndo_tx_timeout = sh_eth_tx_timeout,
1615 .ndo_do_ioctl = sh_eth_do_ioctl,
1616 .ndo_validate_addr = eth_validate_addr,
1617 .ndo_set_mac_address = eth_mac_addr,
1618 .ndo_change_mtu = eth_change_mtu,
1619 };
1620
1621 static int sh_eth_drv_probe(struct platform_device *pdev)
1622 {
1623 int ret, devno = 0;
1624 struct resource *res;
1625 struct net_device *ndev = NULL;
1626 struct sh_eth_private *mdp;
1627 struct sh_eth_plat_data *pd;
1628
1629 /* get base addr */
1630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1631 if (unlikely(res == NULL)) {
1632 dev_err(&pdev->dev, "invalid resource\n");
1633 ret = -EINVAL;
1634 goto out;
1635 }
1636
1637 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1638 if (!ndev) {
1639 dev_err(&pdev->dev, "Could not allocate device.\n");
1640 ret = -ENOMEM;
1641 goto out;
1642 }
1643
1644 /* The sh Ether-specific entries in the device structure. */
1645 ndev->base_addr = res->start;
1646 devno = pdev->id;
1647 if (devno < 0)
1648 devno = 0;
1649
1650 ndev->dma = -1;
1651 ret = platform_get_irq(pdev, 0);
1652 if (ret < 0) {
1653 ret = -ENODEV;
1654 goto out_release;
1655 }
1656 ndev->irq = ret;
1657
1658 SET_NETDEV_DEV(ndev, &pdev->dev);
1659
1660 /* Fill in the fields of the device structure with ethernet values. */
1661 ether_setup(ndev);
1662
1663 mdp = netdev_priv(ndev);
1664 spin_lock_init(&mdp->lock);
1665 mdp->pdev = pdev;
1666 pm_runtime_enable(&pdev->dev);
1667 pm_runtime_resume(&pdev->dev);
1668
1669 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1670 /* get PHY ID */
1671 mdp->phy_id = pd->phy;
1672 /* EDMAC endian */
1673 mdp->edmac_endian = pd->edmac_endian;
1674 mdp->no_ether_link = pd->no_ether_link;
1675 mdp->ether_link_active_low = pd->ether_link_active_low;
1676 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1677
1678 /* set cpu data */
1679 mdp->cd = &sh_eth_my_cpu_data;
1680 sh_eth_set_default_cpu_data(mdp->cd);
1681
1682 /* set function */
1683 ndev->netdev_ops = &sh_eth_netdev_ops;
1684 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1685 ndev->watchdog_timeo = TX_TIMEOUT;
1686
1687 /* debug message level */
1688 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1689 mdp->post_rx = POST_RX >> (devno << 1);
1690 mdp->post_fw = POST_FW >> (devno << 1);
1691
1692 /* read and set MAC address */
1693 read_mac_address(ndev, pd->mac_addr);
1694
1695 /* First device only init */
1696 if (!devno) {
1697 if (mdp->cd->tsu) {
1698 struct resource *rtsu;
1699 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1700 if (!rtsu) {
1701 dev_err(&pdev->dev, "Not found TSU resource\n");
1702 goto out_release;
1703 }
1704 mdp->tsu_addr = ioremap(rtsu->start,
1705 resource_size(rtsu));
1706 }
1707 if (mdp->cd->chip_reset)
1708 mdp->cd->chip_reset(ndev);
1709
1710 if (mdp->cd->tsu) {
1711 /* TSU init (Init only)*/
1712 sh_eth_tsu_init(mdp);
1713 }
1714 }
1715
1716 /* network device register */
1717 ret = register_netdev(ndev);
1718 if (ret)
1719 goto out_release;
1720
1721 /* mdio bus init */
1722 ret = sh_mdio_init(ndev, pdev->id);
1723 if (ret)
1724 goto out_unregister;
1725
1726 /* print device infomation */
1727 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1728 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1729
1730 platform_set_drvdata(pdev, ndev);
1731
1732 return ret;
1733
1734 out_unregister:
1735 unregister_netdev(ndev);
1736
1737 out_release:
1738 /* net_dev free */
1739 if (mdp->tsu_addr)
1740 iounmap(mdp->tsu_addr);
1741 if (ndev)
1742 free_netdev(ndev);
1743
1744 out:
1745 return ret;
1746 }
1747
1748 static int sh_eth_drv_remove(struct platform_device *pdev)
1749 {
1750 struct net_device *ndev = platform_get_drvdata(pdev);
1751 struct sh_eth_private *mdp = netdev_priv(ndev);
1752
1753 iounmap(mdp->tsu_addr);
1754 sh_mdio_release(ndev);
1755 unregister_netdev(ndev);
1756 pm_runtime_disable(&pdev->dev);
1757 free_netdev(ndev);
1758 platform_set_drvdata(pdev, NULL);
1759
1760 return 0;
1761 }
1762
1763 static int sh_eth_runtime_nop(struct device *dev)
1764 {
1765 /*
1766 * Runtime PM callback shared between ->runtime_suspend()
1767 * and ->runtime_resume(). Simply returns success.
1768 *
1769 * This driver re-initializes all registers after
1770 * pm_runtime_get_sync() anyway so there is no need
1771 * to save and restore registers here.
1772 */
1773 return 0;
1774 }
1775
1776 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1777 .runtime_suspend = sh_eth_runtime_nop,
1778 .runtime_resume = sh_eth_runtime_nop,
1779 };
1780
1781 static struct platform_driver sh_eth_driver = {
1782 .probe = sh_eth_drv_probe,
1783 .remove = sh_eth_drv_remove,
1784 .driver = {
1785 .name = CARDNAME,
1786 .pm = &sh_eth_dev_pm_ops,
1787 },
1788 };
1789
1790 static int __init sh_eth_init(void)
1791 {
1792 return platform_driver_register(&sh_eth_driver);
1793 }
1794
1795 static void __exit sh_eth_cleanup(void)
1796 {
1797 platform_driver_unregister(&sh_eth_driver);
1798 }
1799
1800 module_init(sh_eth_init);
1801 module_exit(sh_eth_cleanup);
1802
1803 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1804 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1805 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree