drivers/staging/gma500/mdfld_pyr_cmd.c

   1 /*
   2  * Copyright (c)  2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicensen
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  * Thomas Eaton <thomas.g.eaton@intel.com>
  25  * Scott Rowe <scott.m.rowe@intel.com>
  26 */
  27
  28 #include "mdfld_dsi_dbi.h"
  29 #include "mdfld_dsi_dpi.h"
  30 #include "mdfld_dsi_output.h"
  31 #include "mdfld_output.h"
  32
  33 #include "mdfld_dsi_pkg_sender.h"
  34
  35 #include "displays/pyr_cmd.h"
  36
  37 static struct drm_display_mode *pyr_cmd_get_config_mode(struct drm_device *dev)
  38 {
  39         struct drm_display_mode *mode;
  40
  41         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  42         if (!mode) {
  43                 dev_err(dev->dev, "Out of memory\n");
  44                 return NULL;
  45         }
  46
  47         dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
  48         dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
  49         dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
  50         dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
  51         dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
  52         dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
  53         dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
  54         dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
  55         dev_dbg(dev->dev, "clock is %d\n", mode->clock);
  56
  57         mode->hdisplay = 480;
  58         mode->vdisplay = 864;
  59         mode->hsync_start = 487;
  60         mode->hsync_end = 490;
  61         mode->htotal = 499;
  62         mode->vsync_start = 874;
  63         mode->vsync_end = 878;
  64         mode->vtotal = 886;
  65         mode->clock = 25777;
  66
  67         drm_mode_set_name(mode);
  68         drm_mode_set_crtcinfo(mode, 0);
  69
  70         mode->type |= DRM_MODE_TYPE_PREFERRED;
  71
  72         return mode;
  73 }
  74
  75 static bool pyr_dsi_dbi_mode_fixup(struct drm_encoder *encoder,
  76                                 struct drm_display_mode *mode,
  77                                 struct drm_display_mode *adjusted_mode)
  78 {
  79         struct drm_device *dev = encoder->dev;
  80         struct drm_display_mode *fixed_mode = pyr_cmd_get_config_mode(dev);
  81
  82         if (fixed_mode) {
  83                 adjusted_mode->hdisplay = fixed_mode->hdisplay;
  84                 adjusted_mode->hsync_start = fixed_mode->hsync_start;
  85                 adjusted_mode->hsync_end = fixed_mode->hsync_end;
  86                 adjusted_mode->htotal = fixed_mode->htotal;
  87                 adjusted_mode->vdisplay = fixed_mode->vdisplay;
  88                 adjusted_mode->vsync_start = fixed_mode->vsync_start;
  89                 adjusted_mode->vsync_end = fixed_mode->vsync_end;
  90                 adjusted_mode->vtotal = fixed_mode->vtotal;
  91                 adjusted_mode->clock = fixed_mode->clock;
  92                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  93                 kfree(fixed_mode);
  94         }
  95         return true;
  96 }
  97
  98 static void pyr_dsi_dbi_set_power(struct drm_encoder *encoder, bool on)
  99 {
 100         int ret = 0;
 101         struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
 102         struct mdfld_dsi_dbi_output *dbi_output =
 103                                 MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
 104         struct drm_device *dev = encoder->dev;
 105         struct drm_psb_private *dev_priv = dev->dev_private;
 106         u32 reg_offset = 0;
 107         int pipe = (dbi_output->channel_num == 0) ? 0 : 2;
 108
 109         dev_dbg(dev->dev, "pipe %d : %s, panel on: %s\n", pipe,
 110                         on ? "On" : "Off",
 111                         dbi_output->dbi_panel_on ? "True" : "False");
 112
 113         if (pipe == 2) {
 114                 if (on)
 115                         dev_priv->dual_mipi = true;
 116                 else
 117                         dev_priv->dual_mipi = false;
 118
 119                 reg_offset = MIPIC_REG_OFFSET;
 120         } else {
 121                 if (!on)
 122                         dev_priv->dual_mipi = false;
 123         }
 124
 125         if (!gma_power_begin(dev, true)) {
 126                 dev_err(dev->dev, "hw begin failed\n");
 127                 return;
 128         }
 129
 130
 131         if (on) {
 132                 if (dbi_output->dbi_panel_on)
 133                         goto out_err;
 134
 135                 ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_ON);
 136                 if (ret) {
 137                         dev_err(dev->dev, "power on error\n");
 138                         goto out_err;
 139                 }
 140
 141                 dbi_output->dbi_panel_on = true;
 142
 143                 if (pipe == 2) {
 144                         dev_priv->dbi_panel_on2 = true;
 145                 } else {
 146                         dev_priv->dbi_panel_on = true;
 147                         mdfld_enable_te(dev, 0);
 148                 }
 149         } else {
 150                 if (!dbi_output->dbi_panel_on && !dbi_output->first_boot)
 151                         goto out_err;
 152
 153                 dbi_output->dbi_panel_on = false;
 154                 dbi_output->first_boot = false;
 155
 156                 if (pipe == 2) {
 157                         dev_priv->dbi_panel_on2 = false;
 158                         mdfld_disable_te(dev, 2);
 159                 } else {
 160                         dev_priv->dbi_panel_on = false;
 161                         mdfld_disable_te(dev, 0);
 162
 163                         if (dev_priv->dbi_panel_on2)
 164                                 mdfld_enable_te(dev, 2);
 165                 }
 166
 167                 ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_OFF);
 168                 if (ret) {
 169                         dev_err(dev->dev, "power on error\n");
 170                         goto out_err;
 171                 }
 172         }
 173
 174 out_err:
 175         gma_power_end(dev);
 176
 177         if (ret)
 178                 dev_err(dev->dev, "failed\n");
 179 }
 180
 181 static void pyr_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
 182                                                                 int pipe)
 183 {
 184         struct drm_device *dev = dsi_config->dev;
 185         u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
 186         int lane_count = dsi_config->lane_count;
 187         u32 val = 0;
 188
 189         dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe);
 190
 191         /* In-ready device */
 192         REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
 193
 194         /* Init dsi adapter before kicking off */
 195         REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
 196
 197         /* TODO: figure out how to setup these registers */
 198         REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c600F);
 199         REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset),
 200                                                                 0x000a0014);
 201         REG_WRITE((MIPIA_DBI_BW_CTRL_REG + reg_offset), 0x00000400);
 202         REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000);
 203
 204         /* Enable all interrupts */
 205         REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
 206         /* Max value: 20 clock cycles of txclkesc */
 207         REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f);
 208         /* Min 21 txclkesc, max: ffffh */
 209         REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff);
 210         /* Min: 7d0 max: 4e20 */
 211         REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0);
 212
 213         /* Set up func_prg */
 214         val |= lane_count;
 215         val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET);
 216         val |= DSI_DBI_COLOR_FORMAT_OPTION2;
 217         REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
 218
 219         REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff);
 220         REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff);
 221
 222         /* De-assert dbi_stall when half of DBI FIFO is empty */
 223         /* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */
 224
 225         REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
 226         REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000002);
 227         REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
 228         REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
 229 }
 230
 231 static void pyr_dsi_dbi_mode_set(struct drm_encoder *encoder,
 232                                 struct drm_display_mode *mode,
 233                                 struct drm_display_mode *adjusted_mode)
 234 {
 235         int ret = 0;
 236         struct drm_device *dev = encoder->dev;
 237         struct drm_psb_private *dev_priv = dev->dev_private;
 238         struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
 239         struct mdfld_dsi_dbi_output *dsi_output =
 240                                         MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
 241         struct mdfld_dsi_config *dsi_config =
 242                                 mdfld_dsi_encoder_get_config(dsi_encoder);
 243         struct mdfld_dsi_connector *dsi_connector = dsi_config->connector;
 244         int pipe = dsi_connector->pipe;
 245         u8 param = 0;
 246
 247         /* Regs */
 248         u32 mipi_reg = MIPI;
 249         u32 dspcntr_reg = DSPACNTR;
 250         u32 pipeconf_reg = PIPEACONF;
 251         u32 reg_offset = 0;
 252
 253         /* Values */
 254         u32 dspcntr_val = dev_priv->dspcntr;
 255         u32 pipeconf_val = dev_priv->pipeconf;
 256         u32 h_active_area = mode->hdisplay;
 257         u32 v_active_area = mode->vdisplay;
 258         u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX |
 259                                                         TE_TRIGGER_GPIO_PIN);
 260
 261         dev_dbg(dev->dev, "mipi_val =0x%x\n", mipi_val);
 262
 263         dev_dbg(dev->dev, "type %s\n", (pipe == 2) ? "MIPI2" : "MIPI");
 264         dev_dbg(dev->dev, "h %d v %d\n", mode->hdisplay, mode->vdisplay);
 265
 266         if (pipe == 2) {
 267                 mipi_reg = MIPI_C;
 268                 dspcntr_reg = DSPCCNTR;
 269                 pipeconf_reg = PIPECCONF;
 270
 271                 reg_offset = MIPIC_REG_OFFSET;
 272
 273                 dspcntr_val = dev_priv->dspcntr2;
 274                 pipeconf_val = dev_priv->pipeconf2;
 275         } else {
 276                 mipi_val |= 0x2; /* Two lanes for port A and C respectively */
 277         }
 278
 279         if (!gma_power_begin(dev, true)) {
 280                 dev_err(dev->dev, "hw begin failed\n");
 281                 return;
 282         }
 283
 284         /* Set up pipe related registers */
 285         REG_WRITE(mipi_reg, mipi_val);
 286         REG_READ(mipi_reg);
 287
 288         pyr_dsi_controller_dbi_init(dsi_config, pipe);
 289
 290         msleep(20);
 291
 292         REG_WRITE(dspcntr_reg, dspcntr_val);
 293         REG_READ(dspcntr_reg);
 294
 295         /* 20ms delay before sending exit_sleep_mode */
 296         msleep(20);
 297
 298         /* Send exit_sleep_mode DCS */
 299         ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, NULL,
 300                                                 0, CMD_DATA_SRC_SYSTEM_MEM);
 301         if (ret) {
 302                 dev_err(dev->dev, "sent exit_sleep_mode faild\n");
 303                 goto out_err;
 304         }
 305
 306         /*send set_tear_on DCS*/
 307         ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on,
 308                                         &param, 1, CMD_DATA_SRC_SYSTEM_MEM);
 309         if (ret) {
 310                 dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__);
 311                 goto out_err;
 312         }
 313
 314         /* Do some init stuff */
 315         mdfld_dsi_brightness_init(dsi_config, pipe);
 316         mdfld_dsi_gen_fifo_ready(dev, (MIPIA_GEN_FIFO_STAT_REG + reg_offset),
 317                                 HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
 318
 319         REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR);
 320         REG_READ(pipeconf_reg);
 321
 322         /* TODO: this looks ugly, try to move it to CRTC mode setting */
 323         if (pipe == 2)
 324                 dev_priv->pipeconf2 |= PIPEACONF_DSR;
 325         else
 326                 dev_priv->pipeconf |= PIPEACONF_DSR;
 327
 328         dev_dbg(dev->dev, "pipeconf %x\n",  REG_READ(pipeconf_reg));
 329
 330         ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0,
 331                                 h_active_area - 1, v_active_area - 1);
 332         if (ret) {
 333                 dev_err(dev->dev, "update area failed\n");
 334                 goto out_err;
 335         }
 336
 337 out_err:
 338         gma_power_end(dev);
 339
 340         if (ret)
 341                 dev_err(dev->dev, "mode set failed\n");
 342         else
 343                 dev_dbg(dev->dev, "mode set done successfully\n");
 344 }
 345
 346 static void pyr_dsi_dbi_prepare(struct drm_encoder *encoder)
 347 {
 348         struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
 349         struct mdfld_dsi_dbi_output *dbi_output =
 350                                         MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
 351
 352         dbi_output->mode_flags |= MODE_SETTING_IN_ENCODER;
 353         dbi_output->mode_flags &= ~MODE_SETTING_ENCODER_DONE;
 354
 355         pyr_dsi_dbi_set_power(encoder, false);
 356 }
 357
 358 static void pyr_dsi_dbi_commit(struct drm_encoder *encoder)
 359 {
 360         struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
 361         struct mdfld_dsi_dbi_output *dbi_output =
 362                                         MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
 363         struct drm_device *dev = dbi_output->dev;
 364         struct drm_psb_private *dev_priv = dev->dev_private;
 365         struct psb_drm_dpu_rect rect;
 366
 367         pyr_dsi_dbi_set_power(encoder, true);
 368
 369         dbi_output->mode_flags &= ~MODE_SETTING_IN_ENCODER;
 370
 371         rect.x = rect.y = 0;
 372         rect.width = 864;
 373         rect.height = 480;
 374
 375         if (dbi_output->channel_num == 1) {
 376                 dev_priv->dsr_fb_update |= MDFLD_DSR_2D_3D_2;
 377 #ifdef CONFIG_MDFLD_DSI_DPU
 378                 /* If DPU enabled report a fullscreen damage */
 379                 mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEC, &rect);
 380 #endif
 381         } else {
 382                 dev_priv->dsr_fb_update |= MDFLD_DSR_2D_3D_0;
 383
 384 #ifdef CONFIG_MDFLD_DSI_DPU
 385                 mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEA, &rect);
 386 #endif
 387         }
 388         dbi_output->mode_flags |= MODE_SETTING_ENCODER_DONE;
 389 }
 390
 391 static void pyr_dsi_dbi_dpms(struct drm_encoder *encoder, int mode)
 392 {
 393         struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
 394         struct mdfld_dsi_dbi_output *dbi_output =
 395                                         MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
 396         struct drm_device *dev = dbi_output->dev;
 397         struct drm_psb_private *dev_priv = dev->dev_private;
 398         static bool bdispoff;
 399
 400         dev_dbg(dev->dev, "%s\n",  (mode == DRM_MODE_DPMS_ON ? "on" : "off"));
 401
 402         if (mode == DRM_MODE_DPMS_ON) {
 403                 if (/*gbgfxsuspended && */bdispoff) {
 404                         bdispoff = false;
 405                         dev_priv->dispstatus = true;
 406                         /*gbgfxsuspended = false;
 407                         */
 408                         mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D, 0, 0);
 409                 }
 410                 pyr_dsi_dbi_set_power(encoder, true);
 411         } else {
 412                 bdispoff = true;
 413                 dev_priv->dispstatus = false;
 414                 pyr_dsi_dbi_set_power(encoder, false);
 415         }
 416 }
 417
 418 /*
 419  * Update the DBI MIPI Panel Frame Buffer.
 420  */
 421 static void pyr_dsi_dbi_update_fb(struct mdfld_dsi_dbi_output *dbi_output,
 422                                                                 int pipe)
 423 {
 424         struct mdfld_dsi_pkg_sender *sender =
 425                 mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
 426         struct drm_device *dev = dbi_output->dev;
 427         struct drm_crtc *crtc = dbi_output->base.base.crtc;
 428         struct psb_intel_crtc *psb_crtc = (crtc) ?
 429                                 to_psb_intel_crtc(crtc) : NULL;
 430
 431         u32 dpll_reg = MRST_DPLL_A;
 432         u32 dspcntr_reg = DSPACNTR;
 433         u32 pipeconf_reg = PIPEACONF;
 434         u32 dsplinoff_reg = DSPALINOFF;
 435         u32 dspsurf_reg = DSPASURF;
 436         u32 hs_gen_ctrl_reg = HS_GEN_CTRL_REG;
 437         u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG;
 438         u32 reg_offset = 0;
 439
 440         u32 intr_status;
 441         u32 fifo_stat_reg_val;
 442         u32 dpll_reg_val;
 443         u32 dspcntr_reg_val;
 444         u32 pipeconf_reg_val;
 445
 446         /* If mode setting on-going, back off */
 447         if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
 448                 (psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING) ||
 449                 !(dbi_output->mode_flags & MODE_SETTING_ENCODER_DONE))
 450                 return;
 451
 452         /*
 453          * Look for errors here.  In particular we're checking for whatever
 454          * error status might have appeared during the last frame transmit
 455          * (memory write).
 456          *
 457          * Normally, the bits we're testing here would be set infrequently,
 458          * if at all.  However, one panel (at least) returns at least one
 459          * error bit on most frames.  So we've disabled the kernel message
 460          * for now.
 461          *
 462          * Still clear whatever error bits are set, except don't clear the
 463          * ones that would make the Penwell DSI controller reset if we
 464          * cleared them.
 465          */
 466         intr_status = REG_READ(INTR_STAT_REG);
 467         if ((intr_status & 0x26FFFFFF) != 0) {
 468                 /* dev_err(dev->dev, "DSI status: 0x%08X\n", intr_status); */
 469                 intr_status &= 0x26F3FFFF;
 470                 REG_WRITE(INTR_STAT_REG, intr_status);
 471         }
 472
 473         if (pipe == 2) {
 474                 dspcntr_reg = DSPCCNTR;
 475                 pipeconf_reg = PIPECCONF;
 476                 dsplinoff_reg = DSPCLINOFF;
 477                 dspsurf_reg = DSPCSURF;
 478
 479                 hs_gen_ctrl_reg = HS_GEN_CTRL_REG + MIPIC_REG_OFFSET;
 480                 gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET,
 481
 482                 reg_offset = MIPIC_REG_OFFSET;
 483         }
 484
 485         if (!gma_power_begin(dev, true)) {
 486                 dev_err(dev->dev, "hw begin failed\n");
 487                 return;
 488         }
 489
 490         fifo_stat_reg_val = REG_READ(MIPIA_GEN_FIFO_STAT_REG + reg_offset);
 491         dpll_reg_val = REG_READ(dpll_reg);
 492         dspcntr_reg_val = REG_READ(dspcntr_reg);
 493         pipeconf_reg_val = REG_READ(pipeconf_reg);
 494
 495         if (!(fifo_stat_reg_val & (1 << 27)) ||
 496                 (dpll_reg_val & DPLL_VCO_ENABLE) ||
 497                 !(dspcntr_reg_val & DISPLAY_PLANE_ENABLE) ||
 498                 !(pipeconf_reg_val & DISPLAY_PLANE_ENABLE)) {
 499                 goto update_fb_out0;
 500         }
 501
 502         /* Refresh plane changes */
 503         REG_WRITE(dsplinoff_reg, REG_READ(dsplinoff_reg));
 504         REG_WRITE(dspsurf_reg, REG_READ(dspsurf_reg));
 505         REG_READ(dspsurf_reg);
 506
 507         mdfld_dsi_send_dcs(sender,
 508                            write_mem_start,
 509                            NULL,
 510                            0,
 511                            CMD_DATA_SRC_PIPE,
 512                            MDFLD_DSI_SEND_PACKAGE);
 513
 514         /*
 515          * The idea here is to transmit a Generic Read command after the
 516          * Write Memory Start/Continue commands finish.  This asks for
 517          * the panel to return an "ACK No Errors," or (if it has errors
 518          * to report) an Error Report.  This allows us to monitor the
 519          * panel's perception of the health of the DSI.
 520          */
 521         mdfld_dsi_gen_fifo_ready(dev, gen_fifo_stat_reg,
 522                                 HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
 523         REG_WRITE(hs_gen_ctrl_reg, (1 << WORD_COUNTS_POS) | GEN_READ_0);
 524
 525         dbi_output->dsr_fb_update_done = true;
 526 update_fb_out0:
 527         gma_power_end(dev);
 528 }
 529
 530 /*
 531  * TODO: will be removed later, should work out display interfaces for power
 532  */
 533 void pyr_dsi_adapter_init(struct mdfld_dsi_config *dsi_config, int pipe)
 534 {
 535         if (!dsi_config || (pipe != 0 && pipe != 2)) {
 536                 WARN_ON(1);
 537                 return;
 538         }
 539         pyr_dsi_controller_dbi_init(dsi_config, pipe);
 540 }
 541
 542 static int pyr_cmd_get_panel_info(struct drm_device *dev, int pipe,
 543                                                         struct panel_info *pi)
 544 {
 545         if (!dev || !pi)
 546                 return -EINVAL;
 547
 548         pi->width_mm = PYR_PANEL_WIDTH;
 549         pi->height_mm = PYR_PANEL_HEIGHT;
 550
 551         return 0;
 552 }
 553
 554 /* PYR DBI encoder helper funcs */
 555 static const struct drm_encoder_helper_funcs pyr_dsi_dbi_helper_funcs = {
 556         .dpms = pyr_dsi_dbi_dpms,
 557         .mode_fixup = pyr_dsi_dbi_mode_fixup,
 558         .prepare = pyr_dsi_dbi_prepare,
 559         .mode_set = pyr_dsi_dbi_mode_set,
 560         .commit = pyr_dsi_dbi_commit,
 561 };
 562
 563 /* PYR DBI encoder funcs */
 564 static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs = {
 565         .destroy = drm_encoder_cleanup,
 566 };
 567
 568 void pyr_cmd_init(struct drm_device *dev, struct panel_funcs *p_funcs)
 569 {
 570         p_funcs->encoder_funcs = &mdfld_dsi_dbi_encoder_funcs;
 571         p_funcs->encoder_helper_funcs = &pyr_dsi_dbi_helper_funcs;
 572         p_funcs->get_config_mode = &pyr_cmd_get_config_mode;
 573         p_funcs->update_fb = pyr_dsi_dbi_update_fb;
 574         p_funcs->get_panel_info = pyr_cmd_get_panel_info;
 575 }