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sparc64: Fix cmdline_memory_size handling bugs.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / sparc64 / mm / init.c
blob387d3f666a56eb6c7f6cad87d905e4324ca57432
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/sstate.h>
50 #include <asm/mdesc.h>
51 #include <asm/cpudata.h>
52 #include <asm/irq.h>
53
54 #define MAX_PHYS_ADDRESS (1UL << 42UL)
55 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
56 #define KPTE_BITMAP_BYTES \
57 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
58
59 unsigned long kern_linear_pte_xor[2] __read_mostly;
60
61 /* A bitmap, one bit for every 256MB of physical memory. If the bit
62 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
63 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
64 */
65 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
66
67 #ifndef CONFIG_DEBUG_PAGEALLOC
68 /* A special kernel TSB for 4MB and 256MB linear mappings.
69 * Space is allocated for this right after the trap table
70 * in arch/sparc64/kernel/head.S
71 */
72 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
73 #endif
74
75 #define MAX_BANKS 32
76
77 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
78 static int pavail_ents __initdata;
79
80 static int cmp_p64(const void *a, const void *b)
81 {
82 const struct linux_prom64_registers *x = a, *y = b;
83
84 if (x->phys_addr > y->phys_addr)
85 return 1;
86 if (x->phys_addr < y->phys_addr)
87 return -1;
88 return 0;
89 }
90
91 static void __init read_obp_memory(const char *property,
92 struct linux_prom64_registers *regs,
93 int *num_ents)
94 {
95 int node = prom_finddevice("/memory");
96 int prop_size = prom_getproplen(node, property);
97 int ents, ret, i;
98
99 ents = prop_size / sizeof(struct linux_prom64_registers);
100 if (ents > MAX_BANKS) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property, MAX_BANKS);
104 prom_halt();
105 }
106
107 ret = prom_getproperty(node, property, (char *) regs, prop_size);
108 if (ret == -1) {
109 prom_printf("Couldn't get %s property from /memory.\n");
110 prom_halt();
111 }
112
113 /* Sanitize what we got from the firmware, by page aligning
114 * everything.
115 */
116 for (i = 0; i < ents; i++) {
117 unsigned long base, size;
118
119 base = regs[i].phys_addr;
120 size = regs[i].reg_size;
121
122 size &= PAGE_MASK;
123 if (base & ~PAGE_MASK) {
124 unsigned long new_base = PAGE_ALIGN(base);
125
126 size -= new_base - base;
127 if ((long) size < 0L)
128 size = 0UL;
129 base = new_base;
130 }
131 if (size == 0UL) {
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
135 */
136 memmove(&regs[i], &regs[i + 1],
137 (ents - i - 1) * sizeof(regs[0]));
138 i--;
139 ents--;
140 continue;
141 }
142 regs[i].phys_addr = base;
143 regs[i].reg_size = size;
144 }
145
146 *num_ents = ents;
147
148 sort(regs, ents, sizeof(struct linux_prom64_registers),
149 cmp_p64, NULL);
150 }
151
152 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
153
154 /* Kernel physical address base and size in bytes. */
155 unsigned long kern_base __read_mostly;
156 unsigned long kern_size __read_mostly;
157
158 /* Initial ramdisk setup */
159 extern unsigned long sparc_ramdisk_image64;
160 extern unsigned int sparc_ramdisk_image;
161 extern unsigned int sparc_ramdisk_size;
162
163 struct page *mem_map_zero __read_mostly;
164 EXPORT_SYMBOL(mem_map_zero);
165
166 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
167
168 unsigned long sparc64_kern_pri_context __read_mostly;
169 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
170 unsigned long sparc64_kern_sec_context __read_mostly;
171
172 int num_kernel_image_mappings;
173
174 #ifdef CONFIG_DEBUG_DCFLUSH
175 atomic_t dcpage_flushes = ATOMIC_INIT(0);
176 #ifdef CONFIG_SMP
177 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
178 #endif
179 #endif
180
181 inline void flush_dcache_page_impl(struct page *page)
182 {
183 BUG_ON(tlb_type == hypervisor);
184 #ifdef CONFIG_DEBUG_DCFLUSH
185 atomic_inc(&dcpage_flushes);
186 #endif
187
188 #ifdef DCACHE_ALIASING_POSSIBLE
189 __flush_dcache_page(page_address(page),
190 ((tlb_type == spitfire) &&
191 page_mapping(page) != NULL));
192 #else
193 if (page_mapping(page) != NULL &&
194 tlb_type == spitfire)
195 __flush_icache_page(__pa(page_address(page)));
196 #endif
197 }
198
199 #define PG_dcache_dirty PG_arch_1
200 #define PG_dcache_cpu_shift 32UL
201 #define PG_dcache_cpu_mask \
202 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
203
204 #define dcache_dirty_cpu(page) \
205 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
206
207 static inline void set_dcache_dirty(struct page *page, int this_cpu)
208 {
209 unsigned long mask = this_cpu;
210 unsigned long non_cpu_bits;
211
212 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
213 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
214
215 __asm__ __volatile__("1:\n\t"
216 "ldx [%2], %%g7\n\t"
217 "and %%g7, %1, %%g1\n\t"
218 "or %%g1, %0, %%g1\n\t"
219 "casx [%2], %%g7, %%g1\n\t"
220 "cmp %%g7, %%g1\n\t"
221 "membar #StoreLoad | #StoreStore\n\t"
222 "bne,pn %%xcc, 1b\n\t"
223 " nop"
224 : /* no outputs */
225 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
226 : "g1", "g7");
227 }
228
229 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
230 {
231 unsigned long mask = (1UL << PG_dcache_dirty);
232
233 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
234 "1:\n\t"
235 "ldx [%2], %%g7\n\t"
236 "srlx %%g7, %4, %%g1\n\t"
237 "and %%g1, %3, %%g1\n\t"
238 "cmp %%g1, %0\n\t"
239 "bne,pn %%icc, 2f\n\t"
240 " andn %%g7, %1, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
242 "cmp %%g7, %%g1\n\t"
243 "membar #StoreLoad | #StoreStore\n\t"
244 "bne,pn %%xcc, 1b\n\t"
245 " nop\n"
246 "2:"
247 : /* no outputs */
248 : "r" (cpu), "r" (mask), "r" (&page->flags),
249 "i" (PG_dcache_cpu_mask),
250 "i" (PG_dcache_cpu_shift)
251 : "g1", "g7");
252 }
253
254 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
255 {
256 unsigned long tsb_addr = (unsigned long) ent;
257
258 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
259 tsb_addr = __pa(tsb_addr);
260
261 __tsb_insert(tsb_addr, tag, pte);
262 }
263
264 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
265 unsigned long _PAGE_SZBITS __read_mostly;
266
267 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
268 {
269 struct mm_struct *mm;
270 struct tsb *tsb;
271 unsigned long tag, flags;
272 unsigned long tsb_index, tsb_hash_shift;
273
274 if (tlb_type != hypervisor) {
275 unsigned long pfn = pte_pfn(pte);
276 unsigned long pg_flags;
277 struct page *page;
278
279 if (pfn_valid(pfn) &&
280 (page = pfn_to_page(pfn), page_mapping(page)) &&
281 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
282 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
283 PG_dcache_cpu_mask);
284 int this_cpu = get_cpu();
285
286 /* This is just to optimize away some function calls
287 * in the SMP case.
288 */
289 if (cpu == this_cpu)
290 flush_dcache_page_impl(page);
291 else
292 smp_flush_dcache_page_impl(page, cpu);
293
294 clear_dcache_dirty_cpu(page, cpu);
295
296 put_cpu();
297 }
298 }
299
300 mm = vma->vm_mm;
301
302 tsb_index = MM_TSB_BASE;
303 tsb_hash_shift = PAGE_SHIFT;
304
305 spin_lock_irqsave(&mm->context.lock, flags);
306
307 #ifdef CONFIG_HUGETLB_PAGE
308 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
309 if ((tlb_type == hypervisor &&
310 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
311 (tlb_type != hypervisor &&
312 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
313 tsb_index = MM_TSB_HUGE;
314 tsb_hash_shift = HPAGE_SHIFT;
315 }
316 }
317 #endif
318
319 tsb = mm->context.tsb_block[tsb_index].tsb;
320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, pte_val(pte));
324
325 spin_unlock_irqrestore(&mm->context.lock, flags);
326 }
327
328 void flush_dcache_page(struct page *page)
329 {
330 struct address_space *mapping;
331 int this_cpu;
332
333 if (tlb_type == hypervisor)
334 return;
335
336 /* Do not bother with the expensive D-cache flush if it
337 * is merely the zero page. The 'bigcore' testcase in GDB
338 * causes this case to run millions of times.
339 */
340 if (page == ZERO_PAGE(0))
341 return;
342
343 this_cpu = get_cpu();
344
345 mapping = page_mapping(page);
346 if (mapping && !mapping_mapped(mapping)) {
347 int dirty = test_bit(PG_dcache_dirty, &page->flags);
348 if (dirty) {
349 int dirty_cpu = dcache_dirty_cpu(page);
350
351 if (dirty_cpu == this_cpu)
352 goto out;
353 smp_flush_dcache_page_impl(page, dirty_cpu);
354 }
355 set_dcache_dirty(page, this_cpu);
356 } else {
357 /* We could delay the flush for the !page_mapping
358 * case too. But that case is for exec env/arg
359 * pages and those are %99 certainly going to get
360 * faulted into the tlb (and thus flushed) anyways.
361 */
362 flush_dcache_page_impl(page);
363 }
364
365 out:
366 put_cpu();
367 }
368
369 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
370 {
371 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
372 if (tlb_type == spitfire) {
373 unsigned long kaddr;
374
375 /* This code only runs on Spitfire cpus so this is
376 * why we can assume _PAGE_PADDR_4U.
377 */
378 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
379 unsigned long paddr, mask = _PAGE_PADDR_4U;
380
381 if (kaddr >= PAGE_OFFSET)
382 paddr = kaddr & mask;
383 else {
384 pgd_t *pgdp = pgd_offset_k(kaddr);
385 pud_t *pudp = pud_offset(pgdp, kaddr);
386 pmd_t *pmdp = pmd_offset(pudp, kaddr);
387 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
388
389 paddr = pte_val(*ptep) & mask;
390 }
391 __flush_icache_page(paddr);
392 }
393 }
394 }
395
396 void show_mem(void)
397 {
398 unsigned long total = 0, reserved = 0;
399 unsigned long shared = 0, cached = 0;
400 pg_data_t *pgdat;
401
402 printk(KERN_INFO "Mem-info:\n");
403 show_free_areas();
404 printk(KERN_INFO "Free swap: %6ldkB\n",
405 nr_swap_pages << (PAGE_SHIFT-10));
406 for_each_online_pgdat(pgdat) {
407 unsigned long i, flags;
408
409 pgdat_resize_lock(pgdat, &flags);
410 for (i = 0; i < pgdat->node_spanned_pages; i++) {
411 struct page *page = pgdat_page_nr(pgdat, i);
412 total++;
413 if (PageReserved(page))
414 reserved++;
415 else if (PageSwapCache(page))
416 cached++;
417 else if (page_count(page))
418 shared += page_count(page) - 1;
419 }
420 pgdat_resize_unlock(pgdat, &flags);
421 }
422
423 printk(KERN_INFO "%lu pages of RAM\n", total);
424 printk(KERN_INFO "%lu reserved pages\n", reserved);
425 printk(KERN_INFO "%lu pages shared\n", shared);
426 printk(KERN_INFO "%lu pages swap cached\n", cached);
427
428 printk(KERN_INFO "%lu pages dirty\n",
429 global_page_state(NR_FILE_DIRTY));
430 printk(KERN_INFO "%lu pages writeback\n",
431 global_page_state(NR_WRITEBACK));
432 printk(KERN_INFO "%lu pages mapped\n",
433 global_page_state(NR_FILE_MAPPED));
434 printk(KERN_INFO "%lu pages slab\n",
435 global_page_state(NR_SLAB_RECLAIMABLE) +
436 global_page_state(NR_SLAB_UNRECLAIMABLE));
437 printk(KERN_INFO "%lu pages pagetables\n",
438 global_page_state(NR_PAGETABLE));
439 }
440
441 void mmu_info(struct seq_file *m)
442 {
443 if (tlb_type == cheetah)
444 seq_printf(m, "MMU Type\t: Cheetah\n");
445 else if (tlb_type == cheetah_plus)
446 seq_printf(m, "MMU Type\t: Cheetah+\n");
447 else if (tlb_type == spitfire)
448 seq_printf(m, "MMU Type\t: Spitfire\n");
449 else if (tlb_type == hypervisor)
450 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
451 else
452 seq_printf(m, "MMU Type\t: ???\n");
453
454 #ifdef CONFIG_DEBUG_DCFLUSH
455 seq_printf(m, "DCPageFlushes\t: %d\n",
456 atomic_read(&dcpage_flushes));
457 #ifdef CONFIG_SMP
458 seq_printf(m, "DCPageFlushesXC\t: %d\n",
459 atomic_read(&dcpage_flushes_xcall));
460 #endif /* CONFIG_SMP */
461 #endif /* CONFIG_DEBUG_DCFLUSH */
462 }
463
464 struct linux_prom_translation {
465 unsigned long virt;
466 unsigned long size;
467 unsigned long data;
468 };
469
470 /* Exported for kernel TLB miss handling in ktlb.S */
471 struct linux_prom_translation prom_trans[512] __read_mostly;
472 unsigned int prom_trans_ents __read_mostly;
473
474 /* Exported for SMP bootup purposes. */
475 unsigned long kern_locked_tte_data;
476
477 /* The obp translations are saved based on 8k pagesize, since obp can
478 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
479 * HI_OBP_ADDRESS range are handled in ktlb.S.
480 */
481 static inline int in_obp_range(unsigned long vaddr)
482 {
483 return (vaddr >= LOW_OBP_ADDRESS &&
484 vaddr < HI_OBP_ADDRESS);
485 }
486
487 static int cmp_ptrans(const void *a, const void *b)
488 {
489 const struct linux_prom_translation *x = a, *y = b;
490
491 if (x->virt > y->virt)
492 return 1;
493 if (x->virt < y->virt)
494 return -1;
495 return 0;
496 }
497
498 /* Read OBP translations property into 'prom_trans[]'. */
499 static void __init read_obp_translations(void)
500 {
501 int n, node, ents, first, last, i;
502
503 node = prom_finddevice("/virtual-memory");
504 n = prom_getproplen(node, "translations");
505 if (unlikely(n == 0 || n == -1)) {
506 prom_printf("prom_mappings: Couldn't get size.\n");
507 prom_halt();
508 }
509 if (unlikely(n > sizeof(prom_trans))) {
510 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
511 prom_halt();
512 }
513
514 if ((n = prom_getproperty(node, "translations",
515 (char *)&prom_trans[0],
516 sizeof(prom_trans))) == -1) {
517 prom_printf("prom_mappings: Couldn't get property.\n");
518 prom_halt();
519 }
520
521 n = n / sizeof(struct linux_prom_translation);
522
523 ents = n;
524
525 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
526 cmp_ptrans, NULL);
527
528 /* Now kick out all the non-OBP entries. */
529 for (i = 0; i < ents; i++) {
530 if (in_obp_range(prom_trans[i].virt))
531 break;
532 }
533 first = i;
534 for (; i < ents; i++) {
535 if (!in_obp_range(prom_trans[i].virt))
536 break;
537 }
538 last = i;
539
540 for (i = 0; i < (last - first); i++) {
541 struct linux_prom_translation *src = &prom_trans[i + first];
542 struct linux_prom_translation *dest = &prom_trans[i];
543
544 *dest = *src;
545 }
546 for (; i < ents; i++) {
547 struct linux_prom_translation *dest = &prom_trans[i];
548 dest->virt = dest->size = dest->data = 0x0UL;
549 }
550
551 prom_trans_ents = last - first;
552
553 if (tlb_type == spitfire) {
554 /* Clear diag TTE bits. */
555 for (i = 0; i < prom_trans_ents; i++)
556 prom_trans[i].data &= ~0x0003fe0000000000UL;
557 }
558 }
559
560 static void __init hypervisor_tlb_lock(unsigned long vaddr,
561 unsigned long pte,
562 unsigned long mmu)
563 {
564 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
565
566 if (ret != 0) {
567 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
568 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
569 prom_halt();
570 }
571 }
572
573 static unsigned long kern_large_tte(unsigned long paddr);
574
575 static void __init remap_kernel(void)
576 {
577 unsigned long phys_page, tte_vaddr, tte_data;
578 int i, tlb_ent = sparc64_highest_locked_tlbent();
579
580 tte_vaddr = (unsigned long) KERNBASE;
581 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
582 tte_data = kern_large_tte(phys_page);
583
584 kern_locked_tte_data = tte_data;
585
586 /* Now lock us into the TLBs via Hypervisor or OBP. */
587 if (tlb_type == hypervisor) {
588 for (i = 0; i < num_kernel_image_mappings; i++) {
589 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
590 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
591 tte_vaddr += 0x400000;
592 tte_data += 0x400000;
593 }
594 } else {
595 for (i = 0; i < num_kernel_image_mappings; i++) {
596 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
597 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
598 tte_vaddr += 0x400000;
599 tte_data += 0x400000;
600 }
601 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
602 }
603 if (tlb_type == cheetah_plus) {
604 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
605 CTX_CHEETAH_PLUS_NUC);
606 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
607 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
608 }
609 }
610
611
612 static void __init inherit_prom_mappings(void)
613 {
614 /* Now fixup OBP's idea about where we really are mapped. */
615 printk("Remapping the kernel... ");
616 remap_kernel();
617 printk("done.\n");
618 }
619
620 void prom_world(int enter)
621 {
622 if (!enter)
623 set_fs((mm_segment_t) { get_thread_current_ds() });
624
625 __asm__ __volatile__("flushw");
626 }
627
628 void __flush_dcache_range(unsigned long start, unsigned long end)
629 {
630 unsigned long va;
631
632 if (tlb_type == spitfire) {
633 int n = 0;
634
635 for (va = start; va < end; va += 32) {
636 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
637 if (++n >= 512)
638 break;
639 }
640 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
641 start = __pa(start);
642 end = __pa(end);
643 for (va = start; va < end; va += 32)
644 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645 "membar #Sync"
646 : /* no outputs */
647 : "r" (va),
648 "i" (ASI_DCACHE_INVALIDATE));
649 }
650 }
651
652 /* get_new_mmu_context() uses "cache + 1". */
653 DEFINE_SPINLOCK(ctx_alloc_lock);
654 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
655 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
656 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
657 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
658
659 /* Caller does TLB context flushing on local CPU if necessary.
660 * The caller also ensures that CTX_VALID(mm->context) is false.
661 *
662 * We must be careful about boundary cases so that we never
663 * let the user have CTX 0 (nucleus) or we ever use a CTX
664 * version of zero (and thus NO_CONTEXT would not be caught
665 * by version mis-match tests in mmu_context.h).
666 *
667 * Always invoked with interrupts disabled.
668 */
669 void get_new_mmu_context(struct mm_struct *mm)
670 {
671 unsigned long ctx, new_ctx;
672 unsigned long orig_pgsz_bits;
673 unsigned long flags;
674 int new_version;
675
676 spin_lock_irqsave(&ctx_alloc_lock, flags);
677 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
678 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
679 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
680 new_version = 0;
681 if (new_ctx >= (1 << CTX_NR_BITS)) {
682 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
683 if (new_ctx >= ctx) {
684 int i;
685 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
686 CTX_FIRST_VERSION;
687 if (new_ctx == 1)
688 new_ctx = CTX_FIRST_VERSION;
689
690 /* Don't call memset, for 16 entries that's just
691 * plain silly...
692 */
693 mmu_context_bmap[0] = 3;
694 mmu_context_bmap[1] = 0;
695 mmu_context_bmap[2] = 0;
696 mmu_context_bmap[3] = 0;
697 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
698 mmu_context_bmap[i + 0] = 0;
699 mmu_context_bmap[i + 1] = 0;
700 mmu_context_bmap[i + 2] = 0;
701 mmu_context_bmap[i + 3] = 0;
702 }
703 new_version = 1;
704 goto out;
705 }
706 }
707 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
708 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
709 out:
710 tlb_context_cache = new_ctx;
711 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
712 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
713
714 if (unlikely(new_version))
715 smp_new_mmu_context_version();
716 }
717
718 static int numa_enabled = 1;
719 static int numa_debug;
720
721 static int __init early_numa(char *p)
722 {
723 if (!p)
724 return 0;
725
726 if (strstr(p, "off"))
727 numa_enabled = 0;
728
729 if (strstr(p, "debug"))
730 numa_debug = 1;
731
732 return 0;
733 }
734 early_param("numa", early_numa);
735
736 #define numadbg(f, a...) \
737 do { if (numa_debug) \
738 printk(KERN_INFO f, ## a); \
739 } while (0)
740
741 static void __init find_ramdisk(unsigned long phys_base)
742 {
743 #ifdef CONFIG_BLK_DEV_INITRD
744 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
745 unsigned long ramdisk_image;
746
747 /* Older versions of the bootloader only supported a
748 * 32-bit physical address for the ramdisk image
749 * location, stored at sparc_ramdisk_image. Newer
750 * SILO versions set sparc_ramdisk_image to zero and
751 * provide a full 64-bit physical address at
752 * sparc_ramdisk_image64.
753 */
754 ramdisk_image = sparc_ramdisk_image;
755 if (!ramdisk_image)
756 ramdisk_image = sparc_ramdisk_image64;
757
758 /* Another bootloader quirk. The bootloader normalizes
759 * the physical address to KERNBASE, so we have to
760 * factor that back out and add in the lowest valid
761 * physical page address to get the true physical address.
762 */
763 ramdisk_image -= KERNBASE;
764 ramdisk_image += phys_base;
765
766 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
767 ramdisk_image, sparc_ramdisk_size);
768
769 initrd_start = ramdisk_image;
770 initrd_end = ramdisk_image + sparc_ramdisk_size;
771
772 lmb_reserve(initrd_start, sparc_ramdisk_size);
773
774 initrd_start += PAGE_OFFSET;
775 initrd_end += PAGE_OFFSET;
776 }
777 #endif
778 }
779
780 struct node_mem_mask {
781 unsigned long mask;
782 unsigned long val;
783 unsigned long bootmem_paddr;
784 };
785 static struct node_mem_mask node_masks[MAX_NUMNODES];
786 static int num_node_masks;
787
788 int numa_cpu_lookup_table[NR_CPUS];
789 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
790
791 #ifdef CONFIG_NEED_MULTIPLE_NODES
792 static bootmem_data_t plat_node_bdata[MAX_NUMNODES];
793
794 struct mdesc_mblock {
795 u64 base;
796 u64 size;
797 u64 offset; /* RA-to-PA */
798 };
799 static struct mdesc_mblock *mblocks;
800 static int num_mblocks;
801
802 static unsigned long ra_to_pa(unsigned long addr)
803 {
804 int i;
805
806 for (i = 0; i < num_mblocks; i++) {
807 struct mdesc_mblock *m = &mblocks[i];
808
809 if (addr >= m->base &&
810 addr < (m->base + m->size)) {
811 addr += m->offset;
812 break;
813 }
814 }
815 return addr;
816 }
817
818 static int find_node(unsigned long addr)
819 {
820 int i;
821
822 addr = ra_to_pa(addr);
823 for (i = 0; i < num_node_masks; i++) {
824 struct node_mem_mask *p = &node_masks[i];
825
826 if ((addr & p->mask) == p->val)
827 return i;
828 }
829 return -1;
830 }
831
832 static unsigned long nid_range(unsigned long start, unsigned long end,
833 int *nid)
834 {
835 *nid = find_node(start);
836 start += PAGE_SIZE;
837 while (start < end) {
838 int n = find_node(start);
839
840 if (n != *nid)
841 break;
842 start += PAGE_SIZE;
843 }
844
845 if (start > end)
846 start = end;
847
848 return start;
849 }
850 #else
851 static unsigned long nid_range(unsigned long start, unsigned long end,
852 int *nid)
853 {
854 *nid = 0;
855 return end;
856 }
857 #endif
858
859 /* This must be invoked after performing all of the necessary
860 * add_active_range() calls for 'nid'. We need to be able to get
861 * correct data from get_pfn_range_for_nid().
862 */
863 static void __init allocate_node_data(int nid)
864 {
865 unsigned long paddr, num_pages, start_pfn, end_pfn;
866 struct pglist_data *p;
867
868 #ifdef CONFIG_NEED_MULTIPLE_NODES
869 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
870 SMP_CACHE_BYTES, nid, nid_range);
871 if (!paddr) {
872 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
873 prom_halt();
874 }
875 NODE_DATA(nid) = __va(paddr);
876 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
877
878 NODE_DATA(nid)->bdata = &plat_node_bdata[nid];
879 #endif
880
881 p = NODE_DATA(nid);
882
883 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
884 p->node_start_pfn = start_pfn;
885 p->node_spanned_pages = end_pfn - start_pfn;
886
887 if (p->node_spanned_pages) {
888 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
889
890 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
891 nid_range);
892 if (!paddr) {
893 prom_printf("Cannot allocate bootmap for nid[%d]\n",
894 nid);
895 prom_halt();
896 }
897 node_masks[nid].bootmem_paddr = paddr;
898 }
899 }
900
901 static void init_node_masks_nonnuma(void)
902 {
903 int i;
904
905 numadbg("Initializing tables for non-numa.\n");
906
907 node_masks[0].mask = node_masks[0].val = 0;
908 num_node_masks = 1;
909
910 for (i = 0; i < NR_CPUS; i++)
911 numa_cpu_lookup_table[i] = 0;
912
913 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
914 }
915
916 #ifdef CONFIG_NEED_MULTIPLE_NODES
917 struct pglist_data *node_data[MAX_NUMNODES];
918
919 EXPORT_SYMBOL(numa_cpu_lookup_table);
920 EXPORT_SYMBOL(numa_cpumask_lookup_table);
921 EXPORT_SYMBOL(node_data);
922
923 struct mdesc_mlgroup {
924 u64 node;
925 u64 latency;
926 u64 match;
927 u64 mask;
928 };
929 static struct mdesc_mlgroup *mlgroups;
930 static int num_mlgroups;
931
932 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
933 u32 cfg_handle)
934 {
935 u64 arc;
936
937 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
938 u64 target = mdesc_arc_target(md, arc);
939 const u64 *val;
940
941 val = mdesc_get_property(md, target,
942 "cfg-handle", NULL);
943 if (val && *val == cfg_handle)
944 return 0;
945 }
946 return -ENODEV;
947 }
948
949 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
950 u32 cfg_handle)
951 {
952 u64 arc, candidate, best_latency = ~(u64)0;
953
954 candidate = MDESC_NODE_NULL;
955 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
956 u64 target = mdesc_arc_target(md, arc);
957 const char *name = mdesc_node_name(md, target);
958 const u64 *val;
959
960 if (strcmp(name, "pio-latency-group"))
961 continue;
962
963 val = mdesc_get_property(md, target, "latency", NULL);
964 if (!val)
965 continue;
966
967 if (*val < best_latency) {
968 candidate = target;
969 best_latency = *val;
970 }
971 }
972
973 if (candidate == MDESC_NODE_NULL)
974 return -ENODEV;
975
976 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
977 }
978
979 int of_node_to_nid(struct device_node *dp)
980 {
981 const struct linux_prom64_registers *regs;
982 struct mdesc_handle *md;
983 u32 cfg_handle;
984 int count, nid;
985 u64 grp;
986
987 if (!mlgroups)
988 return -1;
989
990 regs = of_get_property(dp, "reg", NULL);
991 if (!regs)
992 return -1;
993
994 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
995
996 md = mdesc_grab();
997
998 count = 0;
999 nid = -1;
1000 mdesc_for_each_node_by_name(md, grp, "group") {
1001 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1002 nid = count;
1003 break;
1004 }
1005 count++;
1006 }
1007
1008 mdesc_release(md);
1009
1010 return nid;
1011 }
1012
1013 static void add_node_ranges(void)
1014 {
1015 int i;
1016
1017 for (i = 0; i < lmb.memory.cnt; i++) {
1018 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1019 unsigned long start, end;
1020
1021 start = lmb.memory.region[i].base;
1022 end = start + size;
1023 while (start < end) {
1024 unsigned long this_end;
1025 int nid;
1026
1027 this_end = nid_range(start, end, &nid);
1028
1029 numadbg("Adding active range nid[%d] "
1030 "start[%lx] end[%lx]\n",
1031 nid, start, this_end);
1032
1033 add_active_range(nid,
1034 start >> PAGE_SHIFT,
1035 this_end >> PAGE_SHIFT);
1036
1037 start = this_end;
1038 }
1039 }
1040 }
1041
1042 static int __init grab_mlgroups(struct mdesc_handle *md)
1043 {
1044 unsigned long paddr;
1045 int count = 0;
1046 u64 node;
1047
1048 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1049 count++;
1050 if (!count)
1051 return -ENOENT;
1052
1053 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1054 SMP_CACHE_BYTES);
1055 if (!paddr)
1056 return -ENOMEM;
1057
1058 mlgroups = __va(paddr);
1059 num_mlgroups = count;
1060
1061 count = 0;
1062 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1063 struct mdesc_mlgroup *m = &mlgroups[count++];
1064 const u64 *val;
1065
1066 m->node = node;
1067
1068 val = mdesc_get_property(md, node, "latency", NULL);
1069 m->latency = *val;
1070 val = mdesc_get_property(md, node, "address-match", NULL);
1071 m->match = *val;
1072 val = mdesc_get_property(md, node, "address-mask", NULL);
1073 m->mask = *val;
1074
1075 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1076 "match[%lx] mask[%lx]\n",
1077 count - 1, m->node, m->latency, m->match, m->mask);
1078 }
1079
1080 return 0;
1081 }
1082
1083 static int __init grab_mblocks(struct mdesc_handle *md)
1084 {
1085 unsigned long paddr;
1086 int count = 0;
1087 u64 node;
1088
1089 mdesc_for_each_node_by_name(md, node, "mblock")
1090 count++;
1091 if (!count)
1092 return -ENOENT;
1093
1094 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1095 SMP_CACHE_BYTES);
1096 if (!paddr)
1097 return -ENOMEM;
1098
1099 mblocks = __va(paddr);
1100 num_mblocks = count;
1101
1102 count = 0;
1103 mdesc_for_each_node_by_name(md, node, "mblock") {
1104 struct mdesc_mblock *m = &mblocks[count++];
1105 const u64 *val;
1106
1107 val = mdesc_get_property(md, node, "base", NULL);
1108 m->base = *val;
1109 val = mdesc_get_property(md, node, "size", NULL);
1110 m->size = *val;
1111 val = mdesc_get_property(md, node,
1112 "address-congruence-offset", NULL);
1113 m->offset = *val;
1114
1115 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1116 count - 1, m->base, m->size, m->offset);
1117 }
1118
1119 return 0;
1120 }
1121
1122 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1123 u64 grp, cpumask_t *mask)
1124 {
1125 u64 arc;
1126
1127 cpus_clear(*mask);
1128
1129 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1130 u64 target = mdesc_arc_target(md, arc);
1131 const char *name = mdesc_node_name(md, target);
1132 const u64 *id;
1133
1134 if (strcmp(name, "cpu"))
1135 continue;
1136 id = mdesc_get_property(md, target, "id", NULL);
1137 if (*id < NR_CPUS)
1138 cpu_set(*id, *mask);
1139 }
1140 }
1141
1142 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1143 {
1144 int i;
1145
1146 for (i = 0; i < num_mlgroups; i++) {
1147 struct mdesc_mlgroup *m = &mlgroups[i];
1148 if (m->node == node)
1149 return m;
1150 }
1151 return NULL;
1152 }
1153
1154 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1155 int index)
1156 {
1157 struct mdesc_mlgroup *candidate = NULL;
1158 u64 arc, best_latency = ~(u64)0;
1159 struct node_mem_mask *n;
1160
1161 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1162 u64 target = mdesc_arc_target(md, arc);
1163 struct mdesc_mlgroup *m = find_mlgroup(target);
1164 if (!m)
1165 continue;
1166 if (m->latency < best_latency) {
1167 candidate = m;
1168 best_latency = m->latency;
1169 }
1170 }
1171 if (!candidate)
1172 return -ENOENT;
1173
1174 if (num_node_masks != index) {
1175 printk(KERN_ERR "Inconsistent NUMA state, "
1176 "index[%d] != num_node_masks[%d]\n",
1177 index, num_node_masks);
1178 return -EINVAL;
1179 }
1180
1181 n = &node_masks[num_node_masks++];
1182
1183 n->mask = candidate->mask;
1184 n->val = candidate->match;
1185
1186 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1187 index, n->mask, n->val, candidate->latency);
1188
1189 return 0;
1190 }
1191
1192 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1193 int index)
1194 {
1195 cpumask_t mask;
1196 int cpu;
1197
1198 numa_parse_mdesc_group_cpus(md, grp, &mask);
1199
1200 for_each_cpu_mask(cpu, mask)
1201 numa_cpu_lookup_table[cpu] = index;
1202 numa_cpumask_lookup_table[index] = mask;
1203
1204 if (numa_debug) {
1205 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1206 for_each_cpu_mask(cpu, mask)
1207 printk("%d ", cpu);
1208 printk("]\n");
1209 }
1210
1211 return numa_attach_mlgroup(md, grp, index);
1212 }
1213
1214 static int __init numa_parse_mdesc(void)
1215 {
1216 struct mdesc_handle *md = mdesc_grab();
1217 int i, err, count;
1218 u64 node;
1219
1220 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1221 if (node == MDESC_NODE_NULL) {
1222 mdesc_release(md);
1223 return -ENOENT;
1224 }
1225
1226 err = grab_mblocks(md);
1227 if (err < 0)
1228 goto out;
1229
1230 err = grab_mlgroups(md);
1231 if (err < 0)
1232 goto out;
1233
1234 count = 0;
1235 mdesc_for_each_node_by_name(md, node, "group") {
1236 err = numa_parse_mdesc_group(md, node, count);
1237 if (err < 0)
1238 break;
1239 count++;
1240 }
1241
1242 add_node_ranges();
1243
1244 for (i = 0; i < num_node_masks; i++) {
1245 allocate_node_data(i);
1246 node_set_online(i);
1247 }
1248
1249 err = 0;
1250 out:
1251 mdesc_release(md);
1252 return err;
1253 }
1254
1255 static int __init numa_parse_sun4u(void)
1256 {
1257 return -1;
1258 }
1259
1260 static int __init bootmem_init_numa(void)
1261 {
1262 int err = -1;
1263
1264 numadbg("bootmem_init_numa()\n");
1265
1266 if (numa_enabled) {
1267 if (tlb_type == hypervisor)
1268 err = numa_parse_mdesc();
1269 else
1270 err = numa_parse_sun4u();
1271 }
1272 return err;
1273 }
1274
1275 #else
1276
1277 static int bootmem_init_numa(void)
1278 {
1279 return -1;
1280 }
1281
1282 #endif
1283
1284 static void __init bootmem_init_nonnuma(void)
1285 {
1286 unsigned long top_of_ram = lmb_end_of_DRAM();
1287 unsigned long total_ram = lmb_phys_mem_size();
1288 unsigned int i;
1289
1290 numadbg("bootmem_init_nonnuma()\n");
1291
1292 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1293 top_of_ram, total_ram);
1294 printk(KERN_INFO "Memory hole size: %ldMB\n",
1295 (top_of_ram - total_ram) >> 20);
1296
1297 init_node_masks_nonnuma();
1298
1299 for (i = 0; i < lmb.memory.cnt; i++) {
1300 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1301 unsigned long start_pfn, end_pfn;
1302
1303 if (!size)
1304 continue;
1305
1306 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1307 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1308 add_active_range(0, start_pfn, end_pfn);
1309 }
1310
1311 allocate_node_data(0);
1312
1313 node_set_online(0);
1314 }
1315
1316 static void __init reserve_range_in_node(int nid, unsigned long start,
1317 unsigned long end)
1318 {
1319 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1320 nid, start, end);
1321 while (start < end) {
1322 unsigned long this_end;
1323 int n;
1324
1325 this_end = nid_range(start, end, &n);
1326 if (n == nid) {
1327 numadbg(" MATCH reserving range [%lx:%lx]\n",
1328 start, this_end);
1329 reserve_bootmem_node(NODE_DATA(nid), start,
1330 (this_end - start), BOOTMEM_DEFAULT);
1331 } else
1332 numadbg(" NO MATCH, advancing start to %lx\n",
1333 this_end);
1334
1335 start = this_end;
1336 }
1337 }
1338
1339 static void __init trim_reserved_in_node(int nid)
1340 {
1341 int i;
1342
1343 numadbg(" trim_reserved_in_node(%d)\n", nid);
1344
1345 for (i = 0; i < lmb.reserved.cnt; i++) {
1346 unsigned long start = lmb.reserved.region[i].base;
1347 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1348 unsigned long end = start + size;
1349
1350 reserve_range_in_node(nid, start, end);
1351 }
1352 }
1353
1354 static void __init bootmem_init_one_node(int nid)
1355 {
1356 struct pglist_data *p;
1357
1358 numadbg("bootmem_init_one_node(%d)\n", nid);
1359
1360 p = NODE_DATA(nid);
1361
1362 if (p->node_spanned_pages) {
1363 unsigned long paddr = node_masks[nid].bootmem_paddr;
1364 unsigned long end_pfn;
1365
1366 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1367
1368 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1369 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1370
1371 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1372 p->node_start_pfn, end_pfn);
1373
1374 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1375 nid, end_pfn);
1376 free_bootmem_with_active_regions(nid, end_pfn);
1377
1378 trim_reserved_in_node(nid);
1379
1380 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1381 nid);
1382 sparse_memory_present_with_active_regions(nid);
1383 }
1384 }
1385
1386 static unsigned long __init bootmem_init(unsigned long phys_base)
1387 {
1388 unsigned long end_pfn;
1389 int nid;
1390
1391 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1392 max_pfn = max_low_pfn = end_pfn;
1393 min_low_pfn = (phys_base >> PAGE_SHIFT);
1394
1395 if (bootmem_init_numa() < 0)
1396 bootmem_init_nonnuma();
1397
1398 /* XXX cpu notifier XXX */
1399
1400 for_each_online_node(nid)
1401 bootmem_init_one_node(nid);
1402
1403 sparse_init();
1404
1405 return end_pfn;
1406 }
1407
1408 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1409 static int pall_ents __initdata;
1410
1411 #ifdef CONFIG_DEBUG_PAGEALLOC
1412 static unsigned long __ref kernel_map_range(unsigned long pstart,
1413 unsigned long pend, pgprot_t prot)
1414 {
1415 unsigned long vstart = PAGE_OFFSET + pstart;
1416 unsigned long vend = PAGE_OFFSET + pend;
1417 unsigned long alloc_bytes = 0UL;
1418
1419 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1420 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1421 vstart, vend);
1422 prom_halt();
1423 }
1424
1425 while (vstart < vend) {
1426 unsigned long this_end, paddr = __pa(vstart);
1427 pgd_t *pgd = pgd_offset_k(vstart);
1428 pud_t *pud;
1429 pmd_t *pmd;
1430 pte_t *pte;
1431
1432 pud = pud_offset(pgd, vstart);
1433 if (pud_none(*pud)) {
1434 pmd_t *new;
1435
1436 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1437 alloc_bytes += PAGE_SIZE;
1438 pud_populate(&init_mm, pud, new);
1439 }
1440
1441 pmd = pmd_offset(pud, vstart);
1442 if (!pmd_present(*pmd)) {
1443 pte_t *new;
1444
1445 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1446 alloc_bytes += PAGE_SIZE;
1447 pmd_populate_kernel(&init_mm, pmd, new);
1448 }
1449
1450 pte = pte_offset_kernel(pmd, vstart);
1451 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1452 if (this_end > vend)
1453 this_end = vend;
1454
1455 while (vstart < this_end) {
1456 pte_val(*pte) = (paddr | pgprot_val(prot));
1457
1458 vstart += PAGE_SIZE;
1459 paddr += PAGE_SIZE;
1460 pte++;
1461 }
1462 }
1463
1464 return alloc_bytes;
1465 }
1466
1467 extern unsigned int kvmap_linear_patch[1];
1468 #endif /* CONFIG_DEBUG_PAGEALLOC */
1469
1470 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1471 {
1472 const unsigned long shift_256MB = 28;
1473 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1474 const unsigned long size_256MB = (1UL << shift_256MB);
1475
1476 while (start < end) {
1477 long remains;
1478
1479 remains = end - start;
1480 if (remains < size_256MB)
1481 break;
1482
1483 if (start & mask_256MB) {
1484 start = (start + size_256MB) & ~mask_256MB;
1485 continue;
1486 }
1487
1488 while (remains >= size_256MB) {
1489 unsigned long index = start >> shift_256MB;
1490
1491 __set_bit(index, kpte_linear_bitmap);
1492
1493 start += size_256MB;
1494 remains -= size_256MB;
1495 }
1496 }
1497 }
1498
1499 static void __init init_kpte_bitmap(void)
1500 {
1501 unsigned long i;
1502
1503 for (i = 0; i < pall_ents; i++) {
1504 unsigned long phys_start, phys_end;
1505
1506 phys_start = pall[i].phys_addr;
1507 phys_end = phys_start + pall[i].reg_size;
1508
1509 mark_kpte_bitmap(phys_start, phys_end);
1510 }
1511 }
1512
1513 static void __init kernel_physical_mapping_init(void)
1514 {
1515 #ifdef CONFIG_DEBUG_PAGEALLOC
1516 unsigned long i, mem_alloced = 0UL;
1517
1518 for (i = 0; i < pall_ents; i++) {
1519 unsigned long phys_start, phys_end;
1520
1521 phys_start = pall[i].phys_addr;
1522 phys_end = phys_start + pall[i].reg_size;
1523
1524 mem_alloced += kernel_map_range(phys_start, phys_end,
1525 PAGE_KERNEL);
1526 }
1527
1528 printk("Allocated %ld bytes for kernel page tables.\n",
1529 mem_alloced);
1530
1531 kvmap_linear_patch[0] = 0x01000000; /* nop */
1532 flushi(&kvmap_linear_patch[0]);
1533
1534 __flush_tlb_all();
1535 #endif
1536 }
1537
1538 #ifdef CONFIG_DEBUG_PAGEALLOC
1539 void kernel_map_pages(struct page *page, int numpages, int enable)
1540 {
1541 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1542 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1543
1544 kernel_map_range(phys_start, phys_end,
1545 (enable ? PAGE_KERNEL : __pgprot(0)));
1546
1547 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1548 PAGE_OFFSET + phys_end);
1549
1550 /* we should perform an IPI and flush all tlbs,
1551 * but that can deadlock->flush only current cpu.
1552 */
1553 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1554 PAGE_OFFSET + phys_end);
1555 }
1556 #endif
1557
1558 unsigned long __init find_ecache_flush_span(unsigned long size)
1559 {
1560 int i;
1561
1562 for (i = 0; i < pavail_ents; i++) {
1563 if (pavail[i].reg_size >= size)
1564 return pavail[i].phys_addr;
1565 }
1566
1567 return ~0UL;
1568 }
1569
1570 static void __init tsb_phys_patch(void)
1571 {
1572 struct tsb_ldquad_phys_patch_entry *pquad;
1573 struct tsb_phys_patch_entry *p;
1574
1575 pquad = &__tsb_ldquad_phys_patch;
1576 while (pquad < &__tsb_ldquad_phys_patch_end) {
1577 unsigned long addr = pquad->addr;
1578
1579 if (tlb_type == hypervisor)
1580 *(unsigned int *) addr = pquad->sun4v_insn;
1581 else
1582 *(unsigned int *) addr = pquad->sun4u_insn;
1583 wmb();
1584 __asm__ __volatile__("flush %0"
1585 : /* no outputs */
1586 : "r" (addr));
1587
1588 pquad++;
1589 }
1590
1591 p = &__tsb_phys_patch;
1592 while (p < &__tsb_phys_patch_end) {
1593 unsigned long addr = p->addr;
1594
1595 *(unsigned int *) addr = p->insn;
1596 wmb();
1597 __asm__ __volatile__("flush %0"
1598 : /* no outputs */
1599 : "r" (addr));
1600
1601 p++;
1602 }
1603 }
1604
1605 /* Don't mark as init, we give this to the Hypervisor. */
1606 #ifndef CONFIG_DEBUG_PAGEALLOC
1607 #define NUM_KTSB_DESCR 2
1608 #else
1609 #define NUM_KTSB_DESCR 1
1610 #endif
1611 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1612 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1613
1614 static void __init sun4v_ktsb_init(void)
1615 {
1616 unsigned long ktsb_pa;
1617
1618 /* First KTSB for PAGE_SIZE mappings. */
1619 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1620
1621 switch (PAGE_SIZE) {
1622 case 8 * 1024:
1623 default:
1624 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1625 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1626 break;
1627
1628 case 64 * 1024:
1629 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1630 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1631 break;
1632
1633 case 512 * 1024:
1634 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1635 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1636 break;
1637
1638 case 4 * 1024 * 1024:
1639 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1640 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1641 break;
1642 };
1643
1644 ktsb_descr[0].assoc = 1;
1645 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1646 ktsb_descr[0].ctx_idx = 0;
1647 ktsb_descr[0].tsb_base = ktsb_pa;
1648 ktsb_descr[0].resv = 0;
1649
1650 #ifndef CONFIG_DEBUG_PAGEALLOC
1651 /* Second KTSB for 4MB/256MB mappings. */
1652 ktsb_pa = (kern_base +
1653 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1654
1655 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1656 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1657 HV_PGSZ_MASK_256MB);
1658 ktsb_descr[1].assoc = 1;
1659 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1660 ktsb_descr[1].ctx_idx = 0;
1661 ktsb_descr[1].tsb_base = ktsb_pa;
1662 ktsb_descr[1].resv = 0;
1663 #endif
1664 }
1665
1666 void __cpuinit sun4v_ktsb_register(void)
1667 {
1668 unsigned long pa, ret;
1669
1670 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1671
1672 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1673 if (ret != 0) {
1674 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1675 "errors with %lx\n", pa, ret);
1676 prom_halt();
1677 }
1678 }
1679
1680 /* paging_init() sets up the page tables */
1681
1682 extern void central_probe(void);
1683
1684 static unsigned long last_valid_pfn;
1685 pgd_t swapper_pg_dir[2048];
1686
1687 static void sun4u_pgprot_init(void);
1688 static void sun4v_pgprot_init(void);
1689
1690 /* Dummy function */
1691 void __init setup_per_cpu_areas(void)
1692 {
1693 }
1694
1695 void __init paging_init(void)
1696 {
1697 unsigned long end_pfn, shift, phys_base;
1698 unsigned long real_end, i;
1699
1700 /* These build time checkes make sure that the dcache_dirty_cpu()
1701 * page->flags usage will work.
1702 *
1703 * When a page gets marked as dcache-dirty, we store the
1704 * cpu number starting at bit 32 in the page->flags. Also,
1705 * functions like clear_dcache_dirty_cpu use the cpu mask
1706 * in 13-bit signed-immediate instruction fields.
1707 */
1708
1709 /*
1710 * Page flags must not reach into upper 32 bits that are used
1711 * for the cpu number
1712 */
1713 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1714
1715 /*
1716 * The bit fields placed in the high range must not reach below
1717 * the 32 bit boundary. Otherwise we cannot place the cpu field
1718 * at the 32 bit boundary.
1719 */
1720 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1721 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1722
1723 BUILD_BUG_ON(NR_CPUS > 4096);
1724
1725 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1726 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1727
1728 sstate_booting();
1729
1730 /* Invalidate both kernel TSBs. */
1731 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1732 #ifndef CONFIG_DEBUG_PAGEALLOC
1733 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1734 #endif
1735
1736 if (tlb_type == hypervisor)
1737 sun4v_pgprot_init();
1738 else
1739 sun4u_pgprot_init();
1740
1741 if (tlb_type == cheetah_plus ||
1742 tlb_type == hypervisor)
1743 tsb_phys_patch();
1744
1745 if (tlb_type == hypervisor) {
1746 sun4v_patch_tlb_handlers();
1747 sun4v_ktsb_init();
1748 }
1749
1750 lmb_init();
1751
1752 /* Find available physical memory...
1753 *
1754 * Read it twice in order to work around a bug in openfirmware.
1755 * The call to grab this table itself can cause openfirmware to
1756 * allocate memory, which in turn can take away some space from
1757 * the list of available memory. Reading it twice makes sure
1758 * we really do get the final value.
1759 */
1760 read_obp_translations();
1761 read_obp_memory("reg", &pall[0], &pall_ents);
1762 read_obp_memory("available", &pavail[0], &pavail_ents);
1763 read_obp_memory("available", &pavail[0], &pavail_ents);
1764
1765 phys_base = 0xffffffffffffffffUL;
1766 for (i = 0; i < pavail_ents; i++) {
1767 phys_base = min(phys_base, pavail[i].phys_addr);
1768 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1769 }
1770
1771 lmb_reserve(kern_base, kern_size);
1772
1773 find_ramdisk(phys_base);
1774
1775 lmb_enforce_memory_limit(cmdline_memory_size);
1776
1777 lmb_analyze();
1778 lmb_dump_all();
1779
1780 set_bit(0, mmu_context_bmap);
1781
1782 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1783
1784 real_end = (unsigned long)_end;
1785 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1786 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1787 num_kernel_image_mappings);
1788
1789 /* Set kernel pgd to upper alias so physical page computations
1790 * work.
1791 */
1792 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1793
1794 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1795
1796 /* Now can init the kernel/bad page tables. */
1797 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1798 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1799
1800 inherit_prom_mappings();
1801
1802 init_kpte_bitmap();
1803
1804 /* Ok, we can use our TLB miss and window trap handlers safely. */
1805 setup_tba();
1806
1807 __flush_tlb_all();
1808
1809 if (tlb_type == hypervisor)
1810 sun4v_ktsb_register();
1811
1812 /* We must setup the per-cpu areas before we pull in the
1813 * PROM and the MDESC. The code there fills in cpu and
1814 * other information into per-cpu data structures.
1815 */
1816 real_setup_per_cpu_areas();
1817
1818 prom_build_devicetree();
1819
1820 if (tlb_type == hypervisor)
1821 sun4v_mdesc_init();
1822
1823 /* Once the OF device tree and MDESC have been setup, we know
1824 * the list of possible cpus. Therefore we can allocate the
1825 * IRQ stacks.
1826 */
1827 for_each_possible_cpu(i) {
1828 /* XXX Use node local allocations... XXX */
1829 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1830 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1831 }
1832
1833 /* Setup bootmem... */
1834 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1835
1836 #ifndef CONFIG_NEED_MULTIPLE_NODES
1837 max_mapnr = last_valid_pfn;
1838 #endif
1839 kernel_physical_mapping_init();
1840
1841 {
1842 unsigned long max_zone_pfns[MAX_NR_ZONES];
1843
1844 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1845
1846 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1847
1848 free_area_init_nodes(max_zone_pfns);
1849 }
1850
1851 printk("Booting Linux...\n");
1852
1853 central_probe();
1854 cpu_probe();
1855 }
1856
1857 int __init page_in_phys_avail(unsigned long paddr)
1858 {
1859 int i;
1860
1861 paddr &= PAGE_MASK;
1862
1863 for (i = 0; i < pavail_ents; i++) {
1864 unsigned long start, end;
1865
1866 start = pavail[i].phys_addr;
1867 end = start + pavail[i].reg_size;
1868
1869 if (paddr >= start && paddr < end)
1870 return 1;
1871 }
1872 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1873 return 1;
1874 #ifdef CONFIG_BLK_DEV_INITRD
1875 if (paddr >= __pa(initrd_start) &&
1876 paddr < __pa(PAGE_ALIGN(initrd_end)))
1877 return 1;
1878 #endif
1879
1880 return 0;
1881 }
1882
1883 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1884 static int pavail_rescan_ents __initdata;
1885
1886 /* Certain OBP calls, such as fetching "available" properties, can
1887 * claim physical memory. So, along with initializing the valid
1888 * address bitmap, what we do here is refetch the physical available
1889 * memory list again, and make sure it provides at least as much
1890 * memory as 'pavail' does.
1891 */
1892 static void setup_valid_addr_bitmap_from_pavail(void)
1893 {
1894 int i;
1895
1896 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1897
1898 for (i = 0; i < pavail_ents; i++) {
1899 unsigned long old_start, old_end;
1900
1901 old_start = pavail[i].phys_addr;
1902 old_end = old_start + pavail[i].reg_size;
1903 while (old_start < old_end) {
1904 int n;
1905
1906 for (n = 0; n < pavail_rescan_ents; n++) {
1907 unsigned long new_start, new_end;
1908
1909 new_start = pavail_rescan[n].phys_addr;
1910 new_end = new_start +
1911 pavail_rescan[n].reg_size;
1912
1913 if (new_start <= old_start &&
1914 new_end >= (old_start + PAGE_SIZE)) {
1915 set_bit(old_start >> 22,
1916 sparc64_valid_addr_bitmap);
1917 goto do_next_page;
1918 }
1919 }
1920
1921 prom_printf("mem_init: Lost memory in pavail\n");
1922 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1923 pavail[i].phys_addr,
1924 pavail[i].reg_size);
1925 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1926 pavail_rescan[i].phys_addr,
1927 pavail_rescan[i].reg_size);
1928 prom_printf("mem_init: Cannot continue, aborting.\n");
1929 prom_halt();
1930
1931 do_next_page:
1932 old_start += PAGE_SIZE;
1933 }
1934 }
1935 }
1936
1937 void __init mem_init(void)
1938 {
1939 unsigned long codepages, datapages, initpages;
1940 unsigned long addr, last;
1941 int i;
1942
1943 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1944 i += 1;
1945 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1946 if (sparc64_valid_addr_bitmap == NULL) {
1947 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1948 prom_halt();
1949 }
1950 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1951
1952 addr = PAGE_OFFSET + kern_base;
1953 last = PAGE_ALIGN(kern_size) + addr;
1954 while (addr < last) {
1955 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1956 addr += PAGE_SIZE;
1957 }
1958
1959 setup_valid_addr_bitmap_from_pavail();
1960
1961 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1962
1963 #ifdef CONFIG_NEED_MULTIPLE_NODES
1964 for_each_online_node(i) {
1965 if (NODE_DATA(i)->node_spanned_pages != 0) {
1966 totalram_pages +=
1967 free_all_bootmem_node(NODE_DATA(i));
1968 }
1969 }
1970 #else
1971 totalram_pages = free_all_bootmem();
1972 #endif
1973
1974 /* We subtract one to account for the mem_map_zero page
1975 * allocated below.
1976 */
1977 totalram_pages -= 1;
1978 num_physpages = totalram_pages;
1979
1980 /*
1981 * Set up the zero page, mark it reserved, so that page count
1982 * is not manipulated when freeing the page from user ptes.
1983 */
1984 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1985 if (mem_map_zero == NULL) {
1986 prom_printf("paging_init: Cannot alloc zero page.\n");
1987 prom_halt();
1988 }
1989 SetPageReserved(mem_map_zero);
1990
1991 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1992 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1993 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1994 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1995 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1996 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1997
1998 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1999 nr_free_pages() << (PAGE_SHIFT-10),
2000 codepages << (PAGE_SHIFT-10),
2001 datapages << (PAGE_SHIFT-10),
2002 initpages << (PAGE_SHIFT-10),
2003 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2004
2005 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2006 cheetah_ecache_flush_init();
2007 }
2008
2009 void free_initmem(void)
2010 {
2011 unsigned long addr, initend;
2012 int do_free = 1;
2013
2014 /* If the physical memory maps were trimmed by kernel command
2015 * line options, don't even try freeing this initmem stuff up.
2016 * The kernel image could have been in the trimmed out region
2017 * and if so the freeing below will free invalid page structs.
2018 */
2019 if (cmdline_memory_size)
2020 do_free = 0;
2021
2022 /*
2023 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2024 */
2025 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2026 initend = (unsigned long)(__init_end) & PAGE_MASK;
2027 for (; addr < initend; addr += PAGE_SIZE) {
2028 unsigned long page;
2029 struct page *p;
2030
2031 page = (addr +
2032 ((unsigned long) __va(kern_base)) -
2033 ((unsigned long) KERNBASE));
2034 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2035
2036 if (do_free) {
2037 p = virt_to_page(page);
2038
2039 ClearPageReserved(p);
2040 init_page_count(p);
2041 __free_page(p);
2042 num_physpages++;
2043 totalram_pages++;
2044 }
2045 }
2046 }
2047
2048 #ifdef CONFIG_BLK_DEV_INITRD
2049 void free_initrd_mem(unsigned long start, unsigned long end)
2050 {
2051 if (start < end)
2052 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2053 for (; start < end; start += PAGE_SIZE) {
2054 struct page *p = virt_to_page(start);
2055
2056 ClearPageReserved(p);
2057 init_page_count(p);
2058 __free_page(p);
2059 num_physpages++;
2060 totalram_pages++;
2061 }
2062 }
2063 #endif
2064
2065 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2066 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2067 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2068 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2069 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2070 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2071
2072 pgprot_t PAGE_KERNEL __read_mostly;
2073 EXPORT_SYMBOL(PAGE_KERNEL);
2074
2075 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2076 pgprot_t PAGE_COPY __read_mostly;
2077
2078 pgprot_t PAGE_SHARED __read_mostly;
2079 EXPORT_SYMBOL(PAGE_SHARED);
2080
2081 pgprot_t PAGE_EXEC __read_mostly;
2082 unsigned long pg_iobits __read_mostly;
2083
2084 unsigned long _PAGE_IE __read_mostly;
2085 EXPORT_SYMBOL(_PAGE_IE);
2086
2087 unsigned long _PAGE_E __read_mostly;
2088 EXPORT_SYMBOL(_PAGE_E);
2089
2090 unsigned long _PAGE_CACHE __read_mostly;
2091 EXPORT_SYMBOL(_PAGE_CACHE);
2092
2093 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2094
2095 #define VMEMMAP_CHUNK_SHIFT 22
2096 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2097 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2098 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2099
2100 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2101 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2102 unsigned long vmemmap_table[VMEMMAP_SIZE];
2103
2104 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2105 {
2106 unsigned long vstart = (unsigned long) start;
2107 unsigned long vend = (unsigned long) (start + nr);
2108 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2109 unsigned long phys_end = (vend - VMEMMAP_BASE);
2110 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2111 unsigned long end = VMEMMAP_ALIGN(phys_end);
2112 unsigned long pte_base;
2113
2114 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2115 _PAGE_CP_4U | _PAGE_CV_4U |
2116 _PAGE_P_4U | _PAGE_W_4U);
2117 if (tlb_type == hypervisor)
2118 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2119 _PAGE_CP_4V | _PAGE_CV_4V |
2120 _PAGE_P_4V | _PAGE_W_4V);
2121
2122 for (; addr < end; addr += VMEMMAP_CHUNK) {
2123 unsigned long *vmem_pp =
2124 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2125 void *block;
2126
2127 if (!(*vmem_pp & _PAGE_VALID)) {
2128 block = vmemmap_alloc_block(1UL << 22, node);
2129 if (!block)
2130 return -ENOMEM;
2131
2132 *vmem_pp = pte_base | __pa(block);
2133
2134 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2135 "node=%d entry=%lu/%lu\n", start, block, nr,
2136 node,
2137 addr >> VMEMMAP_CHUNK_SHIFT,
2138 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2139 }
2140 }
2141 return 0;
2142 }
2143 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2144
2145 static void prot_init_common(unsigned long page_none,
2146 unsigned long page_shared,
2147 unsigned long page_copy,
2148 unsigned long page_readonly,
2149 unsigned long page_exec_bit)
2150 {
2151 PAGE_COPY = __pgprot(page_copy);
2152 PAGE_SHARED = __pgprot(page_shared);
2153
2154 protection_map[0x0] = __pgprot(page_none);
2155 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2156 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2157 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2158 protection_map[0x4] = __pgprot(page_readonly);
2159 protection_map[0x5] = __pgprot(page_readonly);
2160 protection_map[0x6] = __pgprot(page_copy);
2161 protection_map[0x7] = __pgprot(page_copy);
2162 protection_map[0x8] = __pgprot(page_none);
2163 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2164 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2165 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2166 protection_map[0xc] = __pgprot(page_readonly);
2167 protection_map[0xd] = __pgprot(page_readonly);
2168 protection_map[0xe] = __pgprot(page_shared);
2169 protection_map[0xf] = __pgprot(page_shared);
2170 }
2171
2172 static void __init sun4u_pgprot_init(void)
2173 {
2174 unsigned long page_none, page_shared, page_copy, page_readonly;
2175 unsigned long page_exec_bit;
2176
2177 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2178 _PAGE_CACHE_4U | _PAGE_P_4U |
2179 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2180 _PAGE_EXEC_4U);
2181 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2182 _PAGE_CACHE_4U | _PAGE_P_4U |
2183 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2184 _PAGE_EXEC_4U | _PAGE_L_4U);
2185 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2186
2187 _PAGE_IE = _PAGE_IE_4U;
2188 _PAGE_E = _PAGE_E_4U;
2189 _PAGE_CACHE = _PAGE_CACHE_4U;
2190
2191 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2192 __ACCESS_BITS_4U | _PAGE_E_4U);
2193
2194 #ifdef CONFIG_DEBUG_PAGEALLOC
2195 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2196 0xfffff80000000000;
2197 #else
2198 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2199 0xfffff80000000000;
2200 #endif
2201 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2202 _PAGE_P_4U | _PAGE_W_4U);
2203
2204 /* XXX Should use 256MB on Panther. XXX */
2205 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2206
2207 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2208 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2209 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2210 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2211
2212
2213 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2214 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2215 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2216 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2217 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2218 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2219 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2220
2221 page_exec_bit = _PAGE_EXEC_4U;
2222
2223 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2224 page_exec_bit);
2225 }
2226
2227 static void __init sun4v_pgprot_init(void)
2228 {
2229 unsigned long page_none, page_shared, page_copy, page_readonly;
2230 unsigned long page_exec_bit;
2231
2232 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2233 _PAGE_CACHE_4V | _PAGE_P_4V |
2234 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2235 _PAGE_EXEC_4V);
2236 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2237 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2238
2239 _PAGE_IE = _PAGE_IE_4V;
2240 _PAGE_E = _PAGE_E_4V;
2241 _PAGE_CACHE = _PAGE_CACHE_4V;
2242
2243 #ifdef CONFIG_DEBUG_PAGEALLOC
2244 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2245 0xfffff80000000000;
2246 #else
2247 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2248 0xfffff80000000000;
2249 #endif
2250 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2251 _PAGE_P_4V | _PAGE_W_4V);
2252
2253 #ifdef CONFIG_DEBUG_PAGEALLOC
2254 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2255 0xfffff80000000000;
2256 #else
2257 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2258 0xfffff80000000000;
2259 #endif
2260 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2261 _PAGE_P_4V | _PAGE_W_4V);
2262
2263 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2264 __ACCESS_BITS_4V | _PAGE_E_4V);
2265
2266 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2267 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2268 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2269 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2270 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2271
2272 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2273 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2274 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2275 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2276 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2277 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2278 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2279
2280 page_exec_bit = _PAGE_EXEC_4V;
2281
2282 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2283 page_exec_bit);
2284 }
2285
2286 unsigned long pte_sz_bits(unsigned long sz)
2287 {
2288 if (tlb_type == hypervisor) {
2289 switch (sz) {
2290 case 8 * 1024:
2291 default:
2292 return _PAGE_SZ8K_4V;
2293 case 64 * 1024:
2294 return _PAGE_SZ64K_4V;
2295 case 512 * 1024:
2296 return _PAGE_SZ512K_4V;
2297 case 4 * 1024 * 1024:
2298 return _PAGE_SZ4MB_4V;
2299 };
2300 } else {
2301 switch (sz) {
2302 case 8 * 1024:
2303 default:
2304 return _PAGE_SZ8K_4U;
2305 case 64 * 1024:
2306 return _PAGE_SZ64K_4U;
2307 case 512 * 1024:
2308 return _PAGE_SZ512K_4U;
2309 case 4 * 1024 * 1024:
2310 return _PAGE_SZ4MB_4U;
2311 };
2312 }
2313 }
2314
2315 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2316 {
2317 pte_t pte;
2318
2319 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2320 pte_val(pte) |= (((unsigned long)space) << 32);
2321 pte_val(pte) |= pte_sz_bits(page_size);
2322
2323 return pte;
2324 }
2325
2326 static unsigned long kern_large_tte(unsigned long paddr)
2327 {
2328 unsigned long val;
2329
2330 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2331 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2332 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2333 if (tlb_type == hypervisor)
2334 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2335 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2336 _PAGE_EXEC_4V | _PAGE_W_4V);
2337
2338 return val | paddr;
2339 }
2340
2341 /* If not locked, zap it. */
2342 void __flush_tlb_all(void)
2343 {
2344 unsigned long pstate;
2345 int i;
2346
2347 __asm__ __volatile__("flushw\n\t"
2348 "rdpr %%pstate, %0\n\t"
2349 "wrpr %0, %1, %%pstate"
2350 : "=r" (pstate)
2351 : "i" (PSTATE_IE));
2352 if (tlb_type == hypervisor) {
2353 sun4v_mmu_demap_all();
2354 } else if (tlb_type == spitfire) {
2355 for (i = 0; i < 64; i++) {
2356 /* Spitfire Errata #32 workaround */
2357 /* NOTE: Always runs on spitfire, so no
2358 * cheetah+ page size encodings.
2359 */
2360 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2361 "flush %%g6"
2362 : /* No outputs */
2363 : "r" (0),
2364 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2365
2366 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2367 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2368 "membar #Sync"
2369 : /* no outputs */
2370 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2371 spitfire_put_dtlb_data(i, 0x0UL);
2372 }
2373
2374 /* Spitfire Errata #32 workaround */
2375 /* NOTE: Always runs on spitfire, so no
2376 * cheetah+ page size encodings.
2377 */
2378 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2379 "flush %%g6"
2380 : /* No outputs */
2381 : "r" (0),
2382 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2383
2384 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2385 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2386 "membar #Sync"
2387 : /* no outputs */
2388 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2389 spitfire_put_itlb_data(i, 0x0UL);
2390 }
2391 }
2392 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2393 cheetah_flush_dtlb_all();
2394 cheetah_flush_itlb_all();
2395 }
2396 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2397 : : "r" (pstate));
2398 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree