drivers/pci/hotplug/shpchp.h

   1 /*
   2  * Standard Hot Plug Controller Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29 #ifndef _SHPCHP_H
  30 #define _SHPCHP_H
  31
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/pci_hotplug.h>
  35 #include <linux/delay.h>
  36 #include <linux/sched.h>        /* signal_pending(), struct timer_list */
  37 #include <linux/mutex.h>
  38
  39 #if !defined(MODULE)
  40         #define MY_NAME "shpchp"
  41 #else
  42         #define MY_NAME THIS_MODULE->name
  43 #endif
  44
  45 extern int shpchp_poll_mode;
  46 extern int shpchp_poll_time;
  47 extern int shpchp_debug;
  48 extern struct workqueue_struct *shpchp_wq;
  49
  50 #define dbg(format, arg...)                                             \
  51         do {                                                            \
  52                 if (shpchp_debug)                                       \
  53                         printk("%s: " format, MY_NAME , ## arg);        \
  54         } while (0)
  55 #define err(format, arg...)                                             \
  56         printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
  57 #define info(format, arg...)                                            \
  58         printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
  59 #define warn(format, arg...)                                            \
  60         printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
  61
  62 #define SLOT_NAME_SIZE 10
  63 struct slot {
  64         u8 bus;
  65         u8 device;
  66         u16 status;
  67         u32 number;
  68         u8 is_a_board;
  69         u8 state;
  70         u8 presence_save;
  71         u8 pwr_save;
  72         struct controller *ctrl;
  73         struct hpc_ops *hpc_ops;
  74         struct hotplug_slot *hotplug_slot;
  75         struct list_head        slot_list;
  76         struct delayed_work work;       /* work for button event */
  77         struct mutex lock;
  78         u8 hp_slot;
  79 };
  80
  81 struct event_info {
  82         u32 event_type;
  83         struct slot *p_slot;
  84         struct work_struct work;
  85 };
  86
  87 struct controller {
  88         struct mutex crit_sect;         /* critical section mutex */
  89         struct mutex cmd_lock;          /* command lock */
  90         int num_slots;                  /* Number of slots on ctlr */
  91         int slot_num_inc;               /* 1 or -1 */
  92         struct pci_dev *pci_dev;
  93         struct list_head slot_list;
  94         struct hpc_ops *hpc_ops;
  95         wait_queue_head_t queue;        /* sleep & wake process */
  96         u8 slot_device_offset;
  97         u32 pcix_misc2_reg;     /* for amd pogo errata */
  98         u32 first_slot;         /* First physical slot number */
  99         u32 cap_offset;
 100         unsigned long mmio_base;
 101         unsigned long mmio_size;
 102         void __iomem *creg;
 103         struct timer_list poll_timer;
 104 };
 105
 106 /* Define AMD SHPC ID  */
 107 #define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
 108 #define PCI_DEVICE_ID_AMD_POGO_7458     0x7458
 109
 110 /* AMD PCIX bridge registers */
 111 #define PCIX_MEM_BASE_LIMIT_OFFSET      0x1C
 112 #define PCIX_MISCII_OFFSET              0x48
 113 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET  0x80
 114
 115 /* AMD PCIX_MISCII masks and offsets */
 116 #define PERRNONFATALENABLE_MASK         0x00040000
 117 #define PERRFATALENABLE_MASK            0x00080000
 118 #define PERRFLOODENABLE_MASK            0x00100000
 119 #define SERRNONFATALENABLE_MASK         0x00200000
 120 #define SERRFATALENABLE_MASK            0x00400000
 121
 122 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
 123 #define PERR_OBSERVED_MASK              0x00000001
 124
 125 /* AMD PCIX_MEM_BASE_LIMIT masks */
 126 #define RSE_MASK                        0x40000000
 127
 128 #define INT_BUTTON_IGNORE               0
 129 #define INT_PRESENCE_ON                 1
 130 #define INT_PRESENCE_OFF                2
 131 #define INT_SWITCH_CLOSE                3
 132 #define INT_SWITCH_OPEN                 4
 133 #define INT_POWER_FAULT                 5
 134 #define INT_POWER_FAULT_CLEAR           6
 135 #define INT_BUTTON_PRESS                7
 136 #define INT_BUTTON_RELEASE              8
 137 #define INT_BUTTON_CANCEL               9
 138
 139 #define STATIC_STATE                    0
 140 #define BLINKINGON_STATE                1
 141 #define BLINKINGOFF_STATE               2
 142 #define POWERON_STATE                   3
 143 #define POWEROFF_STATE                  4
 144
 145 /* Error messages */
 146 #define INTERLOCK_OPEN                  0x00000002
 147 #define ADD_NOT_SUPPORTED               0x00000003
 148 #define CARD_FUNCTIONING                0x00000005
 149 #define ADAPTER_NOT_SAME                0x00000006
 150 #define NO_ADAPTER_PRESENT              0x00000009
 151 #define NOT_ENOUGH_RESOURCES            0x0000000B
 152 #define DEVICE_TYPE_NOT_SUPPORTED       0x0000000C
 153 #define WRONG_BUS_FREQUENCY             0x0000000D
 154 #define POWER_FAILURE                   0x0000000E
 155
 156 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
 157 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
 158 extern int shpchp_sysfs_enable_slot(struct slot *slot);
 159 extern int shpchp_sysfs_disable_slot(struct slot *slot);
 160 extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
 161 extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
 162 extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
 163 extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
 164 extern int shpchp_configure_device(struct slot *p_slot);
 165 extern int shpchp_unconfigure_device(struct slot *p_slot);
 166 extern void cleanup_slots(struct controller *ctrl);
 167 extern void shpchp_queue_pushbutton_work(struct work_struct *work);
 168 extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
 169
 170 static inline const char *slot_name(struct slot *slot)
 171 {
 172         return hotplug_slot_name(slot->hotplug_slot);
 173 }
 174
 175 #ifdef CONFIG_ACPI
 176 #include <linux/pci-acpi.h>
 177 static inline int get_hp_params_from_firmware(struct pci_dev *dev,
 178                                               struct hotplug_params *hpp)
 179 {
 180         if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
 181                         return -ENODEV;
 182         return 0;
 183 }
 184
 185 static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
 186 {
 187         u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
 188         return acpi_get_hp_hw_control_from_firmware(dev, flags);
 189 }
 190 #else
 191 #define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
 192 #define get_hp_hw_control_from_firmware(dev) (0)
 193 #endif
 194
 195 struct ctrl_reg {
 196         volatile u32 base_offset;
 197         volatile u32 slot_avail1;
 198         volatile u32 slot_avail2;
 199         volatile u32 slot_config;
 200         volatile u16 sec_bus_config;
 201         volatile u8  msi_ctrl;
 202         volatile u8  prog_interface;
 203         volatile u16 cmd;
 204         volatile u16 cmd_status;
 205         volatile u32 intr_loc;
 206         volatile u32 serr_loc;
 207         volatile u32 serr_intr_enable;
 208         volatile u32 slot1;
 209 } __attribute__ ((packed));
 210
 211 /* offsets to the controller registers based on the above structure layout */
 212 enum ctrl_offsets {
 213         BASE_OFFSET      = offsetof(struct ctrl_reg, base_offset),
 214         SLOT_AVAIL1      = offsetof(struct ctrl_reg, slot_avail1),
 215         SLOT_AVAIL2      = offsetof(struct ctrl_reg, slot_avail2),
 216         SLOT_CONFIG      = offsetof(struct ctrl_reg, slot_config),
 217         SEC_BUS_CONFIG   = offsetof(struct ctrl_reg, sec_bus_config),
 218         MSI_CTRL         = offsetof(struct ctrl_reg, msi_ctrl),
 219         PROG_INTERFACE   = offsetof(struct ctrl_reg, prog_interface),
 220         CMD              = offsetof(struct ctrl_reg, cmd),
 221         CMD_STATUS       = offsetof(struct ctrl_reg, cmd_status),
 222         INTR_LOC         = offsetof(struct ctrl_reg, intr_loc),
 223         SERR_LOC         = offsetof(struct ctrl_reg, serr_loc),
 224         SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
 225         SLOT1            = offsetof(struct ctrl_reg, slot1),
 226 };
 227
 228 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
 229 {
 230         return hotplug_slot->private;
 231 }
 232
 233 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
 234 {
 235         struct slot *slot;
 236
 237         list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
 238                 if (slot->device == device)
 239                         return slot;
 240         }
 241
 242         err("%s: slot (device=0x%x) not found\n", __func__, device);
 243         return NULL;
 244 }
 245
 246 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
 247 {
 248         u32 pcix_misc2_temp;
 249
 250         /* save MiscII register */
 251         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 252
 253         p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
 254
 255         /* clear SERR/PERR enable bits */
 256         pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 257         pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 258         pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 259         pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 260         pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 261         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 262 }
 263
 264 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
 265 {
 266         u32 pcix_misc2_temp;
 267         u32 pcix_bridge_errors_reg;
 268         u32 pcix_mem_base_reg;
 269         u8  perr_set;
 270         u8  rse_set;
 271
 272         /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
 273         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
 274         perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
 275         if (perr_set) {
 276                 dbg ("%s  W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set);
 277
 278                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
 279         }
 280
 281         /* write-one-to-clear Memory_Base_Limit[ RSE ] */
 282         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
 283         rse_set = pcix_mem_base_reg & RSE_MASK;
 284         if (rse_set) {
 285                 dbg ("%s  W1C: Memory_Base_Limit[ RSE ]\n",__func__ );
 286
 287                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
 288         }
 289         /* restore MiscII register */
 290         pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
 291
 292         if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
 293                 pcix_misc2_temp |= SERRFATALENABLE_MASK;
 294         else
 295                 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 296
 297         if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
 298                 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
 299         else
 300                 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 301
 302         if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
 303                 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
 304         else
 305                 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 306
 307         if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
 308                 pcix_misc2_temp |= PERRFATALENABLE_MASK;
 309         else
 310                 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 311
 312         if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
 313                 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
 314         else
 315                 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 316         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 317 }
 318
 319 struct hpc_ops {
 320         int (*power_on_slot)(struct slot *slot);
 321         int (*slot_enable)(struct slot *slot);
 322         int (*slot_disable)(struct slot *slot);
 323         int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
 324         int (*get_power_status)(struct slot *slot, u8 *status);
 325         int (*get_attention_status)(struct slot *slot, u8 *status);
 326         int (*set_attention_status)(struct slot *slot, u8 status);
 327         int (*get_latch_status)(struct slot *slot, u8 *status);
 328         int (*get_adapter_status)(struct slot *slot, u8 *status);
 329         int (*get_max_bus_speed)(struct slot *slot, enum pci_bus_speed *speed);
 330         int (*get_cur_bus_speed)(struct slot *slot, enum pci_bus_speed *speed);
 331         int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
 332         int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
 333         int (*get_prog_int)(struct slot *slot, u8 *prog_int);
 334         int (*query_power_fault)(struct slot *slot);
 335         void (*green_led_on)(struct slot *slot);
 336         void (*green_led_off)(struct slot *slot);
 337         void (*green_led_blink)(struct slot *slot);
 338         void (*release_ctlr)(struct controller *ctrl);
 339         int (*check_cmd_status)(struct controller *ctrl);
 340 };
 341
 342 #endif                          /* _SHPCHP_H */