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davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / board-dm646x-evm.c
blob5ba3cb2daaa0d71bc8a57a403ab2272b1e515232
1 /*
2 * TI DaVinci DM646X EVM board
3 *
4 * Derived from: arch/arm/mach-davinci/board-evm.c
5 * Copyright (C) 2006 Texas Instruments.
6 *
7 * (C) 2007-2008, MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 *
13 */
14
15 /**************************************************************************
16 * Included Files
17 **************************************************************************/
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/leds.h>
22 #include <linux/gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c/at24.h>
26 #include <linux/i2c/pcf857x.h>
27
28 #include <media/tvp514x.h>
29
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/clk.h>
34
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37
38 #include <mach/dm646x.h>
39 #include <mach/common.h>
40 #include <mach/serial.h>
41 #include <mach/i2c.h>
42 #include <mach/nand.h>
43 #include <mach/clock.h>
44 #include <mach/cdce949.h>
45
46 #include "clock.h"
47
48 #define NAND_BLOCK_SIZE SZ_128K
49
50 /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
51 * and U-Boot environment this avoids dependency on any particular combination
52 * of UBL, U-Boot or flashing tools etc.
53 */
54 static struct mtd_partition davinci_nand_partitions[] = {
55 {
56 /* UBL, U-Boot with environment */
57 .name = "bootloader",
58 .offset = MTDPART_OFS_APPEND,
59 .size = 16 * NAND_BLOCK_SIZE,
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 }, {
62 .name = "kernel",
63 .offset = MTDPART_OFS_APPEND,
64 .size = SZ_4M,
65 .mask_flags = 0,
66 }, {
67 .name = "filesystem",
68 .offset = MTDPART_OFS_APPEND,
69 .size = MTDPART_SIZ_FULL,
70 .mask_flags = 0,
71 }
72 };
73
74 static struct davinci_nand_pdata davinci_nand_data = {
75 .mask_cle = 0x80000,
76 .mask_ale = 0x40000,
77 .parts = davinci_nand_partitions,
78 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
79 .ecc_mode = NAND_ECC_HW,
80 .options = 0,
81 };
82
83 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
84 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
85
86 static struct resource davinci_nand_resources[] = {
87 {
88 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
89 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
90 .flags = IORESOURCE_MEM,
91 }, {
92 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
93 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 };
97
98 static struct platform_device davinci_nand_device = {
99 .name = "davinci_nand",
100 .id = 0,
101
102 .num_resources = ARRAY_SIZE(davinci_nand_resources),
103 .resource = davinci_nand_resources,
104
105 .dev = {
106 .platform_data = &davinci_nand_data,
107 },
108 };
109
110 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
111 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
112 #define HAS_ATA 1
113 #else
114 #define HAS_ATA 0
115 #endif
116
117 /* CPLD Register 0 bits to control ATA */
118 #define DM646X_EVM_ATA_RST BIT(0)
119 #define DM646X_EVM_ATA_PWD BIT(1)
120
121 /* CPLD Register 0 Client: used for I/O Control */
122 static int cpld_reg0_probe(struct i2c_client *client,
123 const struct i2c_device_id *id)
124 {
125 if (HAS_ATA) {
126 u8 data;
127 struct i2c_msg msg[2] = {
128 {
129 .addr = client->addr,
130 .flags = I2C_M_RD,
131 .len = 1,
132 .buf = &data,
133 },
134 {
135 .addr = client->addr,
136 .flags = 0,
137 .len = 1,
138 .buf = &data,
139 },
140 };
141
142 /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
143 i2c_transfer(client->adapter, msg, 1);
144 data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
145 i2c_transfer(client->adapter, msg + 1, 1);
146 }
147
148 return 0;
149 }
150
151 static const struct i2c_device_id cpld_reg_ids[] = {
152 { "cpld_reg0", 0, },
153 { },
154 };
155
156 static struct i2c_driver dm6467evm_cpld_driver = {
157 .driver.name = "cpld_reg0",
158 .id_table = cpld_reg_ids,
159 .probe = cpld_reg0_probe,
160 };
161
162 /* LEDS */
163
164 static struct gpio_led evm_leds[] = {
165 { .name = "DS1", .active_low = 1, },
166 { .name = "DS2", .active_low = 1, },
167 { .name = "DS3", .active_low = 1, },
168 { .name = "DS4", .active_low = 1, },
169 };
170
171 static const struct gpio_led_platform_data evm_led_data = {
172 .num_leds = ARRAY_SIZE(evm_leds),
173 .leds = evm_leds,
174 };
175
176 static struct platform_device *evm_led_dev;
177
178 static int evm_led_setup(struct i2c_client *client, int gpio,
179 unsigned int ngpio, void *c)
180 {
181 struct gpio_led *leds = evm_leds;
182 int status;
183
184 while (ngpio--) {
185 leds->gpio = gpio++;
186 leds++;
187 };
188
189 evm_led_dev = platform_device_alloc("leds-gpio", 0);
190 platform_device_add_data(evm_led_dev, &evm_led_data,
191 sizeof(evm_led_data));
192
193 evm_led_dev->dev.parent = &client->dev;
194 status = platform_device_add(evm_led_dev);
195 if (status < 0) {
196 platform_device_put(evm_led_dev);
197 evm_led_dev = NULL;
198 }
199 return status;
200 }
201
202 static int evm_led_teardown(struct i2c_client *client, int gpio,
203 unsigned ngpio, void *c)
204 {
205 if (evm_led_dev) {
206 platform_device_unregister(evm_led_dev);
207 evm_led_dev = NULL;
208 }
209 return 0;
210 }
211
212 static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
213
214 static int evm_sw_setup(struct i2c_client *client, int gpio,
215 unsigned ngpio, void *c)
216 {
217 int status;
218 int i;
219 char label[10];
220
221 for (i = 0; i < 4; ++i) {
222 snprintf(label, 10, "user_sw%d", i);
223 status = gpio_request(gpio, label);
224 if (status)
225 goto out_free;
226 evm_sw_gpio[i] = gpio++;
227
228 status = gpio_direction_input(evm_sw_gpio[i]);
229 if (status) {
230 gpio_free(evm_sw_gpio[i]);
231 evm_sw_gpio[i] = -EINVAL;
232 goto out_free;
233 }
234
235 status = gpio_export(evm_sw_gpio[i], 0);
236 if (status) {
237 gpio_free(evm_sw_gpio[i]);
238 evm_sw_gpio[i] = -EINVAL;
239 goto out_free;
240 }
241 }
242 return status;
243 out_free:
244 for (i = 0; i < 4; ++i) {
245 if (evm_sw_gpio[i] != -EINVAL) {
246 gpio_free(evm_sw_gpio[i]);
247 evm_sw_gpio[i] = -EINVAL;
248 }
249 }
250 return status;
251 }
252
253 static int evm_sw_teardown(struct i2c_client *client, int gpio,
254 unsigned ngpio, void *c)
255 {
256 int i;
257
258 for (i = 0; i < 4; ++i) {
259 if (evm_sw_gpio[i] != -EINVAL) {
260 gpio_unexport(evm_sw_gpio[i]);
261 gpio_free(evm_sw_gpio[i]);
262 evm_sw_gpio[i] = -EINVAL;
263 }
264 }
265 return 0;
266 }
267
268 static int evm_pcf_setup(struct i2c_client *client, int gpio,
269 unsigned int ngpio, void *c)
270 {
271 int status;
272
273 if (ngpio < 8)
274 return -EINVAL;
275
276 status = evm_sw_setup(client, gpio, 4, c);
277 if (status)
278 return status;
279
280 return evm_led_setup(client, gpio+4, 4, c);
281 }
282
283 static int evm_pcf_teardown(struct i2c_client *client, int gpio,
284 unsigned int ngpio, void *c)
285 {
286 BUG_ON(ngpio < 8);
287
288 evm_sw_teardown(client, gpio, 4, c);
289 evm_led_teardown(client, gpio+4, 4, c);
290
291 return 0;
292 }
293
294 static struct pcf857x_platform_data pcf_data = {
295 .gpio_base = DAVINCI_N_GPIO+1,
296 .setup = evm_pcf_setup,
297 .teardown = evm_pcf_teardown,
298 };
299
300 /* Most of this EEPROM is unused, but U-Boot uses some data:
301 * - 0x7f00, 6 bytes Ethernet Address
302 * - ... newer boards may have more
303 */
304
305 static struct at24_platform_data eeprom_info = {
306 .byte_len = (256*1024) / 8,
307 .page_size = 64,
308 .flags = AT24_FLAG_ADDR16,
309 .setup = davinci_get_mac_addr,
310 .context = (void *)0x7f00,
311 };
312
313 static u8 dm646x_iis_serializer_direction[] = {
314 TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
315 };
316
317 static u8 dm646x_dit_serializer_direction[] = {
318 TX_MODE,
319 };
320
321 static struct snd_platform_data dm646x_evm_snd_data[] = {
322 {
323 .tx_dma_offset = 0x400,
324 .rx_dma_offset = 0x400,
325 .op_mode = DAVINCI_MCASP_IIS_MODE,
326 .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
327 .tdm_slots = 2,
328 .serial_dir = dm646x_iis_serializer_direction,
329 .eventq_no = EVENTQ_0,
330 },
331 {
332 .tx_dma_offset = 0x400,
333 .rx_dma_offset = 0,
334 .op_mode = DAVINCI_MCASP_DIT_MODE,
335 .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
336 .tdm_slots = 32,
337 .serial_dir = dm646x_dit_serializer_direction,
338 .eventq_no = EVENTQ_0,
339 },
340 };
341
342 static struct i2c_client *cpld_client;
343
344 static int cpld_video_probe(struct i2c_client *client,
345 const struct i2c_device_id *id)
346 {
347 cpld_client = client;
348 return 0;
349 }
350
351 static int __devexit cpld_video_remove(struct i2c_client *client)
352 {
353 cpld_client = NULL;
354 return 0;
355 }
356
357 static const struct i2c_device_id cpld_video_id[] = {
358 { "cpld_video", 0 },
359 { }
360 };
361
362 static struct i2c_driver cpld_video_driver = {
363 .driver = {
364 .name = "cpld_video",
365 },
366 .probe = cpld_video_probe,
367 .remove = cpld_video_remove,
368 .id_table = cpld_video_id,
369 };
370
371 static void evm_init_cpld(void)
372 {
373 i2c_add_driver(&cpld_video_driver);
374 }
375
376 static struct i2c_board_info __initdata i2c_info[] = {
377 {
378 I2C_BOARD_INFO("24c256", 0x50),
379 .platform_data = &eeprom_info,
380 },
381 {
382 I2C_BOARD_INFO("pcf8574a", 0x38),
383 .platform_data = &pcf_data,
384 },
385 {
386 I2C_BOARD_INFO("cpld_reg0", 0x3a),
387 },
388 {
389 I2C_BOARD_INFO("tlv320aic33", 0x18),
390 },
391 {
392 I2C_BOARD_INFO("cpld_video", 0x3b),
393 },
394 {
395 I2C_BOARD_INFO("cdce949", 0x6c),
396 },
397 };
398
399 static struct davinci_i2c_platform_data i2c_pdata = {
400 .bus_freq = 100 /* kHz */,
401 .bus_delay = 0 /* usec */,
402 };
403
404 #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
405 #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
406 #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
407 #define VCH2CLK_SYSCLK8 (BIT(9))
408 #define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
409 #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
410 #define VCH3CLK_SYSCLK8 (BIT(13))
411 #define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
412
413 #define VIDCH2CLK (BIT(10))
414 #define VIDCH3CLK (BIT(11))
415 #define VIDCH1CLK (BIT(4))
416 #define TVP7002_INPUT (BIT(4))
417 #define TVP5147_INPUT (~BIT(4))
418 #define VPIF_INPUT_ONE_CHANNEL (BIT(5))
419 #define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
420 #define TVP5147_CH0 "tvp514x-0"
421 #define TVP5147_CH1 "tvp514x-1"
422
423 static void __iomem *vpif_vidclkctl_reg;
424 static void __iomem *vpif_vsclkdis_reg;
425 /* spin lock for updating above registers */
426 static spinlock_t vpif_reg_lock;
427
428 static int set_vpif_clock(int mux_mode, int hd)
429 {
430 unsigned long flags;
431 unsigned int value;
432 int val = 0;
433 int err = 0;
434
435 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
436 return -ENXIO;
437
438 /* disable the clock */
439 spin_lock_irqsave(&vpif_reg_lock, flags);
440 value = __raw_readl(vpif_vsclkdis_reg);
441 value |= (VIDCH3CLK | VIDCH2CLK);
442 __raw_writel(value, vpif_vsclkdis_reg);
443 spin_unlock_irqrestore(&vpif_reg_lock, flags);
444
445 val = i2c_smbus_read_byte(cpld_client);
446 if (val < 0)
447 return val;
448
449 if (mux_mode == 1)
450 val &= ~0x40;
451 else
452 val |= 0x40;
453
454 err = i2c_smbus_write_byte(cpld_client, val);
455 if (err)
456 return err;
457
458 value = __raw_readl(vpif_vidclkctl_reg);
459 value &= ~(VCH2CLK_MASK);
460 value &= ~(VCH3CLK_MASK);
461
462 if (hd >= 1)
463 value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
464 else
465 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
466
467 __raw_writel(value, vpif_vidclkctl_reg);
468
469 spin_lock_irqsave(&vpif_reg_lock, flags);
470 value = __raw_readl(vpif_vsclkdis_reg);
471 /* enable the clock */
472 value &= ~(VIDCH3CLK | VIDCH2CLK);
473 __raw_writel(value, vpif_vsclkdis_reg);
474 spin_unlock_irqrestore(&vpif_reg_lock, flags);
475
476 return 0;
477 }
478
479 static struct vpif_subdev_info dm646x_vpif_subdev[] = {
480 {
481 .name = "adv7343",
482 .board_info = {
483 I2C_BOARD_INFO("adv7343", 0x2a),
484 },
485 },
486 {
487 .name = "ths7303",
488 .board_info = {
489 I2C_BOARD_INFO("ths7303", 0x2c),
490 },
491 },
492 };
493
494 static const char *output[] = {
495 "Composite",
496 "Component",
497 "S-Video",
498 };
499
500 static struct vpif_display_config dm646x_vpif_display_config = {
501 .set_clock = set_vpif_clock,
502 .subdevinfo = dm646x_vpif_subdev,
503 .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
504 .output = output,
505 .output_count = ARRAY_SIZE(output),
506 .card_name = "DM646x EVM",
507 };
508
509 /**
510 * setup_vpif_input_path()
511 * @channel: channel id (0 - CH0, 1 - CH1)
512 * @sub_dev_name: ptr sub device name
513 *
514 * This will set vpif input to capture data from tvp514x or
515 * tvp7002.
516 */
517 static int setup_vpif_input_path(int channel, const char *sub_dev_name)
518 {
519 int err = 0;
520 int val;
521
522 /* for channel 1, we don't do anything */
523 if (channel != 0)
524 return 0;
525
526 if (!cpld_client)
527 return -ENXIO;
528
529 val = i2c_smbus_read_byte(cpld_client);
530 if (val < 0)
531 return val;
532
533 if (!strcmp(sub_dev_name, TVP5147_CH0) ||
534 !strcmp(sub_dev_name, TVP5147_CH1))
535 val &= TVP5147_INPUT;
536 else
537 val |= TVP7002_INPUT;
538
539 err = i2c_smbus_write_byte(cpld_client, val);
540 if (err)
541 return err;
542 return 0;
543 }
544
545 /**
546 * setup_vpif_input_channel_mode()
547 * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
548 *
549 * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
550 */
551 static int setup_vpif_input_channel_mode(int mux_mode)
552 {
553 unsigned long flags;
554 int err = 0;
555 int val;
556 u32 value;
557
558 if (!vpif_vsclkdis_reg || !cpld_client)
559 return -ENXIO;
560
561 val = i2c_smbus_read_byte(cpld_client);
562 if (val < 0)
563 return val;
564
565 spin_lock_irqsave(&vpif_reg_lock, flags);
566 value = __raw_readl(vpif_vsclkdis_reg);
567 if (mux_mode) {
568 val &= VPIF_INPUT_TWO_CHANNEL;
569 value |= VIDCH1CLK;
570 } else {
571 val |= VPIF_INPUT_ONE_CHANNEL;
572 value &= ~VIDCH1CLK;
573 }
574 __raw_writel(value, vpif_vsclkdis_reg);
575 spin_unlock_irqrestore(&vpif_reg_lock, flags);
576
577 err = i2c_smbus_write_byte(cpld_client, val);
578 if (err)
579 return err;
580
581 return 0;
582 }
583
584 static struct tvp514x_platform_data tvp5146_pdata = {
585 .clk_polarity = 0,
586 .hs_polarity = 1,
587 .vs_polarity = 1
588 };
589
590 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
591
592 static struct vpif_subdev_info vpif_capture_sdev_info[] = {
593 {
594 .name = TVP5147_CH0,
595 .board_info = {
596 I2C_BOARD_INFO("tvp5146", 0x5d),
597 .platform_data = &tvp5146_pdata,
598 },
599 .input = INPUT_CVBS_VI2B,
600 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
601 .can_route = 1,
602 .vpif_if = {
603 .if_type = VPIF_IF_BT656,
604 .hd_pol = 1,
605 .vd_pol = 1,
606 .fid_pol = 0,
607 },
608 },
609 {
610 .name = TVP5147_CH1,
611 .board_info = {
612 I2C_BOARD_INFO("tvp5146", 0x5c),
613 .platform_data = &tvp5146_pdata,
614 },
615 .input = INPUT_SVIDEO_VI2C_VI1C,
616 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
617 .can_route = 1,
618 .vpif_if = {
619 .if_type = VPIF_IF_BT656,
620 .hd_pol = 1,
621 .vd_pol = 1,
622 .fid_pol = 0,
623 },
624 },
625 };
626
627 static const struct vpif_input dm6467_ch0_inputs[] = {
628 {
629 .input = {
630 .index = 0,
631 .name = "Composite",
632 .type = V4L2_INPUT_TYPE_CAMERA,
633 .std = TVP514X_STD_ALL,
634 },
635 .subdev_name = TVP5147_CH0,
636 },
637 };
638
639 static const struct vpif_input dm6467_ch1_inputs[] = {
640 {
641 .input = {
642 .index = 0,
643 .name = "S-Video",
644 .type = V4L2_INPUT_TYPE_CAMERA,
645 .std = TVP514X_STD_ALL,
646 },
647 .subdev_name = TVP5147_CH1,
648 },
649 };
650
651 static struct vpif_capture_config dm646x_vpif_capture_cfg = {
652 .setup_input_path = setup_vpif_input_path,
653 .setup_input_channel_mode = setup_vpif_input_channel_mode,
654 .subdev_info = vpif_capture_sdev_info,
655 .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
656 .chan_config[0] = {
657 .inputs = dm6467_ch0_inputs,
658 .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
659 },
660 .chan_config[1] = {
661 .inputs = dm6467_ch1_inputs,
662 .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
663 },
664 };
665
666 static void __init evm_init_video(void)
667 {
668 vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
669 vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
670 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
671 pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
672 return;
673 }
674 spin_lock_init(&vpif_reg_lock);
675
676 dm646x_setup_vpif(&dm646x_vpif_display_config,
677 &dm646x_vpif_capture_cfg);
678 }
679
680 static void __init evm_init_i2c(void)
681 {
682 davinci_init_i2c(&i2c_pdata);
683 i2c_add_driver(&dm6467evm_cpld_driver);
684 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
685 evm_init_cpld();
686 evm_init_video();
687 }
688
689 #define CDCE949_XIN_RATE 27000000
690
691 /* CDCE949 support - "lpsc" field is overridden to work as clock number */
692 static struct clk cdce_clk_in = {
693 .name = "cdce_xin",
694 .rate = CDCE949_XIN_RATE,
695 };
696
697 static struct clk_lookup cdce_clks[] = {
698 CLK(NULL, "xin", &cdce_clk_in),
699 CLK(NULL, NULL, NULL),
700 };
701
702 static void __init cdce_clk_init(void)
703 {
704 struct clk_lookup *c;
705 struct clk *clk;
706
707 for (c = cdce_clks; c->clk; c++) {
708 clk = c->clk;
709 clkdev_add(c);
710 clk_register(clk);
711 }
712 }
713
714 static void __init davinci_map_io(void)
715 {
716 dm646x_init();
717 cdce_clk_init();
718 }
719
720 static struct davinci_uart_config uart_config __initdata = {
721 .enabled_uarts = (1 << 0),
722 };
723
724 #define DM646X_EVM_PHY_MASK (0x2)
725 #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
726
727 static __init void evm_init(void)
728 {
729 struct davinci_soc_info *soc_info = &davinci_soc_info;
730
731 evm_init_i2c();
732 davinci_serial_init(&uart_config);
733 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
734 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
735
736 platform_device_register(&davinci_nand_device);
737
738 if (HAS_ATA)
739 dm646x_init_ide();
740
741 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
742 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
743 }
744
745 static __init void davinci_dm646x_evm_irq_init(void)
746 {
747 davinci_irq_init();
748 }
749
750 #define DM646X_EVM_REF_FREQ 27000000
751 #define DM6467T_EVM_REF_FREQ 33000000
752
753 void __init dm646x_board_setup_refclk(struct clk *clk)
754 {
755 if (machine_is_davinci_dm6467tevm())
756 clk->rate = DM6467T_EVM_REF_FREQ;
757 else
758 clk->rate = DM646X_EVM_REF_FREQ;
759 }
760
761 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
762 .phys_io = IO_PHYS,
763 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
764 .boot_params = (0x80000100),
765 .map_io = davinci_map_io,
766 .init_irq = davinci_dm646x_evm_irq_init,
767 .timer = &davinci_timer,
768 .init_machine = evm_init,
769 MACHINE_END
770
771 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
772 .phys_io = IO_PHYS,
773 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
774 .boot_params = (0x80000100),
775 .map_io = davinci_map_io,
776 .init_irq = davinci_dm646x_evm_irq_init,
777 .timer = &davinci_timer,
778 .init_machine = evm_init,
779 MACHINE_END
780
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree