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ASoC: Warn rather than set a silly constraint when we can't do symmetry
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blob7841a8f69998d5351bad0745350edcfa65972208
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <asm/io.h>
52 #include <asm/byteorder.h>
53 #include <asm/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0 0
61 #define BAR_2 2
62
63 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
64 #define TG3_VLAN_TAG_USED 1
65 #else
66 #define TG3_VLAN_TAG_USED 0
67 #endif
68
69 #include "tg3.h"
70
71 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MAJ_NUM 3
73 #define TG3_MIN_NUM 116
74 #define DRV_MODULE_VERSION \
75 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
76 #define DRV_MODULE_RELDATE "December 3, 2010"
77
78 #define TG3_DEF_MAC_MODE 0
79 #define TG3_DEF_RX_MODE 0
80 #define TG3_DEF_TX_MODE 0
81 #define TG3_DEF_MSG_ENABLE \
82 (NETIF_MSG_DRV | \
83 NETIF_MSG_PROBE | \
84 NETIF_MSG_LINK | \
85 NETIF_MSG_TIMER | \
86 NETIF_MSG_IFDOWN | \
87 NETIF_MSG_IFUP | \
88 NETIF_MSG_RX_ERR | \
89 NETIF_MSG_TX_ERR)
90
91 /* length of time before we decide the hardware is borked,
92 * and dev->tx_timeout() should be called to fix the problem
93 */
94 #define TG3_TX_TIMEOUT (5 * HZ)
95
96 /* hardware minimum and maximum for a single frame's data payload */
97 #define TG3_MIN_MTU 60
98 #define TG3_MAX_MTU(tp) \
99 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100
101 /* These numbers seem to be hard coded in the NIC firmware somehow.
102 * You can't change the ring sizes, but you can change where you place
103 * them in the NIC onboard memory.
104 */
105 #define TG3_RX_STD_RING_SIZE(tp) \
106 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
108 RX_STD_MAX_SIZE_5717 : 512)
109 #define TG3_DEF_RX_RING_PENDING 200
110 #define TG3_RX_JMB_RING_SIZE(tp) \
111 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
113 1024 : 256)
114 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
115 #define TG3_RSS_INDIR_TBL_SIZE 128
116
117 /* Do not place this n-ring entries value into the tp struct itself,
118 * we really want to expose these constants to GCC so that modulo et
119 * al. operations are done with shifts and masks instead of with
120 * hw multiply/modulo instructions. Another solution would be to
121 * replace things like '% foo' with '& (foo - 1)'.
122 */
123
124 #define TG3_TX_RING_SIZE 512
125 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
126
127 #define TG3_RX_STD_RING_BYTES(tp) \
128 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
129 #define TG3_RX_JMB_RING_BYTES(tp) \
130 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
131 #define TG3_RX_RCB_RING_BYTES(tp) \
132 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
133 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
134 TG3_TX_RING_SIZE)
135 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
136
137 #define TG3_RX_DMA_ALIGN 16
138 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
139
140 #define TG3_DMA_BYTE_ENAB 64
141
142 #define TG3_RX_STD_DMA_SZ 1536
143 #define TG3_RX_JMB_DMA_SZ 9046
144
145 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
146
147 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
148 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
149
150 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
151 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
152
153 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
154 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
155
156 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
157 * that are at least dword aligned when used in PCIX mode. The driver
158 * works around this bug by double copying the packet. This workaround
159 * is built into the normal double copy length check for efficiency.
160 *
161 * However, the double copy is only necessary on those architectures
162 * where unaligned memory accesses are inefficient. For those architectures
163 * where unaligned memory accesses incur little penalty, we can reintegrate
164 * the 5701 in the normal rx path. Doing so saves a device structure
165 * dereference by hardcoding the double copy threshold in place.
166 */
167 #define TG3_RX_COPY_THRESHOLD 256
168 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
169 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
170 #else
171 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
172 #endif
173
174 /* minimum number of free TX descriptors required to wake up TX process */
175 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
176
177 #define TG3_RAW_IP_ALIGN 2
178
179 /* number of ETHTOOL_GSTATS u64's */
180 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
181
182 #define TG3_NUM_TEST 6
183
184 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
185
186 #define FIRMWARE_TG3 "tigon/tg3.bin"
187 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
188 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
189
190 static char version[] __devinitdata =
191 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
192
193 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
194 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
195 MODULE_LICENSE("GPL");
196 MODULE_VERSION(DRV_MODULE_VERSION);
197 MODULE_FIRMWARE(FIRMWARE_TG3);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
199 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
200
201 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
202 module_param(tg3_debug, int, 0);
203 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
204
205 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
279 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
283 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
284 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
285 {}
286 };
287
288 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
289
290 static const struct {
291 const char string[ETH_GSTRING_LEN];
292 } ethtool_stats_keys[TG3_NUM_STATS] = {
293 { "rx_octets" },
294 { "rx_fragments" },
295 { "rx_ucast_packets" },
296 { "rx_mcast_packets" },
297 { "rx_bcast_packets" },
298 { "rx_fcs_errors" },
299 { "rx_align_errors" },
300 { "rx_xon_pause_rcvd" },
301 { "rx_xoff_pause_rcvd" },
302 { "rx_mac_ctrl_rcvd" },
303 { "rx_xoff_entered" },
304 { "rx_frame_too_long_errors" },
305 { "rx_jabbers" },
306 { "rx_undersize_packets" },
307 { "rx_in_length_errors" },
308 { "rx_out_length_errors" },
309 { "rx_64_or_less_octet_packets" },
310 { "rx_65_to_127_octet_packets" },
311 { "rx_128_to_255_octet_packets" },
312 { "rx_256_to_511_octet_packets" },
313 { "rx_512_to_1023_octet_packets" },
314 { "rx_1024_to_1522_octet_packets" },
315 { "rx_1523_to_2047_octet_packets" },
316 { "rx_2048_to_4095_octet_packets" },
317 { "rx_4096_to_8191_octet_packets" },
318 { "rx_8192_to_9022_octet_packets" },
319
320 { "tx_octets" },
321 { "tx_collisions" },
322
323 { "tx_xon_sent" },
324 { "tx_xoff_sent" },
325 { "tx_flow_control" },
326 { "tx_mac_errors" },
327 { "tx_single_collisions" },
328 { "tx_mult_collisions" },
329 { "tx_deferred" },
330 { "tx_excessive_collisions" },
331 { "tx_late_collisions" },
332 { "tx_collide_2times" },
333 { "tx_collide_3times" },
334 { "tx_collide_4times" },
335 { "tx_collide_5times" },
336 { "tx_collide_6times" },
337 { "tx_collide_7times" },
338 { "tx_collide_8times" },
339 { "tx_collide_9times" },
340 { "tx_collide_10times" },
341 { "tx_collide_11times" },
342 { "tx_collide_12times" },
343 { "tx_collide_13times" },
344 { "tx_collide_14times" },
345 { "tx_collide_15times" },
346 { "tx_ucast_packets" },
347 { "tx_mcast_packets" },
348 { "tx_bcast_packets" },
349 { "tx_carrier_sense_errors" },
350 { "tx_discards" },
351 { "tx_errors" },
352
353 { "dma_writeq_full" },
354 { "dma_write_prioq_full" },
355 { "rxbds_empty" },
356 { "rx_discards" },
357 { "rx_errors" },
358 { "rx_threshold_hit" },
359
360 { "dma_readq_full" },
361 { "dma_read_prioq_full" },
362 { "tx_comp_queue_full" },
363
364 { "ring_set_send_prod_index" },
365 { "ring_status_update" },
366 { "nic_irqs" },
367 { "nic_avoided_irqs" },
368 { "nic_tx_threshold_hit" }
369 };
370
371 static const struct {
372 const char string[ETH_GSTRING_LEN];
373 } ethtool_test_keys[TG3_NUM_TEST] = {
374 { "nvram test (online) " },
375 { "link test (online) " },
376 { "register test (offline)" },
377 { "memory test (offline)" },
378 { "loopback test (offline)" },
379 { "interrupt test (offline)" },
380 };
381
382 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
383 {
384 writel(val, tp->regs + off);
385 }
386
387 static u32 tg3_read32(struct tg3 *tp, u32 off)
388 {
389 return readl(tp->regs + off);
390 }
391
392 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
393 {
394 writel(val, tp->aperegs + off);
395 }
396
397 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
398 {
399 return readl(tp->aperegs + off);
400 }
401
402 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
403 {
404 unsigned long flags;
405
406 spin_lock_irqsave(&tp->indirect_lock, flags);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
408 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
409 spin_unlock_irqrestore(&tp->indirect_lock, flags);
410 }
411
412 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
413 {
414 writel(val, tp->regs + off);
415 readl(tp->regs + off);
416 }
417
418 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
419 {
420 unsigned long flags;
421 u32 val;
422
423 spin_lock_irqsave(&tp->indirect_lock, flags);
424 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
425 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
426 spin_unlock_irqrestore(&tp->indirect_lock, flags);
427 return val;
428 }
429
430 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
431 {
432 unsigned long flags;
433
434 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
435 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
436 TG3_64BIT_REG_LOW, val);
437 return;
438 }
439 if (off == TG3_RX_STD_PROD_IDX_REG) {
440 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
441 TG3_64BIT_REG_LOW, val);
442 return;
443 }
444
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
449
450 /* In indirect mode when disabling interrupts, we also need
451 * to clear the interrupt bit in the GRC local ctrl register.
452 */
453 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
454 (val == 0x1)) {
455 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
456 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
457 }
458 }
459
460 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
461 {
462 unsigned long flags;
463 u32 val;
464
465 spin_lock_irqsave(&tp->indirect_lock, flags);
466 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
467 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
468 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 return val;
470 }
471
472 /* usec_wait specifies the wait time in usec when writing to certain registers
473 * where it is unsafe to read back the register without some delay.
474 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
475 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
476 */
477 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
478 {
479 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
480 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
481 /* Non-posted methods */
482 tp->write32(tp, off, val);
483 else {
484 /* Posted method */
485 tg3_write32(tp, off, val);
486 if (usec_wait)
487 udelay(usec_wait);
488 tp->read32(tp, off);
489 }
490 /* Wait again after the read for the posted method to guarantee that
491 * the wait time is met.
492 */
493 if (usec_wait)
494 udelay(usec_wait);
495 }
496
497 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
498 {
499 tp->write32_mbox(tp, off, val);
500 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
501 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
502 tp->read32_mbox(tp, off);
503 }
504
505 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
506 {
507 void __iomem *mbox = tp->regs + off;
508 writel(val, mbox);
509 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
510 writel(val, mbox);
511 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
512 readl(mbox);
513 }
514
515 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
516 {
517 return readl(tp->regs + off + GRCMBOX_BASE);
518 }
519
520 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
521 {
522 writel(val, tp->regs + off + GRCMBOX_BASE);
523 }
524
525 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
526 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
527 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
528 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
529 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
530
531 #define tw32(reg, val) tp->write32(tp, reg, val)
532 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
533 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
534 #define tr32(reg) tp->read32(tp, reg)
535
536 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
537 {
538 unsigned long flags;
539
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
542 return;
543
544 spin_lock_irqsave(&tp->indirect_lock, flags);
545 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
548
549 /* Always leave this as zero. */
550 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
551 } else {
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
553 tw32_f(TG3PCI_MEM_WIN_DATA, val);
554
555 /* Always leave this as zero. */
556 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
557 }
558 spin_unlock_irqrestore(&tp->indirect_lock, flags);
559 }
560
561 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
562 {
563 unsigned long flags;
564
565 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
566 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
567 *val = 0;
568 return;
569 }
570
571 spin_lock_irqsave(&tp->indirect_lock, flags);
572 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
573 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
574 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
575
576 /* Always leave this as zero. */
577 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
578 } else {
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
580 *val = tr32(TG3PCI_MEM_WIN_DATA);
581
582 /* Always leave this as zero. */
583 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 }
585 spin_unlock_irqrestore(&tp->indirect_lock, flags);
586 }
587
588 static void tg3_ape_lock_init(struct tg3 *tp)
589 {
590 int i;
591 u32 regbase;
592
593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
594 regbase = TG3_APE_LOCK_GRANT;
595 else
596 regbase = TG3_APE_PER_LOCK_GRANT;
597
598 /* Make sure the driver hasn't any stale locks. */
599 for (i = 0; i < 8; i++)
600 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
601 }
602
603 static int tg3_ape_lock(struct tg3 *tp, int locknum)
604 {
605 int i, off;
606 int ret = 0;
607 u32 status, req, gnt;
608
609 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
610 return 0;
611
612 switch (locknum) {
613 case TG3_APE_LOCK_GRC:
614 case TG3_APE_LOCK_MEM:
615 break;
616 default:
617 return -EINVAL;
618 }
619
620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
621 req = TG3_APE_LOCK_REQ;
622 gnt = TG3_APE_LOCK_GRANT;
623 } else {
624 req = TG3_APE_PER_LOCK_REQ;
625 gnt = TG3_APE_PER_LOCK_GRANT;
626 }
627
628 off = 4 * locknum;
629
630 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
631
632 /* Wait for up to 1 millisecond to acquire lock. */
633 for (i = 0; i < 100; i++) {
634 status = tg3_ape_read32(tp, gnt + off);
635 if (status == APE_LOCK_GRANT_DRIVER)
636 break;
637 udelay(10);
638 }
639
640 if (status != APE_LOCK_GRANT_DRIVER) {
641 /* Revoke the lock request. */
642 tg3_ape_write32(tp, gnt + off,
643 APE_LOCK_GRANT_DRIVER);
644
645 ret = -EBUSY;
646 }
647
648 return ret;
649 }
650
651 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
652 {
653 u32 gnt;
654
655 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
656 return;
657
658 switch (locknum) {
659 case TG3_APE_LOCK_GRC:
660 case TG3_APE_LOCK_MEM:
661 break;
662 default:
663 return;
664 }
665
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
667 gnt = TG3_APE_LOCK_GRANT;
668 else
669 gnt = TG3_APE_PER_LOCK_GRANT;
670
671 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
672 }
673
674 static void tg3_disable_ints(struct tg3 *tp)
675 {
676 int i;
677
678 tw32(TG3PCI_MISC_HOST_CTRL,
679 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
680 for (i = 0; i < tp->irq_max; i++)
681 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
682 }
683
684 static void tg3_enable_ints(struct tg3 *tp)
685 {
686 int i;
687
688 tp->irq_sync = 0;
689 wmb();
690
691 tw32(TG3PCI_MISC_HOST_CTRL,
692 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
693
694 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
695 for (i = 0; i < tp->irq_cnt; i++) {
696 struct tg3_napi *tnapi = &tp->napi[i];
697
698 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
699 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
700 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
701
702 tp->coal_now |= tnapi->coal_now;
703 }
704
705 /* Force an initial interrupt */
706 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
707 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
708 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
709 else
710 tw32(HOSTCC_MODE, tp->coal_now);
711
712 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
713 }
714
715 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
716 {
717 struct tg3 *tp = tnapi->tp;
718 struct tg3_hw_status *sblk = tnapi->hw_status;
719 unsigned int work_exists = 0;
720
721 /* check for phy events */
722 if (!(tp->tg3_flags &
723 (TG3_FLAG_USE_LINKCHG_REG |
724 TG3_FLAG_POLL_SERDES))) {
725 if (sblk->status & SD_STATUS_LINK_CHG)
726 work_exists = 1;
727 }
728 /* check for RX/TX work to do */
729 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
730 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
731 work_exists = 1;
732
733 return work_exists;
734 }
735
736 /* tg3_int_reenable
737 * similar to tg3_enable_ints, but it accurately determines whether there
738 * is new work pending and can return without flushing the PIO write
739 * which reenables interrupts
740 */
741 static void tg3_int_reenable(struct tg3_napi *tnapi)
742 {
743 struct tg3 *tp = tnapi->tp;
744
745 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
746 mmiowb();
747
748 /* When doing tagged status, this work check is unnecessary.
749 * The last_tag we write above tells the chip which piece of
750 * work we've completed.
751 */
752 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
753 tg3_has_work(tnapi))
754 tw32(HOSTCC_MODE, tp->coalesce_mode |
755 HOSTCC_MODE_ENABLE | tnapi->coal_now);
756 }
757
758 static void tg3_switch_clocks(struct tg3 *tp)
759 {
760 u32 clock_ctrl;
761 u32 orig_clock_ctrl;
762
763 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
764 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
765 return;
766
767 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
768
769 orig_clock_ctrl = clock_ctrl;
770 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
771 CLOCK_CTRL_CLKRUN_OENABLE |
772 0x1f);
773 tp->pci_clock_ctrl = clock_ctrl;
774
775 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
776 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
779 }
780 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
781 tw32_wait_f(TG3PCI_CLOCK_CTRL,
782 clock_ctrl |
783 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
784 40);
785 tw32_wait_f(TG3PCI_CLOCK_CTRL,
786 clock_ctrl | (CLOCK_CTRL_ALTCLK),
787 40);
788 }
789 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
790 }
791
792 #define PHY_BUSY_LOOPS 5000
793
794 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
795 {
796 u32 frame_val;
797 unsigned int loops;
798 int ret;
799
800 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
801 tw32_f(MAC_MI_MODE,
802 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
803 udelay(80);
804 }
805
806 *val = 0x0;
807
808 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
809 MI_COM_PHY_ADDR_MASK);
810 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
811 MI_COM_REG_ADDR_MASK);
812 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
813
814 tw32_f(MAC_MI_COM, frame_val);
815
816 loops = PHY_BUSY_LOOPS;
817 while (loops != 0) {
818 udelay(10);
819 frame_val = tr32(MAC_MI_COM);
820
821 if ((frame_val & MI_COM_BUSY) == 0) {
822 udelay(5);
823 frame_val = tr32(MAC_MI_COM);
824 break;
825 }
826 loops -= 1;
827 }
828
829 ret = -EBUSY;
830 if (loops != 0) {
831 *val = frame_val & MI_COM_DATA_MASK;
832 ret = 0;
833 }
834
835 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
836 tw32_f(MAC_MI_MODE, tp->mi_mode);
837 udelay(80);
838 }
839
840 return ret;
841 }
842
843 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
844 {
845 u32 frame_val;
846 unsigned int loops;
847 int ret;
848
849 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
850 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
851 return 0;
852
853 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
854 tw32_f(MAC_MI_MODE,
855 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
856 udelay(80);
857 }
858
859 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
860 MI_COM_PHY_ADDR_MASK);
861 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
862 MI_COM_REG_ADDR_MASK);
863 frame_val |= (val & MI_COM_DATA_MASK);
864 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
865
866 tw32_f(MAC_MI_COM, frame_val);
867
868 loops = PHY_BUSY_LOOPS;
869 while (loops != 0) {
870 udelay(10);
871 frame_val = tr32(MAC_MI_COM);
872 if ((frame_val & MI_COM_BUSY) == 0) {
873 udelay(5);
874 frame_val = tr32(MAC_MI_COM);
875 break;
876 }
877 loops -= 1;
878 }
879
880 ret = -EBUSY;
881 if (loops != 0)
882 ret = 0;
883
884 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
885 tw32_f(MAC_MI_MODE, tp->mi_mode);
886 udelay(80);
887 }
888
889 return ret;
890 }
891
892 static int tg3_bmcr_reset(struct tg3 *tp)
893 {
894 u32 phy_control;
895 int limit, err;
896
897 /* OK, reset it, and poll the BMCR_RESET bit until it
898 * clears or we time out.
899 */
900 phy_control = BMCR_RESET;
901 err = tg3_writephy(tp, MII_BMCR, phy_control);
902 if (err != 0)
903 return -EBUSY;
904
905 limit = 5000;
906 while (limit--) {
907 err = tg3_readphy(tp, MII_BMCR, &phy_control);
908 if (err != 0)
909 return -EBUSY;
910
911 if ((phy_control & BMCR_RESET) == 0) {
912 udelay(40);
913 break;
914 }
915 udelay(10);
916 }
917 if (limit < 0)
918 return -EBUSY;
919
920 return 0;
921 }
922
923 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
924 {
925 struct tg3 *tp = bp->priv;
926 u32 val;
927
928 spin_lock_bh(&tp->lock);
929
930 if (tg3_readphy(tp, reg, &val))
931 val = -EIO;
932
933 spin_unlock_bh(&tp->lock);
934
935 return val;
936 }
937
938 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
939 {
940 struct tg3 *tp = bp->priv;
941 u32 ret = 0;
942
943 spin_lock_bh(&tp->lock);
944
945 if (tg3_writephy(tp, reg, val))
946 ret = -EIO;
947
948 spin_unlock_bh(&tp->lock);
949
950 return ret;
951 }
952
953 static int tg3_mdio_reset(struct mii_bus *bp)
954 {
955 return 0;
956 }
957
958 static void tg3_mdio_config_5785(struct tg3 *tp)
959 {
960 u32 val;
961 struct phy_device *phydev;
962
963 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
964 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
965 case PHY_ID_BCM50610:
966 case PHY_ID_BCM50610M:
967 val = MAC_PHYCFG2_50610_LED_MODES;
968 break;
969 case PHY_ID_BCMAC131:
970 val = MAC_PHYCFG2_AC131_LED_MODES;
971 break;
972 case PHY_ID_RTL8211C:
973 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
974 break;
975 case PHY_ID_RTL8201E:
976 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
977 break;
978 default:
979 return;
980 }
981
982 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
983 tw32(MAC_PHYCFG2, val);
984
985 val = tr32(MAC_PHYCFG1);
986 val &= ~(MAC_PHYCFG1_RGMII_INT |
987 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
988 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
989 tw32(MAC_PHYCFG1, val);
990
991 return;
992 }
993
994 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
995 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
996 MAC_PHYCFG2_FMODE_MASK_MASK |
997 MAC_PHYCFG2_GMODE_MASK_MASK |
998 MAC_PHYCFG2_ACT_MASK_MASK |
999 MAC_PHYCFG2_QUAL_MASK_MASK |
1000 MAC_PHYCFG2_INBAND_ENABLE;
1001
1002 tw32(MAC_PHYCFG2, val);
1003
1004 val = tr32(MAC_PHYCFG1);
1005 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1006 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1007 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1009 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1010 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1011 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1012 }
1013 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1014 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1015 tw32(MAC_PHYCFG1, val);
1016
1017 val = tr32(MAC_EXT_RGMII_MODE);
1018 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1019 MAC_RGMII_MODE_RX_QUALITY |
1020 MAC_RGMII_MODE_RX_ACTIVITY |
1021 MAC_RGMII_MODE_RX_ENG_DET |
1022 MAC_RGMII_MODE_TX_ENABLE |
1023 MAC_RGMII_MODE_TX_LOWPWR |
1024 MAC_RGMII_MODE_TX_RESET);
1025 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1026 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1027 val |= MAC_RGMII_MODE_RX_INT_B |
1028 MAC_RGMII_MODE_RX_QUALITY |
1029 MAC_RGMII_MODE_RX_ACTIVITY |
1030 MAC_RGMII_MODE_RX_ENG_DET;
1031 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1032 val |= MAC_RGMII_MODE_TX_ENABLE |
1033 MAC_RGMII_MODE_TX_LOWPWR |
1034 MAC_RGMII_MODE_TX_RESET;
1035 }
1036 tw32(MAC_EXT_RGMII_MODE, val);
1037 }
1038
1039 static void tg3_mdio_start(struct tg3 *tp)
1040 {
1041 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1042 tw32_f(MAC_MI_MODE, tp->mi_mode);
1043 udelay(80);
1044
1045 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1047 tg3_mdio_config_5785(tp);
1048 }
1049
1050 static int tg3_mdio_init(struct tg3 *tp)
1051 {
1052 int i;
1053 u32 reg;
1054 struct phy_device *phydev;
1055
1056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1058 u32 is_serdes;
1059
1060 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1061
1062 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1063 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1064 else
1065 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1066 TG3_CPMU_PHY_STRAP_IS_SERDES;
1067 if (is_serdes)
1068 tp->phy_addr += 7;
1069 } else
1070 tp->phy_addr = TG3_PHY_MII_ADDR;
1071
1072 tg3_mdio_start(tp);
1073
1074 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1075 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1076 return 0;
1077
1078 tp->mdio_bus = mdiobus_alloc();
1079 if (tp->mdio_bus == NULL)
1080 return -ENOMEM;
1081
1082 tp->mdio_bus->name = "tg3 mdio bus";
1083 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1084 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1085 tp->mdio_bus->priv = tp;
1086 tp->mdio_bus->parent = &tp->pdev->dev;
1087 tp->mdio_bus->read = &tg3_mdio_read;
1088 tp->mdio_bus->write = &tg3_mdio_write;
1089 tp->mdio_bus->reset = &tg3_mdio_reset;
1090 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1091 tp->mdio_bus->irq = &tp->mdio_irq[0];
1092
1093 for (i = 0; i < PHY_MAX_ADDR; i++)
1094 tp->mdio_bus->irq[i] = PHY_POLL;
1095
1096 /* The bus registration will look for all the PHYs on the mdio bus.
1097 * Unfortunately, it does not ensure the PHY is powered up before
1098 * accessing the PHY ID registers. A chip reset is the
1099 * quickest way to bring the device back to an operational state..
1100 */
1101 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1102 tg3_bmcr_reset(tp);
1103
1104 i = mdiobus_register(tp->mdio_bus);
1105 if (i) {
1106 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1107 mdiobus_free(tp->mdio_bus);
1108 return i;
1109 }
1110
1111 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1112
1113 if (!phydev || !phydev->drv) {
1114 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1115 mdiobus_unregister(tp->mdio_bus);
1116 mdiobus_free(tp->mdio_bus);
1117 return -ENODEV;
1118 }
1119
1120 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1121 case PHY_ID_BCM57780:
1122 phydev->interface = PHY_INTERFACE_MODE_GMII;
1123 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1124 break;
1125 case PHY_ID_BCM50610:
1126 case PHY_ID_BCM50610M:
1127 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1128 PHY_BRCM_RX_REFCLK_UNUSED |
1129 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1130 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1132 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1133 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1134 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1135 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1136 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1137 /* fallthru */
1138 case PHY_ID_RTL8211C:
1139 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1140 break;
1141 case PHY_ID_RTL8201E:
1142 case PHY_ID_BCMAC131:
1143 phydev->interface = PHY_INTERFACE_MODE_MII;
1144 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1145 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1146 break;
1147 }
1148
1149 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1150
1151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1152 tg3_mdio_config_5785(tp);
1153
1154 return 0;
1155 }
1156
1157 static void tg3_mdio_fini(struct tg3 *tp)
1158 {
1159 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1160 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1161 mdiobus_unregister(tp->mdio_bus);
1162 mdiobus_free(tp->mdio_bus);
1163 }
1164 }
1165
1166 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1167 {
1168 int err;
1169
1170 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1171 if (err)
1172 goto done;
1173
1174 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1175 if (err)
1176 goto done;
1177
1178 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1179 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1180 if (err)
1181 goto done;
1182
1183 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1184
1185 done:
1186 return err;
1187 }
1188
1189 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1190 {
1191 int err;
1192
1193 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1194 if (err)
1195 goto done;
1196
1197 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1198 if (err)
1199 goto done;
1200
1201 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1202 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1203 if (err)
1204 goto done;
1205
1206 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1207
1208 done:
1209 return err;
1210 }
1211
1212 /* tp->lock is held. */
1213 static inline void tg3_generate_fw_event(struct tg3 *tp)
1214 {
1215 u32 val;
1216
1217 val = tr32(GRC_RX_CPU_EVENT);
1218 val |= GRC_RX_CPU_DRIVER_EVENT;
1219 tw32_f(GRC_RX_CPU_EVENT, val);
1220
1221 tp->last_event_jiffies = jiffies;
1222 }
1223
1224 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1225
1226 /* tp->lock is held. */
1227 static void tg3_wait_for_event_ack(struct tg3 *tp)
1228 {
1229 int i;
1230 unsigned int delay_cnt;
1231 long time_remain;
1232
1233 /* If enough time has passed, no wait is necessary. */
1234 time_remain = (long)(tp->last_event_jiffies + 1 +
1235 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1236 (long)jiffies;
1237 if (time_remain < 0)
1238 return;
1239
1240 /* Check if we can shorten the wait time. */
1241 delay_cnt = jiffies_to_usecs(time_remain);
1242 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1243 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1244 delay_cnt = (delay_cnt >> 3) + 1;
1245
1246 for (i = 0; i < delay_cnt; i++) {
1247 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1248 break;
1249 udelay(8);
1250 }
1251 }
1252
1253 /* tp->lock is held. */
1254 static void tg3_ump_link_report(struct tg3 *tp)
1255 {
1256 u32 reg;
1257 u32 val;
1258
1259 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1260 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1261 return;
1262
1263 tg3_wait_for_event_ack(tp);
1264
1265 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1266
1267 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1268
1269 val = 0;
1270 if (!tg3_readphy(tp, MII_BMCR, &reg))
1271 val = reg << 16;
1272 if (!tg3_readphy(tp, MII_BMSR, &reg))
1273 val |= (reg & 0xffff);
1274 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1275
1276 val = 0;
1277 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1278 val = reg << 16;
1279 if (!tg3_readphy(tp, MII_LPA, &reg))
1280 val |= (reg & 0xffff);
1281 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1282
1283 val = 0;
1284 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1285 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1286 val = reg << 16;
1287 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1288 val |= (reg & 0xffff);
1289 }
1290 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1291
1292 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1293 val = reg << 16;
1294 else
1295 val = 0;
1296 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1297
1298 tg3_generate_fw_event(tp);
1299 }
1300
1301 static void tg3_link_report(struct tg3 *tp)
1302 {
1303 if (!netif_carrier_ok(tp->dev)) {
1304 netif_info(tp, link, tp->dev, "Link is down\n");
1305 tg3_ump_link_report(tp);
1306 } else if (netif_msg_link(tp)) {
1307 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1308 (tp->link_config.active_speed == SPEED_1000 ?
1309 1000 :
1310 (tp->link_config.active_speed == SPEED_100 ?
1311 100 : 10)),
1312 (tp->link_config.active_duplex == DUPLEX_FULL ?
1313 "full" : "half"));
1314
1315 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1316 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1317 "on" : "off",
1318 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1319 "on" : "off");
1320 tg3_ump_link_report(tp);
1321 }
1322 }
1323
1324 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1325 {
1326 u16 miireg;
1327
1328 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1329 miireg = ADVERTISE_PAUSE_CAP;
1330 else if (flow_ctrl & FLOW_CTRL_TX)
1331 miireg = ADVERTISE_PAUSE_ASYM;
1332 else if (flow_ctrl & FLOW_CTRL_RX)
1333 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1334 else
1335 miireg = 0;
1336
1337 return miireg;
1338 }
1339
1340 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1341 {
1342 u16 miireg;
1343
1344 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1345 miireg = ADVERTISE_1000XPAUSE;
1346 else if (flow_ctrl & FLOW_CTRL_TX)
1347 miireg = ADVERTISE_1000XPSE_ASYM;
1348 else if (flow_ctrl & FLOW_CTRL_RX)
1349 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1350 else
1351 miireg = 0;
1352
1353 return miireg;
1354 }
1355
1356 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1357 {
1358 u8 cap = 0;
1359
1360 if (lcladv & ADVERTISE_1000XPAUSE) {
1361 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362 if (rmtadv & LPA_1000XPAUSE)
1363 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1364 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1365 cap = FLOW_CTRL_RX;
1366 } else {
1367 if (rmtadv & LPA_1000XPAUSE)
1368 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1369 }
1370 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1371 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1372 cap = FLOW_CTRL_TX;
1373 }
1374
1375 return cap;
1376 }
1377
1378 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1379 {
1380 u8 autoneg;
1381 u8 flowctrl = 0;
1382 u32 old_rx_mode = tp->rx_mode;
1383 u32 old_tx_mode = tp->tx_mode;
1384
1385 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1386 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1387 else
1388 autoneg = tp->link_config.autoneg;
1389
1390 if (autoneg == AUTONEG_ENABLE &&
1391 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1392 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1393 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1394 else
1395 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1396 } else
1397 flowctrl = tp->link_config.flowctrl;
1398
1399 tp->link_config.active_flowctrl = flowctrl;
1400
1401 if (flowctrl & FLOW_CTRL_RX)
1402 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1403 else
1404 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1405
1406 if (old_rx_mode != tp->rx_mode)
1407 tw32_f(MAC_RX_MODE, tp->rx_mode);
1408
1409 if (flowctrl & FLOW_CTRL_TX)
1410 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1411 else
1412 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1413
1414 if (old_tx_mode != tp->tx_mode)
1415 tw32_f(MAC_TX_MODE, tp->tx_mode);
1416 }
1417
1418 static void tg3_adjust_link(struct net_device *dev)
1419 {
1420 u8 oldflowctrl, linkmesg = 0;
1421 u32 mac_mode, lcl_adv, rmt_adv;
1422 struct tg3 *tp = netdev_priv(dev);
1423 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1424
1425 spin_lock_bh(&tp->lock);
1426
1427 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1428 MAC_MODE_HALF_DUPLEX);
1429
1430 oldflowctrl = tp->link_config.active_flowctrl;
1431
1432 if (phydev->link) {
1433 lcl_adv = 0;
1434 rmt_adv = 0;
1435
1436 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1437 mac_mode |= MAC_MODE_PORT_MODE_MII;
1438 else if (phydev->speed == SPEED_1000 ||
1439 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1440 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1441 else
1442 mac_mode |= MAC_MODE_PORT_MODE_MII;
1443
1444 if (phydev->duplex == DUPLEX_HALF)
1445 mac_mode |= MAC_MODE_HALF_DUPLEX;
1446 else {
1447 lcl_adv = tg3_advert_flowctrl_1000T(
1448 tp->link_config.flowctrl);
1449
1450 if (phydev->pause)
1451 rmt_adv = LPA_PAUSE_CAP;
1452 if (phydev->asym_pause)
1453 rmt_adv |= LPA_PAUSE_ASYM;
1454 }
1455
1456 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1457 } else
1458 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1459
1460 if (mac_mode != tp->mac_mode) {
1461 tp->mac_mode = mac_mode;
1462 tw32_f(MAC_MODE, tp->mac_mode);
1463 udelay(40);
1464 }
1465
1466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1467 if (phydev->speed == SPEED_10)
1468 tw32(MAC_MI_STAT,
1469 MAC_MI_STAT_10MBPS_MODE |
1470 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1471 else
1472 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1473 }
1474
1475 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1476 tw32(MAC_TX_LENGTHS,
1477 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1478 (6 << TX_LENGTHS_IPG_SHIFT) |
1479 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1480 else
1481 tw32(MAC_TX_LENGTHS,
1482 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1483 (6 << TX_LENGTHS_IPG_SHIFT) |
1484 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1485
1486 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1487 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1488 phydev->speed != tp->link_config.active_speed ||
1489 phydev->duplex != tp->link_config.active_duplex ||
1490 oldflowctrl != tp->link_config.active_flowctrl)
1491 linkmesg = 1;
1492
1493 tp->link_config.active_speed = phydev->speed;
1494 tp->link_config.active_duplex = phydev->duplex;
1495
1496 spin_unlock_bh(&tp->lock);
1497
1498 if (linkmesg)
1499 tg3_link_report(tp);
1500 }
1501
1502 static int tg3_phy_init(struct tg3 *tp)
1503 {
1504 struct phy_device *phydev;
1505
1506 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1507 return 0;
1508
1509 /* Bring the PHY back to a known state. */
1510 tg3_bmcr_reset(tp);
1511
1512 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514 /* Attach the MAC to the PHY. */
1515 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1516 phydev->dev_flags, phydev->interface);
1517 if (IS_ERR(phydev)) {
1518 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1519 return PTR_ERR(phydev);
1520 }
1521
1522 /* Mask with MAC supported features. */
1523 switch (phydev->interface) {
1524 case PHY_INTERFACE_MODE_GMII:
1525 case PHY_INTERFACE_MODE_RGMII:
1526 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1527 phydev->supported &= (PHY_GBIT_FEATURES |
1528 SUPPORTED_Pause |
1529 SUPPORTED_Asym_Pause);
1530 break;
1531 }
1532 /* fallthru */
1533 case PHY_INTERFACE_MODE_MII:
1534 phydev->supported &= (PHY_BASIC_FEATURES |
1535 SUPPORTED_Pause |
1536 SUPPORTED_Asym_Pause);
1537 break;
1538 default:
1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1540 return -EINVAL;
1541 }
1542
1543 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1544
1545 phydev->advertising = phydev->supported;
1546
1547 return 0;
1548 }
1549
1550 static void tg3_phy_start(struct tg3 *tp)
1551 {
1552 struct phy_device *phydev;
1553
1554 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1555 return;
1556
1557 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1558
1559 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1560 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1561 phydev->speed = tp->link_config.orig_speed;
1562 phydev->duplex = tp->link_config.orig_duplex;
1563 phydev->autoneg = tp->link_config.orig_autoneg;
1564 phydev->advertising = tp->link_config.orig_advertising;
1565 }
1566
1567 phy_start(phydev);
1568
1569 phy_start_aneg(phydev);
1570 }
1571
1572 static void tg3_phy_stop(struct tg3 *tp)
1573 {
1574 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1575 return;
1576
1577 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1578 }
1579
1580 static void tg3_phy_fini(struct tg3 *tp)
1581 {
1582 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1583 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1584 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1585 }
1586 }
1587
1588 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1589 {
1590 int err;
1591
1592 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1593 if (!err)
1594 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1595
1596 return err;
1597 }
1598
1599 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1600 {
1601 int err;
1602
1603 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1604 if (!err)
1605 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1606
1607 return err;
1608 }
1609
1610 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1611 {
1612 u32 phytest;
1613
1614 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1615 u32 phy;
1616
1617 tg3_writephy(tp, MII_TG3_FET_TEST,
1618 phytest | MII_TG3_FET_SHADOW_EN);
1619 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1620 if (enable)
1621 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1622 else
1623 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1624 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1625 }
1626 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1627 }
1628 }
1629
1630 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1631 {
1632 u32 reg;
1633
1634 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1635 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1637 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1638 return;
1639
1640 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1641 tg3_phy_fet_toggle_apd(tp, enable);
1642 return;
1643 }
1644
1645 reg = MII_TG3_MISC_SHDW_WREN |
1646 MII_TG3_MISC_SHDW_SCR5_SEL |
1647 MII_TG3_MISC_SHDW_SCR5_LPED |
1648 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1649 MII_TG3_MISC_SHDW_SCR5_SDTL |
1650 MII_TG3_MISC_SHDW_SCR5_C125OE;
1651 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1652 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1653
1654 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655
1656
1657 reg = MII_TG3_MISC_SHDW_WREN |
1658 MII_TG3_MISC_SHDW_APD_SEL |
1659 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1660 if (enable)
1661 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1662
1663 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1664 }
1665
1666 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1667 {
1668 u32 phy;
1669
1670 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1671 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1672 return;
1673
1674 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1675 u32 ephy;
1676
1677 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1678 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1679
1680 tg3_writephy(tp, MII_TG3_FET_TEST,
1681 ephy | MII_TG3_FET_SHADOW_EN);
1682 if (!tg3_readphy(tp, reg, &phy)) {
1683 if (enable)
1684 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1685 else
1686 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1687 tg3_writephy(tp, reg, phy);
1688 }
1689 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1690 }
1691 } else {
1692 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1693 MII_TG3_AUXCTL_SHDWSEL_MISC;
1694 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1695 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1696 if (enable)
1697 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1698 else
1699 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1700 phy |= MII_TG3_AUXCTL_MISC_WREN;
1701 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1702 }
1703 }
1704 }
1705
1706 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1707 {
1708 u32 val;
1709
1710 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1711 return;
1712
1713 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1714 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1715 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1716 (val | (1 << 15) | (1 << 4)));
1717 }
1718
1719 static void tg3_phy_apply_otp(struct tg3 *tp)
1720 {
1721 u32 otp, phy;
1722
1723 if (!tp->phy_otp)
1724 return;
1725
1726 otp = tp->phy_otp;
1727
1728 /* Enable SM_DSP clock and tx 6dB coding. */
1729 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1730 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1731 MII_TG3_AUXCTL_ACTL_TX_6DB;
1732 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1733
1734 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1735 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1736 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1737
1738 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1739 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1740 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1741
1742 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1743 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1744 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1745
1746 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1747 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1748
1749 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1750 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1751
1752 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1753 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1754 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1755
1756 /* Turn off SM_DSP clock. */
1757 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1758 MII_TG3_AUXCTL_ACTL_TX_6DB;
1759 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1760 }
1761
1762 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1763 {
1764 u32 val;
1765
1766 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1767 return;
1768
1769 tp->setlpicnt = 0;
1770
1771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1772 current_link_up == 1 &&
1773 tp->link_config.active_duplex == DUPLEX_FULL &&
1774 (tp->link_config.active_speed == SPEED_100 ||
1775 tp->link_config.active_speed == SPEED_1000)) {
1776 u32 eeectl;
1777
1778 if (tp->link_config.active_speed == SPEED_1000)
1779 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1780 else
1781 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1782
1783 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1784
1785 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1786 TG3_CL45_D7_EEERES_STAT, &val);
1787
1788 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1789 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1790 tp->setlpicnt = 2;
1791 }
1792
1793 if (!tp->setlpicnt) {
1794 val = tr32(TG3_CPMU_EEE_MODE);
1795 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1796 }
1797 }
1798
1799 static int tg3_wait_macro_done(struct tg3 *tp)
1800 {
1801 int limit = 100;
1802
1803 while (limit--) {
1804 u32 tmp32;
1805
1806 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1807 if ((tmp32 & 0x1000) == 0)
1808 break;
1809 }
1810 }
1811 if (limit < 0)
1812 return -EBUSY;
1813
1814 return 0;
1815 }
1816
1817 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1818 {
1819 static const u32 test_pat[4][6] = {
1820 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1821 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1822 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1823 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1824 };
1825 int chan;
1826
1827 for (chan = 0; chan < 4; chan++) {
1828 int i;
1829
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1831 (chan * 0x2000) | 0x0200);
1832 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1833
1834 for (i = 0; i < 6; i++)
1835 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1836 test_pat[chan][i]);
1837
1838 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1839 if (tg3_wait_macro_done(tp)) {
1840 *resetp = 1;
1841 return -EBUSY;
1842 }
1843
1844 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1845 (chan * 0x2000) | 0x0200);
1846 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1847 if (tg3_wait_macro_done(tp)) {
1848 *resetp = 1;
1849 return -EBUSY;
1850 }
1851
1852 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1853 if (tg3_wait_macro_done(tp)) {
1854 *resetp = 1;
1855 return -EBUSY;
1856 }
1857
1858 for (i = 0; i < 6; i += 2) {
1859 u32 low, high;
1860
1861 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1862 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1863 tg3_wait_macro_done(tp)) {
1864 *resetp = 1;
1865 return -EBUSY;
1866 }
1867 low &= 0x7fff;
1868 high &= 0x000f;
1869 if (low != test_pat[chan][i] ||
1870 high != test_pat[chan][i+1]) {
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1873 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1874
1875 return -EBUSY;
1876 }
1877 }
1878 }
1879
1880 return 0;
1881 }
1882
1883 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1884 {
1885 int chan;
1886
1887 for (chan = 0; chan < 4; chan++) {
1888 int i;
1889
1890 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1891 (chan * 0x2000) | 0x0200);
1892 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1893 for (i = 0; i < 6; i++)
1894 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1895 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1896 if (tg3_wait_macro_done(tp))
1897 return -EBUSY;
1898 }
1899
1900 return 0;
1901 }
1902
1903 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1904 {
1905 u32 reg32, phy9_orig;
1906 int retries, do_phy_reset, err;
1907
1908 retries = 10;
1909 do_phy_reset = 1;
1910 do {
1911 if (do_phy_reset) {
1912 err = tg3_bmcr_reset(tp);
1913 if (err)
1914 return err;
1915 do_phy_reset = 0;
1916 }
1917
1918 /* Disable transmitter and interrupt. */
1919 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1920 continue;
1921
1922 reg32 |= 0x3000;
1923 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1924
1925 /* Set full-duplex, 1000 mbps. */
1926 tg3_writephy(tp, MII_BMCR,
1927 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1928
1929 /* Set to master mode. */
1930 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1931 continue;
1932
1933 tg3_writephy(tp, MII_TG3_CTRL,
1934 (MII_TG3_CTRL_AS_MASTER |
1935 MII_TG3_CTRL_ENABLE_AS_MASTER));
1936
1937 /* Enable SM_DSP_CLOCK and 6dB. */
1938 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939
1940 /* Block the PHY control access. */
1941 tg3_phydsp_write(tp, 0x8005, 0x0800);
1942
1943 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1944 if (!err)
1945 break;
1946 } while (--retries);
1947
1948 err = tg3_phy_reset_chanpat(tp);
1949 if (err)
1950 return err;
1951
1952 tg3_phydsp_write(tp, 0x8005, 0x0000);
1953
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1955 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1956
1957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1959 /* Set Extended packet length bit for jumbo frames */
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1961 } else {
1962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963 }
1964
1965 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1966
1967 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1968 reg32 &= ~0x3000;
1969 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1970 } else if (!err)
1971 err = -EBUSY;
1972
1973 return err;
1974 }
1975
1976 /* This will reset the tigon3 PHY if there is no valid
1977 * link unless the FORCE argument is non-zero.
1978 */
1979 static int tg3_phy_reset(struct tg3 *tp)
1980 {
1981 u32 val, cpmuctrl;
1982 int err;
1983
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1985 val = tr32(GRC_MISC_CFG);
1986 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1987 udelay(40);
1988 }
1989 err = tg3_readphy(tp, MII_BMSR, &val);
1990 err |= tg3_readphy(tp, MII_BMSR, &val);
1991 if (err != 0)
1992 return -EBUSY;
1993
1994 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1995 netif_carrier_off(tp->dev);
1996 tg3_link_report(tp);
1997 }
1998
1999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2002 err = tg3_phy_reset_5703_4_5(tp);
2003 if (err)
2004 return err;
2005 goto out;
2006 }
2007
2008 cpmuctrl = 0;
2009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2010 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2011 cpmuctrl = tr32(TG3_CPMU_CTRL);
2012 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2013 tw32(TG3_CPMU_CTRL,
2014 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2015 }
2016
2017 err = tg3_bmcr_reset(tp);
2018 if (err)
2019 return err;
2020
2021 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2022 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2023 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2024
2025 tw32(TG3_CPMU_CTRL, cpmuctrl);
2026 }
2027
2028 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2029 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2030 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2031 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2032 CPMU_LSPD_1000MB_MACCLK_12_5) {
2033 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2034 udelay(40);
2035 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2036 }
2037 }
2038
2039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2041 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2042 return 0;
2043
2044 tg3_phy_apply_otp(tp);
2045
2046 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2047 tg3_phy_toggle_apd(tp, true);
2048 else
2049 tg3_phy_toggle_apd(tp, false);
2050
2051 out:
2052 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2053 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2054 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2055 tg3_phydsp_write(tp, 0x000a, 0x0323);
2056 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2057 }
2058 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2059 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2060 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2061 }
2062 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2064 tg3_phydsp_write(tp, 0x000a, 0x310b);
2065 tg3_phydsp_write(tp, 0x201f, 0x9506);
2066 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2067 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2068 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2069 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2070 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2071 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2072 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2073 tg3_writephy(tp, MII_TG3_TEST1,
2074 MII_TG3_TEST1_TRIM_EN | 0x4);
2075 } else
2076 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2077 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2078 }
2079 /* Set Extended packet length bit (bit 14) on all chips that */
2080 /* support jumbo frames */
2081 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2082 /* Cannot do read-modify-write on 5401 */
2083 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2084 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2085 /* Set bit 14 with read-modify-write to preserve other bits */
2086 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2087 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2088 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2089 }
2090
2091 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2092 * jumbo frames transmission.
2093 */
2094 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2095 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2096 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2097 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2098 }
2099
2100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2101 /* adjust output voltage */
2102 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2103 }
2104
2105 tg3_phy_toggle_automdix(tp, 1);
2106 tg3_phy_set_wirespeed(tp);
2107 return 0;
2108 }
2109
2110 static void tg3_frob_aux_power(struct tg3 *tp)
2111 {
2112 struct tg3 *tp_peer = tp;
2113
2114 /* The GPIOs do something completely different on 57765. */
2115 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2118 return;
2119
2120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2123 struct net_device *dev_peer;
2124
2125 dev_peer = pci_get_drvdata(tp->pdev_peer);
2126 /* remove_one() may have been run on the peer. */
2127 if (!dev_peer)
2128 tp_peer = tp;
2129 else
2130 tp_peer = netdev_priv(dev_peer);
2131 }
2132
2133 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2135 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2136 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE0 |
2141 GRC_LCLCTRL_GPIO_OE1 |
2142 GRC_LCLCTRL_GPIO_OE2 |
2143 GRC_LCLCTRL_GPIO_OUTPUT0 |
2144 GRC_LCLCTRL_GPIO_OUTPUT1),
2145 100);
2146 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2148 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2149 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2150 GRC_LCLCTRL_GPIO_OE1 |
2151 GRC_LCLCTRL_GPIO_OE2 |
2152 GRC_LCLCTRL_GPIO_OUTPUT0 |
2153 GRC_LCLCTRL_GPIO_OUTPUT1 |
2154 tp->grc_local_ctrl;
2155 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2156
2157 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2158 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2159
2160 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2161 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2162 } else {
2163 u32 no_gpio2;
2164 u32 grc_local_ctrl = 0;
2165
2166 if (tp_peer != tp &&
2167 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2168 return;
2169
2170 /* Workaround to prevent overdrawing Amps. */
2171 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2172 ASIC_REV_5714) {
2173 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2174 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2175 grc_local_ctrl, 100);
2176 }
2177
2178 /* On 5753 and variants, GPIO2 cannot be used. */
2179 no_gpio2 = tp->nic_sram_data_cfg &
2180 NIC_SRAM_DATA_CFG_NO_GPIO2;
2181
2182 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2183 GRC_LCLCTRL_GPIO_OE1 |
2184 GRC_LCLCTRL_GPIO_OE2 |
2185 GRC_LCLCTRL_GPIO_OUTPUT1 |
2186 GRC_LCLCTRL_GPIO_OUTPUT2;
2187 if (no_gpio2) {
2188 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2189 GRC_LCLCTRL_GPIO_OUTPUT2);
2190 }
2191 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2192 grc_local_ctrl, 100);
2193
2194 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2195
2196 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2197 grc_local_ctrl, 100);
2198
2199 if (!no_gpio2) {
2200 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2201 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2202 grc_local_ctrl, 100);
2203 }
2204 }
2205 } else {
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2207 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2208 if (tp_peer != tp &&
2209 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2210 return;
2211
2212 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2213 (GRC_LCLCTRL_GPIO_OE1 |
2214 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2215
2216 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2217 GRC_LCLCTRL_GPIO_OE1, 100);
2218
2219 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2220 (GRC_LCLCTRL_GPIO_OE1 |
2221 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2222 }
2223 }
2224 }
2225
2226 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2227 {
2228 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2229 return 1;
2230 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2231 if (speed != SPEED_10)
2232 return 1;
2233 } else if (speed == SPEED_10)
2234 return 1;
2235
2236 return 0;
2237 }
2238
2239 static int tg3_setup_phy(struct tg3 *, int);
2240
2241 #define RESET_KIND_SHUTDOWN 0
2242 #define RESET_KIND_INIT 1
2243 #define RESET_KIND_SUSPEND 2
2244
2245 static void tg3_write_sig_post_reset(struct tg3 *, int);
2246 static int tg3_halt_cpu(struct tg3 *, u32);
2247
2248 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2249 {
2250 u32 val;
2251
2252 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2254 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2255 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2256
2257 sg_dig_ctrl |=
2258 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2259 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2260 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2261 }
2262 return;
2263 }
2264
2265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2266 tg3_bmcr_reset(tp);
2267 val = tr32(GRC_MISC_CFG);
2268 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2269 udelay(40);
2270 return;
2271 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2272 u32 phytest;
2273 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2274 u32 phy;
2275
2276 tg3_writephy(tp, MII_ADVERTISE, 0);
2277 tg3_writephy(tp, MII_BMCR,
2278 BMCR_ANENABLE | BMCR_ANRESTART);
2279
2280 tg3_writephy(tp, MII_TG3_FET_TEST,
2281 phytest | MII_TG3_FET_SHADOW_EN);
2282 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2283 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2284 tg3_writephy(tp,
2285 MII_TG3_FET_SHDW_AUXMODE4,
2286 phy);
2287 }
2288 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2289 }
2290 return;
2291 } else if (do_low_power) {
2292 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2293 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2294
2295 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2296 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2297 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2298 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2299 MII_TG3_AUXCTL_PCTL_VREG_11V);
2300 }
2301
2302 /* The PHY should not be powered down on some chips because
2303 * of bugs.
2304 */
2305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2308 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2309 return;
2310
2311 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2312 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2313 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2314 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2315 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2316 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2317 }
2318
2319 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2320 }
2321
2322 /* tp->lock is held. */
2323 static int tg3_nvram_lock(struct tg3 *tp)
2324 {
2325 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2326 int i;
2327
2328 if (tp->nvram_lock_cnt == 0) {
2329 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2330 for (i = 0; i < 8000; i++) {
2331 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2332 break;
2333 udelay(20);
2334 }
2335 if (i == 8000) {
2336 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2337 return -ENODEV;
2338 }
2339 }
2340 tp->nvram_lock_cnt++;
2341 }
2342 return 0;
2343 }
2344
2345 /* tp->lock is held. */
2346 static void tg3_nvram_unlock(struct tg3 *tp)
2347 {
2348 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2349 if (tp->nvram_lock_cnt > 0)
2350 tp->nvram_lock_cnt--;
2351 if (tp->nvram_lock_cnt == 0)
2352 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2353 }
2354 }
2355
2356 /* tp->lock is held. */
2357 static void tg3_enable_nvram_access(struct tg3 *tp)
2358 {
2359 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2361 u32 nvaccess = tr32(NVRAM_ACCESS);
2362
2363 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2364 }
2365 }
2366
2367 /* tp->lock is held. */
2368 static void tg3_disable_nvram_access(struct tg3 *tp)
2369 {
2370 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2371 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2372 u32 nvaccess = tr32(NVRAM_ACCESS);
2373
2374 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2375 }
2376 }
2377
2378 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2379 u32 offset, u32 *val)
2380 {
2381 u32 tmp;
2382 int i;
2383
2384 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2385 return -EINVAL;
2386
2387 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2388 EEPROM_ADDR_DEVID_MASK |
2389 EEPROM_ADDR_READ);
2390 tw32(GRC_EEPROM_ADDR,
2391 tmp |
2392 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2393 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2394 EEPROM_ADDR_ADDR_MASK) |
2395 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2396
2397 for (i = 0; i < 1000; i++) {
2398 tmp = tr32(GRC_EEPROM_ADDR);
2399
2400 if (tmp & EEPROM_ADDR_COMPLETE)
2401 break;
2402 msleep(1);
2403 }
2404 if (!(tmp & EEPROM_ADDR_COMPLETE))
2405 return -EBUSY;
2406
2407 tmp = tr32(GRC_EEPROM_DATA);
2408
2409 /*
2410 * The data will always be opposite the native endian
2411 * format. Perform a blind byteswap to compensate.
2412 */
2413 *val = swab32(tmp);
2414
2415 return 0;
2416 }
2417
2418 #define NVRAM_CMD_TIMEOUT 10000
2419
2420 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2421 {
2422 int i;
2423
2424 tw32(NVRAM_CMD, nvram_cmd);
2425 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2426 udelay(10);
2427 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2428 udelay(10);
2429 break;
2430 }
2431 }
2432
2433 if (i == NVRAM_CMD_TIMEOUT)
2434 return -EBUSY;
2435
2436 return 0;
2437 }
2438
2439 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2440 {
2441 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2442 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2443 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2444 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2445 (tp->nvram_jedecnum == JEDEC_ATMEL))
2446
2447 addr = ((addr / tp->nvram_pagesize) <<
2448 ATMEL_AT45DB0X1B_PAGE_POS) +
2449 (addr % tp->nvram_pagesize);
2450
2451 return addr;
2452 }
2453
2454 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2455 {
2456 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2457 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2458 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2459 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2460 (tp->nvram_jedecnum == JEDEC_ATMEL))
2461
2462 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2463 tp->nvram_pagesize) +
2464 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2465
2466 return addr;
2467 }
2468
2469 /* NOTE: Data read in from NVRAM is byteswapped according to
2470 * the byteswapping settings for all other register accesses.
2471 * tg3 devices are BE devices, so on a BE machine, the data
2472 * returned will be exactly as it is seen in NVRAM. On a LE
2473 * machine, the 32-bit value will be byteswapped.
2474 */
2475 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2476 {
2477 int ret;
2478
2479 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2480 return tg3_nvram_read_using_eeprom(tp, offset, val);
2481
2482 offset = tg3_nvram_phys_addr(tp, offset);
2483
2484 if (offset > NVRAM_ADDR_MSK)
2485 return -EINVAL;
2486
2487 ret = tg3_nvram_lock(tp);
2488 if (ret)
2489 return ret;
2490
2491 tg3_enable_nvram_access(tp);
2492
2493 tw32(NVRAM_ADDR, offset);
2494 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2495 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2496
2497 if (ret == 0)
2498 *val = tr32(NVRAM_RDDATA);
2499
2500 tg3_disable_nvram_access(tp);
2501
2502 tg3_nvram_unlock(tp);
2503
2504 return ret;
2505 }
2506
2507 /* Ensures NVRAM data is in bytestream format. */
2508 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2509 {
2510 u32 v;
2511 int res = tg3_nvram_read(tp, offset, &v);
2512 if (!res)
2513 *val = cpu_to_be32(v);
2514 return res;
2515 }
2516
2517 /* tp->lock is held. */
2518 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2519 {
2520 u32 addr_high, addr_low;
2521 int i;
2522
2523 addr_high = ((tp->dev->dev_addr[0] << 8) |
2524 tp->dev->dev_addr[1]);
2525 addr_low = ((tp->dev->dev_addr[2] << 24) |
2526 (tp->dev->dev_addr[3] << 16) |
2527 (tp->dev->dev_addr[4] << 8) |
2528 (tp->dev->dev_addr[5] << 0));
2529 for (i = 0; i < 4; i++) {
2530 if (i == 1 && skip_mac_1)
2531 continue;
2532 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2533 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2534 }
2535
2536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2538 for (i = 0; i < 12; i++) {
2539 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2540 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2541 }
2542 }
2543
2544 addr_high = (tp->dev->dev_addr[0] +
2545 tp->dev->dev_addr[1] +
2546 tp->dev->dev_addr[2] +
2547 tp->dev->dev_addr[3] +
2548 tp->dev->dev_addr[4] +
2549 tp->dev->dev_addr[5]) &
2550 TX_BACKOFF_SEED_MASK;
2551 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2552 }
2553
2554 static void tg3_enable_register_access(struct tg3 *tp)
2555 {
2556 /*
2557 * Make sure register accesses (indirect or otherwise) will function
2558 * correctly.
2559 */
2560 pci_write_config_dword(tp->pdev,
2561 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2562 }
2563
2564 static int tg3_power_up(struct tg3 *tp)
2565 {
2566 tg3_enable_register_access(tp);
2567
2568 pci_set_power_state(tp->pdev, PCI_D0);
2569
2570 /* Switch out of Vaux if it is a NIC */
2571 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2572 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2573
2574 return 0;
2575 }
2576
2577 static int tg3_power_down_prepare(struct tg3 *tp)
2578 {
2579 u32 misc_host_ctrl;
2580 bool device_should_wake, do_low_power;
2581
2582 tg3_enable_register_access(tp);
2583
2584 /* Restore the CLKREQ setting. */
2585 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2586 u16 lnkctl;
2587
2588 pci_read_config_word(tp->pdev,
2589 tp->pcie_cap + PCI_EXP_LNKCTL,
2590 &lnkctl);
2591 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2592 pci_write_config_word(tp->pdev,
2593 tp->pcie_cap + PCI_EXP_LNKCTL,
2594 lnkctl);
2595 }
2596
2597 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2598 tw32(TG3PCI_MISC_HOST_CTRL,
2599 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2600
2601 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2602 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2603
2604 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2605 do_low_power = false;
2606 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2607 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2608 struct phy_device *phydev;
2609 u32 phyid, advertising;
2610
2611 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2612
2613 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2614
2615 tp->link_config.orig_speed = phydev->speed;
2616 tp->link_config.orig_duplex = phydev->duplex;
2617 tp->link_config.orig_autoneg = phydev->autoneg;
2618 tp->link_config.orig_advertising = phydev->advertising;
2619
2620 advertising = ADVERTISED_TP |
2621 ADVERTISED_Pause |
2622 ADVERTISED_Autoneg |
2623 ADVERTISED_10baseT_Half;
2624
2625 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2626 device_should_wake) {
2627 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2628 advertising |=
2629 ADVERTISED_100baseT_Half |
2630 ADVERTISED_100baseT_Full |
2631 ADVERTISED_10baseT_Full;
2632 else
2633 advertising |= ADVERTISED_10baseT_Full;
2634 }
2635
2636 phydev->advertising = advertising;
2637
2638 phy_start_aneg(phydev);
2639
2640 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2641 if (phyid != PHY_ID_BCMAC131) {
2642 phyid &= PHY_BCM_OUI_MASK;
2643 if (phyid == PHY_BCM_OUI_1 ||
2644 phyid == PHY_BCM_OUI_2 ||
2645 phyid == PHY_BCM_OUI_3)
2646 do_low_power = true;
2647 }
2648 }
2649 } else {
2650 do_low_power = true;
2651
2652 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2653 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2654 tp->link_config.orig_speed = tp->link_config.speed;
2655 tp->link_config.orig_duplex = tp->link_config.duplex;
2656 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2657 }
2658
2659 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2660 tp->link_config.speed = SPEED_10;
2661 tp->link_config.duplex = DUPLEX_HALF;
2662 tp->link_config.autoneg = AUTONEG_ENABLE;
2663 tg3_setup_phy(tp, 0);
2664 }
2665 }
2666
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2668 u32 val;
2669
2670 val = tr32(GRC_VCPU_EXT_CTRL);
2671 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2672 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2673 int i;
2674 u32 val;
2675
2676 for (i = 0; i < 200; i++) {
2677 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2678 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2679 break;
2680 msleep(1);
2681 }
2682 }
2683 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2684 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2685 WOL_DRV_STATE_SHUTDOWN |
2686 WOL_DRV_WOL |
2687 WOL_SET_MAGIC_PKT);
2688
2689 if (device_should_wake) {
2690 u32 mac_mode;
2691
2692 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2693 if (do_low_power) {
2694 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2695 udelay(40);
2696 }
2697
2698 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2699 mac_mode = MAC_MODE_PORT_MODE_GMII;
2700 else
2701 mac_mode = MAC_MODE_PORT_MODE_MII;
2702
2703 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2704 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2705 ASIC_REV_5700) {
2706 u32 speed = (tp->tg3_flags &
2707 TG3_FLAG_WOL_SPEED_100MB) ?
2708 SPEED_100 : SPEED_10;
2709 if (tg3_5700_link_polarity(tp, speed))
2710 mac_mode |= MAC_MODE_LINK_POLARITY;
2711 else
2712 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2713 }
2714 } else {
2715 mac_mode = MAC_MODE_PORT_MODE_TBI;
2716 }
2717
2718 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2719 tw32(MAC_LED_CTRL, tp->led_ctrl);
2720
2721 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2722 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2723 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2724 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2725 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2726 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2727
2728 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2729 mac_mode |= MAC_MODE_APE_TX_EN |
2730 MAC_MODE_APE_RX_EN |
2731 MAC_MODE_TDE_ENABLE;
2732
2733 tw32_f(MAC_MODE, mac_mode);
2734 udelay(100);
2735
2736 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2737 udelay(10);
2738 }
2739
2740 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2741 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2742 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2743 u32 base_val;
2744
2745 base_val = tp->pci_clock_ctrl;
2746 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2747 CLOCK_CTRL_TXCLK_DISABLE);
2748
2749 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2750 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2751 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2752 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2754 /* do nothing */
2755 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2756 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2757 u32 newbits1, newbits2;
2758
2759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2760 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2761 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2762 CLOCK_CTRL_TXCLK_DISABLE |
2763 CLOCK_CTRL_ALTCLK);
2764 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2765 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2766 newbits1 = CLOCK_CTRL_625_CORE;
2767 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2768 } else {
2769 newbits1 = CLOCK_CTRL_ALTCLK;
2770 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2771 }
2772
2773 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2774 40);
2775
2776 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2777 40);
2778
2779 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2780 u32 newbits3;
2781
2782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2784 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2785 CLOCK_CTRL_TXCLK_DISABLE |
2786 CLOCK_CTRL_44MHZ_CORE);
2787 } else {
2788 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2789 }
2790
2791 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2792 tp->pci_clock_ctrl | newbits3, 40);
2793 }
2794 }
2795
2796 if (!(device_should_wake) &&
2797 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2798 tg3_power_down_phy(tp, do_low_power);
2799
2800 tg3_frob_aux_power(tp);
2801
2802 /* Workaround for unstable PLL clock */
2803 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2804 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2805 u32 val = tr32(0x7d00);
2806
2807 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2808 tw32(0x7d00, val);
2809 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2810 int err;
2811
2812 err = tg3_nvram_lock(tp);
2813 tg3_halt_cpu(tp, RX_CPU_BASE);
2814 if (!err)
2815 tg3_nvram_unlock(tp);
2816 }
2817 }
2818
2819 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2820
2821 return 0;
2822 }
2823
2824 static void tg3_power_down(struct tg3 *tp)
2825 {
2826 tg3_power_down_prepare(tp);
2827
2828 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2829 pci_set_power_state(tp->pdev, PCI_D3hot);
2830 }
2831
2832 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2833 {
2834 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2835 case MII_TG3_AUX_STAT_10HALF:
2836 *speed = SPEED_10;
2837 *duplex = DUPLEX_HALF;
2838 break;
2839
2840 case MII_TG3_AUX_STAT_10FULL:
2841 *speed = SPEED_10;
2842 *duplex = DUPLEX_FULL;
2843 break;
2844
2845 case MII_TG3_AUX_STAT_100HALF:
2846 *speed = SPEED_100;
2847 *duplex = DUPLEX_HALF;
2848 break;
2849
2850 case MII_TG3_AUX_STAT_100FULL:
2851 *speed = SPEED_100;
2852 *duplex = DUPLEX_FULL;
2853 break;
2854
2855 case MII_TG3_AUX_STAT_1000HALF:
2856 *speed = SPEED_1000;
2857 *duplex = DUPLEX_HALF;
2858 break;
2859
2860 case MII_TG3_AUX_STAT_1000FULL:
2861 *speed = SPEED_1000;
2862 *duplex = DUPLEX_FULL;
2863 break;
2864
2865 default:
2866 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2867 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2868 SPEED_10;
2869 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2870 DUPLEX_HALF;
2871 break;
2872 }
2873 *speed = SPEED_INVALID;
2874 *duplex = DUPLEX_INVALID;
2875 break;
2876 }
2877 }
2878
2879 static void tg3_phy_copper_begin(struct tg3 *tp)
2880 {
2881 u32 new_adv;
2882 int i;
2883
2884 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2885 /* Entering low power mode. Disable gigabit and
2886 * 100baseT advertisements.
2887 */
2888 tg3_writephy(tp, MII_TG3_CTRL, 0);
2889
2890 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2891 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2892 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2893 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2894
2895 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2896 } else if (tp->link_config.speed == SPEED_INVALID) {
2897 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2898 tp->link_config.advertising &=
2899 ~(ADVERTISED_1000baseT_Half |
2900 ADVERTISED_1000baseT_Full);
2901
2902 new_adv = ADVERTISE_CSMA;
2903 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2904 new_adv |= ADVERTISE_10HALF;
2905 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2906 new_adv |= ADVERTISE_10FULL;
2907 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2908 new_adv |= ADVERTISE_100HALF;
2909 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2910 new_adv |= ADVERTISE_100FULL;
2911
2912 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2913
2914 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2915
2916 if (tp->link_config.advertising &
2917 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2918 new_adv = 0;
2919 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2920 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2921 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2922 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2923 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2924 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2925 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2926 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2927 MII_TG3_CTRL_ENABLE_AS_MASTER);
2928 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2929 } else {
2930 tg3_writephy(tp, MII_TG3_CTRL, 0);
2931 }
2932 } else {
2933 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2934 new_adv |= ADVERTISE_CSMA;
2935
2936 /* Asking for a specific link mode. */
2937 if (tp->link_config.speed == SPEED_1000) {
2938 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2939
2940 if (tp->link_config.duplex == DUPLEX_FULL)
2941 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2942 else
2943 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2944 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2945 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2946 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2947 MII_TG3_CTRL_ENABLE_AS_MASTER);
2948 } else {
2949 if (tp->link_config.speed == SPEED_100) {
2950 if (tp->link_config.duplex == DUPLEX_FULL)
2951 new_adv |= ADVERTISE_100FULL;
2952 else
2953 new_adv |= ADVERTISE_100HALF;
2954 } else {
2955 if (tp->link_config.duplex == DUPLEX_FULL)
2956 new_adv |= ADVERTISE_10FULL;
2957 else
2958 new_adv |= ADVERTISE_10HALF;
2959 }
2960 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2961
2962 new_adv = 0;
2963 }
2964
2965 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2966 }
2967
2968 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2969 u32 val;
2970
2971 tw32(TG3_CPMU_EEE_MODE,
2972 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2973
2974 /* Enable SM_DSP clock and tx 6dB coding. */
2975 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2976 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2977 MII_TG3_AUXCTL_ACTL_TX_6DB;
2978 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2979
2980 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2982 !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2983 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2984 val | MII_TG3_DSP_CH34TP2_HIBW01);
2985
2986 val = 0;
2987 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2988 /* Advertise 100-BaseTX EEE ability */
2989 if (tp->link_config.advertising &
2990 ADVERTISED_100baseT_Full)
2991 val |= MDIO_AN_EEE_ADV_100TX;
2992 /* Advertise 1000-BaseT EEE ability */
2993 if (tp->link_config.advertising &
2994 ADVERTISED_1000baseT_Full)
2995 val |= MDIO_AN_EEE_ADV_1000T;
2996 }
2997 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2998
2999 /* Turn off SM_DSP clock. */
3000 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3001 MII_TG3_AUXCTL_ACTL_TX_6DB;
3002 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3003 }
3004
3005 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3006 tp->link_config.speed != SPEED_INVALID) {
3007 u32 bmcr, orig_bmcr;
3008
3009 tp->link_config.active_speed = tp->link_config.speed;
3010 tp->link_config.active_duplex = tp->link_config.duplex;
3011
3012 bmcr = 0;
3013 switch (tp->link_config.speed) {
3014 default:
3015 case SPEED_10:
3016 break;
3017
3018 case SPEED_100:
3019 bmcr |= BMCR_SPEED100;
3020 break;
3021
3022 case SPEED_1000:
3023 bmcr |= TG3_BMCR_SPEED1000;
3024 break;
3025 }
3026
3027 if (tp->link_config.duplex == DUPLEX_FULL)
3028 bmcr |= BMCR_FULLDPLX;
3029
3030 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3031 (bmcr != orig_bmcr)) {
3032 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3033 for (i = 0; i < 1500; i++) {
3034 u32 tmp;
3035
3036 udelay(10);
3037 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3038 tg3_readphy(tp, MII_BMSR, &tmp))
3039 continue;
3040 if (!(tmp & BMSR_LSTATUS)) {
3041 udelay(40);
3042 break;
3043 }
3044 }
3045 tg3_writephy(tp, MII_BMCR, bmcr);
3046 udelay(40);
3047 }
3048 } else {
3049 tg3_writephy(tp, MII_BMCR,
3050 BMCR_ANENABLE | BMCR_ANRESTART);
3051 }
3052 }
3053
3054 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3055 {
3056 int err;
3057
3058 /* Turn off tap power management. */
3059 /* Set Extended packet length bit */
3060 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3061
3062 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3063 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3064 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3065 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3066 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3067
3068 udelay(40);
3069
3070 return err;
3071 }
3072
3073 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3074 {
3075 u32 adv_reg, all_mask = 0;
3076
3077 if (mask & ADVERTISED_10baseT_Half)
3078 all_mask |= ADVERTISE_10HALF;
3079 if (mask & ADVERTISED_10baseT_Full)
3080 all_mask |= ADVERTISE_10FULL;
3081 if (mask & ADVERTISED_100baseT_Half)
3082 all_mask |= ADVERTISE_100HALF;
3083 if (mask & ADVERTISED_100baseT_Full)
3084 all_mask |= ADVERTISE_100FULL;
3085
3086 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3087 return 0;
3088
3089 if ((adv_reg & all_mask) != all_mask)
3090 return 0;
3091 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3092 u32 tg3_ctrl;
3093
3094 all_mask = 0;
3095 if (mask & ADVERTISED_1000baseT_Half)
3096 all_mask |= ADVERTISE_1000HALF;
3097 if (mask & ADVERTISED_1000baseT_Full)
3098 all_mask |= ADVERTISE_1000FULL;
3099
3100 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3101 return 0;
3102
3103 if ((tg3_ctrl & all_mask) != all_mask)
3104 return 0;
3105 }
3106 return 1;
3107 }
3108
3109 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3110 {
3111 u32 curadv, reqadv;
3112
3113 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3114 return 1;
3115
3116 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3117 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3118
3119 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3120 if (curadv != reqadv)
3121 return 0;
3122
3123 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3124 tg3_readphy(tp, MII_LPA, rmtadv);
3125 } else {
3126 /* Reprogram the advertisement register, even if it
3127 * does not affect the current link. If the link
3128 * gets renegotiated in the future, we can save an
3129 * additional renegotiation cycle by advertising
3130 * it correctly in the first place.
3131 */
3132 if (curadv != reqadv) {
3133 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3134 ADVERTISE_PAUSE_ASYM);
3135 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3136 }
3137 }
3138
3139 return 1;
3140 }
3141
3142 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3143 {
3144 int current_link_up;
3145 u32 bmsr, val;
3146 u32 lcl_adv, rmt_adv;
3147 u16 current_speed;
3148 u8 current_duplex;
3149 int i, err;
3150
3151 tw32(MAC_EVENT, 0);
3152
3153 tw32_f(MAC_STATUS,
3154 (MAC_STATUS_SYNC_CHANGED |
3155 MAC_STATUS_CFG_CHANGED |
3156 MAC_STATUS_MI_COMPLETION |
3157 MAC_STATUS_LNKSTATE_CHANGED));
3158 udelay(40);
3159
3160 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3161 tw32_f(MAC_MI_MODE,
3162 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3163 udelay(80);
3164 }
3165
3166 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3167
3168 /* Some third-party PHYs need to be reset on link going
3169 * down.
3170 */
3171 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3174 netif_carrier_ok(tp->dev)) {
3175 tg3_readphy(tp, MII_BMSR, &bmsr);
3176 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3177 !(bmsr & BMSR_LSTATUS))
3178 force_reset = 1;
3179 }
3180 if (force_reset)
3181 tg3_phy_reset(tp);
3182
3183 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3184 tg3_readphy(tp, MII_BMSR, &bmsr);
3185 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3186 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3187 bmsr = 0;
3188
3189 if (!(bmsr & BMSR_LSTATUS)) {
3190 err = tg3_init_5401phy_dsp(tp);
3191 if (err)
3192 return err;
3193
3194 tg3_readphy(tp, MII_BMSR, &bmsr);
3195 for (i = 0; i < 1000; i++) {
3196 udelay(10);
3197 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3198 (bmsr & BMSR_LSTATUS)) {
3199 udelay(40);
3200 break;
3201 }
3202 }
3203
3204 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3205 TG3_PHY_REV_BCM5401_B0 &&
3206 !(bmsr & BMSR_LSTATUS) &&
3207 tp->link_config.active_speed == SPEED_1000) {
3208 err = tg3_phy_reset(tp);
3209 if (!err)
3210 err = tg3_init_5401phy_dsp(tp);
3211 if (err)
3212 return err;
3213 }
3214 }
3215 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3216 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3217 /* 5701 {A0,B0} CRC bug workaround */
3218 tg3_writephy(tp, 0x15, 0x0a75);
3219 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3220 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3221 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3222 }
3223
3224 /* Clear pending interrupts... */
3225 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3226 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3227
3228 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3229 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3230 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3231 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3232
3233 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3234 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3235 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3236 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3237 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3238 else
3239 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3240 }
3241
3242 current_link_up = 0;
3243 current_speed = SPEED_INVALID;
3244 current_duplex = DUPLEX_INVALID;
3245
3246 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3247 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3248 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3249 if (!(val & (1 << 10))) {
3250 val |= (1 << 10);
3251 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3252 goto relink;
3253 }
3254 }
3255
3256 bmsr = 0;
3257 for (i = 0; i < 100; i++) {
3258 tg3_readphy(tp, MII_BMSR, &bmsr);
3259 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3260 (bmsr & BMSR_LSTATUS))
3261 break;
3262 udelay(40);
3263 }
3264
3265 if (bmsr & BMSR_LSTATUS) {
3266 u32 aux_stat, bmcr;
3267
3268 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3269 for (i = 0; i < 2000; i++) {
3270 udelay(10);
3271 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3272 aux_stat)
3273 break;
3274 }
3275
3276 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3277 &current_speed,
3278 &current_duplex);
3279
3280 bmcr = 0;
3281 for (i = 0; i < 200; i++) {
3282 tg3_readphy(tp, MII_BMCR, &bmcr);
3283 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3284 continue;
3285 if (bmcr && bmcr != 0x7fff)
3286 break;
3287 udelay(10);
3288 }
3289
3290 lcl_adv = 0;
3291 rmt_adv = 0;
3292
3293 tp->link_config.active_speed = current_speed;
3294 tp->link_config.active_duplex = current_duplex;
3295
3296 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3297 if ((bmcr & BMCR_ANENABLE) &&
3298 tg3_copper_is_advertising_all(tp,
3299 tp->link_config.advertising)) {
3300 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3301 &rmt_adv))
3302 current_link_up = 1;
3303 }
3304 } else {
3305 if (!(bmcr & BMCR_ANENABLE) &&
3306 tp->link_config.speed == current_speed &&
3307 tp->link_config.duplex == current_duplex &&
3308 tp->link_config.flowctrl ==
3309 tp->link_config.active_flowctrl) {
3310 current_link_up = 1;
3311 }
3312 }
3313
3314 if (current_link_up == 1 &&
3315 tp->link_config.active_duplex == DUPLEX_FULL)
3316 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3317 }
3318
3319 relink:
3320 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3321 tg3_phy_copper_begin(tp);
3322
3323 tg3_readphy(tp, MII_BMSR, &bmsr);
3324 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3325 (bmsr & BMSR_LSTATUS))
3326 current_link_up = 1;
3327 }
3328
3329 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3330 if (current_link_up == 1) {
3331 if (tp->link_config.active_speed == SPEED_100 ||
3332 tp->link_config.active_speed == SPEED_10)
3333 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3334 else
3335 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3336 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3337 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338 else
3339 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340
3341 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3342 if (tp->link_config.active_duplex == DUPLEX_HALF)
3343 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3344
3345 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3346 if (current_link_up == 1 &&
3347 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3348 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3349 else
3350 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3351 }
3352
3353 /* ??? Without this setting Netgear GA302T PHY does not
3354 * ??? send/receive packets...
3355 */
3356 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3357 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3358 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3359 tw32_f(MAC_MI_MODE, tp->mi_mode);
3360 udelay(80);
3361 }
3362
3363 tw32_f(MAC_MODE, tp->mac_mode);
3364 udelay(40);
3365
3366 tg3_phy_eee_adjust(tp, current_link_up);
3367
3368 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3369 /* Polled via timer. */
3370 tw32_f(MAC_EVENT, 0);
3371 } else {
3372 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3373 }
3374 udelay(40);
3375
3376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3377 current_link_up == 1 &&
3378 tp->link_config.active_speed == SPEED_1000 &&
3379 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3380 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3381 udelay(120);
3382 tw32_f(MAC_STATUS,
3383 (MAC_STATUS_SYNC_CHANGED |
3384 MAC_STATUS_CFG_CHANGED));
3385 udelay(40);
3386 tg3_write_mem(tp,
3387 NIC_SRAM_FIRMWARE_MBOX,
3388 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3389 }
3390
3391 /* Prevent send BD corruption. */
3392 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3393 u16 oldlnkctl, newlnkctl;
3394
3395 pci_read_config_word(tp->pdev,
3396 tp->pcie_cap + PCI_EXP_LNKCTL,
3397 &oldlnkctl);
3398 if (tp->link_config.active_speed == SPEED_100 ||
3399 tp->link_config.active_speed == SPEED_10)
3400 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3401 else
3402 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3403 if (newlnkctl != oldlnkctl)
3404 pci_write_config_word(tp->pdev,
3405 tp->pcie_cap + PCI_EXP_LNKCTL,
3406 newlnkctl);
3407 }
3408
3409 if (current_link_up != netif_carrier_ok(tp->dev)) {
3410 if (current_link_up)
3411 netif_carrier_on(tp->dev);
3412 else
3413 netif_carrier_off(tp->dev);
3414 tg3_link_report(tp);
3415 }
3416
3417 return 0;
3418 }
3419
3420 struct tg3_fiber_aneginfo {
3421 int state;
3422 #define ANEG_STATE_UNKNOWN 0
3423 #define ANEG_STATE_AN_ENABLE 1
3424 #define ANEG_STATE_RESTART_INIT 2
3425 #define ANEG_STATE_RESTART 3
3426 #define ANEG_STATE_DISABLE_LINK_OK 4
3427 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3428 #define ANEG_STATE_ABILITY_DETECT 6
3429 #define ANEG_STATE_ACK_DETECT_INIT 7
3430 #define ANEG_STATE_ACK_DETECT 8
3431 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3432 #define ANEG_STATE_COMPLETE_ACK 10
3433 #define ANEG_STATE_IDLE_DETECT_INIT 11
3434 #define ANEG_STATE_IDLE_DETECT 12
3435 #define ANEG_STATE_LINK_OK 13
3436 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3437 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3438
3439 u32 flags;
3440 #define MR_AN_ENABLE 0x00000001
3441 #define MR_RESTART_AN 0x00000002
3442 #define MR_AN_COMPLETE 0x00000004
3443 #define MR_PAGE_RX 0x00000008
3444 #define MR_NP_LOADED 0x00000010
3445 #define MR_TOGGLE_TX 0x00000020
3446 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3447 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3448 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3449 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3450 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3451 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3452 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3453 #define MR_TOGGLE_RX 0x00002000
3454 #define MR_NP_RX 0x00004000
3455
3456 #define MR_LINK_OK 0x80000000
3457
3458 unsigned long link_time, cur_time;
3459
3460 u32 ability_match_cfg;
3461 int ability_match_count;
3462
3463 char ability_match, idle_match, ack_match;
3464
3465 u32 txconfig, rxconfig;
3466 #define ANEG_CFG_NP 0x00000080
3467 #define ANEG_CFG_ACK 0x00000040
3468 #define ANEG_CFG_RF2 0x00000020
3469 #define ANEG_CFG_RF1 0x00000010
3470 #define ANEG_CFG_PS2 0x00000001
3471 #define ANEG_CFG_PS1 0x00008000
3472 #define ANEG_CFG_HD 0x00004000
3473 #define ANEG_CFG_FD 0x00002000
3474 #define ANEG_CFG_INVAL 0x00001f06
3475
3476 };
3477 #define ANEG_OK 0
3478 #define ANEG_DONE 1
3479 #define ANEG_TIMER_ENAB 2
3480 #define ANEG_FAILED -1
3481
3482 #define ANEG_STATE_SETTLE_TIME 10000
3483
3484 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3485 struct tg3_fiber_aneginfo *ap)
3486 {
3487 u16 flowctrl;
3488 unsigned long delta;
3489 u32 rx_cfg_reg;
3490 int ret;
3491
3492 if (ap->state == ANEG_STATE_UNKNOWN) {
3493 ap->rxconfig = 0;
3494 ap->link_time = 0;
3495 ap->cur_time = 0;
3496 ap->ability_match_cfg = 0;
3497 ap->ability_match_count = 0;
3498 ap->ability_match = 0;
3499 ap->idle_match = 0;
3500 ap->ack_match = 0;
3501 }
3502 ap->cur_time++;
3503
3504 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3505 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3506
3507 if (rx_cfg_reg != ap->ability_match_cfg) {
3508 ap->ability_match_cfg = rx_cfg_reg;
3509 ap->ability_match = 0;
3510 ap->ability_match_count = 0;
3511 } else {
3512 if (++ap->ability_match_count > 1) {
3513 ap->ability_match = 1;
3514 ap->ability_match_cfg = rx_cfg_reg;
3515 }
3516 }
3517 if (rx_cfg_reg & ANEG_CFG_ACK)
3518 ap->ack_match = 1;
3519 else
3520 ap->ack_match = 0;
3521
3522 ap->idle_match = 0;
3523 } else {
3524 ap->idle_match = 1;
3525 ap->ability_match_cfg = 0;
3526 ap->ability_match_count = 0;
3527 ap->ability_match = 0;
3528 ap->ack_match = 0;
3529
3530 rx_cfg_reg = 0;
3531 }
3532
3533 ap->rxconfig = rx_cfg_reg;
3534 ret = ANEG_OK;
3535
3536 switch (ap->state) {
3537 case ANEG_STATE_UNKNOWN:
3538 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3539 ap->state = ANEG_STATE_AN_ENABLE;
3540
3541 /* fallthru */
3542 case ANEG_STATE_AN_ENABLE:
3543 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3544 if (ap->flags & MR_AN_ENABLE) {
3545 ap->link_time = 0;
3546 ap->cur_time = 0;
3547 ap->ability_match_cfg = 0;
3548 ap->ability_match_count = 0;
3549 ap->ability_match = 0;
3550 ap->idle_match = 0;
3551 ap->ack_match = 0;
3552
3553 ap->state = ANEG_STATE_RESTART_INIT;
3554 } else {
3555 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3556 }
3557 break;
3558
3559 case ANEG_STATE_RESTART_INIT:
3560 ap->link_time = ap->cur_time;
3561 ap->flags &= ~(MR_NP_LOADED);
3562 ap->txconfig = 0;
3563 tw32(MAC_TX_AUTO_NEG, 0);
3564 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3565 tw32_f(MAC_MODE, tp->mac_mode);
3566 udelay(40);
3567
3568 ret = ANEG_TIMER_ENAB;
3569 ap->state = ANEG_STATE_RESTART;
3570
3571 /* fallthru */
3572 case ANEG_STATE_RESTART:
3573 delta = ap->cur_time - ap->link_time;
3574 if (delta > ANEG_STATE_SETTLE_TIME)
3575 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3576 else
3577 ret = ANEG_TIMER_ENAB;
3578 break;
3579
3580 case ANEG_STATE_DISABLE_LINK_OK:
3581 ret = ANEG_DONE;
3582 break;
3583
3584 case ANEG_STATE_ABILITY_DETECT_INIT:
3585 ap->flags &= ~(MR_TOGGLE_TX);
3586 ap->txconfig = ANEG_CFG_FD;
3587 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3588 if (flowctrl & ADVERTISE_1000XPAUSE)
3589 ap->txconfig |= ANEG_CFG_PS1;
3590 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3591 ap->txconfig |= ANEG_CFG_PS2;
3592 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3593 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3594 tw32_f(MAC_MODE, tp->mac_mode);
3595 udelay(40);
3596
3597 ap->state = ANEG_STATE_ABILITY_DETECT;
3598 break;
3599
3600 case ANEG_STATE_ABILITY_DETECT:
3601 if (ap->ability_match != 0 && ap->rxconfig != 0)
3602 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3603 break;
3604
3605 case ANEG_STATE_ACK_DETECT_INIT:
3606 ap->txconfig |= ANEG_CFG_ACK;
3607 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3608 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3609 tw32_f(MAC_MODE, tp->mac_mode);
3610 udelay(40);
3611
3612 ap->state = ANEG_STATE_ACK_DETECT;
3613
3614 /* fallthru */
3615 case ANEG_STATE_ACK_DETECT:
3616 if (ap->ack_match != 0) {
3617 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3618 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3619 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3620 } else {
3621 ap->state = ANEG_STATE_AN_ENABLE;
3622 }
3623 } else if (ap->ability_match != 0 &&
3624 ap->rxconfig == 0) {
3625 ap->state = ANEG_STATE_AN_ENABLE;
3626 }
3627 break;
3628
3629 case ANEG_STATE_COMPLETE_ACK_INIT:
3630 if (ap->rxconfig & ANEG_CFG_INVAL) {
3631 ret = ANEG_FAILED;
3632 break;
3633 }
3634 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3635 MR_LP_ADV_HALF_DUPLEX |
3636 MR_LP_ADV_SYM_PAUSE |
3637 MR_LP_ADV_ASYM_PAUSE |
3638 MR_LP_ADV_REMOTE_FAULT1 |
3639 MR_LP_ADV_REMOTE_FAULT2 |
3640 MR_LP_ADV_NEXT_PAGE |
3641 MR_TOGGLE_RX |
3642 MR_NP_RX);
3643 if (ap->rxconfig & ANEG_CFG_FD)
3644 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3645 if (ap->rxconfig & ANEG_CFG_HD)
3646 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3647 if (ap->rxconfig & ANEG_CFG_PS1)
3648 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3649 if (ap->rxconfig & ANEG_CFG_PS2)
3650 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3651 if (ap->rxconfig & ANEG_CFG_RF1)
3652 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3653 if (ap->rxconfig & ANEG_CFG_RF2)
3654 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3655 if (ap->rxconfig & ANEG_CFG_NP)
3656 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3657
3658 ap->link_time = ap->cur_time;
3659
3660 ap->flags ^= (MR_TOGGLE_TX);
3661 if (ap->rxconfig & 0x0008)
3662 ap->flags |= MR_TOGGLE_RX;
3663 if (ap->rxconfig & ANEG_CFG_NP)
3664 ap->flags |= MR_NP_RX;
3665 ap->flags |= MR_PAGE_RX;
3666
3667 ap->state = ANEG_STATE_COMPLETE_ACK;
3668 ret = ANEG_TIMER_ENAB;
3669 break;
3670
3671 case ANEG_STATE_COMPLETE_ACK:
3672 if (ap->ability_match != 0 &&
3673 ap->rxconfig == 0) {
3674 ap->state = ANEG_STATE_AN_ENABLE;
3675 break;
3676 }
3677 delta = ap->cur_time - ap->link_time;
3678 if (delta > ANEG_STATE_SETTLE_TIME) {
3679 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3680 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3681 } else {
3682 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3683 !(ap->flags & MR_NP_RX)) {
3684 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685 } else {
3686 ret = ANEG_FAILED;
3687 }
3688 }
3689 }
3690 break;
3691
3692 case ANEG_STATE_IDLE_DETECT_INIT:
3693 ap->link_time = ap->cur_time;
3694 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3695 tw32_f(MAC_MODE, tp->mac_mode);
3696 udelay(40);
3697
3698 ap->state = ANEG_STATE_IDLE_DETECT;
3699 ret = ANEG_TIMER_ENAB;
3700 break;
3701
3702 case ANEG_STATE_IDLE_DETECT:
3703 if (ap->ability_match != 0 &&
3704 ap->rxconfig == 0) {
3705 ap->state = ANEG_STATE_AN_ENABLE;
3706 break;
3707 }
3708 delta = ap->cur_time - ap->link_time;
3709 if (delta > ANEG_STATE_SETTLE_TIME) {
3710 /* XXX another gem from the Broadcom driver :( */
3711 ap->state = ANEG_STATE_LINK_OK;
3712 }
3713 break;
3714
3715 case ANEG_STATE_LINK_OK:
3716 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3717 ret = ANEG_DONE;
3718 break;
3719
3720 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3721 /* ??? unimplemented */
3722 break;
3723
3724 case ANEG_STATE_NEXT_PAGE_WAIT:
3725 /* ??? unimplemented */
3726 break;
3727
3728 default:
3729 ret = ANEG_FAILED;
3730 break;
3731 }
3732
3733 return ret;
3734 }
3735
3736 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3737 {
3738 int res = 0;
3739 struct tg3_fiber_aneginfo aninfo;
3740 int status = ANEG_FAILED;
3741 unsigned int tick;
3742 u32 tmp;
3743
3744 tw32_f(MAC_TX_AUTO_NEG, 0);
3745
3746 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3747 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3748 udelay(40);
3749
3750 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3751 udelay(40);
3752
3753 memset(&aninfo, 0, sizeof(aninfo));
3754 aninfo.flags |= MR_AN_ENABLE;
3755 aninfo.state = ANEG_STATE_UNKNOWN;
3756 aninfo.cur_time = 0;
3757 tick = 0;
3758 while (++tick < 195000) {
3759 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3760 if (status == ANEG_DONE || status == ANEG_FAILED)
3761 break;
3762
3763 udelay(1);
3764 }
3765
3766 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3767 tw32_f(MAC_MODE, tp->mac_mode);
3768 udelay(40);
3769
3770 *txflags = aninfo.txconfig;
3771 *rxflags = aninfo.flags;
3772
3773 if (status == ANEG_DONE &&
3774 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3775 MR_LP_ADV_FULL_DUPLEX)))
3776 res = 1;
3777
3778 return res;
3779 }
3780
3781 static void tg3_init_bcm8002(struct tg3 *tp)
3782 {
3783 u32 mac_status = tr32(MAC_STATUS);
3784 int i;
3785
3786 /* Reset when initting first time or we have a link. */
3787 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3788 !(mac_status & MAC_STATUS_PCS_SYNCED))
3789 return;
3790
3791 /* Set PLL lock range. */
3792 tg3_writephy(tp, 0x16, 0x8007);
3793
3794 /* SW reset */
3795 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3796
3797 /* Wait for reset to complete. */
3798 /* XXX schedule_timeout() ... */
3799 for (i = 0; i < 500; i++)
3800 udelay(10);
3801
3802 /* Config mode; select PMA/Ch 1 regs. */
3803 tg3_writephy(tp, 0x10, 0x8411);
3804
3805 /* Enable auto-lock and comdet, select txclk for tx. */
3806 tg3_writephy(tp, 0x11, 0x0a10);
3807
3808 tg3_writephy(tp, 0x18, 0x00a0);
3809 tg3_writephy(tp, 0x16, 0x41ff);
3810
3811 /* Assert and deassert POR. */
3812 tg3_writephy(tp, 0x13, 0x0400);
3813 udelay(40);
3814 tg3_writephy(tp, 0x13, 0x0000);
3815
3816 tg3_writephy(tp, 0x11, 0x0a50);
3817 udelay(40);
3818 tg3_writephy(tp, 0x11, 0x0a10);
3819
3820 /* Wait for signal to stabilize */
3821 /* XXX schedule_timeout() ... */
3822 for (i = 0; i < 15000; i++)
3823 udelay(10);
3824
3825 /* Deselect the channel register so we can read the PHYID
3826 * later.
3827 */
3828 tg3_writephy(tp, 0x10, 0x8011);
3829 }
3830
3831 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3832 {
3833 u16 flowctrl;
3834 u32 sg_dig_ctrl, sg_dig_status;
3835 u32 serdes_cfg, expected_sg_dig_ctrl;
3836 int workaround, port_a;
3837 int current_link_up;
3838
3839 serdes_cfg = 0;
3840 expected_sg_dig_ctrl = 0;
3841 workaround = 0;
3842 port_a = 1;
3843 current_link_up = 0;
3844
3845 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3846 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3847 workaround = 1;
3848 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3849 port_a = 0;
3850
3851 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3852 /* preserve bits 20-23 for voltage regulator */
3853 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3854 }
3855
3856 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3857
3858 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3859 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3860 if (workaround) {
3861 u32 val = serdes_cfg;
3862
3863 if (port_a)
3864 val |= 0xc010000;
3865 else
3866 val |= 0x4010000;
3867 tw32_f(MAC_SERDES_CFG, val);
3868 }
3869
3870 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3871 }
3872 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3873 tg3_setup_flow_control(tp, 0, 0);
3874 current_link_up = 1;
3875 }
3876 goto out;
3877 }
3878
3879 /* Want auto-negotiation. */
3880 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3881
3882 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3883 if (flowctrl & ADVERTISE_1000XPAUSE)
3884 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3885 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3886 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3887
3888 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3889 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3890 tp->serdes_counter &&
3891 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3892 MAC_STATUS_RCVD_CFG)) ==
3893 MAC_STATUS_PCS_SYNCED)) {
3894 tp->serdes_counter--;
3895 current_link_up = 1;
3896 goto out;
3897 }
3898 restart_autoneg:
3899 if (workaround)
3900 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3901 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3902 udelay(5);
3903 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3904
3905 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3906 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3907 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3908 MAC_STATUS_SIGNAL_DET)) {
3909 sg_dig_status = tr32(SG_DIG_STATUS);
3910 mac_status = tr32(MAC_STATUS);
3911
3912 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3913 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3914 u32 local_adv = 0, remote_adv = 0;
3915
3916 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3917 local_adv |= ADVERTISE_1000XPAUSE;
3918 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3919 local_adv |= ADVERTISE_1000XPSE_ASYM;
3920
3921 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3922 remote_adv |= LPA_1000XPAUSE;
3923 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3924 remote_adv |= LPA_1000XPAUSE_ASYM;
3925
3926 tg3_setup_flow_control(tp, local_adv, remote_adv);
3927 current_link_up = 1;
3928 tp->serdes_counter = 0;
3929 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3930 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3931 if (tp->serdes_counter)
3932 tp->serdes_counter--;
3933 else {
3934 if (workaround) {
3935 u32 val = serdes_cfg;
3936
3937 if (port_a)
3938 val |= 0xc010000;
3939 else
3940 val |= 0x4010000;
3941
3942 tw32_f(MAC_SERDES_CFG, val);
3943 }
3944
3945 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3946 udelay(40);
3947
3948 /* Link parallel detection - link is up */
3949 /* only if we have PCS_SYNC and not */
3950 /* receiving config code words */
3951 mac_status = tr32(MAC_STATUS);
3952 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3953 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3954 tg3_setup_flow_control(tp, 0, 0);
3955 current_link_up = 1;
3956 tp->phy_flags |=
3957 TG3_PHYFLG_PARALLEL_DETECT;
3958 tp->serdes_counter =
3959 SERDES_PARALLEL_DET_TIMEOUT;
3960 } else
3961 goto restart_autoneg;
3962 }
3963 }
3964 } else {
3965 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3966 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3967 }
3968
3969 out:
3970 return current_link_up;
3971 }
3972
3973 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3974 {
3975 int current_link_up = 0;
3976
3977 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3978 goto out;
3979
3980 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3981 u32 txflags, rxflags;
3982 int i;
3983
3984 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3985 u32 local_adv = 0, remote_adv = 0;
3986
3987 if (txflags & ANEG_CFG_PS1)
3988 local_adv |= ADVERTISE_1000XPAUSE;
3989 if (txflags & ANEG_CFG_PS2)
3990 local_adv |= ADVERTISE_1000XPSE_ASYM;
3991
3992 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3993 remote_adv |= LPA_1000XPAUSE;
3994 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3995 remote_adv |= LPA_1000XPAUSE_ASYM;
3996
3997 tg3_setup_flow_control(tp, local_adv, remote_adv);
3998
3999 current_link_up = 1;
4000 }
4001 for (i = 0; i < 30; i++) {
4002 udelay(20);
4003 tw32_f(MAC_STATUS,
4004 (MAC_STATUS_SYNC_CHANGED |
4005 MAC_STATUS_CFG_CHANGED));
4006 udelay(40);
4007 if ((tr32(MAC_STATUS) &
4008 (MAC_STATUS_SYNC_CHANGED |
4009 MAC_STATUS_CFG_CHANGED)) == 0)
4010 break;
4011 }
4012
4013 mac_status = tr32(MAC_STATUS);
4014 if (current_link_up == 0 &&
4015 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4016 !(mac_status & MAC_STATUS_RCVD_CFG))
4017 current_link_up = 1;
4018 } else {
4019 tg3_setup_flow_control(tp, 0, 0);
4020
4021 /* Forcing 1000FD link up. */
4022 current_link_up = 1;
4023
4024 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4025 udelay(40);
4026
4027 tw32_f(MAC_MODE, tp->mac_mode);
4028 udelay(40);
4029 }
4030
4031 out:
4032 return current_link_up;
4033 }
4034
4035 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4036 {
4037 u32 orig_pause_cfg;
4038 u16 orig_active_speed;
4039 u8 orig_active_duplex;
4040 u32 mac_status;
4041 int current_link_up;
4042 int i;
4043
4044 orig_pause_cfg = tp->link_config.active_flowctrl;
4045 orig_active_speed = tp->link_config.active_speed;
4046 orig_active_duplex = tp->link_config.active_duplex;
4047
4048 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4049 netif_carrier_ok(tp->dev) &&
4050 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4051 mac_status = tr32(MAC_STATUS);
4052 mac_status &= (MAC_STATUS_PCS_SYNCED |
4053 MAC_STATUS_SIGNAL_DET |
4054 MAC_STATUS_CFG_CHANGED |
4055 MAC_STATUS_RCVD_CFG);
4056 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4057 MAC_STATUS_SIGNAL_DET)) {
4058 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4059 MAC_STATUS_CFG_CHANGED));
4060 return 0;
4061 }
4062 }
4063
4064 tw32_f(MAC_TX_AUTO_NEG, 0);
4065
4066 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4067 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4068 tw32_f(MAC_MODE, tp->mac_mode);
4069 udelay(40);
4070
4071 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4072 tg3_init_bcm8002(tp);
4073
4074 /* Enable link change event even when serdes polling. */
4075 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4076 udelay(40);
4077
4078 current_link_up = 0;
4079 mac_status = tr32(MAC_STATUS);
4080
4081 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4082 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4083 else
4084 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4085
4086 tp->napi[0].hw_status->status =
4087 (SD_STATUS_UPDATED |
4088 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4089
4090 for (i = 0; i < 100; i++) {
4091 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4092 MAC_STATUS_CFG_CHANGED));
4093 udelay(5);
4094 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4095 MAC_STATUS_CFG_CHANGED |
4096 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4097 break;
4098 }
4099
4100 mac_status = tr32(MAC_STATUS);
4101 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4102 current_link_up = 0;
4103 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4104 tp->serdes_counter == 0) {
4105 tw32_f(MAC_MODE, (tp->mac_mode |
4106 MAC_MODE_SEND_CONFIGS));
4107 udelay(1);
4108 tw32_f(MAC_MODE, tp->mac_mode);
4109 }
4110 }
4111
4112 if (current_link_up == 1) {
4113 tp->link_config.active_speed = SPEED_1000;
4114 tp->link_config.active_duplex = DUPLEX_FULL;
4115 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4116 LED_CTRL_LNKLED_OVERRIDE |
4117 LED_CTRL_1000MBPS_ON));
4118 } else {
4119 tp->link_config.active_speed = SPEED_INVALID;
4120 tp->link_config.active_duplex = DUPLEX_INVALID;
4121 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4122 LED_CTRL_LNKLED_OVERRIDE |
4123 LED_CTRL_TRAFFIC_OVERRIDE));
4124 }
4125
4126 if (current_link_up != netif_carrier_ok(tp->dev)) {
4127 if (current_link_up)
4128 netif_carrier_on(tp->dev);
4129 else
4130 netif_carrier_off(tp->dev);
4131 tg3_link_report(tp);
4132 } else {
4133 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4134 if (orig_pause_cfg != now_pause_cfg ||
4135 orig_active_speed != tp->link_config.active_speed ||
4136 orig_active_duplex != tp->link_config.active_duplex)
4137 tg3_link_report(tp);
4138 }
4139
4140 return 0;
4141 }
4142
4143 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4144 {
4145 int current_link_up, err = 0;
4146 u32 bmsr, bmcr;
4147 u16 current_speed;
4148 u8 current_duplex;
4149 u32 local_adv, remote_adv;
4150
4151 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4152 tw32_f(MAC_MODE, tp->mac_mode);
4153 udelay(40);
4154
4155 tw32(MAC_EVENT, 0);
4156
4157 tw32_f(MAC_STATUS,
4158 (MAC_STATUS_SYNC_CHANGED |
4159 MAC_STATUS_CFG_CHANGED |
4160 MAC_STATUS_MI_COMPLETION |
4161 MAC_STATUS_LNKSTATE_CHANGED));
4162 udelay(40);
4163
4164 if (force_reset)
4165 tg3_phy_reset(tp);
4166
4167 current_link_up = 0;
4168 current_speed = SPEED_INVALID;
4169 current_duplex = DUPLEX_INVALID;
4170
4171 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4172 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4174 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4175 bmsr |= BMSR_LSTATUS;
4176 else
4177 bmsr &= ~BMSR_LSTATUS;
4178 }
4179
4180 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4181
4182 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4183 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4184 /* do nothing, just check for link up at the end */
4185 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4186 u32 adv, new_adv;
4187
4188 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4189 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4190 ADVERTISE_1000XPAUSE |
4191 ADVERTISE_1000XPSE_ASYM |
4192 ADVERTISE_SLCT);
4193
4194 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4195
4196 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4197 new_adv |= ADVERTISE_1000XHALF;
4198 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4199 new_adv |= ADVERTISE_1000XFULL;
4200
4201 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4202 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4203 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4204 tg3_writephy(tp, MII_BMCR, bmcr);
4205
4206 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4207 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4208 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4209
4210 return err;
4211 }
4212 } else {
4213 u32 new_bmcr;
4214
4215 bmcr &= ~BMCR_SPEED1000;
4216 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4217
4218 if (tp->link_config.duplex == DUPLEX_FULL)
4219 new_bmcr |= BMCR_FULLDPLX;
4220
4221 if (new_bmcr != bmcr) {
4222 /* BMCR_SPEED1000 is a reserved bit that needs
4223 * to be set on write.
4224 */
4225 new_bmcr |= BMCR_SPEED1000;
4226
4227 /* Force a linkdown */
4228 if (netif_carrier_ok(tp->dev)) {
4229 u32 adv;
4230
4231 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4232 adv &= ~(ADVERTISE_1000XFULL |
4233 ADVERTISE_1000XHALF |
4234 ADVERTISE_SLCT);
4235 tg3_writephy(tp, MII_ADVERTISE, adv);
4236 tg3_writephy(tp, MII_BMCR, bmcr |
4237 BMCR_ANRESTART |
4238 BMCR_ANENABLE);
4239 udelay(10);
4240 netif_carrier_off(tp->dev);
4241 }
4242 tg3_writephy(tp, MII_BMCR, new_bmcr);
4243 bmcr = new_bmcr;
4244 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4245 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4246 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4247 ASIC_REV_5714) {
4248 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4249 bmsr |= BMSR_LSTATUS;
4250 else
4251 bmsr &= ~BMSR_LSTATUS;
4252 }
4253 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4254 }
4255 }
4256
4257 if (bmsr & BMSR_LSTATUS) {
4258 current_speed = SPEED_1000;
4259 current_link_up = 1;
4260 if (bmcr & BMCR_FULLDPLX)
4261 current_duplex = DUPLEX_FULL;
4262 else
4263 current_duplex = DUPLEX_HALF;
4264
4265 local_adv = 0;
4266 remote_adv = 0;
4267
4268 if (bmcr & BMCR_ANENABLE) {
4269 u32 common;
4270
4271 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4272 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4273 common = local_adv & remote_adv;
4274 if (common & (ADVERTISE_1000XHALF |
4275 ADVERTISE_1000XFULL)) {
4276 if (common & ADVERTISE_1000XFULL)
4277 current_duplex = DUPLEX_FULL;
4278 else
4279 current_duplex = DUPLEX_HALF;
4280 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4281 /* Link is up via parallel detect */
4282 } else {
4283 current_link_up = 0;
4284 }
4285 }
4286 }
4287
4288 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4289 tg3_setup_flow_control(tp, local_adv, remote_adv);
4290
4291 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4292 if (tp->link_config.active_duplex == DUPLEX_HALF)
4293 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4294
4295 tw32_f(MAC_MODE, tp->mac_mode);
4296 udelay(40);
4297
4298 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4299
4300 tp->link_config.active_speed = current_speed;
4301 tp->link_config.active_duplex = current_duplex;
4302
4303 if (current_link_up != netif_carrier_ok(tp->dev)) {
4304 if (current_link_up)
4305 netif_carrier_on(tp->dev);
4306 else {
4307 netif_carrier_off(tp->dev);
4308 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4309 }
4310 tg3_link_report(tp);
4311 }
4312 return err;
4313 }
4314
4315 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4316 {
4317 if (tp->serdes_counter) {
4318 /* Give autoneg time to complete. */
4319 tp->serdes_counter--;
4320 return;
4321 }
4322
4323 if (!netif_carrier_ok(tp->dev) &&
4324 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4325 u32 bmcr;
4326
4327 tg3_readphy(tp, MII_BMCR, &bmcr);
4328 if (bmcr & BMCR_ANENABLE) {
4329 u32 phy1, phy2;
4330
4331 /* Select shadow register 0x1f */
4332 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4333 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4334
4335 /* Select expansion interrupt status register */
4336 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4337 MII_TG3_DSP_EXP1_INT_STAT);
4338 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4339 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4340
4341 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4342 /* We have signal detect and not receiving
4343 * config code words, link is up by parallel
4344 * detection.
4345 */
4346
4347 bmcr &= ~BMCR_ANENABLE;
4348 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4349 tg3_writephy(tp, MII_BMCR, bmcr);
4350 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4351 }
4352 }
4353 } else if (netif_carrier_ok(tp->dev) &&
4354 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4355 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4356 u32 phy2;
4357
4358 /* Select expansion interrupt status register */
4359 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4360 MII_TG3_DSP_EXP1_INT_STAT);
4361 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4362 if (phy2 & 0x20) {
4363 u32 bmcr;
4364
4365 /* Config code words received, turn on autoneg. */
4366 tg3_readphy(tp, MII_BMCR, &bmcr);
4367 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4368
4369 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4370
4371 }
4372 }
4373 }
4374
4375 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4376 {
4377 int err;
4378
4379 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4380 err = tg3_setup_fiber_phy(tp, force_reset);
4381 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4382 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4383 else
4384 err = tg3_setup_copper_phy(tp, force_reset);
4385
4386 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4387 u32 val, scale;
4388
4389 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4390 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4391 scale = 65;
4392 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4393 scale = 6;
4394 else
4395 scale = 12;
4396
4397 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4398 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4399 tw32(GRC_MISC_CFG, val);
4400 }
4401
4402 if (tp->link_config.active_speed == SPEED_1000 &&
4403 tp->link_config.active_duplex == DUPLEX_HALF)
4404 tw32(MAC_TX_LENGTHS,
4405 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4406 (6 << TX_LENGTHS_IPG_SHIFT) |
4407 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4408 else
4409 tw32(MAC_TX_LENGTHS,
4410 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4411 (6 << TX_LENGTHS_IPG_SHIFT) |
4412 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4413
4414 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4415 if (netif_carrier_ok(tp->dev)) {
4416 tw32(HOSTCC_STAT_COAL_TICKS,
4417 tp->coal.stats_block_coalesce_usecs);
4418 } else {
4419 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4420 }
4421 }
4422
4423 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4424 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4425 if (!netif_carrier_ok(tp->dev))
4426 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4427 tp->pwrmgmt_thresh;
4428 else
4429 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4430 tw32(PCIE_PWR_MGMT_THRESH, val);
4431 }
4432
4433 return err;
4434 }
4435
4436 static inline int tg3_irq_sync(struct tg3 *tp)
4437 {
4438 return tp->irq_sync;
4439 }
4440
4441 /* This is called whenever we suspect that the system chipset is re-
4442 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4443 * is bogus tx completions. We try to recover by setting the
4444 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4445 * in the workqueue.
4446 */
4447 static void tg3_tx_recover(struct tg3 *tp)
4448 {
4449 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4450 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4451
4452 netdev_warn(tp->dev,
4453 "The system may be re-ordering memory-mapped I/O "
4454 "cycles to the network device, attempting to recover. "
4455 "Please report the problem to the driver maintainer "
4456 "and include system chipset information.\n");
4457
4458 spin_lock(&tp->lock);
4459 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4460 spin_unlock(&tp->lock);
4461 }
4462
4463 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4464 {
4465 /* Tell compiler to fetch tx indices from memory. */
4466 barrier();
4467 return tnapi->tx_pending -
4468 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4469 }
4470
4471 /* Tigon3 never reports partial packet sends. So we do not
4472 * need special logic to handle SKBs that have not had all
4473 * of their frags sent yet, like SunGEM does.
4474 */
4475 static void tg3_tx(struct tg3_napi *tnapi)
4476 {
4477 struct tg3 *tp = tnapi->tp;
4478 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4479 u32 sw_idx = tnapi->tx_cons;
4480 struct netdev_queue *txq;
4481 int index = tnapi - tp->napi;
4482
4483 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4484 index--;
4485
4486 txq = netdev_get_tx_queue(tp->dev, index);
4487
4488 while (sw_idx != hw_idx) {
4489 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4490 struct sk_buff *skb = ri->skb;
4491 int i, tx_bug = 0;
4492
4493 if (unlikely(skb == NULL)) {
4494 tg3_tx_recover(tp);
4495 return;
4496 }
4497
4498 pci_unmap_single(tp->pdev,
4499 dma_unmap_addr(ri, mapping),
4500 skb_headlen(skb),
4501 PCI_DMA_TODEVICE);
4502
4503 ri->skb = NULL;
4504
4505 sw_idx = NEXT_TX(sw_idx);
4506
4507 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4508 ri = &tnapi->tx_buffers[sw_idx];
4509 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4510 tx_bug = 1;
4511
4512 pci_unmap_page(tp->pdev,
4513 dma_unmap_addr(ri, mapping),
4514 skb_shinfo(skb)->frags[i].size,
4515 PCI_DMA_TODEVICE);
4516 sw_idx = NEXT_TX(sw_idx);
4517 }
4518
4519 dev_kfree_skb(skb);
4520
4521 if (unlikely(tx_bug)) {
4522 tg3_tx_recover(tp);
4523 return;
4524 }
4525 }
4526
4527 tnapi->tx_cons = sw_idx;
4528
4529 /* Need to make the tx_cons update visible to tg3_start_xmit()
4530 * before checking for netif_queue_stopped(). Without the
4531 * memory barrier, there is a small possibility that tg3_start_xmit()
4532 * will miss it and cause the queue to be stopped forever.
4533 */
4534 smp_mb();
4535
4536 if (unlikely(netif_tx_queue_stopped(txq) &&
4537 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4538 __netif_tx_lock(txq, smp_processor_id());
4539 if (netif_tx_queue_stopped(txq) &&
4540 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4541 netif_tx_wake_queue(txq);
4542 __netif_tx_unlock(txq);
4543 }
4544 }
4545
4546 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4547 {
4548 if (!ri->skb)
4549 return;
4550
4551 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4552 map_sz, PCI_DMA_FROMDEVICE);
4553 dev_kfree_skb_any(ri->skb);
4554 ri->skb = NULL;
4555 }
4556
4557 /* Returns size of skb allocated or < 0 on error.
4558 *
4559 * We only need to fill in the address because the other members
4560 * of the RX descriptor are invariant, see tg3_init_rings.
4561 *
4562 * Note the purposeful assymetry of cpu vs. chip accesses. For
4563 * posting buffers we only dirty the first cache line of the RX
4564 * descriptor (containing the address). Whereas for the RX status
4565 * buffers the cpu only reads the last cacheline of the RX descriptor
4566 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4567 */
4568 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4569 u32 opaque_key, u32 dest_idx_unmasked)
4570 {
4571 struct tg3_rx_buffer_desc *desc;
4572 struct ring_info *map;
4573 struct sk_buff *skb;
4574 dma_addr_t mapping;
4575 int skb_size, dest_idx;
4576
4577 switch (opaque_key) {
4578 case RXD_OPAQUE_RING_STD:
4579 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4580 desc = &tpr->rx_std[dest_idx];
4581 map = &tpr->rx_std_buffers[dest_idx];
4582 skb_size = tp->rx_pkt_map_sz;
4583 break;
4584
4585 case RXD_OPAQUE_RING_JUMBO:
4586 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4587 desc = &tpr->rx_jmb[dest_idx].std;
4588 map = &tpr->rx_jmb_buffers[dest_idx];
4589 skb_size = TG3_RX_JMB_MAP_SZ;
4590 break;
4591
4592 default:
4593 return -EINVAL;
4594 }
4595
4596 /* Do not overwrite any of the map or rp information
4597 * until we are sure we can commit to a new buffer.
4598 *
4599 * Callers depend upon this behavior and assume that
4600 * we leave everything unchanged if we fail.
4601 */
4602 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4603 if (skb == NULL)
4604 return -ENOMEM;
4605
4606 skb_reserve(skb, tp->rx_offset);
4607
4608 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4609 PCI_DMA_FROMDEVICE);
4610 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4611 dev_kfree_skb(skb);
4612 return -EIO;
4613 }
4614
4615 map->skb = skb;
4616 dma_unmap_addr_set(map, mapping, mapping);
4617
4618 desc->addr_hi = ((u64)mapping >> 32);
4619 desc->addr_lo = ((u64)mapping & 0xffffffff);
4620
4621 return skb_size;
4622 }
4623
4624 /* We only need to move over in the address because the other
4625 * members of the RX descriptor are invariant. See notes above
4626 * tg3_alloc_rx_skb for full details.
4627 */
4628 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4629 struct tg3_rx_prodring_set *dpr,
4630 u32 opaque_key, int src_idx,
4631 u32 dest_idx_unmasked)
4632 {
4633 struct tg3 *tp = tnapi->tp;
4634 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4635 struct ring_info *src_map, *dest_map;
4636 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4637 int dest_idx;
4638
4639 switch (opaque_key) {
4640 case RXD_OPAQUE_RING_STD:
4641 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4642 dest_desc = &dpr->rx_std[dest_idx];
4643 dest_map = &dpr->rx_std_buffers[dest_idx];
4644 src_desc = &spr->rx_std[src_idx];
4645 src_map = &spr->rx_std_buffers[src_idx];
4646 break;
4647
4648 case RXD_OPAQUE_RING_JUMBO:
4649 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4650 dest_desc = &dpr->rx_jmb[dest_idx].std;
4651 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4652 src_desc = &spr->rx_jmb[src_idx].std;
4653 src_map = &spr->rx_jmb_buffers[src_idx];
4654 break;
4655
4656 default:
4657 return;
4658 }
4659
4660 dest_map->skb = src_map->skb;
4661 dma_unmap_addr_set(dest_map, mapping,
4662 dma_unmap_addr(src_map, mapping));
4663 dest_desc->addr_hi = src_desc->addr_hi;
4664 dest_desc->addr_lo = src_desc->addr_lo;
4665
4666 /* Ensure that the update to the skb happens after the physical
4667 * addresses have been transferred to the new BD location.
4668 */
4669 smp_wmb();
4670
4671 src_map->skb = NULL;
4672 }
4673
4674 /* The RX ring scheme is composed of multiple rings which post fresh
4675 * buffers to the chip, and one special ring the chip uses to report
4676 * status back to the host.
4677 *
4678 * The special ring reports the status of received packets to the
4679 * host. The chip does not write into the original descriptor the
4680 * RX buffer was obtained from. The chip simply takes the original
4681 * descriptor as provided by the host, updates the status and length
4682 * field, then writes this into the next status ring entry.
4683 *
4684 * Each ring the host uses to post buffers to the chip is described
4685 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4686 * it is first placed into the on-chip ram. When the packet's length
4687 * is known, it walks down the TG3_BDINFO entries to select the ring.
4688 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4689 * which is within the range of the new packet's length is chosen.
4690 *
4691 * The "separate ring for rx status" scheme may sound queer, but it makes
4692 * sense from a cache coherency perspective. If only the host writes
4693 * to the buffer post rings, and only the chip writes to the rx status
4694 * rings, then cache lines never move beyond shared-modified state.
4695 * If both the host and chip were to write into the same ring, cache line
4696 * eviction could occur since both entities want it in an exclusive state.
4697 */
4698 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4699 {
4700 struct tg3 *tp = tnapi->tp;
4701 u32 work_mask, rx_std_posted = 0;
4702 u32 std_prod_idx, jmb_prod_idx;
4703 u32 sw_idx = tnapi->rx_rcb_ptr;
4704 u16 hw_idx;
4705 int received;
4706 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4707
4708 hw_idx = *(tnapi->rx_rcb_prod_idx);
4709 /*
4710 * We need to order the read of hw_idx and the read of
4711 * the opaque cookie.
4712 */
4713 rmb();
4714 work_mask = 0;
4715 received = 0;
4716 std_prod_idx = tpr->rx_std_prod_idx;
4717 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4718 while (sw_idx != hw_idx && budget > 0) {
4719 struct ring_info *ri;
4720 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4721 unsigned int len;
4722 struct sk_buff *skb;
4723 dma_addr_t dma_addr;
4724 u32 opaque_key, desc_idx, *post_ptr;
4725 bool hw_vlan __maybe_unused = false;
4726 u16 vtag __maybe_unused = 0;
4727
4728 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4729 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4730 if (opaque_key == RXD_OPAQUE_RING_STD) {
4731 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4732 dma_addr = dma_unmap_addr(ri, mapping);
4733 skb = ri->skb;
4734 post_ptr = &std_prod_idx;
4735 rx_std_posted++;
4736 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4737 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4738 dma_addr = dma_unmap_addr(ri, mapping);
4739 skb = ri->skb;
4740 post_ptr = &jmb_prod_idx;
4741 } else
4742 goto next_pkt_nopost;
4743
4744 work_mask |= opaque_key;
4745
4746 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4747 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4748 drop_it:
4749 tg3_recycle_rx(tnapi, tpr, opaque_key,
4750 desc_idx, *post_ptr);
4751 drop_it_no_recycle:
4752 /* Other statistics kept track of by card. */
4753 tp->rx_dropped++;
4754 goto next_pkt;
4755 }
4756
4757 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4758 ETH_FCS_LEN;
4759
4760 if (len > TG3_RX_COPY_THRESH(tp)) {
4761 int skb_size;
4762
4763 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4764 *post_ptr);
4765 if (skb_size < 0)
4766 goto drop_it;
4767
4768 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4769 PCI_DMA_FROMDEVICE);
4770
4771 /* Ensure that the update to the skb happens
4772 * after the usage of the old DMA mapping.
4773 */
4774 smp_wmb();
4775
4776 ri->skb = NULL;
4777
4778 skb_put(skb, len);
4779 } else {
4780 struct sk_buff *copy_skb;
4781
4782 tg3_recycle_rx(tnapi, tpr, opaque_key,
4783 desc_idx, *post_ptr);
4784
4785 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4786 TG3_RAW_IP_ALIGN);
4787 if (copy_skb == NULL)
4788 goto drop_it_no_recycle;
4789
4790 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4791 skb_put(copy_skb, len);
4792 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4793 skb_copy_from_linear_data(skb, copy_skb->data, len);
4794 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4795
4796 /* We'll reuse the original ring buffer. */
4797 skb = copy_skb;
4798 }
4799
4800 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4801 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4802 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4803 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4804 skb->ip_summed = CHECKSUM_UNNECESSARY;
4805 else
4806 skb_checksum_none_assert(skb);
4807
4808 skb->protocol = eth_type_trans(skb, tp->dev);
4809
4810 if (len > (tp->dev->mtu + ETH_HLEN) &&
4811 skb->protocol != htons(ETH_P_8021Q)) {
4812 dev_kfree_skb(skb);
4813 goto drop_it_no_recycle;
4814 }
4815
4816 if (desc->type_flags & RXD_FLAG_VLAN &&
4817 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4818 vtag = desc->err_vlan & RXD_VLAN_MASK;
4819 #if TG3_VLAN_TAG_USED
4820 if (tp->vlgrp)
4821 hw_vlan = true;
4822 else
4823 #endif
4824 {
4825 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4826 __skb_push(skb, VLAN_HLEN);
4827
4828 memmove(ve, skb->data + VLAN_HLEN,
4829 ETH_ALEN * 2);
4830 ve->h_vlan_proto = htons(ETH_P_8021Q);
4831 ve->h_vlan_TCI = htons(vtag);
4832 }
4833 }
4834
4835 #if TG3_VLAN_TAG_USED
4836 if (hw_vlan)
4837 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4838 else
4839 #endif
4840 napi_gro_receive(&tnapi->napi, skb);
4841
4842 received++;
4843 budget--;
4844
4845 next_pkt:
4846 (*post_ptr)++;
4847
4848 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4849 tpr->rx_std_prod_idx = std_prod_idx &
4850 tp->rx_std_ring_mask;
4851 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4852 tpr->rx_std_prod_idx);
4853 work_mask &= ~RXD_OPAQUE_RING_STD;
4854 rx_std_posted = 0;
4855 }
4856 next_pkt_nopost:
4857 sw_idx++;
4858 sw_idx &= tp->rx_ret_ring_mask;
4859
4860 /* Refresh hw_idx to see if there is new work */
4861 if (sw_idx == hw_idx) {
4862 hw_idx = *(tnapi->rx_rcb_prod_idx);
4863 rmb();
4864 }
4865 }
4866
4867 /* ACK the status ring. */
4868 tnapi->rx_rcb_ptr = sw_idx;
4869 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4870
4871 /* Refill RX ring(s). */
4872 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4873 if (work_mask & RXD_OPAQUE_RING_STD) {
4874 tpr->rx_std_prod_idx = std_prod_idx &
4875 tp->rx_std_ring_mask;
4876 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4877 tpr->rx_std_prod_idx);
4878 }
4879 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4880 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4881 tp->rx_jmb_ring_mask;
4882 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4883 tpr->rx_jmb_prod_idx);
4884 }
4885 mmiowb();
4886 } else if (work_mask) {
4887 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4888 * updated before the producer indices can be updated.
4889 */
4890 smp_wmb();
4891
4892 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4893 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4894
4895 if (tnapi != &tp->napi[1])
4896 napi_schedule(&tp->napi[1].napi);
4897 }
4898
4899 return received;
4900 }
4901
4902 static void tg3_poll_link(struct tg3 *tp)
4903 {
4904 /* handle link change and other phy events */
4905 if (!(tp->tg3_flags &
4906 (TG3_FLAG_USE_LINKCHG_REG |
4907 TG3_FLAG_POLL_SERDES))) {
4908 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4909
4910 if (sblk->status & SD_STATUS_LINK_CHG) {
4911 sblk->status = SD_STATUS_UPDATED |
4912 (sblk->status & ~SD_STATUS_LINK_CHG);
4913 spin_lock(&tp->lock);
4914 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4915 tw32_f(MAC_STATUS,
4916 (MAC_STATUS_SYNC_CHANGED |
4917 MAC_STATUS_CFG_CHANGED |
4918 MAC_STATUS_MI_COMPLETION |
4919 MAC_STATUS_LNKSTATE_CHANGED));
4920 udelay(40);
4921 } else
4922 tg3_setup_phy(tp, 0);
4923 spin_unlock(&tp->lock);
4924 }
4925 }
4926 }
4927
4928 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4929 struct tg3_rx_prodring_set *dpr,
4930 struct tg3_rx_prodring_set *spr)
4931 {
4932 u32 si, di, cpycnt, src_prod_idx;
4933 int i, err = 0;
4934
4935 while (1) {
4936 src_prod_idx = spr->rx_std_prod_idx;
4937
4938 /* Make sure updates to the rx_std_buffers[] entries and the
4939 * standard producer index are seen in the correct order.
4940 */
4941 smp_rmb();
4942
4943 if (spr->rx_std_cons_idx == src_prod_idx)
4944 break;
4945
4946 if (spr->rx_std_cons_idx < src_prod_idx)
4947 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4948 else
4949 cpycnt = tp->rx_std_ring_mask + 1 -
4950 spr->rx_std_cons_idx;
4951
4952 cpycnt = min(cpycnt,
4953 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4954
4955 si = spr->rx_std_cons_idx;
4956 di = dpr->rx_std_prod_idx;
4957
4958 for (i = di; i < di + cpycnt; i++) {
4959 if (dpr->rx_std_buffers[i].skb) {
4960 cpycnt = i - di;
4961 err = -ENOSPC;
4962 break;
4963 }
4964 }
4965
4966 if (!cpycnt)
4967 break;
4968
4969 /* Ensure that updates to the rx_std_buffers ring and the
4970 * shadowed hardware producer ring from tg3_recycle_skb() are
4971 * ordered correctly WRT the skb check above.
4972 */
4973 smp_rmb();
4974
4975 memcpy(&dpr->rx_std_buffers[di],
4976 &spr->rx_std_buffers[si],
4977 cpycnt * sizeof(struct ring_info));
4978
4979 for (i = 0; i < cpycnt; i++, di++, si++) {
4980 struct tg3_rx_buffer_desc *sbd, *dbd;
4981 sbd = &spr->rx_std[si];
4982 dbd = &dpr->rx_std[di];
4983 dbd->addr_hi = sbd->addr_hi;
4984 dbd->addr_lo = sbd->addr_lo;
4985 }
4986
4987 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4988 tp->rx_std_ring_mask;
4989 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4990 tp->rx_std_ring_mask;
4991 }
4992
4993 while (1) {
4994 src_prod_idx = spr->rx_jmb_prod_idx;
4995
4996 /* Make sure updates to the rx_jmb_buffers[] entries and
4997 * the jumbo producer index are seen in the correct order.
4998 */
4999 smp_rmb();
5000
5001 if (spr->rx_jmb_cons_idx == src_prod_idx)
5002 break;
5003
5004 if (spr->rx_jmb_cons_idx < src_prod_idx)
5005 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5006 else
5007 cpycnt = tp->rx_jmb_ring_mask + 1 -
5008 spr->rx_jmb_cons_idx;
5009
5010 cpycnt = min(cpycnt,
5011 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5012
5013 si = spr->rx_jmb_cons_idx;
5014 di = dpr->rx_jmb_prod_idx;
5015
5016 for (i = di; i < di + cpycnt; i++) {
5017 if (dpr->rx_jmb_buffers[i].skb) {
5018 cpycnt = i - di;
5019 err = -ENOSPC;
5020 break;
5021 }
5022 }
5023
5024 if (!cpycnt)
5025 break;
5026
5027 /* Ensure that updates to the rx_jmb_buffers ring and the
5028 * shadowed hardware producer ring from tg3_recycle_skb() are
5029 * ordered correctly WRT the skb check above.
5030 */
5031 smp_rmb();
5032
5033 memcpy(&dpr->rx_jmb_buffers[di],
5034 &spr->rx_jmb_buffers[si],
5035 cpycnt * sizeof(struct ring_info));
5036
5037 for (i = 0; i < cpycnt; i++, di++, si++) {
5038 struct tg3_rx_buffer_desc *sbd, *dbd;
5039 sbd = &spr->rx_jmb[si].std;
5040 dbd = &dpr->rx_jmb[di].std;
5041 dbd->addr_hi = sbd->addr_hi;
5042 dbd->addr_lo = sbd->addr_lo;
5043 }
5044
5045 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5046 tp->rx_jmb_ring_mask;
5047 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5048 tp->rx_jmb_ring_mask;
5049 }
5050
5051 return err;
5052 }
5053
5054 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5055 {
5056 struct tg3 *tp = tnapi->tp;
5057
5058 /* run TX completion thread */
5059 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5060 tg3_tx(tnapi);
5061 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5062 return work_done;
5063 }
5064
5065 /* run RX thread, within the bounds set by NAPI.
5066 * All RX "locking" is done by ensuring outside
5067 * code synchronizes with tg3->napi.poll()
5068 */
5069 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5070 work_done += tg3_rx(tnapi, budget - work_done);
5071
5072 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5073 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5074 int i, err = 0;
5075 u32 std_prod_idx = dpr->rx_std_prod_idx;
5076 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5077
5078 for (i = 1; i < tp->irq_cnt; i++)
5079 err |= tg3_rx_prodring_xfer(tp, dpr,
5080 &tp->napi[i].prodring);
5081
5082 wmb();
5083
5084 if (std_prod_idx != dpr->rx_std_prod_idx)
5085 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5086 dpr->rx_std_prod_idx);
5087
5088 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5089 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5090 dpr->rx_jmb_prod_idx);
5091
5092 mmiowb();
5093
5094 if (err)
5095 tw32_f(HOSTCC_MODE, tp->coal_now);
5096 }
5097
5098 return work_done;
5099 }
5100
5101 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5102 {
5103 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5104 struct tg3 *tp = tnapi->tp;
5105 int work_done = 0;
5106 struct tg3_hw_status *sblk = tnapi->hw_status;
5107
5108 while (1) {
5109 work_done = tg3_poll_work(tnapi, work_done, budget);
5110
5111 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5112 goto tx_recovery;
5113
5114 if (unlikely(work_done >= budget))
5115 break;
5116
5117 /* tp->last_tag is used in tg3_int_reenable() below
5118 * to tell the hw how much work has been processed,
5119 * so we must read it before checking for more work.
5120 */
5121 tnapi->last_tag = sblk->status_tag;
5122 tnapi->last_irq_tag = tnapi->last_tag;
5123 rmb();
5124
5125 /* check for RX/TX work to do */
5126 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5127 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5128 napi_complete(napi);
5129 /* Reenable interrupts. */
5130 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5131 mmiowb();
5132 break;
5133 }
5134 }
5135
5136 return work_done;
5137
5138 tx_recovery:
5139 /* work_done is guaranteed to be less than budget. */
5140 napi_complete(napi);
5141 schedule_work(&tp->reset_task);
5142 return work_done;
5143 }
5144
5145 static int tg3_poll(struct napi_struct *napi, int budget)
5146 {
5147 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5148 struct tg3 *tp = tnapi->tp;
5149 int work_done = 0;
5150 struct tg3_hw_status *sblk = tnapi->hw_status;
5151
5152 while (1) {
5153 tg3_poll_link(tp);
5154
5155 work_done = tg3_poll_work(tnapi, work_done, budget);
5156
5157 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5158 goto tx_recovery;
5159
5160 if (unlikely(work_done >= budget))
5161 break;
5162
5163 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5164 /* tp->last_tag is used in tg3_int_reenable() below
5165 * to tell the hw how much work has been processed,
5166 * so we must read it before checking for more work.
5167 */
5168 tnapi->last_tag = sblk->status_tag;
5169 tnapi->last_irq_tag = tnapi->last_tag;
5170 rmb();
5171 } else
5172 sblk->status &= ~SD_STATUS_UPDATED;
5173
5174 if (likely(!tg3_has_work(tnapi))) {
5175 napi_complete(napi);
5176 tg3_int_reenable(tnapi);
5177 break;
5178 }
5179 }
5180
5181 return work_done;
5182
5183 tx_recovery:
5184 /* work_done is guaranteed to be less than budget. */
5185 napi_complete(napi);
5186 schedule_work(&tp->reset_task);
5187 return work_done;
5188 }
5189
5190 static void tg3_napi_disable(struct tg3 *tp)
5191 {
5192 int i;
5193
5194 for (i = tp->irq_cnt - 1; i >= 0; i--)
5195 napi_disable(&tp->napi[i].napi);
5196 }
5197
5198 static void tg3_napi_enable(struct tg3 *tp)
5199 {
5200 int i;
5201
5202 for (i = 0; i < tp->irq_cnt; i++)
5203 napi_enable(&tp->napi[i].napi);
5204 }
5205
5206 static void tg3_napi_init(struct tg3 *tp)
5207 {
5208 int i;
5209
5210 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5211 for (i = 1; i < tp->irq_cnt; i++)
5212 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5213 }
5214
5215 static void tg3_napi_fini(struct tg3 *tp)
5216 {
5217 int i;
5218
5219 for (i = 0; i < tp->irq_cnt; i++)
5220 netif_napi_del(&tp->napi[i].napi);
5221 }
5222
5223 static inline void tg3_netif_stop(struct tg3 *tp)
5224 {
5225 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5226 tg3_napi_disable(tp);
5227 netif_tx_disable(tp->dev);
5228 }
5229
5230 static inline void tg3_netif_start(struct tg3 *tp)
5231 {
5232 /* NOTE: unconditional netif_tx_wake_all_queues is only
5233 * appropriate so long as all callers are assured to
5234 * have free tx slots (such as after tg3_init_hw)
5235 */
5236 netif_tx_wake_all_queues(tp->dev);
5237
5238 tg3_napi_enable(tp);
5239 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5240 tg3_enable_ints(tp);
5241 }
5242
5243 static void tg3_irq_quiesce(struct tg3 *tp)
5244 {
5245 int i;
5246
5247 BUG_ON(tp->irq_sync);
5248
5249 tp->irq_sync = 1;
5250 smp_mb();
5251
5252 for (i = 0; i < tp->irq_cnt; i++)
5253 synchronize_irq(tp->napi[i].irq_vec);
5254 }
5255
5256 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5257 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5258 * with as well. Most of the time, this is not necessary except when
5259 * shutting down the device.
5260 */
5261 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5262 {
5263 spin_lock_bh(&tp->lock);
5264 if (irq_sync)
5265 tg3_irq_quiesce(tp);
5266 }
5267
5268 static inline void tg3_full_unlock(struct tg3 *tp)
5269 {
5270 spin_unlock_bh(&tp->lock);
5271 }
5272
5273 /* One-shot MSI handler - Chip automatically disables interrupt
5274 * after sending MSI so driver doesn't have to do it.
5275 */
5276 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5277 {
5278 struct tg3_napi *tnapi = dev_id;
5279 struct tg3 *tp = tnapi->tp;
5280
5281 prefetch(tnapi->hw_status);
5282 if (tnapi->rx_rcb)
5283 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5284
5285 if (likely(!tg3_irq_sync(tp)))
5286 napi_schedule(&tnapi->napi);
5287
5288 return IRQ_HANDLED;
5289 }
5290
5291 /* MSI ISR - No need to check for interrupt sharing and no need to
5292 * flush status block and interrupt mailbox. PCI ordering rules
5293 * guarantee that MSI will arrive after the status block.
5294 */
5295 static irqreturn_t tg3_msi(int irq, void *dev_id)
5296 {
5297 struct tg3_napi *tnapi = dev_id;
5298 struct tg3 *tp = tnapi->tp;
5299
5300 prefetch(tnapi->hw_status);
5301 if (tnapi->rx_rcb)
5302 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5303 /*
5304 * Writing any value to intr-mbox-0 clears PCI INTA# and
5305 * chip-internal interrupt pending events.
5306 * Writing non-zero to intr-mbox-0 additional tells the
5307 * NIC to stop sending us irqs, engaging "in-intr-handler"
5308 * event coalescing.
5309 */
5310 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5311 if (likely(!tg3_irq_sync(tp)))
5312 napi_schedule(&tnapi->napi);
5313
5314 return IRQ_RETVAL(1);
5315 }
5316
5317 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5318 {
5319 struct tg3_napi *tnapi = dev_id;
5320 struct tg3 *tp = tnapi->tp;
5321 struct tg3_hw_status *sblk = tnapi->hw_status;
5322 unsigned int handled = 1;
5323
5324 /* In INTx mode, it is possible for the interrupt to arrive at
5325 * the CPU before the status block posted prior to the interrupt.
5326 * Reading the PCI State register will confirm whether the
5327 * interrupt is ours and will flush the status block.
5328 */
5329 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5330 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5331 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5332 handled = 0;
5333 goto out;
5334 }
5335 }
5336
5337 /*
5338 * Writing any value to intr-mbox-0 clears PCI INTA# and
5339 * chip-internal interrupt pending events.
5340 * Writing non-zero to intr-mbox-0 additional tells the
5341 * NIC to stop sending us irqs, engaging "in-intr-handler"
5342 * event coalescing.
5343 *
5344 * Flush the mailbox to de-assert the IRQ immediately to prevent
5345 * spurious interrupts. The flush impacts performance but
5346 * excessive spurious interrupts can be worse in some cases.
5347 */
5348 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5349 if (tg3_irq_sync(tp))
5350 goto out;
5351 sblk->status &= ~SD_STATUS_UPDATED;
5352 if (likely(tg3_has_work(tnapi))) {
5353 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5354 napi_schedule(&tnapi->napi);
5355 } else {
5356 /* No work, shared interrupt perhaps? re-enable
5357 * interrupts, and flush that PCI write
5358 */
5359 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5360 0x00000000);
5361 }
5362 out:
5363 return IRQ_RETVAL(handled);
5364 }
5365
5366 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5367 {
5368 struct tg3_napi *tnapi = dev_id;
5369 struct tg3 *tp = tnapi->tp;
5370 struct tg3_hw_status *sblk = tnapi->hw_status;
5371 unsigned int handled = 1;
5372
5373 /* In INTx mode, it is possible for the interrupt to arrive at
5374 * the CPU before the status block posted prior to the interrupt.
5375 * Reading the PCI State register will confirm whether the
5376 * interrupt is ours and will flush the status block.
5377 */
5378 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5379 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5380 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5381 handled = 0;
5382 goto out;
5383 }
5384 }
5385
5386 /*
5387 * writing any value to intr-mbox-0 clears PCI INTA# and
5388 * chip-internal interrupt pending events.
5389 * writing non-zero to intr-mbox-0 additional tells the
5390 * NIC to stop sending us irqs, engaging "in-intr-handler"
5391 * event coalescing.
5392 *
5393 * Flush the mailbox to de-assert the IRQ immediately to prevent
5394 * spurious interrupts. The flush impacts performance but
5395 * excessive spurious interrupts can be worse in some cases.
5396 */
5397 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5398
5399 /*
5400 * In a shared interrupt configuration, sometimes other devices'
5401 * interrupts will scream. We record the current status tag here
5402 * so that the above check can report that the screaming interrupts
5403 * are unhandled. Eventually they will be silenced.
5404 */
5405 tnapi->last_irq_tag = sblk->status_tag;
5406
5407 if (tg3_irq_sync(tp))
5408 goto out;
5409
5410 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5411
5412 napi_schedule(&tnapi->napi);
5413
5414 out:
5415 return IRQ_RETVAL(handled);
5416 }
5417
5418 /* ISR for interrupt test */
5419 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5420 {
5421 struct tg3_napi *tnapi = dev_id;
5422 struct tg3 *tp = tnapi->tp;
5423 struct tg3_hw_status *sblk = tnapi->hw_status;
5424
5425 if ((sblk->status & SD_STATUS_UPDATED) ||
5426 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5427 tg3_disable_ints(tp);
5428 return IRQ_RETVAL(1);
5429 }
5430 return IRQ_RETVAL(0);
5431 }
5432
5433 static int tg3_init_hw(struct tg3 *, int);
5434 static int tg3_halt(struct tg3 *, int, int);
5435
5436 /* Restart hardware after configuration changes, self-test, etc.
5437 * Invoked with tp->lock held.
5438 */
5439 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5440 __releases(tp->lock)
5441 __acquires(tp->lock)
5442 {
5443 int err;
5444
5445 err = tg3_init_hw(tp, reset_phy);
5446 if (err) {
5447 netdev_err(tp->dev,
5448 "Failed to re-initialize device, aborting\n");
5449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5450 tg3_full_unlock(tp);
5451 del_timer_sync(&tp->timer);
5452 tp->irq_sync = 0;
5453 tg3_napi_enable(tp);
5454 dev_close(tp->dev);
5455 tg3_full_lock(tp, 0);
5456 }
5457 return err;
5458 }
5459
5460 #ifdef CONFIG_NET_POLL_CONTROLLER
5461 static void tg3_poll_controller(struct net_device *dev)
5462 {
5463 int i;
5464 struct tg3 *tp = netdev_priv(dev);
5465
5466 for (i = 0; i < tp->irq_cnt; i++)
5467 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5468 }
5469 #endif
5470
5471 static void tg3_reset_task(struct work_struct *work)
5472 {
5473 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5474 int err;
5475 unsigned int restart_timer;
5476
5477 tg3_full_lock(tp, 0);
5478
5479 if (!netif_running(tp->dev)) {
5480 tg3_full_unlock(tp);
5481 return;
5482 }
5483
5484 tg3_full_unlock(tp);
5485
5486 tg3_phy_stop(tp);
5487
5488 tg3_netif_stop(tp);
5489
5490 tg3_full_lock(tp, 1);
5491
5492 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5493 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5494
5495 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5496 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5497 tp->write32_rx_mbox = tg3_write_flush_reg32;
5498 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5499 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5500 }
5501
5502 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5503 err = tg3_init_hw(tp, 1);
5504 if (err)
5505 goto out;
5506
5507 tg3_netif_start(tp);
5508
5509 if (restart_timer)
5510 mod_timer(&tp->timer, jiffies + 1);
5511
5512 out:
5513 tg3_full_unlock(tp);
5514
5515 if (!err)
5516 tg3_phy_start(tp);
5517 }
5518
5519 static void tg3_dump_short_state(struct tg3 *tp)
5520 {
5521 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5522 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5523 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5524 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5525 }
5526
5527 static void tg3_tx_timeout(struct net_device *dev)
5528 {
5529 struct tg3 *tp = netdev_priv(dev);
5530
5531 if (netif_msg_tx_err(tp)) {
5532 netdev_err(dev, "transmit timed out, resetting\n");
5533 tg3_dump_short_state(tp);
5534 }
5535
5536 schedule_work(&tp->reset_task);
5537 }
5538
5539 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5540 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5541 {
5542 u32 base = (u32) mapping & 0xffffffff;
5543
5544 return (base > 0xffffdcc0) && (base + len + 8 < base);
5545 }
5546
5547 /* Test for DMA addresses > 40-bit */
5548 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5549 int len)
5550 {
5551 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5552 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5553 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5554 return 0;
5555 #else
5556 return 0;
5557 #endif
5558 }
5559
5560 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5561
5562 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5563 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5564 struct sk_buff *skb, u32 last_plus_one,
5565 u32 *start, u32 base_flags, u32 mss)
5566 {
5567 struct tg3 *tp = tnapi->tp;
5568 struct sk_buff *new_skb;
5569 dma_addr_t new_addr = 0;
5570 u32 entry = *start;
5571 int i, ret = 0;
5572
5573 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5574 new_skb = skb_copy(skb, GFP_ATOMIC);
5575 else {
5576 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5577
5578 new_skb = skb_copy_expand(skb,
5579 skb_headroom(skb) + more_headroom,
5580 skb_tailroom(skb), GFP_ATOMIC);
5581 }
5582
5583 if (!new_skb) {
5584 ret = -1;
5585 } else {
5586 /* New SKB is guaranteed to be linear. */
5587 entry = *start;
5588 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5589 PCI_DMA_TODEVICE);
5590 /* Make sure the mapping succeeded */
5591 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5592 ret = -1;
5593 dev_kfree_skb(new_skb);
5594 new_skb = NULL;
5595
5596 /* Make sure new skb does not cross any 4G boundaries.
5597 * Drop the packet if it does.
5598 */
5599 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5600 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5601 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5602 PCI_DMA_TODEVICE);
5603 ret = -1;
5604 dev_kfree_skb(new_skb);
5605 new_skb = NULL;
5606 } else {
5607 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5608 base_flags, 1 | (mss << 1));
5609 *start = NEXT_TX(entry);
5610 }
5611 }
5612
5613 /* Now clean up the sw ring entries. */
5614 i = 0;
5615 while (entry != last_plus_one) {
5616 int len;
5617
5618 if (i == 0)
5619 len = skb_headlen(skb);
5620 else
5621 len = skb_shinfo(skb)->frags[i-1].size;
5622
5623 pci_unmap_single(tp->pdev,
5624 dma_unmap_addr(&tnapi->tx_buffers[entry],
5625 mapping),
5626 len, PCI_DMA_TODEVICE);
5627 if (i == 0) {
5628 tnapi->tx_buffers[entry].skb = new_skb;
5629 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5630 new_addr);
5631 } else {
5632 tnapi->tx_buffers[entry].skb = NULL;
5633 }
5634 entry = NEXT_TX(entry);
5635 i++;
5636 }
5637
5638 dev_kfree_skb(skb);
5639
5640 return ret;
5641 }
5642
5643 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5644 dma_addr_t mapping, int len, u32 flags,
5645 u32 mss_and_is_end)
5646 {
5647 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5648 int is_end = (mss_and_is_end & 0x1);
5649 u32 mss = (mss_and_is_end >> 1);
5650 u32 vlan_tag = 0;
5651
5652 if (is_end)
5653 flags |= TXD_FLAG_END;
5654 if (flags & TXD_FLAG_VLAN) {
5655 vlan_tag = flags >> 16;
5656 flags &= 0xffff;
5657 }
5658 vlan_tag |= (mss << TXD_MSS_SHIFT);
5659
5660 txd->addr_hi = ((u64) mapping >> 32);
5661 txd->addr_lo = ((u64) mapping & 0xffffffff);
5662 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5663 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5664 }
5665
5666 /* hard_start_xmit for devices that don't have any bugs and
5667 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5668 */
5669 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5670 struct net_device *dev)
5671 {
5672 struct tg3 *tp = netdev_priv(dev);
5673 u32 len, entry, base_flags, mss;
5674 dma_addr_t mapping;
5675 struct tg3_napi *tnapi;
5676 struct netdev_queue *txq;
5677 unsigned int i, last;
5678
5679 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5680 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5681 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5682 tnapi++;
5683
5684 /* We are running in BH disabled context with netif_tx_lock
5685 * and TX reclaim runs via tp->napi.poll inside of a software
5686 * interrupt. Furthermore, IRQ processing runs lockless so we have
5687 * no IRQ context deadlocks to worry about either. Rejoice!
5688 */
5689 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5690 if (!netif_tx_queue_stopped(txq)) {
5691 netif_tx_stop_queue(txq);
5692
5693 /* This is a hard error, log it. */
5694 netdev_err(dev,
5695 "BUG! Tx Ring full when queue awake!\n");
5696 }
5697 return NETDEV_TX_BUSY;
5698 }
5699
5700 entry = tnapi->tx_prod;
5701 base_flags = 0;
5702 mss = skb_shinfo(skb)->gso_size;
5703 if (mss) {
5704 int tcp_opt_len, ip_tcp_len;
5705 u32 hdrlen;
5706
5707 if (skb_header_cloned(skb) &&
5708 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5709 dev_kfree_skb(skb);
5710 goto out_unlock;
5711 }
5712
5713 if (skb_is_gso_v6(skb)) {
5714 hdrlen = skb_headlen(skb) - ETH_HLEN;
5715 } else {
5716 struct iphdr *iph = ip_hdr(skb);
5717
5718 tcp_opt_len = tcp_optlen(skb);
5719 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5720
5721 iph->check = 0;
5722 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5723 hdrlen = ip_tcp_len + tcp_opt_len;
5724 }
5725
5726 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5727 mss |= (hdrlen & 0xc) << 12;
5728 if (hdrlen & 0x10)
5729 base_flags |= 0x00000010;
5730 base_flags |= (hdrlen & 0x3e0) << 5;
5731 } else
5732 mss |= hdrlen << 9;
5733
5734 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5735 TXD_FLAG_CPU_POST_DMA);
5736
5737 tcp_hdr(skb)->check = 0;
5738
5739 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5740 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5741 }
5742
5743 #if TG3_VLAN_TAG_USED
5744 if (vlan_tx_tag_present(skb))
5745 base_flags |= (TXD_FLAG_VLAN |
5746 (vlan_tx_tag_get(skb) << 16));
5747 #endif
5748
5749 len = skb_headlen(skb);
5750
5751 /* Queue skb data, a.k.a. the main skb fragment. */
5752 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5753 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5754 dev_kfree_skb(skb);
5755 goto out_unlock;
5756 }
5757
5758 tnapi->tx_buffers[entry].skb = skb;
5759 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5760
5761 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5762 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5763 base_flags |= TXD_FLAG_JMB_PKT;
5764
5765 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5766 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5767
5768 entry = NEXT_TX(entry);
5769
5770 /* Now loop through additional data fragments, and queue them. */
5771 if (skb_shinfo(skb)->nr_frags > 0) {
5772 last = skb_shinfo(skb)->nr_frags - 1;
5773 for (i = 0; i <= last; i++) {
5774 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5775
5776 len = frag->size;
5777 mapping = pci_map_page(tp->pdev,
5778 frag->page,
5779 frag->page_offset,
5780 len, PCI_DMA_TODEVICE);
5781 if (pci_dma_mapping_error(tp->pdev, mapping))
5782 goto dma_error;
5783
5784 tnapi->tx_buffers[entry].skb = NULL;
5785 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5786 mapping);
5787
5788 tg3_set_txd(tnapi, entry, mapping, len,
5789 base_flags, (i == last) | (mss << 1));
5790
5791 entry = NEXT_TX(entry);
5792 }
5793 }
5794
5795 /* Packets are ready, update Tx producer idx local and on card. */
5796 tw32_tx_mbox(tnapi->prodmbox, entry);
5797
5798 tnapi->tx_prod = entry;
5799 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5800 netif_tx_stop_queue(txq);
5801
5802 /* netif_tx_stop_queue() must be done before checking
5803 * checking tx index in tg3_tx_avail() below, because in
5804 * tg3_tx(), we update tx index before checking for
5805 * netif_tx_queue_stopped().
5806 */
5807 smp_mb();
5808 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5809 netif_tx_wake_queue(txq);
5810 }
5811
5812 out_unlock:
5813 mmiowb();
5814
5815 return NETDEV_TX_OK;
5816
5817 dma_error:
5818 last = i;
5819 entry = tnapi->tx_prod;
5820 tnapi->tx_buffers[entry].skb = NULL;
5821 pci_unmap_single(tp->pdev,
5822 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5823 skb_headlen(skb),
5824 PCI_DMA_TODEVICE);
5825 for (i = 0; i <= last; i++) {
5826 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5827 entry = NEXT_TX(entry);
5828
5829 pci_unmap_page(tp->pdev,
5830 dma_unmap_addr(&tnapi->tx_buffers[entry],
5831 mapping),
5832 frag->size, PCI_DMA_TODEVICE);
5833 }
5834
5835 dev_kfree_skb(skb);
5836 return NETDEV_TX_OK;
5837 }
5838
5839 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5840 struct net_device *);
5841
5842 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5843 * TSO header is greater than 80 bytes.
5844 */
5845 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5846 {
5847 struct sk_buff *segs, *nskb;
5848 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5849
5850 /* Estimate the number of fragments in the worst case */
5851 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5852 netif_stop_queue(tp->dev);
5853
5854 /* netif_tx_stop_queue() must be done before checking
5855 * checking tx index in tg3_tx_avail() below, because in
5856 * tg3_tx(), we update tx index before checking for
5857 * netif_tx_queue_stopped().
5858 */
5859 smp_mb();
5860 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5861 return NETDEV_TX_BUSY;
5862
5863 netif_wake_queue(tp->dev);
5864 }
5865
5866 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5867 if (IS_ERR(segs))
5868 goto tg3_tso_bug_end;
5869
5870 do {
5871 nskb = segs;
5872 segs = segs->next;
5873 nskb->next = NULL;
5874 tg3_start_xmit_dma_bug(nskb, tp->dev);
5875 } while (segs);
5876
5877 tg3_tso_bug_end:
5878 dev_kfree_skb(skb);
5879
5880 return NETDEV_TX_OK;
5881 }
5882
5883 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5884 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5885 */
5886 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5887 struct net_device *dev)
5888 {
5889 struct tg3 *tp = netdev_priv(dev);
5890 u32 len, entry, base_flags, mss;
5891 int would_hit_hwbug;
5892 dma_addr_t mapping;
5893 struct tg3_napi *tnapi;
5894 struct netdev_queue *txq;
5895 unsigned int i, last;
5896
5897 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5898 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5899 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5900 tnapi++;
5901
5902 /* We are running in BH disabled context with netif_tx_lock
5903 * and TX reclaim runs via tp->napi.poll inside of a software
5904 * interrupt. Furthermore, IRQ processing runs lockless so we have
5905 * no IRQ context deadlocks to worry about either. Rejoice!
5906 */
5907 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5908 if (!netif_tx_queue_stopped(txq)) {
5909 netif_tx_stop_queue(txq);
5910
5911 /* This is a hard error, log it. */
5912 netdev_err(dev,
5913 "BUG! Tx Ring full when queue awake!\n");
5914 }
5915 return NETDEV_TX_BUSY;
5916 }
5917
5918 entry = tnapi->tx_prod;
5919 base_flags = 0;
5920 if (skb->ip_summed == CHECKSUM_PARTIAL)
5921 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5922
5923 mss = skb_shinfo(skb)->gso_size;
5924 if (mss) {
5925 struct iphdr *iph;
5926 u32 tcp_opt_len, hdr_len;
5927
5928 if (skb_header_cloned(skb) &&
5929 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5930 dev_kfree_skb(skb);
5931 goto out_unlock;
5932 }
5933
5934 iph = ip_hdr(skb);
5935 tcp_opt_len = tcp_optlen(skb);
5936
5937 if (skb_is_gso_v6(skb)) {
5938 hdr_len = skb_headlen(skb) - ETH_HLEN;
5939 } else {
5940 u32 ip_tcp_len;
5941
5942 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5943 hdr_len = ip_tcp_len + tcp_opt_len;
5944
5945 iph->check = 0;
5946 iph->tot_len = htons(mss + hdr_len);
5947 }
5948
5949 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5950 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5951 return tg3_tso_bug(tp, skb);
5952
5953 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5954 TXD_FLAG_CPU_POST_DMA);
5955
5956 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5957 tcp_hdr(skb)->check = 0;
5958 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5959 } else
5960 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5961 iph->daddr, 0,
5962 IPPROTO_TCP,
5963 0);
5964
5965 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5966 mss |= (hdr_len & 0xc) << 12;
5967 if (hdr_len & 0x10)
5968 base_flags |= 0x00000010;
5969 base_flags |= (hdr_len & 0x3e0) << 5;
5970 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5971 mss |= hdr_len << 9;
5972 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5974 if (tcp_opt_len || iph->ihl > 5) {
5975 int tsflags;
5976
5977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5978 mss |= (tsflags << 11);
5979 }
5980 } else {
5981 if (tcp_opt_len || iph->ihl > 5) {
5982 int tsflags;
5983
5984 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5985 base_flags |= tsflags << 12;
5986 }
5987 }
5988 }
5989 #if TG3_VLAN_TAG_USED
5990 if (vlan_tx_tag_present(skb))
5991 base_flags |= (TXD_FLAG_VLAN |
5992 (vlan_tx_tag_get(skb) << 16));
5993 #endif
5994
5995 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5996 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5997 base_flags |= TXD_FLAG_JMB_PKT;
5998
5999 len = skb_headlen(skb);
6000
6001 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6002 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6003 dev_kfree_skb(skb);
6004 goto out_unlock;
6005 }
6006
6007 tnapi->tx_buffers[entry].skb = skb;
6008 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6009
6010 would_hit_hwbug = 0;
6011
6012 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6013 would_hit_hwbug = 1;
6014
6015 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6016 tg3_4g_overflow_test(mapping, len))
6017 would_hit_hwbug = 1;
6018
6019 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6020 tg3_40bit_overflow_test(tp, mapping, len))
6021 would_hit_hwbug = 1;
6022
6023 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6024 would_hit_hwbug = 1;
6025
6026 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6027 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6028
6029 entry = NEXT_TX(entry);
6030
6031 /* Now loop through additional data fragments, and queue them. */
6032 if (skb_shinfo(skb)->nr_frags > 0) {
6033 last = skb_shinfo(skb)->nr_frags - 1;
6034 for (i = 0; i <= last; i++) {
6035 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6036
6037 len = frag->size;
6038 mapping = pci_map_page(tp->pdev,
6039 frag->page,
6040 frag->page_offset,
6041 len, PCI_DMA_TODEVICE);
6042
6043 tnapi->tx_buffers[entry].skb = NULL;
6044 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6045 mapping);
6046 if (pci_dma_mapping_error(tp->pdev, mapping))
6047 goto dma_error;
6048
6049 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6050 len <= 8)
6051 would_hit_hwbug = 1;
6052
6053 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6054 tg3_4g_overflow_test(mapping, len))
6055 would_hit_hwbug = 1;
6056
6057 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6058 tg3_40bit_overflow_test(tp, mapping, len))
6059 would_hit_hwbug = 1;
6060
6061 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6062 tg3_set_txd(tnapi, entry, mapping, len,
6063 base_flags, (i == last)|(mss << 1));
6064 else
6065 tg3_set_txd(tnapi, entry, mapping, len,
6066 base_flags, (i == last));
6067
6068 entry = NEXT_TX(entry);
6069 }
6070 }
6071
6072 if (would_hit_hwbug) {
6073 u32 last_plus_one = entry;
6074 u32 start;
6075
6076 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6077 start &= (TG3_TX_RING_SIZE - 1);
6078
6079 /* If the workaround fails due to memory/mapping
6080 * failure, silently drop this packet.
6081 */
6082 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6083 &start, base_flags, mss))
6084 goto out_unlock;
6085
6086 entry = start;
6087 }
6088
6089 /* Packets are ready, update Tx producer idx local and on card. */
6090 tw32_tx_mbox(tnapi->prodmbox, entry);
6091
6092 tnapi->tx_prod = entry;
6093 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6094 netif_tx_stop_queue(txq);
6095
6096 /* netif_tx_stop_queue() must be done before checking
6097 * checking tx index in tg3_tx_avail() below, because in
6098 * tg3_tx(), we update tx index before checking for
6099 * netif_tx_queue_stopped().
6100 */
6101 smp_mb();
6102 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6103 netif_tx_wake_queue(txq);
6104 }
6105
6106 out_unlock:
6107 mmiowb();
6108
6109 return NETDEV_TX_OK;
6110
6111 dma_error:
6112 last = i;
6113 entry = tnapi->tx_prod;
6114 tnapi->tx_buffers[entry].skb = NULL;
6115 pci_unmap_single(tp->pdev,
6116 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6117 skb_headlen(skb),
6118 PCI_DMA_TODEVICE);
6119 for (i = 0; i <= last; i++) {
6120 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6121 entry = NEXT_TX(entry);
6122
6123 pci_unmap_page(tp->pdev,
6124 dma_unmap_addr(&tnapi->tx_buffers[entry],
6125 mapping),
6126 frag->size, PCI_DMA_TODEVICE);
6127 }
6128
6129 dev_kfree_skb(skb);
6130 return NETDEV_TX_OK;
6131 }
6132
6133 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6134 int new_mtu)
6135 {
6136 dev->mtu = new_mtu;
6137
6138 if (new_mtu > ETH_DATA_LEN) {
6139 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6140 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6141 ethtool_op_set_tso(dev, 0);
6142 } else {
6143 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6144 }
6145 } else {
6146 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6147 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6148 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6149 }
6150 }
6151
6152 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6153 {
6154 struct tg3 *tp = netdev_priv(dev);
6155 int err;
6156
6157 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6158 return -EINVAL;
6159
6160 if (!netif_running(dev)) {
6161 /* We'll just catch it later when the
6162 * device is up'd.
6163 */
6164 tg3_set_mtu(dev, tp, new_mtu);
6165 return 0;
6166 }
6167
6168 tg3_phy_stop(tp);
6169
6170 tg3_netif_stop(tp);
6171
6172 tg3_full_lock(tp, 1);
6173
6174 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6175
6176 tg3_set_mtu(dev, tp, new_mtu);
6177
6178 err = tg3_restart_hw(tp, 0);
6179
6180 if (!err)
6181 tg3_netif_start(tp);
6182
6183 tg3_full_unlock(tp);
6184
6185 if (!err)
6186 tg3_phy_start(tp);
6187
6188 return err;
6189 }
6190
6191 static void tg3_rx_prodring_free(struct tg3 *tp,
6192 struct tg3_rx_prodring_set *tpr)
6193 {
6194 int i;
6195
6196 if (tpr != &tp->napi[0].prodring) {
6197 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6198 i = (i + 1) & tp->rx_std_ring_mask)
6199 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6200 tp->rx_pkt_map_sz);
6201
6202 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6203 for (i = tpr->rx_jmb_cons_idx;
6204 i != tpr->rx_jmb_prod_idx;
6205 i = (i + 1) & tp->rx_jmb_ring_mask) {
6206 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6207 TG3_RX_JMB_MAP_SZ);
6208 }
6209 }
6210
6211 return;
6212 }
6213
6214 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6215 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6216 tp->rx_pkt_map_sz);
6217
6218 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6219 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6220 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6221 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6222 TG3_RX_JMB_MAP_SZ);
6223 }
6224 }
6225
6226 /* Initialize rx rings for packet processing.
6227 *
6228 * The chip has been shut down and the driver detached from
6229 * the networking, so no interrupts or new tx packets will
6230 * end up in the driver. tp->{tx,}lock are held and thus
6231 * we may not sleep.
6232 */
6233 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6234 struct tg3_rx_prodring_set *tpr)
6235 {
6236 u32 i, rx_pkt_dma_sz;
6237
6238 tpr->rx_std_cons_idx = 0;
6239 tpr->rx_std_prod_idx = 0;
6240 tpr->rx_jmb_cons_idx = 0;
6241 tpr->rx_jmb_prod_idx = 0;
6242
6243 if (tpr != &tp->napi[0].prodring) {
6244 memset(&tpr->rx_std_buffers[0], 0,
6245 TG3_RX_STD_BUFF_RING_SIZE(tp));
6246 if (tpr->rx_jmb_buffers)
6247 memset(&tpr->rx_jmb_buffers[0], 0,
6248 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6249 goto done;
6250 }
6251
6252 /* Zero out all descriptors. */
6253 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6254
6255 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6256 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6257 tp->dev->mtu > ETH_DATA_LEN)
6258 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6259 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6260
6261 /* Initialize invariants of the rings, we only set this
6262 * stuff once. This works because the card does not
6263 * write into the rx buffer posting rings.
6264 */
6265 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6266 struct tg3_rx_buffer_desc *rxd;
6267
6268 rxd = &tpr->rx_std[i];
6269 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6270 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6271 rxd->opaque = (RXD_OPAQUE_RING_STD |
6272 (i << RXD_OPAQUE_INDEX_SHIFT));
6273 }
6274
6275 /* Now allocate fresh SKBs for each rx ring. */
6276 for (i = 0; i < tp->rx_pending; i++) {
6277 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6278 netdev_warn(tp->dev,
6279 "Using a smaller RX standard ring. Only "
6280 "%d out of %d buffers were allocated "
6281 "successfully\n", i, tp->rx_pending);
6282 if (i == 0)
6283 goto initfail;
6284 tp->rx_pending = i;
6285 break;
6286 }
6287 }
6288
6289 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6290 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6291 goto done;
6292
6293 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6294
6295 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6296 goto done;
6297
6298 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6299 struct tg3_rx_buffer_desc *rxd;
6300
6301 rxd = &tpr->rx_jmb[i].std;
6302 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6303 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6304 RXD_FLAG_JUMBO;
6305 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6306 (i << RXD_OPAQUE_INDEX_SHIFT));
6307 }
6308
6309 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6310 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6311 netdev_warn(tp->dev,
6312 "Using a smaller RX jumbo ring. Only %d "
6313 "out of %d buffers were allocated "
6314 "successfully\n", i, tp->rx_jumbo_pending);
6315 if (i == 0)
6316 goto initfail;
6317 tp->rx_jumbo_pending = i;
6318 break;
6319 }
6320 }
6321
6322 done:
6323 return 0;
6324
6325 initfail:
6326 tg3_rx_prodring_free(tp, tpr);
6327 return -ENOMEM;
6328 }
6329
6330 static void tg3_rx_prodring_fini(struct tg3 *tp,
6331 struct tg3_rx_prodring_set *tpr)
6332 {
6333 kfree(tpr->rx_std_buffers);
6334 tpr->rx_std_buffers = NULL;
6335 kfree(tpr->rx_jmb_buffers);
6336 tpr->rx_jmb_buffers = NULL;
6337 if (tpr->rx_std) {
6338 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6339 tpr->rx_std, tpr->rx_std_mapping);
6340 tpr->rx_std = NULL;
6341 }
6342 if (tpr->rx_jmb) {
6343 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6344 tpr->rx_jmb, tpr->rx_jmb_mapping);
6345 tpr->rx_jmb = NULL;
6346 }
6347 }
6348
6349 static int tg3_rx_prodring_init(struct tg3 *tp,
6350 struct tg3_rx_prodring_set *tpr)
6351 {
6352 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6353 GFP_KERNEL);
6354 if (!tpr->rx_std_buffers)
6355 return -ENOMEM;
6356
6357 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6358 TG3_RX_STD_RING_BYTES(tp),
6359 &tpr->rx_std_mapping,
6360 GFP_KERNEL);
6361 if (!tpr->rx_std)
6362 goto err_out;
6363
6364 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6365 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6366 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6367 GFP_KERNEL);
6368 if (!tpr->rx_jmb_buffers)
6369 goto err_out;
6370
6371 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6372 TG3_RX_JMB_RING_BYTES(tp),
6373 &tpr->rx_jmb_mapping,
6374 GFP_KERNEL);
6375 if (!tpr->rx_jmb)
6376 goto err_out;
6377 }
6378
6379 return 0;
6380
6381 err_out:
6382 tg3_rx_prodring_fini(tp, tpr);
6383 return -ENOMEM;
6384 }
6385
6386 /* Free up pending packets in all rx/tx rings.
6387 *
6388 * The chip has been shut down and the driver detached from
6389 * the networking, so no interrupts or new tx packets will
6390 * end up in the driver. tp->{tx,}lock is not held and we are not
6391 * in an interrupt context and thus may sleep.
6392 */
6393 static void tg3_free_rings(struct tg3 *tp)
6394 {
6395 int i, j;
6396
6397 for (j = 0; j < tp->irq_cnt; j++) {
6398 struct tg3_napi *tnapi = &tp->napi[j];
6399
6400 tg3_rx_prodring_free(tp, &tnapi->prodring);
6401
6402 if (!tnapi->tx_buffers)
6403 continue;
6404
6405 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6406 struct ring_info *txp;
6407 struct sk_buff *skb;
6408 unsigned int k;
6409
6410 txp = &tnapi->tx_buffers[i];
6411 skb = txp->skb;
6412
6413 if (skb == NULL) {
6414 i++;
6415 continue;
6416 }
6417
6418 pci_unmap_single(tp->pdev,
6419 dma_unmap_addr(txp, mapping),
6420 skb_headlen(skb),
6421 PCI_DMA_TODEVICE);
6422 txp->skb = NULL;
6423
6424 i++;
6425
6426 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6427 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6428 pci_unmap_page(tp->pdev,
6429 dma_unmap_addr(txp, mapping),
6430 skb_shinfo(skb)->frags[k].size,
6431 PCI_DMA_TODEVICE);
6432 i++;
6433 }
6434
6435 dev_kfree_skb_any(skb);
6436 }
6437 }
6438 }
6439
6440 /* Initialize tx/rx rings for packet processing.
6441 *
6442 * The chip has been shut down and the driver detached from
6443 * the networking, so no interrupts or new tx packets will
6444 * end up in the driver. tp->{tx,}lock are held and thus
6445 * we may not sleep.
6446 */
6447 static int tg3_init_rings(struct tg3 *tp)
6448 {
6449 int i;
6450
6451 /* Free up all the SKBs. */
6452 tg3_free_rings(tp);
6453
6454 for (i = 0; i < tp->irq_cnt; i++) {
6455 struct tg3_napi *tnapi = &tp->napi[i];
6456
6457 tnapi->last_tag = 0;
6458 tnapi->last_irq_tag = 0;
6459 tnapi->hw_status->status = 0;
6460 tnapi->hw_status->status_tag = 0;
6461 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6462
6463 tnapi->tx_prod = 0;
6464 tnapi->tx_cons = 0;
6465 if (tnapi->tx_ring)
6466 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6467
6468 tnapi->rx_rcb_ptr = 0;
6469 if (tnapi->rx_rcb)
6470 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6471
6472 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6473 tg3_free_rings(tp);
6474 return -ENOMEM;
6475 }
6476 }
6477
6478 return 0;
6479 }
6480
6481 /*
6482 * Must not be invoked with interrupt sources disabled and
6483 * the hardware shutdown down.
6484 */
6485 static void tg3_free_consistent(struct tg3 *tp)
6486 {
6487 int i;
6488
6489 for (i = 0; i < tp->irq_cnt; i++) {
6490 struct tg3_napi *tnapi = &tp->napi[i];
6491
6492 if (tnapi->tx_ring) {
6493 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6494 tnapi->tx_ring, tnapi->tx_desc_mapping);
6495 tnapi->tx_ring = NULL;
6496 }
6497
6498 kfree(tnapi->tx_buffers);
6499 tnapi->tx_buffers = NULL;
6500
6501 if (tnapi->rx_rcb) {
6502 dma_free_coherent(&tp->pdev->dev,
6503 TG3_RX_RCB_RING_BYTES(tp),
6504 tnapi->rx_rcb,
6505 tnapi->rx_rcb_mapping);
6506 tnapi->rx_rcb = NULL;
6507 }
6508
6509 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6510
6511 if (tnapi->hw_status) {
6512 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6513 tnapi->hw_status,
6514 tnapi->status_mapping);
6515 tnapi->hw_status = NULL;
6516 }
6517 }
6518
6519 if (tp->hw_stats) {
6520 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6521 tp->hw_stats, tp->stats_mapping);
6522 tp->hw_stats = NULL;
6523 }
6524 }
6525
6526 /*
6527 * Must not be invoked with interrupt sources disabled and
6528 * the hardware shutdown down. Can sleep.
6529 */
6530 static int tg3_alloc_consistent(struct tg3 *tp)
6531 {
6532 int i;
6533
6534 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6535 sizeof(struct tg3_hw_stats),
6536 &tp->stats_mapping,
6537 GFP_KERNEL);
6538 if (!tp->hw_stats)
6539 goto err_out;
6540
6541 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6542
6543 for (i = 0; i < tp->irq_cnt; i++) {
6544 struct tg3_napi *tnapi = &tp->napi[i];
6545 struct tg3_hw_status *sblk;
6546
6547 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6548 TG3_HW_STATUS_SIZE,
6549 &tnapi->status_mapping,
6550 GFP_KERNEL);
6551 if (!tnapi->hw_status)
6552 goto err_out;
6553
6554 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6555 sblk = tnapi->hw_status;
6556
6557 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6558 goto err_out;
6559
6560 /* If multivector TSS is enabled, vector 0 does not handle
6561 * tx interrupts. Don't allocate any resources for it.
6562 */
6563 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6564 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6565 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6566 TG3_TX_RING_SIZE,
6567 GFP_KERNEL);
6568 if (!tnapi->tx_buffers)
6569 goto err_out;
6570
6571 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6572 TG3_TX_RING_BYTES,
6573 &tnapi->tx_desc_mapping,
6574 GFP_KERNEL);
6575 if (!tnapi->tx_ring)
6576 goto err_out;
6577 }
6578
6579 /*
6580 * When RSS is enabled, the status block format changes
6581 * slightly. The "rx_jumbo_consumer", "reserved",
6582 * and "rx_mini_consumer" members get mapped to the
6583 * other three rx return ring producer indexes.
6584 */
6585 switch (i) {
6586 default:
6587 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6588 break;
6589 case 2:
6590 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6591 break;
6592 case 3:
6593 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6594 break;
6595 case 4:
6596 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6597 break;
6598 }
6599
6600 /*
6601 * If multivector RSS is enabled, vector 0 does not handle
6602 * rx or tx interrupts. Don't allocate any resources for it.
6603 */
6604 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6605 continue;
6606
6607 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6608 TG3_RX_RCB_RING_BYTES(tp),
6609 &tnapi->rx_rcb_mapping,
6610 GFP_KERNEL);
6611 if (!tnapi->rx_rcb)
6612 goto err_out;
6613
6614 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6615 }
6616
6617 return 0;
6618
6619 err_out:
6620 tg3_free_consistent(tp);
6621 return -ENOMEM;
6622 }
6623
6624 #define MAX_WAIT_CNT 1000
6625
6626 /* To stop a block, clear the enable bit and poll till it
6627 * clears. tp->lock is held.
6628 */
6629 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6630 {
6631 unsigned int i;
6632 u32 val;
6633
6634 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6635 switch (ofs) {
6636 case RCVLSC_MODE:
6637 case DMAC_MODE:
6638 case MBFREE_MODE:
6639 case BUFMGR_MODE:
6640 case MEMARB_MODE:
6641 /* We can't enable/disable these bits of the
6642 * 5705/5750, just say success.
6643 */
6644 return 0;
6645
6646 default:
6647 break;
6648 }
6649 }
6650
6651 val = tr32(ofs);
6652 val &= ~enable_bit;
6653 tw32_f(ofs, val);
6654
6655 for (i = 0; i < MAX_WAIT_CNT; i++) {
6656 udelay(100);
6657 val = tr32(ofs);
6658 if ((val & enable_bit) == 0)
6659 break;
6660 }
6661
6662 if (i == MAX_WAIT_CNT && !silent) {
6663 dev_err(&tp->pdev->dev,
6664 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6665 ofs, enable_bit);
6666 return -ENODEV;
6667 }
6668
6669 return 0;
6670 }
6671
6672 /* tp->lock is held. */
6673 static int tg3_abort_hw(struct tg3 *tp, int silent)
6674 {
6675 int i, err;
6676
6677 tg3_disable_ints(tp);
6678
6679 tp->rx_mode &= ~RX_MODE_ENABLE;
6680 tw32_f(MAC_RX_MODE, tp->rx_mode);
6681 udelay(10);
6682
6683 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6684 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6685 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6686 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6689
6690 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6691 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6692 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6693 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6694 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6695 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6696 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6697
6698 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6699 tw32_f(MAC_MODE, tp->mac_mode);
6700 udelay(40);
6701
6702 tp->tx_mode &= ~TX_MODE_ENABLE;
6703 tw32_f(MAC_TX_MODE, tp->tx_mode);
6704
6705 for (i = 0; i < MAX_WAIT_CNT; i++) {
6706 udelay(100);
6707 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6708 break;
6709 }
6710 if (i >= MAX_WAIT_CNT) {
6711 dev_err(&tp->pdev->dev,
6712 "%s timed out, TX_MODE_ENABLE will not clear "
6713 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6714 err |= -ENODEV;
6715 }
6716
6717 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6718 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6719 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6720
6721 tw32(FTQ_RESET, 0xffffffff);
6722 tw32(FTQ_RESET, 0x00000000);
6723
6724 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6725 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6726
6727 for (i = 0; i < tp->irq_cnt; i++) {
6728 struct tg3_napi *tnapi = &tp->napi[i];
6729 if (tnapi->hw_status)
6730 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6731 }
6732 if (tp->hw_stats)
6733 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6734
6735 return err;
6736 }
6737
6738 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6739 {
6740 int i;
6741 u32 apedata;
6742
6743 /* NCSI does not support APE events */
6744 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6745 return;
6746
6747 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6748 if (apedata != APE_SEG_SIG_MAGIC)
6749 return;
6750
6751 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6752 if (!(apedata & APE_FW_STATUS_READY))
6753 return;
6754
6755 /* Wait for up to 1 millisecond for APE to service previous event. */
6756 for (i = 0; i < 10; i++) {
6757 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6758 return;
6759
6760 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6761
6762 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6763 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6764 event | APE_EVENT_STATUS_EVENT_PENDING);
6765
6766 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6767
6768 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6769 break;
6770
6771 udelay(100);
6772 }
6773
6774 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6775 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6776 }
6777
6778 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6779 {
6780 u32 event;
6781 u32 apedata;
6782
6783 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6784 return;
6785
6786 switch (kind) {
6787 case RESET_KIND_INIT:
6788 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6789 APE_HOST_SEG_SIG_MAGIC);
6790 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6791 APE_HOST_SEG_LEN_MAGIC);
6792 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6793 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6794 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6795 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6796 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6797 APE_HOST_BEHAV_NO_PHYLOCK);
6798 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6799 TG3_APE_HOST_DRVR_STATE_START);
6800
6801 event = APE_EVENT_STATUS_STATE_START;
6802 break;
6803 case RESET_KIND_SHUTDOWN:
6804 /* With the interface we are currently using,
6805 * APE does not track driver state. Wiping
6806 * out the HOST SEGMENT SIGNATURE forces
6807 * the APE to assume OS absent status.
6808 */
6809 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6810
6811 if (device_may_wakeup(&tp->pdev->dev) &&
6812 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6813 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6814 TG3_APE_HOST_WOL_SPEED_AUTO);
6815 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6816 } else
6817 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6818
6819 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6820
6821 event = APE_EVENT_STATUS_STATE_UNLOAD;
6822 break;
6823 case RESET_KIND_SUSPEND:
6824 event = APE_EVENT_STATUS_STATE_SUSPEND;
6825 break;
6826 default:
6827 return;
6828 }
6829
6830 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6831
6832 tg3_ape_send_event(tp, event);
6833 }
6834
6835 /* tp->lock is held. */
6836 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6837 {
6838 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6839 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6840
6841 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6842 switch (kind) {
6843 case RESET_KIND_INIT:
6844 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6845 DRV_STATE_START);
6846 break;
6847
6848 case RESET_KIND_SHUTDOWN:
6849 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6850 DRV_STATE_UNLOAD);
6851 break;
6852
6853 case RESET_KIND_SUSPEND:
6854 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6855 DRV_STATE_SUSPEND);
6856 break;
6857
6858 default:
6859 break;
6860 }
6861 }
6862
6863 if (kind == RESET_KIND_INIT ||
6864 kind == RESET_KIND_SUSPEND)
6865 tg3_ape_driver_state_change(tp, kind);
6866 }
6867
6868 /* tp->lock is held. */
6869 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6870 {
6871 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6872 switch (kind) {
6873 case RESET_KIND_INIT:
6874 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6875 DRV_STATE_START_DONE);
6876 break;
6877
6878 case RESET_KIND_SHUTDOWN:
6879 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6880 DRV_STATE_UNLOAD_DONE);
6881 break;
6882
6883 default:
6884 break;
6885 }
6886 }
6887
6888 if (kind == RESET_KIND_SHUTDOWN)
6889 tg3_ape_driver_state_change(tp, kind);
6890 }
6891
6892 /* tp->lock is held. */
6893 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6894 {
6895 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6896 switch (kind) {
6897 case RESET_KIND_INIT:
6898 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6899 DRV_STATE_START);
6900 break;
6901
6902 case RESET_KIND_SHUTDOWN:
6903 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6904 DRV_STATE_UNLOAD);
6905 break;
6906
6907 case RESET_KIND_SUSPEND:
6908 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6909 DRV_STATE_SUSPEND);
6910 break;
6911
6912 default:
6913 break;
6914 }
6915 }
6916 }
6917
6918 static int tg3_poll_fw(struct tg3 *tp)
6919 {
6920 int i;
6921 u32 val;
6922
6923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6924 /* Wait up to 20ms for init done. */
6925 for (i = 0; i < 200; i++) {
6926 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6927 return 0;
6928 udelay(100);
6929 }
6930 return -ENODEV;
6931 }
6932
6933 /* Wait for firmware initialization to complete. */
6934 for (i = 0; i < 100000; i++) {
6935 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6936 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6937 break;
6938 udelay(10);
6939 }
6940
6941 /* Chip might not be fitted with firmware. Some Sun onboard
6942 * parts are configured like that. So don't signal the timeout
6943 * of the above loop as an error, but do report the lack of
6944 * running firmware once.
6945 */
6946 if (i >= 100000 &&
6947 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6948 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6949
6950 netdev_info(tp->dev, "No firmware running\n");
6951 }
6952
6953 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6954 /* The 57765 A0 needs a little more
6955 * time to do some important work.
6956 */
6957 mdelay(10);
6958 }
6959
6960 return 0;
6961 }
6962
6963 /* Save PCI command register before chip reset */
6964 static void tg3_save_pci_state(struct tg3 *tp)
6965 {
6966 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6967 }
6968
6969 /* Restore PCI state after chip reset */
6970 static void tg3_restore_pci_state(struct tg3 *tp)
6971 {
6972 u32 val;
6973
6974 /* Re-enable indirect register accesses. */
6975 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6976 tp->misc_host_ctrl);
6977
6978 /* Set MAX PCI retry to zero. */
6979 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6980 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6981 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6982 val |= PCISTATE_RETRY_SAME_DMA;
6983 /* Allow reads and writes to the APE register and memory space. */
6984 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6985 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6986 PCISTATE_ALLOW_APE_SHMEM_WR |
6987 PCISTATE_ALLOW_APE_PSPACE_WR;
6988 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6989
6990 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6991
6992 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6993 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6994 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6995 else {
6996 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6997 tp->pci_cacheline_sz);
6998 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6999 tp->pci_lat_timer);
7000 }
7001 }
7002
7003 /* Make sure PCI-X relaxed ordering bit is clear. */
7004 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7005 u16 pcix_cmd;
7006
7007 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7008 &pcix_cmd);
7009 pcix_cmd &= ~PCI_X_CMD_ERO;
7010 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7011 pcix_cmd);
7012 }
7013
7014 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7015
7016 /* Chip reset on 5780 will reset MSI enable bit,
7017 * so need to restore it.
7018 */
7019 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7020 u16 ctrl;
7021
7022 pci_read_config_word(tp->pdev,
7023 tp->msi_cap + PCI_MSI_FLAGS,
7024 &ctrl);
7025 pci_write_config_word(tp->pdev,
7026 tp->msi_cap + PCI_MSI_FLAGS,
7027 ctrl | PCI_MSI_FLAGS_ENABLE);
7028 val = tr32(MSGINT_MODE);
7029 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7030 }
7031 }
7032 }
7033
7034 static void tg3_stop_fw(struct tg3 *);
7035
7036 /* tp->lock is held. */
7037 static int tg3_chip_reset(struct tg3 *tp)
7038 {
7039 u32 val;
7040 void (*write_op)(struct tg3 *, u32, u32);
7041 int i, err;
7042
7043 tg3_nvram_lock(tp);
7044
7045 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7046
7047 /* No matching tg3_nvram_unlock() after this because
7048 * chip reset below will undo the nvram lock.
7049 */
7050 tp->nvram_lock_cnt = 0;
7051
7052 /* GRC_MISC_CFG core clock reset will clear the memory
7053 * enable bit in PCI register 4 and the MSI enable bit
7054 * on some chips, so we save relevant registers here.
7055 */
7056 tg3_save_pci_state(tp);
7057
7058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7059 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7060 tw32(GRC_FASTBOOT_PC, 0);
7061
7062 /*
7063 * We must avoid the readl() that normally takes place.
7064 * It locks machines, causes machine checks, and other
7065 * fun things. So, temporarily disable the 5701
7066 * hardware workaround, while we do the reset.
7067 */
7068 write_op = tp->write32;
7069 if (write_op == tg3_write_flush_reg32)
7070 tp->write32 = tg3_write32;
7071
7072 /* Prevent the irq handler from reading or writing PCI registers
7073 * during chip reset when the memory enable bit in the PCI command
7074 * register may be cleared. The chip does not generate interrupt
7075 * at this time, but the irq handler may still be called due to irq
7076 * sharing or irqpoll.
7077 */
7078 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7079 for (i = 0; i < tp->irq_cnt; i++) {
7080 struct tg3_napi *tnapi = &tp->napi[i];
7081 if (tnapi->hw_status) {
7082 tnapi->hw_status->status = 0;
7083 tnapi->hw_status->status_tag = 0;
7084 }
7085 tnapi->last_tag = 0;
7086 tnapi->last_irq_tag = 0;
7087 }
7088 smp_mb();
7089
7090 for (i = 0; i < tp->irq_cnt; i++)
7091 synchronize_irq(tp->napi[i].irq_vec);
7092
7093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7094 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7095 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7096 }
7097
7098 /* do the reset */
7099 val = GRC_MISC_CFG_CORECLK_RESET;
7100
7101 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7102 /* Force PCIe 1.0a mode */
7103 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7104 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7105 tr32(TG3_PCIE_PHY_TSTCTL) ==
7106 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7107 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7108
7109 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7110 tw32(GRC_MISC_CFG, (1 << 29));
7111 val |= (1 << 29);
7112 }
7113 }
7114
7115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7116 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7117 tw32(GRC_VCPU_EXT_CTRL,
7118 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7119 }
7120
7121 /* Manage gphy power for all CPMU absent PCIe devices. */
7122 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7123 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7124 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7125
7126 tw32(GRC_MISC_CFG, val);
7127
7128 /* restore 5701 hardware bug workaround write method */
7129 tp->write32 = write_op;
7130
7131 /* Unfortunately, we have to delay before the PCI read back.
7132 * Some 575X chips even will not respond to a PCI cfg access
7133 * when the reset command is given to the chip.
7134 *
7135 * How do these hardware designers expect things to work
7136 * properly if the PCI write is posted for a long period
7137 * of time? It is always necessary to have some method by
7138 * which a register read back can occur to push the write
7139 * out which does the reset.
7140 *
7141 * For most tg3 variants the trick below was working.
7142 * Ho hum...
7143 */
7144 udelay(120);
7145
7146 /* Flush PCI posted writes. The normal MMIO registers
7147 * are inaccessible at this time so this is the only
7148 * way to make this reliably (actually, this is no longer
7149 * the case, see above). I tried to use indirect
7150 * register read/write but this upset some 5701 variants.
7151 */
7152 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7153
7154 udelay(120);
7155
7156 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7157 u16 val16;
7158
7159 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7160 int i;
7161 u32 cfg_val;
7162
7163 /* Wait for link training to complete. */
7164 for (i = 0; i < 5000; i++)
7165 udelay(100);
7166
7167 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7168 pci_write_config_dword(tp->pdev, 0xc4,
7169 cfg_val | (1 << 15));
7170 }
7171
7172 /* Clear the "no snoop" and "relaxed ordering" bits. */
7173 pci_read_config_word(tp->pdev,
7174 tp->pcie_cap + PCI_EXP_DEVCTL,
7175 &val16);
7176 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7177 PCI_EXP_DEVCTL_NOSNOOP_EN);
7178 /*
7179 * Older PCIe devices only support the 128 byte
7180 * MPS setting. Enforce the restriction.
7181 */
7182 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7183 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7184 pci_write_config_word(tp->pdev,
7185 tp->pcie_cap + PCI_EXP_DEVCTL,
7186 val16);
7187
7188 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7189
7190 /* Clear error status */
7191 pci_write_config_word(tp->pdev,
7192 tp->pcie_cap + PCI_EXP_DEVSTA,
7193 PCI_EXP_DEVSTA_CED |
7194 PCI_EXP_DEVSTA_NFED |
7195 PCI_EXP_DEVSTA_FED |
7196 PCI_EXP_DEVSTA_URD);
7197 }
7198
7199 tg3_restore_pci_state(tp);
7200
7201 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7202
7203 val = 0;
7204 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7205 val = tr32(MEMARB_MODE);
7206 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7207
7208 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7209 tg3_stop_fw(tp);
7210 tw32(0x5000, 0x400);
7211 }
7212
7213 tw32(GRC_MODE, tp->grc_mode);
7214
7215 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7216 val = tr32(0xc4);
7217
7218 tw32(0xc4, val | (1 << 15));
7219 }
7220
7221 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7223 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7224 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7225 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7226 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7227 }
7228
7229 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7230 tp->mac_mode = MAC_MODE_APE_TX_EN |
7231 MAC_MODE_APE_RX_EN |
7232 MAC_MODE_TDE_ENABLE;
7233
7234 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7235 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7236 val = tp->mac_mode;
7237 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7238 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7239 val = tp->mac_mode;
7240 } else
7241 val = 0;
7242
7243 tw32_f(MAC_MODE, val);
7244 udelay(40);
7245
7246 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7247
7248 err = tg3_poll_fw(tp);
7249 if (err)
7250 return err;
7251
7252 tg3_mdio_start(tp);
7253
7254 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7255 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7256 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7257 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7258 val = tr32(0x7c00);
7259
7260 tw32(0x7c00, val | (1 << 25));
7261 }
7262
7263 /* Reprobe ASF enable state. */
7264 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7265 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7266 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7267 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7268 u32 nic_cfg;
7269
7270 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7271 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7272 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7273 tp->last_event_jiffies = jiffies;
7274 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7275 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7276 }
7277 }
7278
7279 return 0;
7280 }
7281
7282 /* tp->lock is held. */
7283 static void tg3_stop_fw(struct tg3 *tp)
7284 {
7285 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7286 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7287 /* Wait for RX cpu to ACK the previous event. */
7288 tg3_wait_for_event_ack(tp);
7289
7290 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7291
7292 tg3_generate_fw_event(tp);
7293
7294 /* Wait for RX cpu to ACK this event. */
7295 tg3_wait_for_event_ack(tp);
7296 }
7297 }
7298
7299 /* tp->lock is held. */
7300 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7301 {
7302 int err;
7303
7304 tg3_stop_fw(tp);
7305
7306 tg3_write_sig_pre_reset(tp, kind);
7307
7308 tg3_abort_hw(tp, silent);
7309 err = tg3_chip_reset(tp);
7310
7311 __tg3_set_mac_addr(tp, 0);
7312
7313 tg3_write_sig_legacy(tp, kind);
7314 tg3_write_sig_post_reset(tp, kind);
7315
7316 if (err)
7317 return err;
7318
7319 return 0;
7320 }
7321
7322 #define RX_CPU_SCRATCH_BASE 0x30000
7323 #define RX_CPU_SCRATCH_SIZE 0x04000
7324 #define TX_CPU_SCRATCH_BASE 0x34000
7325 #define TX_CPU_SCRATCH_SIZE 0x04000
7326
7327 /* tp->lock is held. */
7328 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7329 {
7330 int i;
7331
7332 BUG_ON(offset == TX_CPU_BASE &&
7333 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7334
7335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7336 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7337
7338 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7339 return 0;
7340 }
7341 if (offset == RX_CPU_BASE) {
7342 for (i = 0; i < 10000; i++) {
7343 tw32(offset + CPU_STATE, 0xffffffff);
7344 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7345 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7346 break;
7347 }
7348
7349 tw32(offset + CPU_STATE, 0xffffffff);
7350 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7351 udelay(10);
7352 } else {
7353 for (i = 0; i < 10000; i++) {
7354 tw32(offset + CPU_STATE, 0xffffffff);
7355 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7356 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7357 break;
7358 }
7359 }
7360
7361 if (i >= 10000) {
7362 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7363 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7364 return -ENODEV;
7365 }
7366
7367 /* Clear firmware's nvram arbitration. */
7368 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7369 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7370 return 0;
7371 }
7372
7373 struct fw_info {
7374 unsigned int fw_base;
7375 unsigned int fw_len;
7376 const __be32 *fw_data;
7377 };
7378
7379 /* tp->lock is held. */
7380 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7381 int cpu_scratch_size, struct fw_info *info)
7382 {
7383 int err, lock_err, i;
7384 void (*write_op)(struct tg3 *, u32, u32);
7385
7386 if (cpu_base == TX_CPU_BASE &&
7387 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7388 netdev_err(tp->dev,
7389 "%s: Trying to load TX cpu firmware which is 5705\n",
7390 __func__);
7391 return -EINVAL;
7392 }
7393
7394 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7395 write_op = tg3_write_mem;
7396 else
7397 write_op = tg3_write_indirect_reg32;
7398
7399 /* It is possible that bootcode is still loading at this point.
7400 * Get the nvram lock first before halting the cpu.
7401 */
7402 lock_err = tg3_nvram_lock(tp);
7403 err = tg3_halt_cpu(tp, cpu_base);
7404 if (!lock_err)
7405 tg3_nvram_unlock(tp);
7406 if (err)
7407 goto out;
7408
7409 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7410 write_op(tp, cpu_scratch_base + i, 0);
7411 tw32(cpu_base + CPU_STATE, 0xffffffff);
7412 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7413 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7414 write_op(tp, (cpu_scratch_base +
7415 (info->fw_base & 0xffff) +
7416 (i * sizeof(u32))),
7417 be32_to_cpu(info->fw_data[i]));
7418
7419 err = 0;
7420
7421 out:
7422 return err;
7423 }
7424
7425 /* tp->lock is held. */
7426 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7427 {
7428 struct fw_info info;
7429 const __be32 *fw_data;
7430 int err, i;
7431
7432 fw_data = (void *)tp->fw->data;
7433
7434 /* Firmware blob starts with version numbers, followed by
7435 start address and length. We are setting complete length.
7436 length = end_address_of_bss - start_address_of_text.
7437 Remainder is the blob to be loaded contiguously
7438 from start address. */
7439
7440 info.fw_base = be32_to_cpu(fw_data[1]);
7441 info.fw_len = tp->fw->size - 12;
7442 info.fw_data = &fw_data[3];
7443
7444 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7445 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7446 &info);
7447 if (err)
7448 return err;
7449
7450 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7451 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7452 &info);
7453 if (err)
7454 return err;
7455
7456 /* Now startup only the RX cpu. */
7457 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7458 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7459
7460 for (i = 0; i < 5; i++) {
7461 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7462 break;
7463 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7464 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7465 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7466 udelay(1000);
7467 }
7468 if (i >= 5) {
7469 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7470 "should be %08x\n", __func__,
7471 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7472 return -ENODEV;
7473 }
7474 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7475 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7476
7477 return 0;
7478 }
7479
7480 /* 5705 needs a special version of the TSO firmware. */
7481
7482 /* tp->lock is held. */
7483 static int tg3_load_tso_firmware(struct tg3 *tp)
7484 {
7485 struct fw_info info;
7486 const __be32 *fw_data;
7487 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7488 int err, i;
7489
7490 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7491 return 0;
7492
7493 fw_data = (void *)tp->fw->data;
7494
7495 /* Firmware blob starts with version numbers, followed by
7496 start address and length. We are setting complete length.
7497 length = end_address_of_bss - start_address_of_text.
7498 Remainder is the blob to be loaded contiguously
7499 from start address. */
7500
7501 info.fw_base = be32_to_cpu(fw_data[1]);
7502 cpu_scratch_size = tp->fw_len;
7503 info.fw_len = tp->fw->size - 12;
7504 info.fw_data = &fw_data[3];
7505
7506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7507 cpu_base = RX_CPU_BASE;
7508 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7509 } else {
7510 cpu_base = TX_CPU_BASE;
7511 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7512 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7513 }
7514
7515 err = tg3_load_firmware_cpu(tp, cpu_base,
7516 cpu_scratch_base, cpu_scratch_size,
7517 &info);
7518 if (err)
7519 return err;
7520
7521 /* Now startup the cpu. */
7522 tw32(cpu_base + CPU_STATE, 0xffffffff);
7523 tw32_f(cpu_base + CPU_PC, info.fw_base);
7524
7525 for (i = 0; i < 5; i++) {
7526 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7527 break;
7528 tw32(cpu_base + CPU_STATE, 0xffffffff);
7529 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7530 tw32_f(cpu_base + CPU_PC, info.fw_base);
7531 udelay(1000);
7532 }
7533 if (i >= 5) {
7534 netdev_err(tp->dev,
7535 "%s fails to set CPU PC, is %08x should be %08x\n",
7536 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7537 return -ENODEV;
7538 }
7539 tw32(cpu_base + CPU_STATE, 0xffffffff);
7540 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7541 return 0;
7542 }
7543
7544
7545 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7546 {
7547 struct tg3 *tp = netdev_priv(dev);
7548 struct sockaddr *addr = p;
7549 int err = 0, skip_mac_1 = 0;
7550
7551 if (!is_valid_ether_addr(addr->sa_data))
7552 return -EINVAL;
7553
7554 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7555
7556 if (!netif_running(dev))
7557 return 0;
7558
7559 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7560 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7561
7562 addr0_high = tr32(MAC_ADDR_0_HIGH);
7563 addr0_low = tr32(MAC_ADDR_0_LOW);
7564 addr1_high = tr32(MAC_ADDR_1_HIGH);
7565 addr1_low = tr32(MAC_ADDR_1_LOW);
7566
7567 /* Skip MAC addr 1 if ASF is using it. */
7568 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7569 !(addr1_high == 0 && addr1_low == 0))
7570 skip_mac_1 = 1;
7571 }
7572 spin_lock_bh(&tp->lock);
7573 __tg3_set_mac_addr(tp, skip_mac_1);
7574 spin_unlock_bh(&tp->lock);
7575
7576 return err;
7577 }
7578
7579 /* tp->lock is held. */
7580 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7581 dma_addr_t mapping, u32 maxlen_flags,
7582 u32 nic_addr)
7583 {
7584 tg3_write_mem(tp,
7585 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7586 ((u64) mapping >> 32));
7587 tg3_write_mem(tp,
7588 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7589 ((u64) mapping & 0xffffffff));
7590 tg3_write_mem(tp,
7591 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7592 maxlen_flags);
7593
7594 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7595 tg3_write_mem(tp,
7596 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7597 nic_addr);
7598 }
7599
7600 static void __tg3_set_rx_mode(struct net_device *);
7601 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7602 {
7603 int i;
7604
7605 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7606 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7607 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7608 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7609 } else {
7610 tw32(HOSTCC_TXCOL_TICKS, 0);
7611 tw32(HOSTCC_TXMAX_FRAMES, 0);
7612 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7613 }
7614
7615 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7616 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7617 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7618 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7619 } else {
7620 tw32(HOSTCC_RXCOL_TICKS, 0);
7621 tw32(HOSTCC_RXMAX_FRAMES, 0);
7622 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7623 }
7624
7625 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7626 u32 val = ec->stats_block_coalesce_usecs;
7627
7628 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7629 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7630
7631 if (!netif_carrier_ok(tp->dev))
7632 val = 0;
7633
7634 tw32(HOSTCC_STAT_COAL_TICKS, val);
7635 }
7636
7637 for (i = 0; i < tp->irq_cnt - 1; i++) {
7638 u32 reg;
7639
7640 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7641 tw32(reg, ec->rx_coalesce_usecs);
7642 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7643 tw32(reg, ec->rx_max_coalesced_frames);
7644 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7645 tw32(reg, ec->rx_max_coalesced_frames_irq);
7646
7647 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7648 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7649 tw32(reg, ec->tx_coalesce_usecs);
7650 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7651 tw32(reg, ec->tx_max_coalesced_frames);
7652 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7653 tw32(reg, ec->tx_max_coalesced_frames_irq);
7654 }
7655 }
7656
7657 for (; i < tp->irq_max - 1; i++) {
7658 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7659 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7660 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7661
7662 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7663 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7664 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7665 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7666 }
7667 }
7668 }
7669
7670 /* tp->lock is held. */
7671 static void tg3_rings_reset(struct tg3 *tp)
7672 {
7673 int i;
7674 u32 stblk, txrcb, rxrcb, limit;
7675 struct tg3_napi *tnapi = &tp->napi[0];
7676
7677 /* Disable all transmit rings but the first. */
7678 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7679 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7680 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7682 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7683 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7684 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7685 else
7686 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7687
7688 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7689 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7690 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7691 BDINFO_FLAGS_DISABLED);
7692
7693
7694 /* Disable all receive return rings but the first. */
7695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7697 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7698 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7699 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7700 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7702 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7703 else
7704 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7705
7706 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7707 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7708 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7709 BDINFO_FLAGS_DISABLED);
7710
7711 /* Disable interrupts */
7712 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7713
7714 /* Zero mailbox registers. */
7715 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7716 for (i = 1; i < tp->irq_max; i++) {
7717 tp->napi[i].tx_prod = 0;
7718 tp->napi[i].tx_cons = 0;
7719 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7720 tw32_mailbox(tp->napi[i].prodmbox, 0);
7721 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7722 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7723 }
7724 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7725 tw32_mailbox(tp->napi[0].prodmbox, 0);
7726 } else {
7727 tp->napi[0].tx_prod = 0;
7728 tp->napi[0].tx_cons = 0;
7729 tw32_mailbox(tp->napi[0].prodmbox, 0);
7730 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7731 }
7732
7733 /* Make sure the NIC-based send BD rings are disabled. */
7734 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7735 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7736 for (i = 0; i < 16; i++)
7737 tw32_tx_mbox(mbox + i * 8, 0);
7738 }
7739
7740 txrcb = NIC_SRAM_SEND_RCB;
7741 rxrcb = NIC_SRAM_RCV_RET_RCB;
7742
7743 /* Clear status block in ram. */
7744 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7745
7746 /* Set status block DMA address */
7747 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7748 ((u64) tnapi->status_mapping >> 32));
7749 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7750 ((u64) tnapi->status_mapping & 0xffffffff));
7751
7752 if (tnapi->tx_ring) {
7753 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7754 (TG3_TX_RING_SIZE <<
7755 BDINFO_FLAGS_MAXLEN_SHIFT),
7756 NIC_SRAM_TX_BUFFER_DESC);
7757 txrcb += TG3_BDINFO_SIZE;
7758 }
7759
7760 if (tnapi->rx_rcb) {
7761 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7762 (tp->rx_ret_ring_mask + 1) <<
7763 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7764 rxrcb += TG3_BDINFO_SIZE;
7765 }
7766
7767 stblk = HOSTCC_STATBLCK_RING1;
7768
7769 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7770 u64 mapping = (u64)tnapi->status_mapping;
7771 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7772 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7773
7774 /* Clear status block in ram. */
7775 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7776
7777 if (tnapi->tx_ring) {
7778 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7779 (TG3_TX_RING_SIZE <<
7780 BDINFO_FLAGS_MAXLEN_SHIFT),
7781 NIC_SRAM_TX_BUFFER_DESC);
7782 txrcb += TG3_BDINFO_SIZE;
7783 }
7784
7785 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7786 ((tp->rx_ret_ring_mask + 1) <<
7787 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7788
7789 stblk += 8;
7790 rxrcb += TG3_BDINFO_SIZE;
7791 }
7792 }
7793
7794 /* tp->lock is held. */
7795 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7796 {
7797 u32 val, rdmac_mode;
7798 int i, err, limit;
7799 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7800
7801 tg3_disable_ints(tp);
7802
7803 tg3_stop_fw(tp);
7804
7805 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7806
7807 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7808 tg3_abort_hw(tp, 1);
7809
7810 /* Enable MAC control of LPI */
7811 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7812 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7813 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7814 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7815
7816 tw32_f(TG3_CPMU_EEE_CTRL,
7817 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7818
7819 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7820 TG3_CPMU_EEEMD_LPI_IN_TX |
7821 TG3_CPMU_EEEMD_LPI_IN_RX |
7822 TG3_CPMU_EEEMD_EEE_ENABLE;
7823
7824 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7825 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7826
7827 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7828 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7829
7830 tw32_f(TG3_CPMU_EEE_MODE, val);
7831
7832 tw32_f(TG3_CPMU_EEE_DBTMR1,
7833 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7834 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7835
7836 tw32_f(TG3_CPMU_EEE_DBTMR2,
7837 TG3_CPMU_DBTMR1_APE_TX_2047US |
7838 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7839 }
7840
7841 if (reset_phy)
7842 tg3_phy_reset(tp);
7843
7844 err = tg3_chip_reset(tp);
7845 if (err)
7846 return err;
7847
7848 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7849
7850 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7851 val = tr32(TG3_CPMU_CTRL);
7852 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7853 tw32(TG3_CPMU_CTRL, val);
7854
7855 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7856 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7857 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7858 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7859
7860 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7861 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7862 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7863 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7864
7865 val = tr32(TG3_CPMU_HST_ACC);
7866 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7867 val |= CPMU_HST_ACC_MACCLK_6_25;
7868 tw32(TG3_CPMU_HST_ACC, val);
7869 }
7870
7871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7872 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7873 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7874 PCIE_PWR_MGMT_L1_THRESH_4MS;
7875 tw32(PCIE_PWR_MGMT_THRESH, val);
7876
7877 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7878 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7879
7880 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7881
7882 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7883 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7884 }
7885
7886 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7887 u32 grc_mode = tr32(GRC_MODE);
7888
7889 /* Access the lower 1K of PL PCIE block registers. */
7890 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7891 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7892
7893 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7894 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7895 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7896
7897 tw32(GRC_MODE, grc_mode);
7898 }
7899
7900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7901 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7902 u32 grc_mode = tr32(GRC_MODE);
7903
7904 /* Access the lower 1K of PL PCIE block registers. */
7905 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7906 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7907
7908 val = tr32(TG3_PCIE_TLDLPL_PORT +
7909 TG3_PCIE_PL_LO_PHYCTL5);
7910 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7911 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7912
7913 tw32(GRC_MODE, grc_mode);
7914 }
7915
7916 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7917 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7918 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7919 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7920 }
7921
7922 /* This works around an issue with Athlon chipsets on
7923 * B3 tigon3 silicon. This bit has no effect on any
7924 * other revision. But do not set this on PCI Express
7925 * chips and don't even touch the clocks if the CPMU is present.
7926 */
7927 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7928 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7929 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7930 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7931 }
7932
7933 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7934 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7935 val = tr32(TG3PCI_PCISTATE);
7936 val |= PCISTATE_RETRY_SAME_DMA;
7937 tw32(TG3PCI_PCISTATE, val);
7938 }
7939
7940 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7941 /* Allow reads and writes to the
7942 * APE register and memory space.
7943 */
7944 val = tr32(TG3PCI_PCISTATE);
7945 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7946 PCISTATE_ALLOW_APE_SHMEM_WR |
7947 PCISTATE_ALLOW_APE_PSPACE_WR;
7948 tw32(TG3PCI_PCISTATE, val);
7949 }
7950
7951 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7952 /* Enable some hw fixes. */
7953 val = tr32(TG3PCI_MSI_DATA);
7954 val |= (1 << 26) | (1 << 28) | (1 << 29);
7955 tw32(TG3PCI_MSI_DATA, val);
7956 }
7957
7958 /* Descriptor ring init may make accesses to the
7959 * NIC SRAM area to setup the TX descriptors, so we
7960 * can only do this after the hardware has been
7961 * successfully reset.
7962 */
7963 err = tg3_init_rings(tp);
7964 if (err)
7965 return err;
7966
7967 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7968 val = tr32(TG3PCI_DMA_RW_CTRL) &
7969 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7970 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7971 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7972 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7973 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7974 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7975 /* This value is determined during the probe time DMA
7976 * engine test, tg3_test_dma.
7977 */
7978 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7979 }
7980
7981 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7982 GRC_MODE_4X_NIC_SEND_RINGS |
7983 GRC_MODE_NO_TX_PHDR_CSUM |
7984 GRC_MODE_NO_RX_PHDR_CSUM);
7985 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7986
7987 /* Pseudo-header checksum is done by hardware logic and not
7988 * the offload processers, so make the chip do the pseudo-
7989 * header checksums on receive. For transmit it is more
7990 * convenient to do the pseudo-header checksum in software
7991 * as Linux does that on transmit for us in all cases.
7992 */
7993 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7994
7995 tw32(GRC_MODE,
7996 tp->grc_mode |
7997 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7998
7999 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8000 val = tr32(GRC_MISC_CFG);
8001 val &= ~0xff;
8002 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8003 tw32(GRC_MISC_CFG, val);
8004
8005 /* Initialize MBUF/DESC pool. */
8006 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8007 /* Do nothing. */
8008 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8009 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8011 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8012 else
8013 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8014 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8015 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8016 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8017 int fw_len;
8018
8019 fw_len = tp->fw_len;
8020 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8021 tw32(BUFMGR_MB_POOL_ADDR,
8022 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8023 tw32(BUFMGR_MB_POOL_SIZE,
8024 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8025 }
8026
8027 if (tp->dev->mtu <= ETH_DATA_LEN) {
8028 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8029 tp->bufmgr_config.mbuf_read_dma_low_water);
8030 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8031 tp->bufmgr_config.mbuf_mac_rx_low_water);
8032 tw32(BUFMGR_MB_HIGH_WATER,
8033 tp->bufmgr_config.mbuf_high_water);
8034 } else {
8035 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8036 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8037 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8038 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8039 tw32(BUFMGR_MB_HIGH_WATER,
8040 tp->bufmgr_config.mbuf_high_water_jumbo);
8041 }
8042 tw32(BUFMGR_DMA_LOW_WATER,
8043 tp->bufmgr_config.dma_low_water);
8044 tw32(BUFMGR_DMA_HIGH_WATER,
8045 tp->bufmgr_config.dma_high_water);
8046
8047 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8049 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8050 tw32(BUFMGR_MODE, val);
8051 for (i = 0; i < 2000; i++) {
8052 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8053 break;
8054 udelay(10);
8055 }
8056 if (i >= 2000) {
8057 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8058 return -ENODEV;
8059 }
8060
8061 /* Setup replenish threshold. */
8062 val = tp->rx_pending / 8;
8063 if (val == 0)
8064 val = 1;
8065 else if (val > tp->rx_std_max_post)
8066 val = tp->rx_std_max_post;
8067 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8068 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8069 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8070
8071 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8072 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8073 }
8074
8075 tw32(RCVBDI_STD_THRESH, val);
8076
8077 /* Initialize TG3_BDINFO's at:
8078 * RCVDBDI_STD_BD: standard eth size rx ring
8079 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8080 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8081 *
8082 * like so:
8083 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8084 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8085 * ring attribute flags
8086 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8087 *
8088 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8089 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8090 *
8091 * The size of each ring is fixed in the firmware, but the location is
8092 * configurable.
8093 */
8094 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8095 ((u64) tpr->rx_std_mapping >> 32));
8096 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8097 ((u64) tpr->rx_std_mapping & 0xffffffff));
8098 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8100 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8101 NIC_SRAM_RX_BUFFER_DESC);
8102
8103 /* Disable the mini ring */
8104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8105 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8106 BDINFO_FLAGS_DISABLED);
8107
8108 /* Program the jumbo buffer descriptor ring control
8109 * blocks on those devices that have them.
8110 */
8111 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8112 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8113 /* Setup replenish threshold. */
8114 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8115
8116 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8117 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8118 ((u64) tpr->rx_jmb_mapping >> 32));
8119 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8120 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8121 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8122 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8123 BDINFO_FLAGS_USE_EXT_RECV);
8124 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8126 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8127 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8128 } else {
8129 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8130 BDINFO_FLAGS_DISABLED);
8131 }
8132
8133 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8135 val = RX_STD_MAX_SIZE_5705;
8136 else
8137 val = RX_STD_MAX_SIZE_5717;
8138 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8139 val |= (TG3_RX_STD_DMA_SZ << 2);
8140 } else
8141 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8142 } else
8143 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8144
8145 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8146
8147 tpr->rx_std_prod_idx = tp->rx_pending;
8148 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8149
8150 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8151 tp->rx_jumbo_pending : 0;
8152 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8153
8154 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8155 tw32(STD_REPLENISH_LWM, 32);
8156 tw32(JMB_REPLENISH_LWM, 16);
8157 }
8158
8159 tg3_rings_reset(tp);
8160
8161 /* Initialize MAC address and backoff seed. */
8162 __tg3_set_mac_addr(tp, 0);
8163
8164 /* MTU + ethernet header + FCS + optional VLAN tag */
8165 tw32(MAC_RX_MTU_SIZE,
8166 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8167
8168 /* The slot time is changed by tg3_setup_phy if we
8169 * run at gigabit with half duplex.
8170 */
8171 tw32(MAC_TX_LENGTHS,
8172 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8173 (6 << TX_LENGTHS_IPG_SHIFT) |
8174 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8175
8176 /* Receive rules. */
8177 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8178 tw32(RCVLPC_CONFIG, 0x0181);
8179
8180 /* Calculate RDMAC_MODE setting early, we need it to determine
8181 * the RCVLPC_STATE_ENABLE mask.
8182 */
8183 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8184 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8185 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8186 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8187 RDMAC_MODE_LNGREAD_ENAB);
8188
8189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8190 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8191
8192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8195 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8196 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8197 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8198
8199 /* If statement applies to 5705 and 5750 PCI devices only */
8200 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8201 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8202 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8203 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8204 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8205 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8206 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8207 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8208 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8209 }
8210 }
8211
8212 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8213 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8214
8215 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8216 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8217
8218 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8221 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8222
8223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8227 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8228 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8230 val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
8231 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
8232 }
8233 tw32(TG3_RDMA_RSRVCTRL_REG,
8234 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8235 }
8236
8237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8238 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8239 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8240 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8241 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8242 }
8243
8244 /* Receive/send statistics. */
8245 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8246 val = tr32(RCVLPC_STATS_ENABLE);
8247 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8248 tw32(RCVLPC_STATS_ENABLE, val);
8249 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8250 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8251 val = tr32(RCVLPC_STATS_ENABLE);
8252 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8253 tw32(RCVLPC_STATS_ENABLE, val);
8254 } else {
8255 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8256 }
8257 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8258 tw32(SNDDATAI_STATSENAB, 0xffffff);
8259 tw32(SNDDATAI_STATSCTRL,
8260 (SNDDATAI_SCTRL_ENABLE |
8261 SNDDATAI_SCTRL_FASTUPD));
8262
8263 /* Setup host coalescing engine. */
8264 tw32(HOSTCC_MODE, 0);
8265 for (i = 0; i < 2000; i++) {
8266 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8267 break;
8268 udelay(10);
8269 }
8270
8271 __tg3_set_coalesce(tp, &tp->coal);
8272
8273 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8274 /* Status/statistics block address. See tg3_timer,
8275 * the tg3_periodic_fetch_stats call there, and
8276 * tg3_get_stats to see how this works for 5705/5750 chips.
8277 */
8278 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8279 ((u64) tp->stats_mapping >> 32));
8280 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8281 ((u64) tp->stats_mapping & 0xffffffff));
8282 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8283
8284 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8285
8286 /* Clear statistics and status block memory areas */
8287 for (i = NIC_SRAM_STATS_BLK;
8288 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8289 i += sizeof(u32)) {
8290 tg3_write_mem(tp, i, 0);
8291 udelay(40);
8292 }
8293 }
8294
8295 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8296
8297 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8298 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8299 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8300 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8301
8302 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8303 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8304 /* reset to prevent losing 1st rx packet intermittently */
8305 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8306 udelay(10);
8307 }
8308
8309 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8310 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8311 else
8312 tp->mac_mode = 0;
8313 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8314 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8315 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8316 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8317 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8318 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8319 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8320 udelay(40);
8321
8322 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8323 * If TG3_FLG2_IS_NIC is zero, we should read the
8324 * register to preserve the GPIO settings for LOMs. The GPIOs,
8325 * whether used as inputs or outputs, are set by boot code after
8326 * reset.
8327 */
8328 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8329 u32 gpio_mask;
8330
8331 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8332 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8333 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8334
8335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8336 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8337 GRC_LCLCTRL_GPIO_OUTPUT3;
8338
8339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8340 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8341
8342 tp->grc_local_ctrl &= ~gpio_mask;
8343 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8344
8345 /* GPIO1 must be driven high for eeprom write protect */
8346 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8347 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8348 GRC_LCLCTRL_GPIO_OUTPUT1);
8349 }
8350 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8351 udelay(100);
8352
8353 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8354 val = tr32(MSGINT_MODE);
8355 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8356 tw32(MSGINT_MODE, val);
8357 }
8358
8359 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8360 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8361 udelay(40);
8362 }
8363
8364 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8365 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8366 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8367 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8368 WDMAC_MODE_LNGREAD_ENAB);
8369
8370 /* If statement applies to 5705 and 5750 PCI devices only */
8371 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8372 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8373 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8374 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8375 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8376 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8377 /* nothing */
8378 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8379 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8380 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8381 val |= WDMAC_MODE_RX_ACCEL;
8382 }
8383 }
8384
8385 /* Enable host coalescing bug fix */
8386 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8387 val |= WDMAC_MODE_STATUS_TAG_FIX;
8388
8389 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8390 val |= WDMAC_MODE_BURST_ALL_DATA;
8391
8392 tw32_f(WDMAC_MODE, val);
8393 udelay(40);
8394
8395 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8396 u16 pcix_cmd;
8397
8398 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8399 &pcix_cmd);
8400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8401 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8402 pcix_cmd |= PCI_X_CMD_READ_2K;
8403 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8404 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8405 pcix_cmd |= PCI_X_CMD_READ_2K;
8406 }
8407 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8408 pcix_cmd);
8409 }
8410
8411 tw32_f(RDMAC_MODE, rdmac_mode);
8412 udelay(40);
8413
8414 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8415 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8416 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8417
8418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8419 tw32(SNDDATAC_MODE,
8420 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8421 else
8422 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8423
8424 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8425 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8426 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8429 val |= RCVDBDI_MODE_LRG_RING_SZ;
8430 tw32(RCVDBDI_MODE, val);
8431 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8432 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8433 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8434 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8435 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8436 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8437 tw32(SNDBDI_MODE, val);
8438 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8439
8440 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8441 err = tg3_load_5701_a0_firmware_fix(tp);
8442 if (err)
8443 return err;
8444 }
8445
8446 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8447 err = tg3_load_tso_firmware(tp);
8448 if (err)
8449 return err;
8450 }
8451
8452 tp->tx_mode = TX_MODE_ENABLE;
8453 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8455 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8456 tw32_f(MAC_TX_MODE, tp->tx_mode);
8457 udelay(100);
8458
8459 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8460 u32 reg = MAC_RSS_INDIR_TBL_0;
8461 u8 *ent = (u8 *)&val;
8462
8463 /* Setup the indirection table */
8464 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8465 int idx = i % sizeof(val);
8466
8467 ent[idx] = i % (tp->irq_cnt - 1);
8468 if (idx == sizeof(val) - 1) {
8469 tw32(reg, val);
8470 reg += 4;
8471 }
8472 }
8473
8474 /* Setup the "secret" hash key. */
8475 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8476 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8477 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8478 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8479 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8480 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8481 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8482 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8483 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8484 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8485 }
8486
8487 tp->rx_mode = RX_MODE_ENABLE;
8488 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8489 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8490
8491 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8492 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8493 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8494 RX_MODE_RSS_IPV6_HASH_EN |
8495 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8496 RX_MODE_RSS_IPV4_HASH_EN |
8497 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8498
8499 tw32_f(MAC_RX_MODE, tp->rx_mode);
8500 udelay(10);
8501
8502 tw32(MAC_LED_CTRL, tp->led_ctrl);
8503
8504 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8505 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8506 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8507 udelay(10);
8508 }
8509 tw32_f(MAC_RX_MODE, tp->rx_mode);
8510 udelay(10);
8511
8512 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8513 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8514 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8515 /* Set drive transmission level to 1.2V */
8516 /* only if the signal pre-emphasis bit is not set */
8517 val = tr32(MAC_SERDES_CFG);
8518 val &= 0xfffff000;
8519 val |= 0x880;
8520 tw32(MAC_SERDES_CFG, val);
8521 }
8522 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8523 tw32(MAC_SERDES_CFG, 0x616000);
8524 }
8525
8526 /* Prevent chip from dropping frames when flow control
8527 * is enabled.
8528 */
8529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8530 val = 1;
8531 else
8532 val = 2;
8533 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8534
8535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8536 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8537 /* Use hardware link auto-negotiation */
8538 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8539 }
8540
8541 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8542 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8543 u32 tmp;
8544
8545 tmp = tr32(SERDES_RX_CTRL);
8546 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8547 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8548 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8549 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8550 }
8551
8552 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8553 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8554 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8555 tp->link_config.speed = tp->link_config.orig_speed;
8556 tp->link_config.duplex = tp->link_config.orig_duplex;
8557 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8558 }
8559
8560 err = tg3_setup_phy(tp, 0);
8561 if (err)
8562 return err;
8563
8564 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8565 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8566 u32 tmp;
8567
8568 /* Clear CRC stats. */
8569 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8570 tg3_writephy(tp, MII_TG3_TEST1,
8571 tmp | MII_TG3_TEST1_CRC_EN);
8572 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8573 }
8574 }
8575 }
8576
8577 __tg3_set_rx_mode(tp->dev);
8578
8579 /* Initialize receive rules. */
8580 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8581 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8582 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8583 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8584
8585 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8586 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8587 limit = 8;
8588 else
8589 limit = 16;
8590 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8591 limit -= 4;
8592 switch (limit) {
8593 case 16:
8594 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8595 case 15:
8596 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8597 case 14:
8598 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8599 case 13:
8600 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8601 case 12:
8602 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8603 case 11:
8604 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8605 case 10:
8606 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8607 case 9:
8608 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8609 case 8:
8610 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8611 case 7:
8612 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8613 case 6:
8614 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8615 case 5:
8616 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8617 case 4:
8618 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8619 case 3:
8620 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8621 case 2:
8622 case 1:
8623
8624 default:
8625 break;
8626 }
8627
8628 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8629 /* Write our heartbeat update interval to APE. */
8630 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8631 APE_HOST_HEARTBEAT_INT_DISABLE);
8632
8633 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8634
8635 return 0;
8636 }
8637
8638 /* Called at device open time to get the chip ready for
8639 * packet processing. Invoked with tp->lock held.
8640 */
8641 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8642 {
8643 tg3_switch_clocks(tp);
8644
8645 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8646
8647 return tg3_reset_hw(tp, reset_phy);
8648 }
8649
8650 #define TG3_STAT_ADD32(PSTAT, REG) \
8651 do { u32 __val = tr32(REG); \
8652 (PSTAT)->low += __val; \
8653 if ((PSTAT)->low < __val) \
8654 (PSTAT)->high += 1; \
8655 } while (0)
8656
8657 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8658 {
8659 struct tg3_hw_stats *sp = tp->hw_stats;
8660
8661 if (!netif_carrier_ok(tp->dev))
8662 return;
8663
8664 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8665 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8666 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8667 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8668 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8669 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8670 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8671 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8672 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8673 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8674 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8675 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8676 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8677
8678 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8679 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8680 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8681 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8682 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8683 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8684 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8685 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8686 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8687 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8688 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8689 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8690 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8691 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8692
8693 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8694 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8695 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8696 }
8697
8698 static void tg3_timer(unsigned long __opaque)
8699 {
8700 struct tg3 *tp = (struct tg3 *) __opaque;
8701
8702 if (tp->irq_sync)
8703 goto restart_timer;
8704
8705 spin_lock(&tp->lock);
8706
8707 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8708 /* All of this garbage is because when using non-tagged
8709 * IRQ status the mailbox/status_block protocol the chip
8710 * uses with the cpu is race prone.
8711 */
8712 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8713 tw32(GRC_LOCAL_CTRL,
8714 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8715 } else {
8716 tw32(HOSTCC_MODE, tp->coalesce_mode |
8717 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8718 }
8719
8720 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8721 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8722 spin_unlock(&tp->lock);
8723 schedule_work(&tp->reset_task);
8724 return;
8725 }
8726 }
8727
8728 /* This part only runs once per second. */
8729 if (!--tp->timer_counter) {
8730 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8731 tg3_periodic_fetch_stats(tp);
8732
8733 if (tp->setlpicnt && !--tp->setlpicnt) {
8734 u32 val = tr32(TG3_CPMU_EEE_MODE);
8735 tw32(TG3_CPMU_EEE_MODE,
8736 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8737 }
8738
8739 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8740 u32 mac_stat;
8741 int phy_event;
8742
8743 mac_stat = tr32(MAC_STATUS);
8744
8745 phy_event = 0;
8746 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8747 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8748 phy_event = 1;
8749 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8750 phy_event = 1;
8751
8752 if (phy_event)
8753 tg3_setup_phy(tp, 0);
8754 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8755 u32 mac_stat = tr32(MAC_STATUS);
8756 int need_setup = 0;
8757
8758 if (netif_carrier_ok(tp->dev) &&
8759 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8760 need_setup = 1;
8761 }
8762 if (!netif_carrier_ok(tp->dev) &&
8763 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8764 MAC_STATUS_SIGNAL_DET))) {
8765 need_setup = 1;
8766 }
8767 if (need_setup) {
8768 if (!tp->serdes_counter) {
8769 tw32_f(MAC_MODE,
8770 (tp->mac_mode &
8771 ~MAC_MODE_PORT_MODE_MASK));
8772 udelay(40);
8773 tw32_f(MAC_MODE, tp->mac_mode);
8774 udelay(40);
8775 }
8776 tg3_setup_phy(tp, 0);
8777 }
8778 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8779 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8780 tg3_serdes_parallel_detect(tp);
8781 }
8782
8783 tp->timer_counter = tp->timer_multiplier;
8784 }
8785
8786 /* Heartbeat is only sent once every 2 seconds.
8787 *
8788 * The heartbeat is to tell the ASF firmware that the host
8789 * driver is still alive. In the event that the OS crashes,
8790 * ASF needs to reset the hardware to free up the FIFO space
8791 * that may be filled with rx packets destined for the host.
8792 * If the FIFO is full, ASF will no longer function properly.
8793 *
8794 * Unintended resets have been reported on real time kernels
8795 * where the timer doesn't run on time. Netpoll will also have
8796 * same problem.
8797 *
8798 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8799 * to check the ring condition when the heartbeat is expiring
8800 * before doing the reset. This will prevent most unintended
8801 * resets.
8802 */
8803 if (!--tp->asf_counter) {
8804 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8805 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8806 tg3_wait_for_event_ack(tp);
8807
8808 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8809 FWCMD_NICDRV_ALIVE3);
8810 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8811 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8812 TG3_FW_UPDATE_TIMEOUT_SEC);
8813
8814 tg3_generate_fw_event(tp);
8815 }
8816 tp->asf_counter = tp->asf_multiplier;
8817 }
8818
8819 spin_unlock(&tp->lock);
8820
8821 restart_timer:
8822 tp->timer.expires = jiffies + tp->timer_offset;
8823 add_timer(&tp->timer);
8824 }
8825
8826 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8827 {
8828 irq_handler_t fn;
8829 unsigned long flags;
8830 char *name;
8831 struct tg3_napi *tnapi = &tp->napi[irq_num];
8832
8833 if (tp->irq_cnt == 1)
8834 name = tp->dev->name;
8835 else {
8836 name = &tnapi->irq_lbl[0];
8837 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8838 name[IFNAMSIZ-1] = 0;
8839 }
8840
8841 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8842 fn = tg3_msi;
8843 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8844 fn = tg3_msi_1shot;
8845 flags = IRQF_SAMPLE_RANDOM;
8846 } else {
8847 fn = tg3_interrupt;
8848 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8849 fn = tg3_interrupt_tagged;
8850 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8851 }
8852
8853 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8854 }
8855
8856 static int tg3_test_interrupt(struct tg3 *tp)
8857 {
8858 struct tg3_napi *tnapi = &tp->napi[0];
8859 struct net_device *dev = tp->dev;
8860 int err, i, intr_ok = 0;
8861 u32 val;
8862
8863 if (!netif_running(dev))
8864 return -ENODEV;
8865
8866 tg3_disable_ints(tp);
8867
8868 free_irq(tnapi->irq_vec, tnapi);
8869
8870 /*
8871 * Turn off MSI one shot mode. Otherwise this test has no
8872 * observable way to know whether the interrupt was delivered.
8873 */
8874 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8875 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8876 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8877 tw32(MSGINT_MODE, val);
8878 }
8879
8880 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8881 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8882 if (err)
8883 return err;
8884
8885 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8886 tg3_enable_ints(tp);
8887
8888 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8889 tnapi->coal_now);
8890
8891 for (i = 0; i < 5; i++) {
8892 u32 int_mbox, misc_host_ctrl;
8893
8894 int_mbox = tr32_mailbox(tnapi->int_mbox);
8895 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8896
8897 if ((int_mbox != 0) ||
8898 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8899 intr_ok = 1;
8900 break;
8901 }
8902
8903 msleep(10);
8904 }
8905
8906 tg3_disable_ints(tp);
8907
8908 free_irq(tnapi->irq_vec, tnapi);
8909
8910 err = tg3_request_irq(tp, 0);
8911
8912 if (err)
8913 return err;
8914
8915 if (intr_ok) {
8916 /* Reenable MSI one shot mode. */
8917 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8918 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8919 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8920 tw32(MSGINT_MODE, val);
8921 }
8922 return 0;
8923 }
8924
8925 return -EIO;
8926 }
8927
8928 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8929 * successfully restored
8930 */
8931 static int tg3_test_msi(struct tg3 *tp)
8932 {
8933 int err;
8934 u16 pci_cmd;
8935
8936 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8937 return 0;
8938
8939 /* Turn off SERR reporting in case MSI terminates with Master
8940 * Abort.
8941 */
8942 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8943 pci_write_config_word(tp->pdev, PCI_COMMAND,
8944 pci_cmd & ~PCI_COMMAND_SERR);
8945
8946 err = tg3_test_interrupt(tp);
8947
8948 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8949
8950 if (!err)
8951 return 0;
8952
8953 /* other failures */
8954 if (err != -EIO)
8955 return err;
8956
8957 /* MSI test failed, go back to INTx mode */
8958 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8959 "to INTx mode. Please report this failure to the PCI "
8960 "maintainer and include system chipset information\n");
8961
8962 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8963
8964 pci_disable_msi(tp->pdev);
8965
8966 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8967 tp->napi[0].irq_vec = tp->pdev->irq;
8968
8969 err = tg3_request_irq(tp, 0);
8970 if (err)
8971 return err;
8972
8973 /* Need to reset the chip because the MSI cycle may have terminated
8974 * with Master Abort.
8975 */
8976 tg3_full_lock(tp, 1);
8977
8978 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8979 err = tg3_init_hw(tp, 1);
8980
8981 tg3_full_unlock(tp);
8982
8983 if (err)
8984 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8985
8986 return err;
8987 }
8988
8989 static int tg3_request_firmware(struct tg3 *tp)
8990 {
8991 const __be32 *fw_data;
8992
8993 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8994 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8995 tp->fw_needed);
8996 return -ENOENT;
8997 }
8998
8999 fw_data = (void *)tp->fw->data;
9000
9001 /* Firmware blob starts with version numbers, followed by
9002 * start address and _full_ length including BSS sections
9003 * (which must be longer than the actual data, of course
9004 */
9005
9006 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9007 if (tp->fw_len < (tp->fw->size - 12)) {
9008 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9009 tp->fw_len, tp->fw_needed);
9010 release_firmware(tp->fw);
9011 tp->fw = NULL;
9012 return -EINVAL;
9013 }
9014
9015 /* We no longer need firmware; we have it. */
9016 tp->fw_needed = NULL;
9017 return 0;
9018 }
9019
9020 static bool tg3_enable_msix(struct tg3 *tp)
9021 {
9022 int i, rc, cpus = num_online_cpus();
9023 struct msix_entry msix_ent[tp->irq_max];
9024
9025 if (cpus == 1)
9026 /* Just fallback to the simpler MSI mode. */
9027 return false;
9028
9029 /*
9030 * We want as many rx rings enabled as there are cpus.
9031 * The first MSIX vector only deals with link interrupts, etc,
9032 * so we add one to the number of vectors we are requesting.
9033 */
9034 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9035
9036 for (i = 0; i < tp->irq_max; i++) {
9037 msix_ent[i].entry = i;
9038 msix_ent[i].vector = 0;
9039 }
9040
9041 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9042 if (rc < 0) {
9043 return false;
9044 } else if (rc != 0) {
9045 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9046 return false;
9047 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9048 tp->irq_cnt, rc);
9049 tp->irq_cnt = rc;
9050 }
9051
9052 for (i = 0; i < tp->irq_max; i++)
9053 tp->napi[i].irq_vec = msix_ent[i].vector;
9054
9055 netif_set_real_num_tx_queues(tp->dev, 1);
9056 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9057 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9058 pci_disable_msix(tp->pdev);
9059 return false;
9060 }
9061
9062 if (tp->irq_cnt > 1) {
9063 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9065 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9066 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9067 }
9068 }
9069
9070 return true;
9071 }
9072
9073 static void tg3_ints_init(struct tg3 *tp)
9074 {
9075 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9076 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9077 /* All MSI supporting chips should support tagged
9078 * status. Assert that this is the case.
9079 */
9080 netdev_warn(tp->dev,
9081 "MSI without TAGGED_STATUS? Not using MSI\n");
9082 goto defcfg;
9083 }
9084
9085 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9086 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9087 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9088 pci_enable_msi(tp->pdev) == 0)
9089 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9090
9091 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9092 u32 msi_mode = tr32(MSGINT_MODE);
9093 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9094 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9095 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9096 }
9097 defcfg:
9098 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9099 tp->irq_cnt = 1;
9100 tp->napi[0].irq_vec = tp->pdev->irq;
9101 netif_set_real_num_tx_queues(tp->dev, 1);
9102 netif_set_real_num_rx_queues(tp->dev, 1);
9103 }
9104 }
9105
9106 static void tg3_ints_fini(struct tg3 *tp)
9107 {
9108 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9109 pci_disable_msix(tp->pdev);
9110 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9111 pci_disable_msi(tp->pdev);
9112 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9113 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9114 }
9115
9116 static int tg3_open(struct net_device *dev)
9117 {
9118 struct tg3 *tp = netdev_priv(dev);
9119 int i, err;
9120
9121 if (tp->fw_needed) {
9122 err = tg3_request_firmware(tp);
9123 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9124 if (err)
9125 return err;
9126 } else if (err) {
9127 netdev_warn(tp->dev, "TSO capability disabled\n");
9128 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9129 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9130 netdev_notice(tp->dev, "TSO capability restored\n");
9131 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9132 }
9133 }
9134
9135 netif_carrier_off(tp->dev);
9136
9137 err = tg3_power_up(tp);
9138 if (err)
9139 return err;
9140
9141 tg3_full_lock(tp, 0);
9142
9143 tg3_disable_ints(tp);
9144 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9145
9146 tg3_full_unlock(tp);
9147
9148 /*
9149 * Setup interrupts first so we know how
9150 * many NAPI resources to allocate
9151 */
9152 tg3_ints_init(tp);
9153
9154 /* The placement of this call is tied
9155 * to the setup and use of Host TX descriptors.
9156 */
9157 err = tg3_alloc_consistent(tp);
9158 if (err)
9159 goto err_out1;
9160
9161 tg3_napi_init(tp);
9162
9163 tg3_napi_enable(tp);
9164
9165 for (i = 0; i < tp->irq_cnt; i++) {
9166 struct tg3_napi *tnapi = &tp->napi[i];
9167 err = tg3_request_irq(tp, i);
9168 if (err) {
9169 for (i--; i >= 0; i--)
9170 free_irq(tnapi->irq_vec, tnapi);
9171 break;
9172 }
9173 }
9174
9175 if (err)
9176 goto err_out2;
9177
9178 tg3_full_lock(tp, 0);
9179
9180 err = tg3_init_hw(tp, 1);
9181 if (err) {
9182 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9183 tg3_free_rings(tp);
9184 } else {
9185 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9186 tp->timer_offset = HZ;
9187 else
9188 tp->timer_offset = HZ / 10;
9189
9190 BUG_ON(tp->timer_offset > HZ);
9191 tp->timer_counter = tp->timer_multiplier =
9192 (HZ / tp->timer_offset);
9193 tp->asf_counter = tp->asf_multiplier =
9194 ((HZ / tp->timer_offset) * 2);
9195
9196 init_timer(&tp->timer);
9197 tp->timer.expires = jiffies + tp->timer_offset;
9198 tp->timer.data = (unsigned long) tp;
9199 tp->timer.function = tg3_timer;
9200 }
9201
9202 tg3_full_unlock(tp);
9203
9204 if (err)
9205 goto err_out3;
9206
9207 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9208 err = tg3_test_msi(tp);
9209
9210 if (err) {
9211 tg3_full_lock(tp, 0);
9212 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9213 tg3_free_rings(tp);
9214 tg3_full_unlock(tp);
9215
9216 goto err_out2;
9217 }
9218
9219 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9220 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9221 u32 val = tr32(PCIE_TRANSACTION_CFG);
9222
9223 tw32(PCIE_TRANSACTION_CFG,
9224 val | PCIE_TRANS_CFG_1SHOT_MSI);
9225 }
9226 }
9227
9228 tg3_phy_start(tp);
9229
9230 tg3_full_lock(tp, 0);
9231
9232 add_timer(&tp->timer);
9233 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9234 tg3_enable_ints(tp);
9235
9236 tg3_full_unlock(tp);
9237
9238 netif_tx_start_all_queues(dev);
9239
9240 return 0;
9241
9242 err_out3:
9243 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9244 struct tg3_napi *tnapi = &tp->napi[i];
9245 free_irq(tnapi->irq_vec, tnapi);
9246 }
9247
9248 err_out2:
9249 tg3_napi_disable(tp);
9250 tg3_napi_fini(tp);
9251 tg3_free_consistent(tp);
9252
9253 err_out1:
9254 tg3_ints_fini(tp);
9255 return err;
9256 }
9257
9258 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9259 struct rtnl_link_stats64 *);
9260 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9261
9262 static int tg3_close(struct net_device *dev)
9263 {
9264 int i;
9265 struct tg3 *tp = netdev_priv(dev);
9266
9267 tg3_napi_disable(tp);
9268 cancel_work_sync(&tp->reset_task);
9269
9270 netif_tx_stop_all_queues(dev);
9271
9272 del_timer_sync(&tp->timer);
9273
9274 tg3_phy_stop(tp);
9275
9276 tg3_full_lock(tp, 1);
9277
9278 tg3_disable_ints(tp);
9279
9280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9281 tg3_free_rings(tp);
9282 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9283
9284 tg3_full_unlock(tp);
9285
9286 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9287 struct tg3_napi *tnapi = &tp->napi[i];
9288 free_irq(tnapi->irq_vec, tnapi);
9289 }
9290
9291 tg3_ints_fini(tp);
9292
9293 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9294
9295 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9296 sizeof(tp->estats_prev));
9297
9298 tg3_napi_fini(tp);
9299
9300 tg3_free_consistent(tp);
9301
9302 tg3_power_down(tp);
9303
9304 netif_carrier_off(tp->dev);
9305
9306 return 0;
9307 }
9308
9309 static inline u64 get_stat64(tg3_stat64_t *val)
9310 {
9311 return ((u64)val->high << 32) | ((u64)val->low);
9312 }
9313
9314 static u64 calc_crc_errors(struct tg3 *tp)
9315 {
9316 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9317
9318 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9319 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9320 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9321 u32 val;
9322
9323 spin_lock_bh(&tp->lock);
9324 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9325 tg3_writephy(tp, MII_TG3_TEST1,
9326 val | MII_TG3_TEST1_CRC_EN);
9327 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9328 } else
9329 val = 0;
9330 spin_unlock_bh(&tp->lock);
9331
9332 tp->phy_crc_errors += val;
9333
9334 return tp->phy_crc_errors;
9335 }
9336
9337 return get_stat64(&hw_stats->rx_fcs_errors);
9338 }
9339
9340 #define ESTAT_ADD(member) \
9341 estats->member = old_estats->member + \
9342 get_stat64(&hw_stats->member)
9343
9344 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9345 {
9346 struct tg3_ethtool_stats *estats = &tp->estats;
9347 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9348 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9349
9350 if (!hw_stats)
9351 return old_estats;
9352
9353 ESTAT_ADD(rx_octets);
9354 ESTAT_ADD(rx_fragments);
9355 ESTAT_ADD(rx_ucast_packets);
9356 ESTAT_ADD(rx_mcast_packets);
9357 ESTAT_ADD(rx_bcast_packets);
9358 ESTAT_ADD(rx_fcs_errors);
9359 ESTAT_ADD(rx_align_errors);
9360 ESTAT_ADD(rx_xon_pause_rcvd);
9361 ESTAT_ADD(rx_xoff_pause_rcvd);
9362 ESTAT_ADD(rx_mac_ctrl_rcvd);
9363 ESTAT_ADD(rx_xoff_entered);
9364 ESTAT_ADD(rx_frame_too_long_errors);
9365 ESTAT_ADD(rx_jabbers);
9366 ESTAT_ADD(rx_undersize_packets);
9367 ESTAT_ADD(rx_in_length_errors);
9368 ESTAT_ADD(rx_out_length_errors);
9369 ESTAT_ADD(rx_64_or_less_octet_packets);
9370 ESTAT_ADD(rx_65_to_127_octet_packets);
9371 ESTAT_ADD(rx_128_to_255_octet_packets);
9372 ESTAT_ADD(rx_256_to_511_octet_packets);
9373 ESTAT_ADD(rx_512_to_1023_octet_packets);
9374 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9375 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9376 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9377 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9378 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9379
9380 ESTAT_ADD(tx_octets);
9381 ESTAT_ADD(tx_collisions);
9382 ESTAT_ADD(tx_xon_sent);
9383 ESTAT_ADD(tx_xoff_sent);
9384 ESTAT_ADD(tx_flow_control);
9385 ESTAT_ADD(tx_mac_errors);
9386 ESTAT_ADD(tx_single_collisions);
9387 ESTAT_ADD(tx_mult_collisions);
9388 ESTAT_ADD(tx_deferred);
9389 ESTAT_ADD(tx_excessive_collisions);
9390 ESTAT_ADD(tx_late_collisions);
9391 ESTAT_ADD(tx_collide_2times);
9392 ESTAT_ADD(tx_collide_3times);
9393 ESTAT_ADD(tx_collide_4times);
9394 ESTAT_ADD(tx_collide_5times);
9395 ESTAT_ADD(tx_collide_6times);
9396 ESTAT_ADD(tx_collide_7times);
9397 ESTAT_ADD(tx_collide_8times);
9398 ESTAT_ADD(tx_collide_9times);
9399 ESTAT_ADD(tx_collide_10times);
9400 ESTAT_ADD(tx_collide_11times);
9401 ESTAT_ADD(tx_collide_12times);
9402 ESTAT_ADD(tx_collide_13times);
9403 ESTAT_ADD(tx_collide_14times);
9404 ESTAT_ADD(tx_collide_15times);
9405 ESTAT_ADD(tx_ucast_packets);
9406 ESTAT_ADD(tx_mcast_packets);
9407 ESTAT_ADD(tx_bcast_packets);
9408 ESTAT_ADD(tx_carrier_sense_errors);
9409 ESTAT_ADD(tx_discards);
9410 ESTAT_ADD(tx_errors);
9411
9412 ESTAT_ADD(dma_writeq_full);
9413 ESTAT_ADD(dma_write_prioq_full);
9414 ESTAT_ADD(rxbds_empty);
9415 ESTAT_ADD(rx_discards);
9416 ESTAT_ADD(rx_errors);
9417 ESTAT_ADD(rx_threshold_hit);
9418
9419 ESTAT_ADD(dma_readq_full);
9420 ESTAT_ADD(dma_read_prioq_full);
9421 ESTAT_ADD(tx_comp_queue_full);
9422
9423 ESTAT_ADD(ring_set_send_prod_index);
9424 ESTAT_ADD(ring_status_update);
9425 ESTAT_ADD(nic_irqs);
9426 ESTAT_ADD(nic_avoided_irqs);
9427 ESTAT_ADD(nic_tx_threshold_hit);
9428
9429 return estats;
9430 }
9431
9432 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9433 struct rtnl_link_stats64 *stats)
9434 {
9435 struct tg3 *tp = netdev_priv(dev);
9436 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9437 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9438
9439 if (!hw_stats)
9440 return old_stats;
9441
9442 stats->rx_packets = old_stats->rx_packets +
9443 get_stat64(&hw_stats->rx_ucast_packets) +
9444 get_stat64(&hw_stats->rx_mcast_packets) +
9445 get_stat64(&hw_stats->rx_bcast_packets);
9446
9447 stats->tx_packets = old_stats->tx_packets +
9448 get_stat64(&hw_stats->tx_ucast_packets) +
9449 get_stat64(&hw_stats->tx_mcast_packets) +
9450 get_stat64(&hw_stats->tx_bcast_packets);
9451
9452 stats->rx_bytes = old_stats->rx_bytes +
9453 get_stat64(&hw_stats->rx_octets);
9454 stats->tx_bytes = old_stats->tx_bytes +
9455 get_stat64(&hw_stats->tx_octets);
9456
9457 stats->rx_errors = old_stats->rx_errors +
9458 get_stat64(&hw_stats->rx_errors);
9459 stats->tx_errors = old_stats->tx_errors +
9460 get_stat64(&hw_stats->tx_errors) +
9461 get_stat64(&hw_stats->tx_mac_errors) +
9462 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9463 get_stat64(&hw_stats->tx_discards);
9464
9465 stats->multicast = old_stats->multicast +
9466 get_stat64(&hw_stats->rx_mcast_packets);
9467 stats->collisions = old_stats->collisions +
9468 get_stat64(&hw_stats->tx_collisions);
9469
9470 stats->rx_length_errors = old_stats->rx_length_errors +
9471 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9472 get_stat64(&hw_stats->rx_undersize_packets);
9473
9474 stats->rx_over_errors = old_stats->rx_over_errors +
9475 get_stat64(&hw_stats->rxbds_empty);
9476 stats->rx_frame_errors = old_stats->rx_frame_errors +
9477 get_stat64(&hw_stats->rx_align_errors);
9478 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9479 get_stat64(&hw_stats->tx_discards);
9480 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9481 get_stat64(&hw_stats->tx_carrier_sense_errors);
9482
9483 stats->rx_crc_errors = old_stats->rx_crc_errors +
9484 calc_crc_errors(tp);
9485
9486 stats->rx_missed_errors = old_stats->rx_missed_errors +
9487 get_stat64(&hw_stats->rx_discards);
9488
9489 stats->rx_dropped = tp->rx_dropped;
9490
9491 return stats;
9492 }
9493
9494 static inline u32 calc_crc(unsigned char *buf, int len)
9495 {
9496 u32 reg;
9497 u32 tmp;
9498 int j, k;
9499
9500 reg = 0xffffffff;
9501
9502 for (j = 0; j < len; j++) {
9503 reg ^= buf[j];
9504
9505 for (k = 0; k < 8; k++) {
9506 tmp = reg & 0x01;
9507
9508 reg >>= 1;
9509
9510 if (tmp)
9511 reg ^= 0xedb88320;
9512 }
9513 }
9514
9515 return ~reg;
9516 }
9517
9518 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9519 {
9520 /* accept or reject all multicast frames */
9521 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9522 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9523 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9524 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9525 }
9526
9527 static void __tg3_set_rx_mode(struct net_device *dev)
9528 {
9529 struct tg3 *tp = netdev_priv(dev);
9530 u32 rx_mode;
9531
9532 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9533 RX_MODE_KEEP_VLAN_TAG);
9534
9535 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9536 * flag clear.
9537 */
9538 #if TG3_VLAN_TAG_USED
9539 if (!tp->vlgrp &&
9540 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9541 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9542 #else
9543 /* By definition, VLAN is disabled always in this
9544 * case.
9545 */
9546 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9547 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9548 #endif
9549
9550 if (dev->flags & IFF_PROMISC) {
9551 /* Promiscuous mode. */
9552 rx_mode |= RX_MODE_PROMISC;
9553 } else if (dev->flags & IFF_ALLMULTI) {
9554 /* Accept all multicast. */
9555 tg3_set_multi(tp, 1);
9556 } else if (netdev_mc_empty(dev)) {
9557 /* Reject all multicast. */
9558 tg3_set_multi(tp, 0);
9559 } else {
9560 /* Accept one or more multicast(s). */
9561 struct netdev_hw_addr *ha;
9562 u32 mc_filter[4] = { 0, };
9563 u32 regidx;
9564 u32 bit;
9565 u32 crc;
9566
9567 netdev_for_each_mc_addr(ha, dev) {
9568 crc = calc_crc(ha->addr, ETH_ALEN);
9569 bit = ~crc & 0x7f;
9570 regidx = (bit & 0x60) >> 5;
9571 bit &= 0x1f;
9572 mc_filter[regidx] |= (1 << bit);
9573 }
9574
9575 tw32(MAC_HASH_REG_0, mc_filter[0]);
9576 tw32(MAC_HASH_REG_1, mc_filter[1]);
9577 tw32(MAC_HASH_REG_2, mc_filter[2]);
9578 tw32(MAC_HASH_REG_3, mc_filter[3]);
9579 }
9580
9581 if (rx_mode != tp->rx_mode) {
9582 tp->rx_mode = rx_mode;
9583 tw32_f(MAC_RX_MODE, rx_mode);
9584 udelay(10);
9585 }
9586 }
9587
9588 static void tg3_set_rx_mode(struct net_device *dev)
9589 {
9590 struct tg3 *tp = netdev_priv(dev);
9591
9592 if (!netif_running(dev))
9593 return;
9594
9595 tg3_full_lock(tp, 0);
9596 __tg3_set_rx_mode(dev);
9597 tg3_full_unlock(tp);
9598 }
9599
9600 #define TG3_REGDUMP_LEN (32 * 1024)
9601
9602 static int tg3_get_regs_len(struct net_device *dev)
9603 {
9604 return TG3_REGDUMP_LEN;
9605 }
9606
9607 static void tg3_get_regs(struct net_device *dev,
9608 struct ethtool_regs *regs, void *_p)
9609 {
9610 u32 *p = _p;
9611 struct tg3 *tp = netdev_priv(dev);
9612 u8 *orig_p = _p;
9613 int i;
9614
9615 regs->version = 0;
9616
9617 memset(p, 0, TG3_REGDUMP_LEN);
9618
9619 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9620 return;
9621
9622 tg3_full_lock(tp, 0);
9623
9624 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9625 #define GET_REG32_LOOP(base, len) \
9626 do { p = (u32 *)(orig_p + (base)); \
9627 for (i = 0; i < len; i += 4) \
9628 __GET_REG32((base) + i); \
9629 } while (0)
9630 #define GET_REG32_1(reg) \
9631 do { p = (u32 *)(orig_p + (reg)); \
9632 __GET_REG32((reg)); \
9633 } while (0)
9634
9635 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9636 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9637 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9638 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9639 GET_REG32_1(SNDDATAC_MODE);
9640 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9641 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9642 GET_REG32_1(SNDBDC_MODE);
9643 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9644 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9645 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9646 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9647 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9648 GET_REG32_1(RCVDCC_MODE);
9649 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9650 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9651 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9652 GET_REG32_1(MBFREE_MODE);
9653 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9654 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9655 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9656 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9657 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9658 GET_REG32_1(RX_CPU_MODE);
9659 GET_REG32_1(RX_CPU_STATE);
9660 GET_REG32_1(RX_CPU_PGMCTR);
9661 GET_REG32_1(RX_CPU_HWBKPT);
9662 GET_REG32_1(TX_CPU_MODE);
9663 GET_REG32_1(TX_CPU_STATE);
9664 GET_REG32_1(TX_CPU_PGMCTR);
9665 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9666 GET_REG32_LOOP(FTQ_RESET, 0x120);
9667 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9668 GET_REG32_1(DMAC_MODE);
9669 GET_REG32_LOOP(GRC_MODE, 0x4c);
9670 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9671 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9672
9673 #undef __GET_REG32
9674 #undef GET_REG32_LOOP
9675 #undef GET_REG32_1
9676
9677 tg3_full_unlock(tp);
9678 }
9679
9680 static int tg3_get_eeprom_len(struct net_device *dev)
9681 {
9682 struct tg3 *tp = netdev_priv(dev);
9683
9684 return tp->nvram_size;
9685 }
9686
9687 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9688 {
9689 struct tg3 *tp = netdev_priv(dev);
9690 int ret;
9691 u8 *pd;
9692 u32 i, offset, len, b_offset, b_count;
9693 __be32 val;
9694
9695 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9696 return -EINVAL;
9697
9698 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9699 return -EAGAIN;
9700
9701 offset = eeprom->offset;
9702 len = eeprom->len;
9703 eeprom->len = 0;
9704
9705 eeprom->magic = TG3_EEPROM_MAGIC;
9706
9707 if (offset & 3) {
9708 /* adjustments to start on required 4 byte boundary */
9709 b_offset = offset & 3;
9710 b_count = 4 - b_offset;
9711 if (b_count > len) {
9712 /* i.e. offset=1 len=2 */
9713 b_count = len;
9714 }
9715 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9716 if (ret)
9717 return ret;
9718 memcpy(data, ((char *)&val) + b_offset, b_count);
9719 len -= b_count;
9720 offset += b_count;
9721 eeprom->len += b_count;
9722 }
9723
9724 /* read bytes upto the last 4 byte boundary */
9725 pd = &data[eeprom->len];
9726 for (i = 0; i < (len - (len & 3)); i += 4) {
9727 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9728 if (ret) {
9729 eeprom->len += i;
9730 return ret;
9731 }
9732 memcpy(pd + i, &val, 4);
9733 }
9734 eeprom->len += i;
9735
9736 if (len & 3) {
9737 /* read last bytes not ending on 4 byte boundary */
9738 pd = &data[eeprom->len];
9739 b_count = len & 3;
9740 b_offset = offset + len - b_count;
9741 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9742 if (ret)
9743 return ret;
9744 memcpy(pd, &val, b_count);
9745 eeprom->len += b_count;
9746 }
9747 return 0;
9748 }
9749
9750 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9751
9752 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9753 {
9754 struct tg3 *tp = netdev_priv(dev);
9755 int ret;
9756 u32 offset, len, b_offset, odd_len;
9757 u8 *buf;
9758 __be32 start, end;
9759
9760 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9761 return -EAGAIN;
9762
9763 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9764 eeprom->magic != TG3_EEPROM_MAGIC)
9765 return -EINVAL;
9766
9767 offset = eeprom->offset;
9768 len = eeprom->len;
9769
9770 if ((b_offset = (offset & 3))) {
9771 /* adjustments to start on required 4 byte boundary */
9772 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9773 if (ret)
9774 return ret;
9775 len += b_offset;
9776 offset &= ~3;
9777 if (len < 4)
9778 len = 4;
9779 }
9780
9781 odd_len = 0;
9782 if (len & 3) {
9783 /* adjustments to end on required 4 byte boundary */
9784 odd_len = 1;
9785 len = (len + 3) & ~3;
9786 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9787 if (ret)
9788 return ret;
9789 }
9790
9791 buf = data;
9792 if (b_offset || odd_len) {
9793 buf = kmalloc(len, GFP_KERNEL);
9794 if (!buf)
9795 return -ENOMEM;
9796 if (b_offset)
9797 memcpy(buf, &start, 4);
9798 if (odd_len)
9799 memcpy(buf+len-4, &end, 4);
9800 memcpy(buf + b_offset, data, eeprom->len);
9801 }
9802
9803 ret = tg3_nvram_write_block(tp, offset, len, buf);
9804
9805 if (buf != data)
9806 kfree(buf);
9807
9808 return ret;
9809 }
9810
9811 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9812 {
9813 struct tg3 *tp = netdev_priv(dev);
9814
9815 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9816 struct phy_device *phydev;
9817 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9818 return -EAGAIN;
9819 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9820 return phy_ethtool_gset(phydev, cmd);
9821 }
9822
9823 cmd->supported = (SUPPORTED_Autoneg);
9824
9825 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9826 cmd->supported |= (SUPPORTED_1000baseT_Half |
9827 SUPPORTED_1000baseT_Full);
9828
9829 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9830 cmd->supported |= (SUPPORTED_100baseT_Half |
9831 SUPPORTED_100baseT_Full |
9832 SUPPORTED_10baseT_Half |
9833 SUPPORTED_10baseT_Full |
9834 SUPPORTED_TP);
9835 cmd->port = PORT_TP;
9836 } else {
9837 cmd->supported |= SUPPORTED_FIBRE;
9838 cmd->port = PORT_FIBRE;
9839 }
9840
9841 cmd->advertising = tp->link_config.advertising;
9842 if (netif_running(dev)) {
9843 cmd->speed = tp->link_config.active_speed;
9844 cmd->duplex = tp->link_config.active_duplex;
9845 } else {
9846 cmd->speed = SPEED_INVALID;
9847 cmd->duplex = DUPLEX_INVALID;
9848 }
9849 cmd->phy_address = tp->phy_addr;
9850 cmd->transceiver = XCVR_INTERNAL;
9851 cmd->autoneg = tp->link_config.autoneg;
9852 cmd->maxtxpkt = 0;
9853 cmd->maxrxpkt = 0;
9854 return 0;
9855 }
9856
9857 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9858 {
9859 struct tg3 *tp = netdev_priv(dev);
9860
9861 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9862 struct phy_device *phydev;
9863 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9864 return -EAGAIN;
9865 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9866 return phy_ethtool_sset(phydev, cmd);
9867 }
9868
9869 if (cmd->autoneg != AUTONEG_ENABLE &&
9870 cmd->autoneg != AUTONEG_DISABLE)
9871 return -EINVAL;
9872
9873 if (cmd->autoneg == AUTONEG_DISABLE &&
9874 cmd->duplex != DUPLEX_FULL &&
9875 cmd->duplex != DUPLEX_HALF)
9876 return -EINVAL;
9877
9878 if (cmd->autoneg == AUTONEG_ENABLE) {
9879 u32 mask = ADVERTISED_Autoneg |
9880 ADVERTISED_Pause |
9881 ADVERTISED_Asym_Pause;
9882
9883 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9884 mask |= ADVERTISED_1000baseT_Half |
9885 ADVERTISED_1000baseT_Full;
9886
9887 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9888 mask |= ADVERTISED_100baseT_Half |
9889 ADVERTISED_100baseT_Full |
9890 ADVERTISED_10baseT_Half |
9891 ADVERTISED_10baseT_Full |
9892 ADVERTISED_TP;
9893 else
9894 mask |= ADVERTISED_FIBRE;
9895
9896 if (cmd->advertising & ~mask)
9897 return -EINVAL;
9898
9899 mask &= (ADVERTISED_1000baseT_Half |
9900 ADVERTISED_1000baseT_Full |
9901 ADVERTISED_100baseT_Half |
9902 ADVERTISED_100baseT_Full |
9903 ADVERTISED_10baseT_Half |
9904 ADVERTISED_10baseT_Full);
9905
9906 cmd->advertising &= mask;
9907 } else {
9908 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9909 if (cmd->speed != SPEED_1000)
9910 return -EINVAL;
9911
9912 if (cmd->duplex != DUPLEX_FULL)
9913 return -EINVAL;
9914 } else {
9915 if (cmd->speed != SPEED_100 &&
9916 cmd->speed != SPEED_10)
9917 return -EINVAL;
9918 }
9919 }
9920
9921 tg3_full_lock(tp, 0);
9922
9923 tp->link_config.autoneg = cmd->autoneg;
9924 if (cmd->autoneg == AUTONEG_ENABLE) {
9925 tp->link_config.advertising = (cmd->advertising |
9926 ADVERTISED_Autoneg);
9927 tp->link_config.speed = SPEED_INVALID;
9928 tp->link_config.duplex = DUPLEX_INVALID;
9929 } else {
9930 tp->link_config.advertising = 0;
9931 tp->link_config.speed = cmd->speed;
9932 tp->link_config.duplex = cmd->duplex;
9933 }
9934
9935 tp->link_config.orig_speed = tp->link_config.speed;
9936 tp->link_config.orig_duplex = tp->link_config.duplex;
9937 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9938
9939 if (netif_running(dev))
9940 tg3_setup_phy(tp, 1);
9941
9942 tg3_full_unlock(tp);
9943
9944 return 0;
9945 }
9946
9947 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9948 {
9949 struct tg3 *tp = netdev_priv(dev);
9950
9951 strcpy(info->driver, DRV_MODULE_NAME);
9952 strcpy(info->version, DRV_MODULE_VERSION);
9953 strcpy(info->fw_version, tp->fw_ver);
9954 strcpy(info->bus_info, pci_name(tp->pdev));
9955 }
9956
9957 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9958 {
9959 struct tg3 *tp = netdev_priv(dev);
9960
9961 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9962 device_can_wakeup(&tp->pdev->dev))
9963 wol->supported = WAKE_MAGIC;
9964 else
9965 wol->supported = 0;
9966 wol->wolopts = 0;
9967 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9968 device_can_wakeup(&tp->pdev->dev))
9969 wol->wolopts = WAKE_MAGIC;
9970 memset(&wol->sopass, 0, sizeof(wol->sopass));
9971 }
9972
9973 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9974 {
9975 struct tg3 *tp = netdev_priv(dev);
9976 struct device *dp = &tp->pdev->dev;
9977
9978 if (wol->wolopts & ~WAKE_MAGIC)
9979 return -EINVAL;
9980 if ((wol->wolopts & WAKE_MAGIC) &&
9981 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9982 return -EINVAL;
9983
9984 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9985
9986 spin_lock_bh(&tp->lock);
9987 if (device_may_wakeup(dp))
9988 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9989 else
9990 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9991 spin_unlock_bh(&tp->lock);
9992
9993
9994 return 0;
9995 }
9996
9997 static u32 tg3_get_msglevel(struct net_device *dev)
9998 {
9999 struct tg3 *tp = netdev_priv(dev);
10000 return tp->msg_enable;
10001 }
10002
10003 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10004 {
10005 struct tg3 *tp = netdev_priv(dev);
10006 tp->msg_enable = value;
10007 }
10008
10009 static int tg3_set_tso(struct net_device *dev, u32 value)
10010 {
10011 struct tg3 *tp = netdev_priv(dev);
10012
10013 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10014 if (value)
10015 return -EINVAL;
10016 return 0;
10017 }
10018 if ((dev->features & NETIF_F_IPV6_CSUM) &&
10019 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10020 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10021 if (value) {
10022 dev->features |= NETIF_F_TSO6;
10023 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10025 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10026 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10029 dev->features |= NETIF_F_TSO_ECN;
10030 } else
10031 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10032 }
10033 return ethtool_op_set_tso(dev, value);
10034 }
10035
10036 static int tg3_nway_reset(struct net_device *dev)
10037 {
10038 struct tg3 *tp = netdev_priv(dev);
10039 int r;
10040
10041 if (!netif_running(dev))
10042 return -EAGAIN;
10043
10044 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10045 return -EINVAL;
10046
10047 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10048 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10049 return -EAGAIN;
10050 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10051 } else {
10052 u32 bmcr;
10053
10054 spin_lock_bh(&tp->lock);
10055 r = -EINVAL;
10056 tg3_readphy(tp, MII_BMCR, &bmcr);
10057 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10058 ((bmcr & BMCR_ANENABLE) ||
10059 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10060 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10061 BMCR_ANENABLE);
10062 r = 0;
10063 }
10064 spin_unlock_bh(&tp->lock);
10065 }
10066
10067 return r;
10068 }
10069
10070 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10071 {
10072 struct tg3 *tp = netdev_priv(dev);
10073
10074 ering->rx_max_pending = tp->rx_std_ring_mask;
10075 ering->rx_mini_max_pending = 0;
10076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10077 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10078 else
10079 ering->rx_jumbo_max_pending = 0;
10080
10081 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10082
10083 ering->rx_pending = tp->rx_pending;
10084 ering->rx_mini_pending = 0;
10085 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10086 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10087 else
10088 ering->rx_jumbo_pending = 0;
10089
10090 ering->tx_pending = tp->napi[0].tx_pending;
10091 }
10092
10093 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10094 {
10095 struct tg3 *tp = netdev_priv(dev);
10096 int i, irq_sync = 0, err = 0;
10097
10098 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10099 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10100 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10101 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10102 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10103 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10104 return -EINVAL;
10105
10106 if (netif_running(dev)) {
10107 tg3_phy_stop(tp);
10108 tg3_netif_stop(tp);
10109 irq_sync = 1;
10110 }
10111
10112 tg3_full_lock(tp, irq_sync);
10113
10114 tp->rx_pending = ering->rx_pending;
10115
10116 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10117 tp->rx_pending > 63)
10118 tp->rx_pending = 63;
10119 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10120
10121 for (i = 0; i < tp->irq_max; i++)
10122 tp->napi[i].tx_pending = ering->tx_pending;
10123
10124 if (netif_running(dev)) {
10125 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10126 err = tg3_restart_hw(tp, 1);
10127 if (!err)
10128 tg3_netif_start(tp);
10129 }
10130
10131 tg3_full_unlock(tp);
10132
10133 if (irq_sync && !err)
10134 tg3_phy_start(tp);
10135
10136 return err;
10137 }
10138
10139 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10140 {
10141 struct tg3 *tp = netdev_priv(dev);
10142
10143 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10144
10145 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10146 epause->rx_pause = 1;
10147 else
10148 epause->rx_pause = 0;
10149
10150 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10151 epause->tx_pause = 1;
10152 else
10153 epause->tx_pause = 0;
10154 }
10155
10156 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10157 {
10158 struct tg3 *tp = netdev_priv(dev);
10159 int err = 0;
10160
10161 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10162 u32 newadv;
10163 struct phy_device *phydev;
10164
10165 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10166
10167 if (!(phydev->supported & SUPPORTED_Pause) ||
10168 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10169 (epause->rx_pause != epause->tx_pause)))
10170 return -EINVAL;
10171
10172 tp->link_config.flowctrl = 0;
10173 if (epause->rx_pause) {
10174 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10175
10176 if (epause->tx_pause) {
10177 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10178 newadv = ADVERTISED_Pause;
10179 } else
10180 newadv = ADVERTISED_Pause |
10181 ADVERTISED_Asym_Pause;
10182 } else if (epause->tx_pause) {
10183 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10184 newadv = ADVERTISED_Asym_Pause;
10185 } else
10186 newadv = 0;
10187
10188 if (epause->autoneg)
10189 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10190 else
10191 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10192
10193 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10194 u32 oldadv = phydev->advertising &
10195 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10196 if (oldadv != newadv) {
10197 phydev->advertising &=
10198 ~(ADVERTISED_Pause |
10199 ADVERTISED_Asym_Pause);
10200 phydev->advertising |= newadv;
10201 if (phydev->autoneg) {
10202 /*
10203 * Always renegotiate the link to
10204 * inform our link partner of our
10205 * flow control settings, even if the
10206 * flow control is forced. Let
10207 * tg3_adjust_link() do the final
10208 * flow control setup.
10209 */
10210 return phy_start_aneg(phydev);
10211 }
10212 }
10213
10214 if (!epause->autoneg)
10215 tg3_setup_flow_control(tp, 0, 0);
10216 } else {
10217 tp->link_config.orig_advertising &=
10218 ~(ADVERTISED_Pause |
10219 ADVERTISED_Asym_Pause);
10220 tp->link_config.orig_advertising |= newadv;
10221 }
10222 } else {
10223 int irq_sync = 0;
10224
10225 if (netif_running(dev)) {
10226 tg3_netif_stop(tp);
10227 irq_sync = 1;
10228 }
10229
10230 tg3_full_lock(tp, irq_sync);
10231
10232 if (epause->autoneg)
10233 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10234 else
10235 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10236 if (epause->rx_pause)
10237 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10238 else
10239 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10240 if (epause->tx_pause)
10241 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10242 else
10243 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10244
10245 if (netif_running(dev)) {
10246 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10247 err = tg3_restart_hw(tp, 1);
10248 if (!err)
10249 tg3_netif_start(tp);
10250 }
10251
10252 tg3_full_unlock(tp);
10253 }
10254
10255 return err;
10256 }
10257
10258 static u32 tg3_get_rx_csum(struct net_device *dev)
10259 {
10260 struct tg3 *tp = netdev_priv(dev);
10261 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10262 }
10263
10264 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10265 {
10266 struct tg3 *tp = netdev_priv(dev);
10267
10268 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10269 if (data != 0)
10270 return -EINVAL;
10271 return 0;
10272 }
10273
10274 spin_lock_bh(&tp->lock);
10275 if (data)
10276 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10277 else
10278 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10279 spin_unlock_bh(&tp->lock);
10280
10281 return 0;
10282 }
10283
10284 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10285 {
10286 struct tg3 *tp = netdev_priv(dev);
10287
10288 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10289 if (data != 0)
10290 return -EINVAL;
10291 return 0;
10292 }
10293
10294 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10295 ethtool_op_set_tx_ipv6_csum(dev, data);
10296 else
10297 ethtool_op_set_tx_csum(dev, data);
10298
10299 return 0;
10300 }
10301
10302 static int tg3_get_sset_count(struct net_device *dev, int sset)
10303 {
10304 switch (sset) {
10305 case ETH_SS_TEST:
10306 return TG3_NUM_TEST;
10307 case ETH_SS_STATS:
10308 return TG3_NUM_STATS;
10309 default:
10310 return -EOPNOTSUPP;
10311 }
10312 }
10313
10314 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10315 {
10316 switch (stringset) {
10317 case ETH_SS_STATS:
10318 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10319 break;
10320 case ETH_SS_TEST:
10321 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10322 break;
10323 default:
10324 WARN_ON(1); /* we need a WARN() */
10325 break;
10326 }
10327 }
10328
10329 static int tg3_phys_id(struct net_device *dev, u32 data)
10330 {
10331 struct tg3 *tp = netdev_priv(dev);
10332 int i;
10333
10334 if (!netif_running(tp->dev))
10335 return -EAGAIN;
10336
10337 if (data == 0)
10338 data = UINT_MAX / 2;
10339
10340 for (i = 0; i < (data * 2); i++) {
10341 if ((i % 2) == 0)
10342 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10343 LED_CTRL_1000MBPS_ON |
10344 LED_CTRL_100MBPS_ON |
10345 LED_CTRL_10MBPS_ON |
10346 LED_CTRL_TRAFFIC_OVERRIDE |
10347 LED_CTRL_TRAFFIC_BLINK |
10348 LED_CTRL_TRAFFIC_LED);
10349
10350 else
10351 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10352 LED_CTRL_TRAFFIC_OVERRIDE);
10353
10354 if (msleep_interruptible(500))
10355 break;
10356 }
10357 tw32(MAC_LED_CTRL, tp->led_ctrl);
10358 return 0;
10359 }
10360
10361 static void tg3_get_ethtool_stats(struct net_device *dev,
10362 struct ethtool_stats *estats, u64 *tmp_stats)
10363 {
10364 struct tg3 *tp = netdev_priv(dev);
10365 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10366 }
10367
10368 #define NVRAM_TEST_SIZE 0x100
10369 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10370 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10371 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10372 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10373 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10374
10375 static int tg3_test_nvram(struct tg3 *tp)
10376 {
10377 u32 csum, magic;
10378 __be32 *buf;
10379 int i, j, k, err = 0, size;
10380
10381 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10382 return 0;
10383
10384 if (tg3_nvram_read(tp, 0, &magic) != 0)
10385 return -EIO;
10386
10387 if (magic == TG3_EEPROM_MAGIC)
10388 size = NVRAM_TEST_SIZE;
10389 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10390 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10391 TG3_EEPROM_SB_FORMAT_1) {
10392 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10393 case TG3_EEPROM_SB_REVISION_0:
10394 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10395 break;
10396 case TG3_EEPROM_SB_REVISION_2:
10397 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10398 break;
10399 case TG3_EEPROM_SB_REVISION_3:
10400 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10401 break;
10402 default:
10403 return 0;
10404 }
10405 } else
10406 return 0;
10407 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10408 size = NVRAM_SELFBOOT_HW_SIZE;
10409 else
10410 return -EIO;
10411
10412 buf = kmalloc(size, GFP_KERNEL);
10413 if (buf == NULL)
10414 return -ENOMEM;
10415
10416 err = -EIO;
10417 for (i = 0, j = 0; i < size; i += 4, j++) {
10418 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10419 if (err)
10420 break;
10421 }
10422 if (i < size)
10423 goto out;
10424
10425 /* Selfboot format */
10426 magic = be32_to_cpu(buf[0]);
10427 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10428 TG3_EEPROM_MAGIC_FW) {
10429 u8 *buf8 = (u8 *) buf, csum8 = 0;
10430
10431 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10432 TG3_EEPROM_SB_REVISION_2) {
10433 /* For rev 2, the csum doesn't include the MBA. */
10434 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10435 csum8 += buf8[i];
10436 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10437 csum8 += buf8[i];
10438 } else {
10439 for (i = 0; i < size; i++)
10440 csum8 += buf8[i];
10441 }
10442
10443 if (csum8 == 0) {
10444 err = 0;
10445 goto out;
10446 }
10447
10448 err = -EIO;
10449 goto out;
10450 }
10451
10452 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10453 TG3_EEPROM_MAGIC_HW) {
10454 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10455 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10456 u8 *buf8 = (u8 *) buf;
10457
10458 /* Separate the parity bits and the data bytes. */
10459 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10460 if ((i == 0) || (i == 8)) {
10461 int l;
10462 u8 msk;
10463
10464 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10465 parity[k++] = buf8[i] & msk;
10466 i++;
10467 } else if (i == 16) {
10468 int l;
10469 u8 msk;
10470
10471 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10472 parity[k++] = buf8[i] & msk;
10473 i++;
10474
10475 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10476 parity[k++] = buf8[i] & msk;
10477 i++;
10478 }
10479 data[j++] = buf8[i];
10480 }
10481
10482 err = -EIO;
10483 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10484 u8 hw8 = hweight8(data[i]);
10485
10486 if ((hw8 & 0x1) && parity[i])
10487 goto out;
10488 else if (!(hw8 & 0x1) && !parity[i])
10489 goto out;
10490 }
10491 err = 0;
10492 goto out;
10493 }
10494
10495 /* Bootstrap checksum at offset 0x10 */
10496 csum = calc_crc((unsigned char *) buf, 0x10);
10497 if (csum != be32_to_cpu(buf[0x10/4]))
10498 goto out;
10499
10500 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10501 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10502 if (csum != be32_to_cpu(buf[0xfc/4]))
10503 goto out;
10504
10505 err = 0;
10506
10507 out:
10508 kfree(buf);
10509 return err;
10510 }
10511
10512 #define TG3_SERDES_TIMEOUT_SEC 2
10513 #define TG3_COPPER_TIMEOUT_SEC 6
10514
10515 static int tg3_test_link(struct tg3 *tp)
10516 {
10517 int i, max;
10518
10519 if (!netif_running(tp->dev))
10520 return -ENODEV;
10521
10522 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10523 max = TG3_SERDES_TIMEOUT_SEC;
10524 else
10525 max = TG3_COPPER_TIMEOUT_SEC;
10526
10527 for (i = 0; i < max; i++) {
10528 if (netif_carrier_ok(tp->dev))
10529 return 0;
10530
10531 if (msleep_interruptible(1000))
10532 break;
10533 }
10534
10535 return -EIO;
10536 }
10537
10538 /* Only test the commonly used registers */
10539 static int tg3_test_registers(struct tg3 *tp)
10540 {
10541 int i, is_5705, is_5750;
10542 u32 offset, read_mask, write_mask, val, save_val, read_val;
10543 static struct {
10544 u16 offset;
10545 u16 flags;
10546 #define TG3_FL_5705 0x1
10547 #define TG3_FL_NOT_5705 0x2
10548 #define TG3_FL_NOT_5788 0x4
10549 #define TG3_FL_NOT_5750 0x8
10550 u32 read_mask;
10551 u32 write_mask;
10552 } reg_tbl[] = {
10553 /* MAC Control Registers */
10554 { MAC_MODE, TG3_FL_NOT_5705,
10555 0x00000000, 0x00ef6f8c },
10556 { MAC_MODE, TG3_FL_5705,
10557 0x00000000, 0x01ef6b8c },
10558 { MAC_STATUS, TG3_FL_NOT_5705,
10559 0x03800107, 0x00000000 },
10560 { MAC_STATUS, TG3_FL_5705,
10561 0x03800100, 0x00000000 },
10562 { MAC_ADDR_0_HIGH, 0x0000,
10563 0x00000000, 0x0000ffff },
10564 { MAC_ADDR_0_LOW, 0x0000,
10565 0x00000000, 0xffffffff },
10566 { MAC_RX_MTU_SIZE, 0x0000,
10567 0x00000000, 0x0000ffff },
10568 { MAC_TX_MODE, 0x0000,
10569 0x00000000, 0x00000070 },
10570 { MAC_TX_LENGTHS, 0x0000,
10571 0x00000000, 0x00003fff },
10572 { MAC_RX_MODE, TG3_FL_NOT_5705,
10573 0x00000000, 0x000007fc },
10574 { MAC_RX_MODE, TG3_FL_5705,
10575 0x00000000, 0x000007dc },
10576 { MAC_HASH_REG_0, 0x0000,
10577 0x00000000, 0xffffffff },
10578 { MAC_HASH_REG_1, 0x0000,
10579 0x00000000, 0xffffffff },
10580 { MAC_HASH_REG_2, 0x0000,
10581 0x00000000, 0xffffffff },
10582 { MAC_HASH_REG_3, 0x0000,
10583 0x00000000, 0xffffffff },
10584
10585 /* Receive Data and Receive BD Initiator Control Registers. */
10586 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10587 0x00000000, 0xffffffff },
10588 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10589 0x00000000, 0xffffffff },
10590 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10591 0x00000000, 0x00000003 },
10592 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10593 0x00000000, 0xffffffff },
10594 { RCVDBDI_STD_BD+0, 0x0000,
10595 0x00000000, 0xffffffff },
10596 { RCVDBDI_STD_BD+4, 0x0000,
10597 0x00000000, 0xffffffff },
10598 { RCVDBDI_STD_BD+8, 0x0000,
10599 0x00000000, 0xffff0002 },
10600 { RCVDBDI_STD_BD+0xc, 0x0000,
10601 0x00000000, 0xffffffff },
10602
10603 /* Receive BD Initiator Control Registers. */
10604 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10605 0x00000000, 0xffffffff },
10606 { RCVBDI_STD_THRESH, TG3_FL_5705,
10607 0x00000000, 0x000003ff },
10608 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10609 0x00000000, 0xffffffff },
10610
10611 /* Host Coalescing Control Registers. */
10612 { HOSTCC_MODE, TG3_FL_NOT_5705,
10613 0x00000000, 0x00000004 },
10614 { HOSTCC_MODE, TG3_FL_5705,
10615 0x00000000, 0x000000f6 },
10616 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10617 0x00000000, 0xffffffff },
10618 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10619 0x00000000, 0x000003ff },
10620 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10621 0x00000000, 0xffffffff },
10622 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10623 0x00000000, 0x000003ff },
10624 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10625 0x00000000, 0xffffffff },
10626 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10627 0x00000000, 0x000000ff },
10628 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10629 0x00000000, 0xffffffff },
10630 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10631 0x00000000, 0x000000ff },
10632 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10633 0x00000000, 0xffffffff },
10634 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10635 0x00000000, 0xffffffff },
10636 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10637 0x00000000, 0xffffffff },
10638 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10639 0x00000000, 0x000000ff },
10640 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10641 0x00000000, 0xffffffff },
10642 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10643 0x00000000, 0x000000ff },
10644 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10645 0x00000000, 0xffffffff },
10646 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10647 0x00000000, 0xffffffff },
10648 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10649 0x00000000, 0xffffffff },
10650 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10651 0x00000000, 0xffffffff },
10652 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10653 0x00000000, 0xffffffff },
10654 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10655 0xffffffff, 0x00000000 },
10656 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10657 0xffffffff, 0x00000000 },
10658
10659 /* Buffer Manager Control Registers. */
10660 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10661 0x00000000, 0x007fff80 },
10662 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10663 0x00000000, 0x007fffff },
10664 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10665 0x00000000, 0x0000003f },
10666 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10667 0x00000000, 0x000001ff },
10668 { BUFMGR_MB_HIGH_WATER, 0x0000,
10669 0x00000000, 0x000001ff },
10670 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10671 0xffffffff, 0x00000000 },
10672 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10673 0xffffffff, 0x00000000 },
10674
10675 /* Mailbox Registers */
10676 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10677 0x00000000, 0x000001ff },
10678 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10679 0x00000000, 0x000001ff },
10680 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10681 0x00000000, 0x000007ff },
10682 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10683 0x00000000, 0x000001ff },
10684
10685 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10686 };
10687
10688 is_5705 = is_5750 = 0;
10689 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10690 is_5705 = 1;
10691 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10692 is_5750 = 1;
10693 }
10694
10695 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10696 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10697 continue;
10698
10699 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10700 continue;
10701
10702 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10703 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10704 continue;
10705
10706 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10707 continue;
10708
10709 offset = (u32) reg_tbl[i].offset;
10710 read_mask = reg_tbl[i].read_mask;
10711 write_mask = reg_tbl[i].write_mask;
10712
10713 /* Save the original register content */
10714 save_val = tr32(offset);
10715
10716 /* Determine the read-only value. */
10717 read_val = save_val & read_mask;
10718
10719 /* Write zero to the register, then make sure the read-only bits
10720 * are not changed and the read/write bits are all zeros.
10721 */
10722 tw32(offset, 0);
10723
10724 val = tr32(offset);
10725
10726 /* Test the read-only and read/write bits. */
10727 if (((val & read_mask) != read_val) || (val & write_mask))
10728 goto out;
10729
10730 /* Write ones to all the bits defined by RdMask and WrMask, then
10731 * make sure the read-only bits are not changed and the
10732 * read/write bits are all ones.
10733 */
10734 tw32(offset, read_mask | write_mask);
10735
10736 val = tr32(offset);
10737
10738 /* Test the read-only bits. */
10739 if ((val & read_mask) != read_val)
10740 goto out;
10741
10742 /* Test the read/write bits. */
10743 if ((val & write_mask) != write_mask)
10744 goto out;
10745
10746 tw32(offset, save_val);
10747 }
10748
10749 return 0;
10750
10751 out:
10752 if (netif_msg_hw(tp))
10753 netdev_err(tp->dev,
10754 "Register test failed at offset %x\n", offset);
10755 tw32(offset, save_val);
10756 return -EIO;
10757 }
10758
10759 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10760 {
10761 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10762 int i;
10763 u32 j;
10764
10765 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10766 for (j = 0; j < len; j += 4) {
10767 u32 val;
10768
10769 tg3_write_mem(tp, offset + j, test_pattern[i]);
10770 tg3_read_mem(tp, offset + j, &val);
10771 if (val != test_pattern[i])
10772 return -EIO;
10773 }
10774 }
10775 return 0;
10776 }
10777
10778 static int tg3_test_memory(struct tg3 *tp)
10779 {
10780 static struct mem_entry {
10781 u32 offset;
10782 u32 len;
10783 } mem_tbl_570x[] = {
10784 { 0x00000000, 0x00b50},
10785 { 0x00002000, 0x1c000},
10786 { 0xffffffff, 0x00000}
10787 }, mem_tbl_5705[] = {
10788 { 0x00000100, 0x0000c},
10789 { 0x00000200, 0x00008},
10790 { 0x00004000, 0x00800},
10791 { 0x00006000, 0x01000},
10792 { 0x00008000, 0x02000},
10793 { 0x00010000, 0x0e000},
10794 { 0xffffffff, 0x00000}
10795 }, mem_tbl_5755[] = {
10796 { 0x00000200, 0x00008},
10797 { 0x00004000, 0x00800},
10798 { 0x00006000, 0x00800},
10799 { 0x00008000, 0x02000},
10800 { 0x00010000, 0x0c000},
10801 { 0xffffffff, 0x00000}
10802 }, mem_tbl_5906[] = {
10803 { 0x00000200, 0x00008},
10804 { 0x00004000, 0x00400},
10805 { 0x00006000, 0x00400},
10806 { 0x00008000, 0x01000},
10807 { 0x00010000, 0x01000},
10808 { 0xffffffff, 0x00000}
10809 }, mem_tbl_5717[] = {
10810 { 0x00000200, 0x00008},
10811 { 0x00010000, 0x0a000},
10812 { 0x00020000, 0x13c00},
10813 { 0xffffffff, 0x00000}
10814 }, mem_tbl_57765[] = {
10815 { 0x00000200, 0x00008},
10816 { 0x00004000, 0x00800},
10817 { 0x00006000, 0x09800},
10818 { 0x00010000, 0x0a000},
10819 { 0xffffffff, 0x00000}
10820 };
10821 struct mem_entry *mem_tbl;
10822 int err = 0;
10823 int i;
10824
10825 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10826 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10827 mem_tbl = mem_tbl_5717;
10828 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10829 mem_tbl = mem_tbl_57765;
10830 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10831 mem_tbl = mem_tbl_5755;
10832 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10833 mem_tbl = mem_tbl_5906;
10834 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10835 mem_tbl = mem_tbl_5705;
10836 else
10837 mem_tbl = mem_tbl_570x;
10838
10839 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10840 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10841 if (err)
10842 break;
10843 }
10844
10845 return err;
10846 }
10847
10848 #define TG3_MAC_LOOPBACK 0
10849 #define TG3_PHY_LOOPBACK 1
10850
10851 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10852 {
10853 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10854 u32 desc_idx, coal_now;
10855 struct sk_buff *skb, *rx_skb;
10856 u8 *tx_data;
10857 dma_addr_t map;
10858 int num_pkts, tx_len, rx_len, i, err;
10859 struct tg3_rx_buffer_desc *desc;
10860 struct tg3_napi *tnapi, *rnapi;
10861 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10862
10863 tnapi = &tp->napi[0];
10864 rnapi = &tp->napi[0];
10865 if (tp->irq_cnt > 1) {
10866 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10867 rnapi = &tp->napi[1];
10868 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10869 tnapi = &tp->napi[1];
10870 }
10871 coal_now = tnapi->coal_now | rnapi->coal_now;
10872
10873 if (loopback_mode == TG3_MAC_LOOPBACK) {
10874 /* HW errata - mac loopback fails in some cases on 5780.
10875 * Normal traffic and PHY loopback are not affected by
10876 * errata.
10877 */
10878 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10879 return 0;
10880
10881 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10882 MAC_MODE_PORT_INT_LPBACK;
10883 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10884 mac_mode |= MAC_MODE_LINK_POLARITY;
10885 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10886 mac_mode |= MAC_MODE_PORT_MODE_MII;
10887 else
10888 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10889 tw32(MAC_MODE, mac_mode);
10890 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10891 u32 val;
10892
10893 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10894 tg3_phy_fet_toggle_apd(tp, false);
10895 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10896 } else
10897 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10898
10899 tg3_phy_toggle_automdix(tp, 0);
10900
10901 tg3_writephy(tp, MII_BMCR, val);
10902 udelay(40);
10903
10904 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10905 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10906 tg3_writephy(tp, MII_TG3_FET_PTEST,
10907 MII_TG3_FET_PTEST_FRC_TX_LINK |
10908 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10909 /* The write needs to be flushed for the AC131 */
10910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10911 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10912 mac_mode |= MAC_MODE_PORT_MODE_MII;
10913 } else
10914 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10915
10916 /* reset to prevent losing 1st rx packet intermittently */
10917 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10918 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10919 udelay(10);
10920 tw32_f(MAC_RX_MODE, tp->rx_mode);
10921 }
10922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10923 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10924 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10925 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10926 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10927 mac_mode |= MAC_MODE_LINK_POLARITY;
10928 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10929 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10930 }
10931 tw32(MAC_MODE, mac_mode);
10932 } else {
10933 return -EINVAL;
10934 }
10935
10936 err = -EIO;
10937
10938 tx_len = 1514;
10939 skb = netdev_alloc_skb(tp->dev, tx_len);
10940 if (!skb)
10941 return -ENOMEM;
10942
10943 tx_data = skb_put(skb, tx_len);
10944 memcpy(tx_data, tp->dev->dev_addr, 6);
10945 memset(tx_data + 6, 0x0, 8);
10946
10947 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10948
10949 for (i = 14; i < tx_len; i++)
10950 tx_data[i] = (u8) (i & 0xff);
10951
10952 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10953 if (pci_dma_mapping_error(tp->pdev, map)) {
10954 dev_kfree_skb(skb);
10955 return -EIO;
10956 }
10957
10958 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10959 rnapi->coal_now);
10960
10961 udelay(10);
10962
10963 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10964
10965 num_pkts = 0;
10966
10967 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10968
10969 tnapi->tx_prod++;
10970 num_pkts++;
10971
10972 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10973 tr32_mailbox(tnapi->prodmbox);
10974
10975 udelay(10);
10976
10977 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10978 for (i = 0; i < 35; i++) {
10979 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10980 coal_now);
10981
10982 udelay(10);
10983
10984 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10985 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10986 if ((tx_idx == tnapi->tx_prod) &&
10987 (rx_idx == (rx_start_idx + num_pkts)))
10988 break;
10989 }
10990
10991 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10992 dev_kfree_skb(skb);
10993
10994 if (tx_idx != tnapi->tx_prod)
10995 goto out;
10996
10997 if (rx_idx != rx_start_idx + num_pkts)
10998 goto out;
10999
11000 desc = &rnapi->rx_rcb[rx_start_idx];
11001 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11002 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11003 if (opaque_key != RXD_OPAQUE_RING_STD)
11004 goto out;
11005
11006 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11007 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11008 goto out;
11009
11010 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11011 if (rx_len != tx_len)
11012 goto out;
11013
11014 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11015
11016 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11017 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11018
11019 for (i = 14; i < tx_len; i++) {
11020 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11021 goto out;
11022 }
11023 err = 0;
11024
11025 /* tg3_free_rings will unmap and free the rx_skb */
11026 out:
11027 return err;
11028 }
11029
11030 #define TG3_MAC_LOOPBACK_FAILED 1
11031 #define TG3_PHY_LOOPBACK_FAILED 2
11032 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11033 TG3_PHY_LOOPBACK_FAILED)
11034
11035 static int tg3_test_loopback(struct tg3 *tp)
11036 {
11037 int err = 0;
11038 u32 cpmuctrl = 0;
11039
11040 if (!netif_running(tp->dev))
11041 return TG3_LOOPBACK_FAILED;
11042
11043 err = tg3_reset_hw(tp, 1);
11044 if (err)
11045 return TG3_LOOPBACK_FAILED;
11046
11047 /* Turn off gphy autopowerdown. */
11048 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11049 tg3_phy_toggle_apd(tp, false);
11050
11051 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11052 int i;
11053 u32 status;
11054
11055 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11056
11057 /* Wait for up to 40 microseconds to acquire lock. */
11058 for (i = 0; i < 4; i++) {
11059 status = tr32(TG3_CPMU_MUTEX_GNT);
11060 if (status == CPMU_MUTEX_GNT_DRIVER)
11061 break;
11062 udelay(10);
11063 }
11064
11065 if (status != CPMU_MUTEX_GNT_DRIVER)
11066 return TG3_LOOPBACK_FAILED;
11067
11068 /* Turn off link-based power management. */
11069 cpmuctrl = tr32(TG3_CPMU_CTRL);
11070 tw32(TG3_CPMU_CTRL,
11071 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11072 CPMU_CTRL_LINK_AWARE_MODE));
11073 }
11074
11075 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11076 err |= TG3_MAC_LOOPBACK_FAILED;
11077
11078 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11079 tw32(TG3_CPMU_CTRL, cpmuctrl);
11080
11081 /* Release the mutex */
11082 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11083 }
11084
11085 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11086 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11087 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11088 err |= TG3_PHY_LOOPBACK_FAILED;
11089 }
11090
11091 /* Re-enable gphy autopowerdown. */
11092 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11093 tg3_phy_toggle_apd(tp, true);
11094
11095 return err;
11096 }
11097
11098 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11099 u64 *data)
11100 {
11101 struct tg3 *tp = netdev_priv(dev);
11102
11103 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11104 tg3_power_up(tp);
11105
11106 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11107
11108 if (tg3_test_nvram(tp) != 0) {
11109 etest->flags |= ETH_TEST_FL_FAILED;
11110 data[0] = 1;
11111 }
11112 if (tg3_test_link(tp) != 0) {
11113 etest->flags |= ETH_TEST_FL_FAILED;
11114 data[1] = 1;
11115 }
11116 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11117 int err, err2 = 0, irq_sync = 0;
11118
11119 if (netif_running(dev)) {
11120 tg3_phy_stop(tp);
11121 tg3_netif_stop(tp);
11122 irq_sync = 1;
11123 }
11124
11125 tg3_full_lock(tp, irq_sync);
11126
11127 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11128 err = tg3_nvram_lock(tp);
11129 tg3_halt_cpu(tp, RX_CPU_BASE);
11130 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11131 tg3_halt_cpu(tp, TX_CPU_BASE);
11132 if (!err)
11133 tg3_nvram_unlock(tp);
11134
11135 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11136 tg3_phy_reset(tp);
11137
11138 if (tg3_test_registers(tp) != 0) {
11139 etest->flags |= ETH_TEST_FL_FAILED;
11140 data[2] = 1;
11141 }
11142 if (tg3_test_memory(tp) != 0) {
11143 etest->flags |= ETH_TEST_FL_FAILED;
11144 data[3] = 1;
11145 }
11146 if ((data[4] = tg3_test_loopback(tp)) != 0)
11147 etest->flags |= ETH_TEST_FL_FAILED;
11148
11149 tg3_full_unlock(tp);
11150
11151 if (tg3_test_interrupt(tp) != 0) {
11152 etest->flags |= ETH_TEST_FL_FAILED;
11153 data[5] = 1;
11154 }
11155
11156 tg3_full_lock(tp, 0);
11157
11158 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11159 if (netif_running(dev)) {
11160 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11161 err2 = tg3_restart_hw(tp, 1);
11162 if (!err2)
11163 tg3_netif_start(tp);
11164 }
11165
11166 tg3_full_unlock(tp);
11167
11168 if (irq_sync && !err2)
11169 tg3_phy_start(tp);
11170 }
11171 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11172 tg3_power_down(tp);
11173
11174 }
11175
11176 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11177 {
11178 struct mii_ioctl_data *data = if_mii(ifr);
11179 struct tg3 *tp = netdev_priv(dev);
11180 int err;
11181
11182 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11183 struct phy_device *phydev;
11184 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11185 return -EAGAIN;
11186 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11187 return phy_mii_ioctl(phydev, ifr, cmd);
11188 }
11189
11190 switch (cmd) {
11191 case SIOCGMIIPHY:
11192 data->phy_id = tp->phy_addr;
11193
11194 /* fallthru */
11195 case SIOCGMIIREG: {
11196 u32 mii_regval;
11197
11198 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11199 break; /* We have no PHY */
11200
11201 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11202 return -EAGAIN;
11203
11204 spin_lock_bh(&tp->lock);
11205 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11206 spin_unlock_bh(&tp->lock);
11207
11208 data->val_out = mii_regval;
11209
11210 return err;
11211 }
11212
11213 case SIOCSMIIREG:
11214 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11215 break; /* We have no PHY */
11216
11217 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11218 return -EAGAIN;
11219
11220 spin_lock_bh(&tp->lock);
11221 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11222 spin_unlock_bh(&tp->lock);
11223
11224 return err;
11225
11226 default:
11227 /* do nothing */
11228 break;
11229 }
11230 return -EOPNOTSUPP;
11231 }
11232
11233 #if TG3_VLAN_TAG_USED
11234 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11235 {
11236 struct tg3 *tp = netdev_priv(dev);
11237
11238 if (!netif_running(dev)) {
11239 tp->vlgrp = grp;
11240 return;
11241 }
11242
11243 tg3_netif_stop(tp);
11244
11245 tg3_full_lock(tp, 0);
11246
11247 tp->vlgrp = grp;
11248
11249 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11250 __tg3_set_rx_mode(dev);
11251
11252 tg3_netif_start(tp);
11253
11254 tg3_full_unlock(tp);
11255 }
11256 #endif
11257
11258 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11259 {
11260 struct tg3 *tp = netdev_priv(dev);
11261
11262 memcpy(ec, &tp->coal, sizeof(*ec));
11263 return 0;
11264 }
11265
11266 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11267 {
11268 struct tg3 *tp = netdev_priv(dev);
11269 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11270 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11271
11272 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11273 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11274 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11275 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11276 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11277 }
11278
11279 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11280 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11281 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11282 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11283 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11284 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11285 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11286 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11287 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11288 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11289 return -EINVAL;
11290
11291 /* No rx interrupts will be generated if both are zero */
11292 if ((ec->rx_coalesce_usecs == 0) &&
11293 (ec->rx_max_coalesced_frames == 0))
11294 return -EINVAL;
11295
11296 /* No tx interrupts will be generated if both are zero */
11297 if ((ec->tx_coalesce_usecs == 0) &&
11298 (ec->tx_max_coalesced_frames == 0))
11299 return -EINVAL;
11300
11301 /* Only copy relevant parameters, ignore all others. */
11302 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11303 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11304 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11305 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11306 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11307 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11308 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11309 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11310 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11311
11312 if (netif_running(dev)) {
11313 tg3_full_lock(tp, 0);
11314 __tg3_set_coalesce(tp, &tp->coal);
11315 tg3_full_unlock(tp);
11316 }
11317 return 0;
11318 }
11319
11320 static const struct ethtool_ops tg3_ethtool_ops = {
11321 .get_settings = tg3_get_settings,
11322 .set_settings = tg3_set_settings,
11323 .get_drvinfo = tg3_get_drvinfo,
11324 .get_regs_len = tg3_get_regs_len,
11325 .get_regs = tg3_get_regs,
11326 .get_wol = tg3_get_wol,
11327 .set_wol = tg3_set_wol,
11328 .get_msglevel = tg3_get_msglevel,
11329 .set_msglevel = tg3_set_msglevel,
11330 .nway_reset = tg3_nway_reset,
11331 .get_link = ethtool_op_get_link,
11332 .get_eeprom_len = tg3_get_eeprom_len,
11333 .get_eeprom = tg3_get_eeprom,
11334 .set_eeprom = tg3_set_eeprom,
11335 .get_ringparam = tg3_get_ringparam,
11336 .set_ringparam = tg3_set_ringparam,
11337 .get_pauseparam = tg3_get_pauseparam,
11338 .set_pauseparam = tg3_set_pauseparam,
11339 .get_rx_csum = tg3_get_rx_csum,
11340 .set_rx_csum = tg3_set_rx_csum,
11341 .set_tx_csum = tg3_set_tx_csum,
11342 .set_sg = ethtool_op_set_sg,
11343 .set_tso = tg3_set_tso,
11344 .self_test = tg3_self_test,
11345 .get_strings = tg3_get_strings,
11346 .phys_id = tg3_phys_id,
11347 .get_ethtool_stats = tg3_get_ethtool_stats,
11348 .get_coalesce = tg3_get_coalesce,
11349 .set_coalesce = tg3_set_coalesce,
11350 .get_sset_count = tg3_get_sset_count,
11351 };
11352
11353 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11354 {
11355 u32 cursize, val, magic;
11356
11357 tp->nvram_size = EEPROM_CHIP_SIZE;
11358
11359 if (tg3_nvram_read(tp, 0, &magic) != 0)
11360 return;
11361
11362 if ((magic != TG3_EEPROM_MAGIC) &&
11363 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11364 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11365 return;
11366
11367 /*
11368 * Size the chip by reading offsets at increasing powers of two.
11369 * When we encounter our validation signature, we know the addressing
11370 * has wrapped around, and thus have our chip size.
11371 */
11372 cursize = 0x10;
11373
11374 while (cursize < tp->nvram_size) {
11375 if (tg3_nvram_read(tp, cursize, &val) != 0)
11376 return;
11377
11378 if (val == magic)
11379 break;
11380
11381 cursize <<= 1;
11382 }
11383
11384 tp->nvram_size = cursize;
11385 }
11386
11387 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11388 {
11389 u32 val;
11390
11391 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11392 tg3_nvram_read(tp, 0, &val) != 0)
11393 return;
11394
11395 /* Selfboot format */
11396 if (val != TG3_EEPROM_MAGIC) {
11397 tg3_get_eeprom_size(tp);
11398 return;
11399 }
11400
11401 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11402 if (val != 0) {
11403 /* This is confusing. We want to operate on the
11404 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11405 * call will read from NVRAM and byteswap the data
11406 * according to the byteswapping settings for all
11407 * other register accesses. This ensures the data we
11408 * want will always reside in the lower 16-bits.
11409 * However, the data in NVRAM is in LE format, which
11410 * means the data from the NVRAM read will always be
11411 * opposite the endianness of the CPU. The 16-bit
11412 * byteswap then brings the data to CPU endianness.
11413 */
11414 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11415 return;
11416 }
11417 }
11418 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11419 }
11420
11421 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11422 {
11423 u32 nvcfg1;
11424
11425 nvcfg1 = tr32(NVRAM_CFG1);
11426 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11427 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11428 } else {
11429 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11430 tw32(NVRAM_CFG1, nvcfg1);
11431 }
11432
11433 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11434 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11435 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11436 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11437 tp->nvram_jedecnum = JEDEC_ATMEL;
11438 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440 break;
11441 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11442 tp->nvram_jedecnum = JEDEC_ATMEL;
11443 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11444 break;
11445 case FLASH_VENDOR_ATMEL_EEPROM:
11446 tp->nvram_jedecnum = JEDEC_ATMEL;
11447 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449 break;
11450 case FLASH_VENDOR_ST:
11451 tp->nvram_jedecnum = JEDEC_ST;
11452 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11453 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11454 break;
11455 case FLASH_VENDOR_SAIFUN:
11456 tp->nvram_jedecnum = JEDEC_SAIFUN;
11457 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11458 break;
11459 case FLASH_VENDOR_SST_SMALL:
11460 case FLASH_VENDOR_SST_LARGE:
11461 tp->nvram_jedecnum = JEDEC_SST;
11462 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11463 break;
11464 }
11465 } else {
11466 tp->nvram_jedecnum = JEDEC_ATMEL;
11467 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11468 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11469 }
11470 }
11471
11472 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11473 {
11474 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11475 case FLASH_5752PAGE_SIZE_256:
11476 tp->nvram_pagesize = 256;
11477 break;
11478 case FLASH_5752PAGE_SIZE_512:
11479 tp->nvram_pagesize = 512;
11480 break;
11481 case FLASH_5752PAGE_SIZE_1K:
11482 tp->nvram_pagesize = 1024;
11483 break;
11484 case FLASH_5752PAGE_SIZE_2K:
11485 tp->nvram_pagesize = 2048;
11486 break;
11487 case FLASH_5752PAGE_SIZE_4K:
11488 tp->nvram_pagesize = 4096;
11489 break;
11490 case FLASH_5752PAGE_SIZE_264:
11491 tp->nvram_pagesize = 264;
11492 break;
11493 case FLASH_5752PAGE_SIZE_528:
11494 tp->nvram_pagesize = 528;
11495 break;
11496 }
11497 }
11498
11499 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11500 {
11501 u32 nvcfg1;
11502
11503 nvcfg1 = tr32(NVRAM_CFG1);
11504
11505 /* NVRAM protection for TPM */
11506 if (nvcfg1 & (1 << 27))
11507 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11508
11509 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11510 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11511 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11512 tp->nvram_jedecnum = JEDEC_ATMEL;
11513 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11514 break;
11515 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11516 tp->nvram_jedecnum = JEDEC_ATMEL;
11517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519 break;
11520 case FLASH_5752VENDOR_ST_M45PE10:
11521 case FLASH_5752VENDOR_ST_M45PE20:
11522 case FLASH_5752VENDOR_ST_M45PE40:
11523 tp->nvram_jedecnum = JEDEC_ST;
11524 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11525 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11526 break;
11527 }
11528
11529 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11530 tg3_nvram_get_pagesize(tp, nvcfg1);
11531 } else {
11532 /* For eeprom, set pagesize to maximum eeprom size */
11533 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11534
11535 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11536 tw32(NVRAM_CFG1, nvcfg1);
11537 }
11538 }
11539
11540 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11541 {
11542 u32 nvcfg1, protect = 0;
11543
11544 nvcfg1 = tr32(NVRAM_CFG1);
11545
11546 /* NVRAM protection for TPM */
11547 if (nvcfg1 & (1 << 27)) {
11548 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11549 protect = 1;
11550 }
11551
11552 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11553 switch (nvcfg1) {
11554 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11555 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11556 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11557 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11558 tp->nvram_jedecnum = JEDEC_ATMEL;
11559 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11560 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11561 tp->nvram_pagesize = 264;
11562 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11563 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11564 tp->nvram_size = (protect ? 0x3e200 :
11565 TG3_NVRAM_SIZE_512KB);
11566 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11567 tp->nvram_size = (protect ? 0x1f200 :
11568 TG3_NVRAM_SIZE_256KB);
11569 else
11570 tp->nvram_size = (protect ? 0x1f200 :
11571 TG3_NVRAM_SIZE_128KB);
11572 break;
11573 case FLASH_5752VENDOR_ST_M45PE10:
11574 case FLASH_5752VENDOR_ST_M45PE20:
11575 case FLASH_5752VENDOR_ST_M45PE40:
11576 tp->nvram_jedecnum = JEDEC_ST;
11577 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11578 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11579 tp->nvram_pagesize = 256;
11580 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11581 tp->nvram_size = (protect ?
11582 TG3_NVRAM_SIZE_64KB :
11583 TG3_NVRAM_SIZE_128KB);
11584 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11585 tp->nvram_size = (protect ?
11586 TG3_NVRAM_SIZE_64KB :
11587 TG3_NVRAM_SIZE_256KB);
11588 else
11589 tp->nvram_size = (protect ?
11590 TG3_NVRAM_SIZE_128KB :
11591 TG3_NVRAM_SIZE_512KB);
11592 break;
11593 }
11594 }
11595
11596 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11597 {
11598 u32 nvcfg1;
11599
11600 nvcfg1 = tr32(NVRAM_CFG1);
11601
11602 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11603 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11604 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11605 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11606 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11607 tp->nvram_jedecnum = JEDEC_ATMEL;
11608 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11609 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11610
11611 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11612 tw32(NVRAM_CFG1, nvcfg1);
11613 break;
11614 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11615 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11616 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11617 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11618 tp->nvram_jedecnum = JEDEC_ATMEL;
11619 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11620 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11621 tp->nvram_pagesize = 264;
11622 break;
11623 case FLASH_5752VENDOR_ST_M45PE10:
11624 case FLASH_5752VENDOR_ST_M45PE20:
11625 case FLASH_5752VENDOR_ST_M45PE40:
11626 tp->nvram_jedecnum = JEDEC_ST;
11627 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11628 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11629 tp->nvram_pagesize = 256;
11630 break;
11631 }
11632 }
11633
11634 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11635 {
11636 u32 nvcfg1, protect = 0;
11637
11638 nvcfg1 = tr32(NVRAM_CFG1);
11639
11640 /* NVRAM protection for TPM */
11641 if (nvcfg1 & (1 << 27)) {
11642 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11643 protect = 1;
11644 }
11645
11646 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11647 switch (nvcfg1) {
11648 case FLASH_5761VENDOR_ATMEL_ADB021D:
11649 case FLASH_5761VENDOR_ATMEL_ADB041D:
11650 case FLASH_5761VENDOR_ATMEL_ADB081D:
11651 case FLASH_5761VENDOR_ATMEL_ADB161D:
11652 case FLASH_5761VENDOR_ATMEL_MDB021D:
11653 case FLASH_5761VENDOR_ATMEL_MDB041D:
11654 case FLASH_5761VENDOR_ATMEL_MDB081D:
11655 case FLASH_5761VENDOR_ATMEL_MDB161D:
11656 tp->nvram_jedecnum = JEDEC_ATMEL;
11657 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11658 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11659 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11660 tp->nvram_pagesize = 256;
11661 break;
11662 case FLASH_5761VENDOR_ST_A_M45PE20:
11663 case FLASH_5761VENDOR_ST_A_M45PE40:
11664 case FLASH_5761VENDOR_ST_A_M45PE80:
11665 case FLASH_5761VENDOR_ST_A_M45PE16:
11666 case FLASH_5761VENDOR_ST_M_M45PE20:
11667 case FLASH_5761VENDOR_ST_M_M45PE40:
11668 case FLASH_5761VENDOR_ST_M_M45PE80:
11669 case FLASH_5761VENDOR_ST_M_M45PE16:
11670 tp->nvram_jedecnum = JEDEC_ST;
11671 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11672 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11673 tp->nvram_pagesize = 256;
11674 break;
11675 }
11676
11677 if (protect) {
11678 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11679 } else {
11680 switch (nvcfg1) {
11681 case FLASH_5761VENDOR_ATMEL_ADB161D:
11682 case FLASH_5761VENDOR_ATMEL_MDB161D:
11683 case FLASH_5761VENDOR_ST_A_M45PE16:
11684 case FLASH_5761VENDOR_ST_M_M45PE16:
11685 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11686 break;
11687 case FLASH_5761VENDOR_ATMEL_ADB081D:
11688 case FLASH_5761VENDOR_ATMEL_MDB081D:
11689 case FLASH_5761VENDOR_ST_A_M45PE80:
11690 case FLASH_5761VENDOR_ST_M_M45PE80:
11691 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11692 break;
11693 case FLASH_5761VENDOR_ATMEL_ADB041D:
11694 case FLASH_5761VENDOR_ATMEL_MDB041D:
11695 case FLASH_5761VENDOR_ST_A_M45PE40:
11696 case FLASH_5761VENDOR_ST_M_M45PE40:
11697 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11698 break;
11699 case FLASH_5761VENDOR_ATMEL_ADB021D:
11700 case FLASH_5761VENDOR_ATMEL_MDB021D:
11701 case FLASH_5761VENDOR_ST_A_M45PE20:
11702 case FLASH_5761VENDOR_ST_M_M45PE20:
11703 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11704 break;
11705 }
11706 }
11707 }
11708
11709 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11710 {
11711 tp->nvram_jedecnum = JEDEC_ATMEL;
11712 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11713 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11714 }
11715
11716 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11717 {
11718 u32 nvcfg1;
11719
11720 nvcfg1 = tr32(NVRAM_CFG1);
11721
11722 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11723 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11724 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11725 tp->nvram_jedecnum = JEDEC_ATMEL;
11726 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11727 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11728
11729 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11730 tw32(NVRAM_CFG1, nvcfg1);
11731 return;
11732 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11733 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11734 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11735 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11736 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11737 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11738 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11739 tp->nvram_jedecnum = JEDEC_ATMEL;
11740 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11741 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11742
11743 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11744 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11745 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11746 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11747 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11748 break;
11749 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11750 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11751 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11752 break;
11753 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11754 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11755 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11756 break;
11757 }
11758 break;
11759 case FLASH_5752VENDOR_ST_M45PE10:
11760 case FLASH_5752VENDOR_ST_M45PE20:
11761 case FLASH_5752VENDOR_ST_M45PE40:
11762 tp->nvram_jedecnum = JEDEC_ST;
11763 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11764 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11765
11766 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11767 case FLASH_5752VENDOR_ST_M45PE10:
11768 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11769 break;
11770 case FLASH_5752VENDOR_ST_M45PE20:
11771 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11772 break;
11773 case FLASH_5752VENDOR_ST_M45PE40:
11774 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11775 break;
11776 }
11777 break;
11778 default:
11779 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11780 return;
11781 }
11782
11783 tg3_nvram_get_pagesize(tp, nvcfg1);
11784 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11785 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11786 }
11787
11788
11789 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11790 {
11791 u32 nvcfg1;
11792
11793 nvcfg1 = tr32(NVRAM_CFG1);
11794
11795 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11796 case FLASH_5717VENDOR_ATMEL_EEPROM:
11797 case FLASH_5717VENDOR_MICRO_EEPROM:
11798 tp->nvram_jedecnum = JEDEC_ATMEL;
11799 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11800 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11801
11802 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11803 tw32(NVRAM_CFG1, nvcfg1);
11804 return;
11805 case FLASH_5717VENDOR_ATMEL_MDB011D:
11806 case FLASH_5717VENDOR_ATMEL_ADB011B:
11807 case FLASH_5717VENDOR_ATMEL_ADB011D:
11808 case FLASH_5717VENDOR_ATMEL_MDB021D:
11809 case FLASH_5717VENDOR_ATMEL_ADB021B:
11810 case FLASH_5717VENDOR_ATMEL_ADB021D:
11811 case FLASH_5717VENDOR_ATMEL_45USPT:
11812 tp->nvram_jedecnum = JEDEC_ATMEL;
11813 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11814 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11815
11816 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11817 case FLASH_5717VENDOR_ATMEL_MDB021D:
11818 case FLASH_5717VENDOR_ATMEL_ADB021B:
11819 case FLASH_5717VENDOR_ATMEL_ADB021D:
11820 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11821 break;
11822 default:
11823 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11824 break;
11825 }
11826 break;
11827 case FLASH_5717VENDOR_ST_M_M25PE10:
11828 case FLASH_5717VENDOR_ST_A_M25PE10:
11829 case FLASH_5717VENDOR_ST_M_M45PE10:
11830 case FLASH_5717VENDOR_ST_A_M45PE10:
11831 case FLASH_5717VENDOR_ST_M_M25PE20:
11832 case FLASH_5717VENDOR_ST_A_M25PE20:
11833 case FLASH_5717VENDOR_ST_M_M45PE20:
11834 case FLASH_5717VENDOR_ST_A_M45PE20:
11835 case FLASH_5717VENDOR_ST_25USPT:
11836 case FLASH_5717VENDOR_ST_45USPT:
11837 tp->nvram_jedecnum = JEDEC_ST;
11838 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11839 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11840
11841 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11842 case FLASH_5717VENDOR_ST_M_M25PE20:
11843 case FLASH_5717VENDOR_ST_A_M25PE20:
11844 case FLASH_5717VENDOR_ST_M_M45PE20:
11845 case FLASH_5717VENDOR_ST_A_M45PE20:
11846 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11847 break;
11848 default:
11849 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11850 break;
11851 }
11852 break;
11853 default:
11854 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11855 return;
11856 }
11857
11858 tg3_nvram_get_pagesize(tp, nvcfg1);
11859 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11860 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11861 }
11862
11863 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11864 static void __devinit tg3_nvram_init(struct tg3 *tp)
11865 {
11866 tw32_f(GRC_EEPROM_ADDR,
11867 (EEPROM_ADDR_FSM_RESET |
11868 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11869 EEPROM_ADDR_CLKPERD_SHIFT)));
11870
11871 msleep(1);
11872
11873 /* Enable seeprom accesses. */
11874 tw32_f(GRC_LOCAL_CTRL,
11875 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11876 udelay(100);
11877
11878 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11879 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11880 tp->tg3_flags |= TG3_FLAG_NVRAM;
11881
11882 if (tg3_nvram_lock(tp)) {
11883 netdev_warn(tp->dev,
11884 "Cannot get nvram lock, %s failed\n",
11885 __func__);
11886 return;
11887 }
11888 tg3_enable_nvram_access(tp);
11889
11890 tp->nvram_size = 0;
11891
11892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11893 tg3_get_5752_nvram_info(tp);
11894 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11895 tg3_get_5755_nvram_info(tp);
11896 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11899 tg3_get_5787_nvram_info(tp);
11900 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11901 tg3_get_5761_nvram_info(tp);
11902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11903 tg3_get_5906_nvram_info(tp);
11904 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11906 tg3_get_57780_nvram_info(tp);
11907 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11909 tg3_get_5717_nvram_info(tp);
11910 else
11911 tg3_get_nvram_info(tp);
11912
11913 if (tp->nvram_size == 0)
11914 tg3_get_nvram_size(tp);
11915
11916 tg3_disable_nvram_access(tp);
11917 tg3_nvram_unlock(tp);
11918
11919 } else {
11920 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11921
11922 tg3_get_eeprom_size(tp);
11923 }
11924 }
11925
11926 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11927 u32 offset, u32 len, u8 *buf)
11928 {
11929 int i, j, rc = 0;
11930 u32 val;
11931
11932 for (i = 0; i < len; i += 4) {
11933 u32 addr;
11934 __be32 data;
11935
11936 addr = offset + i;
11937
11938 memcpy(&data, buf + i, 4);
11939
11940 /*
11941 * The SEEPROM interface expects the data to always be opposite
11942 * the native endian format. We accomplish this by reversing
11943 * all the operations that would have been performed on the
11944 * data from a call to tg3_nvram_read_be32().
11945 */
11946 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11947
11948 val = tr32(GRC_EEPROM_ADDR);
11949 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11950
11951 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11952 EEPROM_ADDR_READ);
11953 tw32(GRC_EEPROM_ADDR, val |
11954 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11955 (addr & EEPROM_ADDR_ADDR_MASK) |
11956 EEPROM_ADDR_START |
11957 EEPROM_ADDR_WRITE);
11958
11959 for (j = 0; j < 1000; j++) {
11960 val = tr32(GRC_EEPROM_ADDR);
11961
11962 if (val & EEPROM_ADDR_COMPLETE)
11963 break;
11964 msleep(1);
11965 }
11966 if (!(val & EEPROM_ADDR_COMPLETE)) {
11967 rc = -EBUSY;
11968 break;
11969 }
11970 }
11971
11972 return rc;
11973 }
11974
11975 /* offset and length are dword aligned */
11976 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11977 u8 *buf)
11978 {
11979 int ret = 0;
11980 u32 pagesize = tp->nvram_pagesize;
11981 u32 pagemask = pagesize - 1;
11982 u32 nvram_cmd;
11983 u8 *tmp;
11984
11985 tmp = kmalloc(pagesize, GFP_KERNEL);
11986 if (tmp == NULL)
11987 return -ENOMEM;
11988
11989 while (len) {
11990 int j;
11991 u32 phy_addr, page_off, size;
11992
11993 phy_addr = offset & ~pagemask;
11994
11995 for (j = 0; j < pagesize; j += 4) {
11996 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11997 (__be32 *) (tmp + j));
11998 if (ret)
11999 break;
12000 }
12001 if (ret)
12002 break;
12003
12004 page_off = offset & pagemask;
12005 size = pagesize;
12006 if (len < size)
12007 size = len;
12008
12009 len -= size;
12010
12011 memcpy(tmp + page_off, buf, size);
12012
12013 offset = offset + (pagesize - page_off);
12014
12015 tg3_enable_nvram_access(tp);
12016
12017 /*
12018 * Before we can erase the flash page, we need
12019 * to issue a special "write enable" command.
12020 */
12021 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12022
12023 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12024 break;
12025
12026 /* Erase the target page */
12027 tw32(NVRAM_ADDR, phy_addr);
12028
12029 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12030 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12031
12032 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12033 break;
12034
12035 /* Issue another write enable to start the write. */
12036 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12037
12038 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12039 break;
12040
12041 for (j = 0; j < pagesize; j += 4) {
12042 __be32 data;
12043
12044 data = *((__be32 *) (tmp + j));
12045
12046 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12047
12048 tw32(NVRAM_ADDR, phy_addr + j);
12049
12050 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12051 NVRAM_CMD_WR;
12052
12053 if (j == 0)
12054 nvram_cmd |= NVRAM_CMD_FIRST;
12055 else if (j == (pagesize - 4))
12056 nvram_cmd |= NVRAM_CMD_LAST;
12057
12058 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12059 break;
12060 }
12061 if (ret)
12062 break;
12063 }
12064
12065 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12066 tg3_nvram_exec_cmd(tp, nvram_cmd);
12067
12068 kfree(tmp);
12069
12070 return ret;
12071 }
12072
12073 /* offset and length are dword aligned */
12074 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12075 u8 *buf)
12076 {
12077 int i, ret = 0;
12078
12079 for (i = 0; i < len; i += 4, offset += 4) {
12080 u32 page_off, phy_addr, nvram_cmd;
12081 __be32 data;
12082
12083 memcpy(&data, buf + i, 4);
12084 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12085
12086 page_off = offset % tp->nvram_pagesize;
12087
12088 phy_addr = tg3_nvram_phys_addr(tp, offset);
12089
12090 tw32(NVRAM_ADDR, phy_addr);
12091
12092 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12093
12094 if (page_off == 0 || i == 0)
12095 nvram_cmd |= NVRAM_CMD_FIRST;
12096 if (page_off == (tp->nvram_pagesize - 4))
12097 nvram_cmd |= NVRAM_CMD_LAST;
12098
12099 if (i == (len - 4))
12100 nvram_cmd |= NVRAM_CMD_LAST;
12101
12102 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12103 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12104 (tp->nvram_jedecnum == JEDEC_ST) &&
12105 (nvram_cmd & NVRAM_CMD_FIRST)) {
12106
12107 if ((ret = tg3_nvram_exec_cmd(tp,
12108 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12109 NVRAM_CMD_DONE)))
12110
12111 break;
12112 }
12113 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12114 /* We always do complete word writes to eeprom. */
12115 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12116 }
12117
12118 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12119 break;
12120 }
12121 return ret;
12122 }
12123
12124 /* offset and length are dword aligned */
12125 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12126 {
12127 int ret;
12128
12129 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12130 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12131 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12132 udelay(40);
12133 }
12134
12135 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12136 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12137 } else {
12138 u32 grc_mode;
12139
12140 ret = tg3_nvram_lock(tp);
12141 if (ret)
12142 return ret;
12143
12144 tg3_enable_nvram_access(tp);
12145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12146 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12147 tw32(NVRAM_WRITE1, 0x406);
12148
12149 grc_mode = tr32(GRC_MODE);
12150 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12151
12152 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12153 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12154
12155 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12156 buf);
12157 } else {
12158 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12159 buf);
12160 }
12161
12162 grc_mode = tr32(GRC_MODE);
12163 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12164
12165 tg3_disable_nvram_access(tp);
12166 tg3_nvram_unlock(tp);
12167 }
12168
12169 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12170 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12171 udelay(40);
12172 }
12173
12174 return ret;
12175 }
12176
12177 struct subsys_tbl_ent {
12178 u16 subsys_vendor, subsys_devid;
12179 u32 phy_id;
12180 };
12181
12182 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12183 /* Broadcom boards. */
12184 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12185 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12186 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12187 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12188 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12189 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12190 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12191 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12192 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12193 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12194 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12195 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12196 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12197 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12198 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12199 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12200 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12201 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12202 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12203 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12204 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12205 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12206
12207 /* 3com boards. */
12208 { TG3PCI_SUBVENDOR_ID_3COM,
12209 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12210 { TG3PCI_SUBVENDOR_ID_3COM,
12211 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12212 { TG3PCI_SUBVENDOR_ID_3COM,
12213 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12214 { TG3PCI_SUBVENDOR_ID_3COM,
12215 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12216 { TG3PCI_SUBVENDOR_ID_3COM,
12217 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12218
12219 /* DELL boards. */
12220 { TG3PCI_SUBVENDOR_ID_DELL,
12221 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12222 { TG3PCI_SUBVENDOR_ID_DELL,
12223 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12224 { TG3PCI_SUBVENDOR_ID_DELL,
12225 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12226 { TG3PCI_SUBVENDOR_ID_DELL,
12227 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12228
12229 /* Compaq boards. */
12230 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12231 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12232 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12233 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12234 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12235 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12236 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12237 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12238 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12239 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12240
12241 /* IBM boards. */
12242 { TG3PCI_SUBVENDOR_ID_IBM,
12243 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12244 };
12245
12246 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12247 {
12248 int i;
12249
12250 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12251 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12252 tp->pdev->subsystem_vendor) &&
12253 (subsys_id_to_phy_id[i].subsys_devid ==
12254 tp->pdev->subsystem_device))
12255 return &subsys_id_to_phy_id[i];
12256 }
12257 return NULL;
12258 }
12259
12260 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12261 {
12262 u32 val;
12263 u16 pmcsr;
12264
12265 /* On some early chips the SRAM cannot be accessed in D3hot state,
12266 * so need make sure we're in D0.
12267 */
12268 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12269 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12270 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12271 msleep(1);
12272
12273 /* Make sure register accesses (indirect or otherwise)
12274 * will function correctly.
12275 */
12276 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12277 tp->misc_host_ctrl);
12278
12279 /* The memory arbiter has to be enabled in order for SRAM accesses
12280 * to succeed. Normally on powerup the tg3 chip firmware will make
12281 * sure it is enabled, but other entities such as system netboot
12282 * code might disable it.
12283 */
12284 val = tr32(MEMARB_MODE);
12285 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12286
12287 tp->phy_id = TG3_PHY_ID_INVALID;
12288 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12289
12290 /* Assume an onboard device and WOL capable by default. */
12291 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12292
12293 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12294 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12295 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12296 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12297 }
12298 val = tr32(VCPU_CFGSHDW);
12299 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12300 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12301 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12302 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12303 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12304 goto done;
12305 }
12306
12307 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12308 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12309 u32 nic_cfg, led_cfg;
12310 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12311 int eeprom_phy_serdes = 0;
12312
12313 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12314 tp->nic_sram_data_cfg = nic_cfg;
12315
12316 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12317 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12318 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12319 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12320 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12321 (ver > 0) && (ver < 0x100))
12322 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12323
12324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12325 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12326
12327 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12328 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12329 eeprom_phy_serdes = 1;
12330
12331 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12332 if (nic_phy_id != 0) {
12333 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12334 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12335
12336 eeprom_phy_id = (id1 >> 16) << 10;
12337 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12338 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12339 } else
12340 eeprom_phy_id = 0;
12341
12342 tp->phy_id = eeprom_phy_id;
12343 if (eeprom_phy_serdes) {
12344 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12345 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12346 else
12347 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12348 }
12349
12350 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12351 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12352 SHASTA_EXT_LED_MODE_MASK);
12353 else
12354 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12355
12356 switch (led_cfg) {
12357 default:
12358 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12359 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12360 break;
12361
12362 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12363 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12364 break;
12365
12366 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12367 tp->led_ctrl = LED_CTRL_MODE_MAC;
12368
12369 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12370 * read on some older 5700/5701 bootcode.
12371 */
12372 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12373 ASIC_REV_5700 ||
12374 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12375 ASIC_REV_5701)
12376 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12377
12378 break;
12379
12380 case SHASTA_EXT_LED_SHARED:
12381 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12382 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12383 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12384 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12385 LED_CTRL_MODE_PHY_2);
12386 break;
12387
12388 case SHASTA_EXT_LED_MAC:
12389 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12390 break;
12391
12392 case SHASTA_EXT_LED_COMBO:
12393 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12394 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12395 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12396 LED_CTRL_MODE_PHY_2);
12397 break;
12398
12399 }
12400
12401 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12403 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12404 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12405
12406 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12407 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12408
12409 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12410 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12411 if ((tp->pdev->subsystem_vendor ==
12412 PCI_VENDOR_ID_ARIMA) &&
12413 (tp->pdev->subsystem_device == 0x205a ||
12414 tp->pdev->subsystem_device == 0x2063))
12415 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12416 } else {
12417 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12418 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12419 }
12420
12421 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12422 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12423 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12424 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12425 }
12426
12427 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12428 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12429 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12430
12431 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12432 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12433 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12434
12435 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12436 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12437 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12438
12439 if (cfg2 & (1 << 17))
12440 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12441
12442 /* serdes signal pre-emphasis in register 0x590 set by */
12443 /* bootcode if bit 18 is set */
12444 if (cfg2 & (1 << 18))
12445 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12446
12447 if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
12448 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12449 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12450 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12451 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12452
12453 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12454 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12455 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12456 u32 cfg3;
12457
12458 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12459 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12460 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12461 }
12462
12463 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12464 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12465 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12466 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12467 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12468 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12469 }
12470 done:
12471 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12472 device_set_wakeup_enable(&tp->pdev->dev,
12473 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12474 }
12475
12476 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12477 {
12478 int i;
12479 u32 val;
12480
12481 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12482 tw32(OTP_CTRL, cmd);
12483
12484 /* Wait for up to 1 ms for command to execute. */
12485 for (i = 0; i < 100; i++) {
12486 val = tr32(OTP_STATUS);
12487 if (val & OTP_STATUS_CMD_DONE)
12488 break;
12489 udelay(10);
12490 }
12491
12492 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12493 }
12494
12495 /* Read the gphy configuration from the OTP region of the chip. The gphy
12496 * configuration is a 32-bit value that straddles the alignment boundary.
12497 * We do two 32-bit reads and then shift and merge the results.
12498 */
12499 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12500 {
12501 u32 bhalf_otp, thalf_otp;
12502
12503 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12504
12505 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12506 return 0;
12507
12508 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12509
12510 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12511 return 0;
12512
12513 thalf_otp = tr32(OTP_READ_DATA);
12514
12515 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12516
12517 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12518 return 0;
12519
12520 bhalf_otp = tr32(OTP_READ_DATA);
12521
12522 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12523 }
12524
12525 static int __devinit tg3_phy_probe(struct tg3 *tp)
12526 {
12527 u32 hw_phy_id_1, hw_phy_id_2;
12528 u32 hw_phy_id, hw_phy_id_masked;
12529 int err;
12530
12531 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12532 return tg3_phy_init(tp);
12533
12534 /* Reading the PHY ID register can conflict with ASF
12535 * firmware access to the PHY hardware.
12536 */
12537 err = 0;
12538 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12539 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12540 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12541 } else {
12542 /* Now read the physical PHY_ID from the chip and verify
12543 * that it is sane. If it doesn't look good, we fall back
12544 * to either the hard-coded table based PHY_ID and failing
12545 * that the value found in the eeprom area.
12546 */
12547 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12548 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12549
12550 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12551 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12552 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12553
12554 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12555 }
12556
12557 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12558 tp->phy_id = hw_phy_id;
12559 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12560 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12561 else
12562 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12563 } else {
12564 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12565 /* Do nothing, phy ID already set up in
12566 * tg3_get_eeprom_hw_cfg().
12567 */
12568 } else {
12569 struct subsys_tbl_ent *p;
12570
12571 /* No eeprom signature? Try the hardcoded
12572 * subsys device table.
12573 */
12574 p = tg3_lookup_by_subsys(tp);
12575 if (!p)
12576 return -ENODEV;
12577
12578 tp->phy_id = p->phy_id;
12579 if (!tp->phy_id ||
12580 tp->phy_id == TG3_PHY_ID_BCM8002)
12581 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12582 }
12583 }
12584
12585 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12586 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12587 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12588 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12589 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12590 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12591
12592 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12593 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12594 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12595 u32 bmsr, adv_reg, tg3_ctrl, mask;
12596
12597 tg3_readphy(tp, MII_BMSR, &bmsr);
12598 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12599 (bmsr & BMSR_LSTATUS))
12600 goto skip_phy_reset;
12601
12602 err = tg3_phy_reset(tp);
12603 if (err)
12604 return err;
12605
12606 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12607 ADVERTISE_100HALF | ADVERTISE_100FULL |
12608 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12609 tg3_ctrl = 0;
12610 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12611 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12612 MII_TG3_CTRL_ADV_1000_FULL);
12613 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12614 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12615 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12616 MII_TG3_CTRL_ENABLE_AS_MASTER);
12617 }
12618
12619 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12620 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12621 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12622 if (!tg3_copper_is_advertising_all(tp, mask)) {
12623 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12624
12625 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12626 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12627
12628 tg3_writephy(tp, MII_BMCR,
12629 BMCR_ANENABLE | BMCR_ANRESTART);
12630 }
12631 tg3_phy_set_wirespeed(tp);
12632
12633 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12634 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12635 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12636 }
12637
12638 skip_phy_reset:
12639 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12640 err = tg3_init_5401phy_dsp(tp);
12641 if (err)
12642 return err;
12643
12644 err = tg3_init_5401phy_dsp(tp);
12645 }
12646
12647 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12648 tp->link_config.advertising =
12649 (ADVERTISED_1000baseT_Half |
12650 ADVERTISED_1000baseT_Full |
12651 ADVERTISED_Autoneg |
12652 ADVERTISED_FIBRE);
12653 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12654 tp->link_config.advertising &=
12655 ~(ADVERTISED_1000baseT_Half |
12656 ADVERTISED_1000baseT_Full);
12657
12658 return err;
12659 }
12660
12661 static void __devinit tg3_read_vpd(struct tg3 *tp)
12662 {
12663 u8 *vpd_data;
12664 unsigned int block_end, rosize, len;
12665 int j, i = 0;
12666 u32 magic;
12667
12668 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12669 tg3_nvram_read(tp, 0x0, &magic))
12670 goto out_no_vpd;
12671
12672 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12673 if (!vpd_data)
12674 goto out_no_vpd;
12675
12676 if (magic == TG3_EEPROM_MAGIC) {
12677 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12678 u32 tmp;
12679
12680 /* The data is in little-endian format in NVRAM.
12681 * Use the big-endian read routines to preserve
12682 * the byte order as it exists in NVRAM.
12683 */
12684 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12685 goto out_not_found;
12686
12687 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12688 }
12689 } else {
12690 ssize_t cnt;
12691 unsigned int pos = 0;
12692
12693 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12694 cnt = pci_read_vpd(tp->pdev, pos,
12695 TG3_NVM_VPD_LEN - pos,
12696 &vpd_data[pos]);
12697 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12698 cnt = 0;
12699 else if (cnt < 0)
12700 goto out_not_found;
12701 }
12702 if (pos != TG3_NVM_VPD_LEN)
12703 goto out_not_found;
12704 }
12705
12706 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12707 PCI_VPD_LRDT_RO_DATA);
12708 if (i < 0)
12709 goto out_not_found;
12710
12711 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12712 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12713 i += PCI_VPD_LRDT_TAG_SIZE;
12714
12715 if (block_end > TG3_NVM_VPD_LEN)
12716 goto out_not_found;
12717
12718 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12719 PCI_VPD_RO_KEYWORD_MFR_ID);
12720 if (j > 0) {
12721 len = pci_vpd_info_field_size(&vpd_data[j]);
12722
12723 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12724 if (j + len > block_end || len != 4 ||
12725 memcmp(&vpd_data[j], "1028", 4))
12726 goto partno;
12727
12728 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12729 PCI_VPD_RO_KEYWORD_VENDOR0);
12730 if (j < 0)
12731 goto partno;
12732
12733 len = pci_vpd_info_field_size(&vpd_data[j]);
12734
12735 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12736 if (j + len > block_end)
12737 goto partno;
12738
12739 memcpy(tp->fw_ver, &vpd_data[j], len);
12740 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12741 }
12742
12743 partno:
12744 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12745 PCI_VPD_RO_KEYWORD_PARTNO);
12746 if (i < 0)
12747 goto out_not_found;
12748
12749 len = pci_vpd_info_field_size(&vpd_data[i]);
12750
12751 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12752 if (len > TG3_BPN_SIZE ||
12753 (len + i) > TG3_NVM_VPD_LEN)
12754 goto out_not_found;
12755
12756 memcpy(tp->board_part_number, &vpd_data[i], len);
12757
12758 out_not_found:
12759 kfree(vpd_data);
12760 if (tp->board_part_number[0])
12761 return;
12762
12763 out_no_vpd:
12764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12765 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12766 strcpy(tp->board_part_number, "BCM5717");
12767 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12768 strcpy(tp->board_part_number, "BCM5718");
12769 else
12770 goto nomatch;
12771 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12772 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12773 strcpy(tp->board_part_number, "BCM57780");
12774 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12775 strcpy(tp->board_part_number, "BCM57760");
12776 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12777 strcpy(tp->board_part_number, "BCM57790");
12778 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12779 strcpy(tp->board_part_number, "BCM57788");
12780 else
12781 goto nomatch;
12782 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12783 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12784 strcpy(tp->board_part_number, "BCM57761");
12785 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12786 strcpy(tp->board_part_number, "BCM57765");
12787 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12788 strcpy(tp->board_part_number, "BCM57781");
12789 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12790 strcpy(tp->board_part_number, "BCM57785");
12791 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12792 strcpy(tp->board_part_number, "BCM57791");
12793 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12794 strcpy(tp->board_part_number, "BCM57795");
12795 else
12796 goto nomatch;
12797 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12798 strcpy(tp->board_part_number, "BCM95906");
12799 } else {
12800 nomatch:
12801 strcpy(tp->board_part_number, "none");
12802 }
12803 }
12804
12805 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12806 {
12807 u32 val;
12808
12809 if (tg3_nvram_read(tp, offset, &val) ||
12810 (val & 0xfc000000) != 0x0c000000 ||
12811 tg3_nvram_read(tp, offset + 4, &val) ||
12812 val != 0)
12813 return 0;
12814
12815 return 1;
12816 }
12817
12818 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12819 {
12820 u32 val, offset, start, ver_offset;
12821 int i, dst_off;
12822 bool newver = false;
12823
12824 if (tg3_nvram_read(tp, 0xc, &offset) ||
12825 tg3_nvram_read(tp, 0x4, &start))
12826 return;
12827
12828 offset = tg3_nvram_logical_addr(tp, offset);
12829
12830 if (tg3_nvram_read(tp, offset, &val))
12831 return;
12832
12833 if ((val & 0xfc000000) == 0x0c000000) {
12834 if (tg3_nvram_read(tp, offset + 4, &val))
12835 return;
12836
12837 if (val == 0)
12838 newver = true;
12839 }
12840
12841 dst_off = strlen(tp->fw_ver);
12842
12843 if (newver) {
12844 if (TG3_VER_SIZE - dst_off < 16 ||
12845 tg3_nvram_read(tp, offset + 8, &ver_offset))
12846 return;
12847
12848 offset = offset + ver_offset - start;
12849 for (i = 0; i < 16; i += 4) {
12850 __be32 v;
12851 if (tg3_nvram_read_be32(tp, offset + i, &v))
12852 return;
12853
12854 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12855 }
12856 } else {
12857 u32 major, minor;
12858
12859 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12860 return;
12861
12862 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12863 TG3_NVM_BCVER_MAJSFT;
12864 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12865 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12866 "v%d.%02d", major, minor);
12867 }
12868 }
12869
12870 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12871 {
12872 u32 val, major, minor;
12873
12874 /* Use native endian representation */
12875 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12876 return;
12877
12878 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12879 TG3_NVM_HWSB_CFG1_MAJSFT;
12880 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12881 TG3_NVM_HWSB_CFG1_MINSFT;
12882
12883 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12884 }
12885
12886 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12887 {
12888 u32 offset, major, minor, build;
12889
12890 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12891
12892 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12893 return;
12894
12895 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12896 case TG3_EEPROM_SB_REVISION_0:
12897 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12898 break;
12899 case TG3_EEPROM_SB_REVISION_2:
12900 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12901 break;
12902 case TG3_EEPROM_SB_REVISION_3:
12903 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12904 break;
12905 case TG3_EEPROM_SB_REVISION_4:
12906 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12907 break;
12908 case TG3_EEPROM_SB_REVISION_5:
12909 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12910 break;
12911 case TG3_EEPROM_SB_REVISION_6:
12912 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12913 break;
12914 default:
12915 return;
12916 }
12917
12918 if (tg3_nvram_read(tp, offset, &val))
12919 return;
12920
12921 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12922 TG3_EEPROM_SB_EDH_BLD_SHFT;
12923 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12924 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12925 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12926
12927 if (minor > 99 || build > 26)
12928 return;
12929
12930 offset = strlen(tp->fw_ver);
12931 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12932 " v%d.%02d", major, minor);
12933
12934 if (build > 0) {
12935 offset = strlen(tp->fw_ver);
12936 if (offset < TG3_VER_SIZE - 1)
12937 tp->fw_ver[offset] = 'a' + build - 1;
12938 }
12939 }
12940
12941 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12942 {
12943 u32 val, offset, start;
12944 int i, vlen;
12945
12946 for (offset = TG3_NVM_DIR_START;
12947 offset < TG3_NVM_DIR_END;
12948 offset += TG3_NVM_DIRENT_SIZE) {
12949 if (tg3_nvram_read(tp, offset, &val))
12950 return;
12951
12952 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12953 break;
12954 }
12955
12956 if (offset == TG3_NVM_DIR_END)
12957 return;
12958
12959 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12960 start = 0x08000000;
12961 else if (tg3_nvram_read(tp, offset - 4, &start))
12962 return;
12963
12964 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12965 !tg3_fw_img_is_valid(tp, offset) ||
12966 tg3_nvram_read(tp, offset + 8, &val))
12967 return;
12968
12969 offset += val - start;
12970
12971 vlen = strlen(tp->fw_ver);
12972
12973 tp->fw_ver[vlen++] = ',';
12974 tp->fw_ver[vlen++] = ' ';
12975
12976 for (i = 0; i < 4; i++) {
12977 __be32 v;
12978 if (tg3_nvram_read_be32(tp, offset, &v))
12979 return;
12980
12981 offset += sizeof(v);
12982
12983 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12984 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12985 break;
12986 }
12987
12988 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12989 vlen += sizeof(v);
12990 }
12991 }
12992
12993 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12994 {
12995 int vlen;
12996 u32 apedata;
12997 char *fwtype;
12998
12999 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13000 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13001 return;
13002
13003 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13004 if (apedata != APE_SEG_SIG_MAGIC)
13005 return;
13006
13007 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13008 if (!(apedata & APE_FW_STATUS_READY))
13009 return;
13010
13011 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13012
13013 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13014 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13015 fwtype = "NCSI";
13016 } else {
13017 fwtype = "DASH";
13018 }
13019
13020 vlen = strlen(tp->fw_ver);
13021
13022 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13023 fwtype,
13024 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13025 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13026 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13027 (apedata & APE_FW_VERSION_BLDMSK));
13028 }
13029
13030 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13031 {
13032 u32 val;
13033 bool vpd_vers = false;
13034
13035 if (tp->fw_ver[0] != 0)
13036 vpd_vers = true;
13037
13038 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13039 strcat(tp->fw_ver, "sb");
13040 return;
13041 }
13042
13043 if (tg3_nvram_read(tp, 0, &val))
13044 return;
13045
13046 if (val == TG3_EEPROM_MAGIC)
13047 tg3_read_bc_ver(tp);
13048 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13049 tg3_read_sb_ver(tp, val);
13050 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13051 tg3_read_hwsb_ver(tp);
13052 else
13053 return;
13054
13055 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13056 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13057 goto done;
13058
13059 tg3_read_mgmtfw_ver(tp);
13060
13061 done:
13062 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13063 }
13064
13065 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13066
13067 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13068 {
13069 #if TG3_VLAN_TAG_USED
13070 dev->vlan_features |= flags;
13071 #endif
13072 }
13073
13074 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13075 {
13076 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13078 return 4096;
13079 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13080 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13081 return 1024;
13082 else
13083 return 512;
13084 }
13085
13086 DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
13087 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13088 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13089 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13090 { },
13091 };
13092
13093 static int __devinit tg3_get_invariants(struct tg3 *tp)
13094 {
13095 u32 misc_ctrl_reg;
13096 u32 pci_state_reg, grc_misc_cfg;
13097 u32 val;
13098 u16 pci_cmd;
13099 int err;
13100
13101 /* Force memory write invalidate off. If we leave it on,
13102 * then on 5700_BX chips we have to enable a workaround.
13103 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13104 * to match the cacheline size. The Broadcom driver have this
13105 * workaround but turns MWI off all the times so never uses
13106 * it. This seems to suggest that the workaround is insufficient.
13107 */
13108 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13109 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13110 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13111
13112 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13113 * has the register indirect write enable bit set before
13114 * we try to access any of the MMIO registers. It is also
13115 * critical that the PCI-X hw workaround situation is decided
13116 * before that as well.
13117 */
13118 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13119 &misc_ctrl_reg);
13120
13121 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13122 MISC_HOST_CTRL_CHIPREV_SHIFT);
13123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13124 u32 prod_id_asic_rev;
13125
13126 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13128 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13129 pci_read_config_dword(tp->pdev,
13130 TG3PCI_GEN2_PRODID_ASICREV,
13131 &prod_id_asic_rev);
13132 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13133 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13134 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13135 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13136 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13137 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13138 pci_read_config_dword(tp->pdev,
13139 TG3PCI_GEN15_PRODID_ASICREV,
13140 &prod_id_asic_rev);
13141 else
13142 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13143 &prod_id_asic_rev);
13144
13145 tp->pci_chip_rev_id = prod_id_asic_rev;
13146 }
13147
13148 /* Wrong chip ID in 5752 A0. This code can be removed later
13149 * as A0 is not in production.
13150 */
13151 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13152 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13153
13154 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13155 * we need to disable memory and use config. cycles
13156 * only to access all registers. The 5702/03 chips
13157 * can mistakenly decode the special cycles from the
13158 * ICH chipsets as memory write cycles, causing corruption
13159 * of register and memory space. Only certain ICH bridges
13160 * will drive special cycles with non-zero data during the
13161 * address phase which can fall within the 5703's address
13162 * range. This is not an ICH bug as the PCI spec allows
13163 * non-zero address during special cycles. However, only
13164 * these ICH bridges are known to drive non-zero addresses
13165 * during special cycles.
13166 *
13167 * Since special cycles do not cross PCI bridges, we only
13168 * enable this workaround if the 5703 is on the secondary
13169 * bus of these ICH bridges.
13170 */
13171 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13172 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13173 static struct tg3_dev_id {
13174 u32 vendor;
13175 u32 device;
13176 u32 rev;
13177 } ich_chipsets[] = {
13178 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13179 PCI_ANY_ID },
13180 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13181 PCI_ANY_ID },
13182 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13183 0xa },
13184 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13185 PCI_ANY_ID },
13186 { },
13187 };
13188 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13189 struct pci_dev *bridge = NULL;
13190
13191 while (pci_id->vendor != 0) {
13192 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13193 bridge);
13194 if (!bridge) {
13195 pci_id++;
13196 continue;
13197 }
13198 if (pci_id->rev != PCI_ANY_ID) {
13199 if (bridge->revision > pci_id->rev)
13200 continue;
13201 }
13202 if (bridge->subordinate &&
13203 (bridge->subordinate->number ==
13204 tp->pdev->bus->number)) {
13205
13206 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13207 pci_dev_put(bridge);
13208 break;
13209 }
13210 }
13211 }
13212
13213 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13214 static struct tg3_dev_id {
13215 u32 vendor;
13216 u32 device;
13217 } bridge_chipsets[] = {
13218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13219 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13220 { },
13221 };
13222 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13223 struct pci_dev *bridge = NULL;
13224
13225 while (pci_id->vendor != 0) {
13226 bridge = pci_get_device(pci_id->vendor,
13227 pci_id->device,
13228 bridge);
13229 if (!bridge) {
13230 pci_id++;
13231 continue;
13232 }
13233 if (bridge->subordinate &&
13234 (bridge->subordinate->number <=
13235 tp->pdev->bus->number) &&
13236 (bridge->subordinate->subordinate >=
13237 tp->pdev->bus->number)) {
13238 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13239 pci_dev_put(bridge);
13240 break;
13241 }
13242 }
13243 }
13244
13245 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13246 * DMA addresses > 40-bit. This bridge may have other additional
13247 * 57xx devices behind it in some 4-port NIC designs for example.
13248 * Any tg3 device found behind the bridge will also need the 40-bit
13249 * DMA workaround.
13250 */
13251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13253 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13254 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13255 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13256 } else {
13257 struct pci_dev *bridge = NULL;
13258
13259 do {
13260 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13261 PCI_DEVICE_ID_SERVERWORKS_EPB,
13262 bridge);
13263 if (bridge && bridge->subordinate &&
13264 (bridge->subordinate->number <=
13265 tp->pdev->bus->number) &&
13266 (bridge->subordinate->subordinate >=
13267 tp->pdev->bus->number)) {
13268 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13269 pci_dev_put(bridge);
13270 break;
13271 }
13272 } while (bridge);
13273 }
13274
13275 /* Initialize misc host control in PCI block. */
13276 tp->misc_host_ctrl |= (misc_ctrl_reg &
13277 MISC_HOST_CTRL_CHIPREV);
13278 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13279 tp->misc_host_ctrl);
13280
13281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13284 tp->pdev_peer = tg3_find_peer(tp);
13285
13286 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13289 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13290
13291 /* Intentionally exclude ASIC_REV_5906 */
13292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13294 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13295 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13298 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13299 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13300
13301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13302 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13303 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13304 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13305 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13306 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13307
13308 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13309 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13310 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13311
13312 /* 5700 B0 chips do not support checksumming correctly due
13313 * to hardware bugs.
13314 */
13315 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13316 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13317 else {
13318 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13319
13320 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13321 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13322 features |= NETIF_F_IPV6_CSUM;
13323 tp->dev->features |= features;
13324 vlan_features_add(tp->dev, features);
13325 }
13326
13327 /* Determine TSO capabilities */
13328 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13329 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13330 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13332 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13333 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13334 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13336 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13337 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13338 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13339 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13340 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13341 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13343 tp->fw_needed = FIRMWARE_TG3TSO5;
13344 else
13345 tp->fw_needed = FIRMWARE_TG3TSO;
13346 }
13347
13348 tp->irq_max = 1;
13349
13350 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13351 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13352 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13353 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13354 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13355 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13356 tp->pdev_peer == tp->pdev))
13357 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13358
13359 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13360 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13361 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13362 }
13363
13364 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13365 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13366 tp->irq_max = TG3_IRQ_MAX_VECS;
13367 }
13368 }
13369
13370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13373 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13374 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13375 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13376 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13377 }
13378
13379 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13380 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13381
13382 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13383 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13384 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13385 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13386
13387 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13388 &pci_state_reg);
13389
13390 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13391 if (tp->pcie_cap != 0) {
13392 u16 lnkctl;
13393
13394 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13395
13396 tp->pcie_readrq = 4096;
13397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13398 u16 word;
13399
13400 pci_read_config_word(tp->pdev,
13401 tp->pcie_cap + PCI_EXP_LNKSTA,
13402 &word);
13403 switch (word & PCI_EXP_LNKSTA_CLS) {
13404 case PCI_EXP_LNKSTA_CLS_2_5GB:
13405 word &= PCI_EXP_LNKSTA_NLW;
13406 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13407 switch (word) {
13408 case 2:
13409 tp->pcie_readrq = 2048;
13410 break;
13411 case 4:
13412 tp->pcie_readrq = 1024;
13413 break;
13414 }
13415 break;
13416
13417 case PCI_EXP_LNKSTA_CLS_5_0GB:
13418 word &= PCI_EXP_LNKSTA_NLW;
13419 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13420 switch (word) {
13421 case 1:
13422 tp->pcie_readrq = 2048;
13423 break;
13424 case 2:
13425 tp->pcie_readrq = 1024;
13426 break;
13427 case 4:
13428 tp->pcie_readrq = 512;
13429 break;
13430 }
13431 }
13432 }
13433
13434 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13435
13436 pci_read_config_word(tp->pdev,
13437 tp->pcie_cap + PCI_EXP_LNKCTL,
13438 &lnkctl);
13439 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13441 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13444 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13445 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13446 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13447 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13448 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13449 }
13450 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13451 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13452 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13453 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13454 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13455 if (!tp->pcix_cap) {
13456 dev_err(&tp->pdev->dev,
13457 "Cannot find PCI-X capability, aborting\n");
13458 return -EIO;
13459 }
13460
13461 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13462 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13463 }
13464
13465 /* If we have an AMD 762 or VIA K8T800 chipset, write
13466 * reordering to the mailbox registers done by the host
13467 * controller can cause major troubles. We read back from
13468 * every mailbox register write to force the writes to be
13469 * posted to the chip in order.
13470 */
13471 if (pci_dev_present(write_reorder_chipsets) &&
13472 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13473 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13474
13475 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13476 &tp->pci_cacheline_sz);
13477 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13478 &tp->pci_lat_timer);
13479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13480 tp->pci_lat_timer < 64) {
13481 tp->pci_lat_timer = 64;
13482 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13483 tp->pci_lat_timer);
13484 }
13485
13486 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13487 /* 5700 BX chips need to have their TX producer index
13488 * mailboxes written twice to workaround a bug.
13489 */
13490 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13491
13492 /* If we are in PCI-X mode, enable register write workaround.
13493 *
13494 * The workaround is to use indirect register accesses
13495 * for all chip writes not to mailbox registers.
13496 */
13497 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13498 u32 pm_reg;
13499
13500 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13501
13502 /* The chip can have it's power management PCI config
13503 * space registers clobbered due to this bug.
13504 * So explicitly force the chip into D0 here.
13505 */
13506 pci_read_config_dword(tp->pdev,
13507 tp->pm_cap + PCI_PM_CTRL,
13508 &pm_reg);
13509 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13510 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13511 pci_write_config_dword(tp->pdev,
13512 tp->pm_cap + PCI_PM_CTRL,
13513 pm_reg);
13514
13515 /* Also, force SERR#/PERR# in PCI command. */
13516 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13517 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13518 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13519 }
13520 }
13521
13522 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13523 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13524 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13525 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13526
13527 /* Chip-specific fixup from Broadcom driver */
13528 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13529 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13530 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13531 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13532 }
13533
13534 /* Default fast path register access methods */
13535 tp->read32 = tg3_read32;
13536 tp->write32 = tg3_write32;
13537 tp->read32_mbox = tg3_read32;
13538 tp->write32_mbox = tg3_write32;
13539 tp->write32_tx_mbox = tg3_write32;
13540 tp->write32_rx_mbox = tg3_write32;
13541
13542 /* Various workaround register access methods */
13543 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13544 tp->write32 = tg3_write_indirect_reg32;
13545 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13546 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13547 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13548 /*
13549 * Back to back register writes can cause problems on these
13550 * chips, the workaround is to read back all reg writes
13551 * except those to mailbox regs.
13552 *
13553 * See tg3_write_indirect_reg32().
13554 */
13555 tp->write32 = tg3_write_flush_reg32;
13556 }
13557
13558 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13559 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13560 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13561 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13562 tp->write32_rx_mbox = tg3_write_flush_reg32;
13563 }
13564
13565 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13566 tp->read32 = tg3_read_indirect_reg32;
13567 tp->write32 = tg3_write_indirect_reg32;
13568 tp->read32_mbox = tg3_read_indirect_mbox;
13569 tp->write32_mbox = tg3_write_indirect_mbox;
13570 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13571 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13572
13573 iounmap(tp->regs);
13574 tp->regs = NULL;
13575
13576 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13577 pci_cmd &= ~PCI_COMMAND_MEMORY;
13578 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13579 }
13580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13581 tp->read32_mbox = tg3_read32_mbox_5906;
13582 tp->write32_mbox = tg3_write32_mbox_5906;
13583 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13584 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13585 }
13586
13587 if (tp->write32 == tg3_write_indirect_reg32 ||
13588 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13591 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13592
13593 /* Get eeprom hw config before calling tg3_set_power_state().
13594 * In particular, the TG3_FLG2_IS_NIC flag must be
13595 * determined before calling tg3_set_power_state() so that
13596 * we know whether or not to switch out of Vaux power.
13597 * When the flag is set, it means that GPIO1 is used for eeprom
13598 * write protect and also implies that it is a LOM where GPIOs
13599 * are not used to switch power.
13600 */
13601 tg3_get_eeprom_hw_cfg(tp);
13602
13603 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13604 /* Allow reads and writes to the
13605 * APE register and memory space.
13606 */
13607 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13608 PCISTATE_ALLOW_APE_SHMEM_WR |
13609 PCISTATE_ALLOW_APE_PSPACE_WR;
13610 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13611 pci_state_reg);
13612 }
13613
13614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13615 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13618 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13619 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13620
13621 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13622 * GPIO1 driven high will bring 5700's external PHY out of reset.
13623 * It is also used as eeprom write protect on LOMs.
13624 */
13625 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13626 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13627 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13628 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13629 GRC_LCLCTRL_GPIO_OUTPUT1);
13630 /* Unused GPIO3 must be driven as output on 5752 because there
13631 * are no pull-up resistors on unused GPIO pins.
13632 */
13633 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13634 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13635
13636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13639 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13640
13641 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13642 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13643 /* Turn off the debug UART. */
13644 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13645 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13646 /* Keep VMain power. */
13647 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13648 GRC_LCLCTRL_GPIO_OUTPUT0;
13649 }
13650
13651 /* Force the chip into D0. */
13652 err = tg3_power_up(tp);
13653 if (err) {
13654 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13655 return err;
13656 }
13657
13658 /* Derive initial jumbo mode from MTU assigned in
13659 * ether_setup() via the alloc_etherdev() call
13660 */
13661 if (tp->dev->mtu > ETH_DATA_LEN &&
13662 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13663 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13664
13665 /* Determine WakeOnLan speed to use. */
13666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13667 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13668 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13669 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13670 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13671 } else {
13672 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13673 }
13674
13675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13676 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13677
13678 /* A few boards don't want Ethernet@WireSpeed phy feature */
13679 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13680 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13681 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13682 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13683 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13684 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13685 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13686
13687 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13688 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13689 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13690 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13691 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13692
13693 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13694 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13695 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13696 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13697 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13702 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13703 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13704 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13705 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13706 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13707 } else
13708 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13709 }
13710
13711 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13712 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13713 tp->phy_otp = tg3_read_otp_phycfg(tp);
13714 if (tp->phy_otp == 0)
13715 tp->phy_otp = TG3_OTP_DEFAULT;
13716 }
13717
13718 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13719 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13720 else
13721 tp->mi_mode = MAC_MI_MODE_BASE;
13722
13723 tp->coalesce_mode = 0;
13724 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13725 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13726 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13727
13728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13729 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13730 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13731
13732 err = tg3_mdio_init(tp);
13733 if (err)
13734 return err;
13735
13736 /* Initialize data/descriptor byte/word swapping. */
13737 val = tr32(GRC_MODE);
13738 val &= GRC_MODE_HOST_STACKUP;
13739 tw32(GRC_MODE, val | tp->grc_mode);
13740
13741 tg3_switch_clocks(tp);
13742
13743 /* Clear this out for sanity. */
13744 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13745
13746 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13747 &pci_state_reg);
13748 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13749 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13750 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13751
13752 if (chiprevid == CHIPREV_ID_5701_A0 ||
13753 chiprevid == CHIPREV_ID_5701_B0 ||
13754 chiprevid == CHIPREV_ID_5701_B2 ||
13755 chiprevid == CHIPREV_ID_5701_B5) {
13756 void __iomem *sram_base;
13757
13758 /* Write some dummy words into the SRAM status block
13759 * area, see if it reads back correctly. If the return
13760 * value is bad, force enable the PCIX workaround.
13761 */
13762 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13763
13764 writel(0x00000000, sram_base);
13765 writel(0x00000000, sram_base + 4);
13766 writel(0xffffffff, sram_base + 4);
13767 if (readl(sram_base) != 0x00000000)
13768 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13769 }
13770 }
13771
13772 udelay(50);
13773 tg3_nvram_init(tp);
13774
13775 grc_misc_cfg = tr32(GRC_MISC_CFG);
13776 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13777
13778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13779 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13780 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13781 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13782
13783 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13784 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13785 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13786 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13787 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13788 HOSTCC_MODE_CLRTICK_TXBD);
13789
13790 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13791 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13792 tp->misc_host_ctrl);
13793 }
13794
13795 /* Preserve the APE MAC_MODE bits */
13796 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13797 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13798 else
13799 tp->mac_mode = TG3_DEF_MAC_MODE;
13800
13801 /* these are limited to 10/100 only */
13802 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13803 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13804 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13805 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13806 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13807 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13808 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13809 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13810 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13811 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13812 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13813 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13814 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13815 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13816 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13817 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13818
13819 err = tg3_phy_probe(tp);
13820 if (err) {
13821 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13822 /* ... but do not return immediately ... */
13823 tg3_mdio_fini(tp);
13824 }
13825
13826 tg3_read_vpd(tp);
13827 tg3_read_fw_ver(tp);
13828
13829 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13830 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13831 } else {
13832 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13833 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13834 else
13835 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13836 }
13837
13838 /* 5700 {AX,BX} chips have a broken status block link
13839 * change bit implementation, so we must use the
13840 * status register in those cases.
13841 */
13842 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13843 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13844 else
13845 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13846
13847 /* The led_ctrl is set during tg3_phy_probe, here we might
13848 * have to force the link status polling mechanism based
13849 * upon subsystem IDs.
13850 */
13851 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13852 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13853 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13854 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13855 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13856 }
13857
13858 /* For all SERDES we poll the MAC status register. */
13859 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13860 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13861 else
13862 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13863
13864 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13865 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13867 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13868 tp->rx_offset -= NET_IP_ALIGN;
13869 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13870 tp->rx_copy_thresh = ~(u16)0;
13871 #endif
13872 }
13873
13874 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13875 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13876 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13877
13878 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13879
13880 /* Increment the rx prod index on the rx std ring by at most
13881 * 8 for these chips to workaround hw errata.
13882 */
13883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13886 tp->rx_std_max_post = 8;
13887
13888 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13889 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13890 PCIE_PWR_MGMT_L1_THRESH_MSK;
13891
13892 return err;
13893 }
13894
13895 #ifdef CONFIG_SPARC
13896 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13897 {
13898 struct net_device *dev = tp->dev;
13899 struct pci_dev *pdev = tp->pdev;
13900 struct device_node *dp = pci_device_to_OF_node(pdev);
13901 const unsigned char *addr;
13902 int len;
13903
13904 addr = of_get_property(dp, "local-mac-address", &len);
13905 if (addr && len == 6) {
13906 memcpy(dev->dev_addr, addr, 6);
13907 memcpy(dev->perm_addr, dev->dev_addr, 6);
13908 return 0;
13909 }
13910 return -ENODEV;
13911 }
13912
13913 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13914 {
13915 struct net_device *dev = tp->dev;
13916
13917 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13918 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13919 return 0;
13920 }
13921 #endif
13922
13923 static int __devinit tg3_get_device_address(struct tg3 *tp)
13924 {
13925 struct net_device *dev = tp->dev;
13926 u32 hi, lo, mac_offset;
13927 int addr_ok = 0;
13928
13929 #ifdef CONFIG_SPARC
13930 if (!tg3_get_macaddr_sparc(tp))
13931 return 0;
13932 #endif
13933
13934 mac_offset = 0x7c;
13935 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13936 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13937 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13938 mac_offset = 0xcc;
13939 if (tg3_nvram_lock(tp))
13940 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13941 else
13942 tg3_nvram_unlock(tp);
13943 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13945 if (PCI_FUNC(tp->pdev->devfn) & 1)
13946 mac_offset = 0xcc;
13947 if (PCI_FUNC(tp->pdev->devfn) > 1)
13948 mac_offset += 0x18c;
13949 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13950 mac_offset = 0x10;
13951
13952 /* First try to get it from MAC address mailbox. */
13953 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13954 if ((hi >> 16) == 0x484b) {
13955 dev->dev_addr[0] = (hi >> 8) & 0xff;
13956 dev->dev_addr[1] = (hi >> 0) & 0xff;
13957
13958 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13959 dev->dev_addr[2] = (lo >> 24) & 0xff;
13960 dev->dev_addr[3] = (lo >> 16) & 0xff;
13961 dev->dev_addr[4] = (lo >> 8) & 0xff;
13962 dev->dev_addr[5] = (lo >> 0) & 0xff;
13963
13964 /* Some old bootcode may report a 0 MAC address in SRAM */
13965 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13966 }
13967 if (!addr_ok) {
13968 /* Next, try NVRAM. */
13969 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13970 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13971 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13972 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13973 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13974 }
13975 /* Finally just fetch it out of the MAC control regs. */
13976 else {
13977 hi = tr32(MAC_ADDR_0_HIGH);
13978 lo = tr32(MAC_ADDR_0_LOW);
13979
13980 dev->dev_addr[5] = lo & 0xff;
13981 dev->dev_addr[4] = (lo >> 8) & 0xff;
13982 dev->dev_addr[3] = (lo >> 16) & 0xff;
13983 dev->dev_addr[2] = (lo >> 24) & 0xff;
13984 dev->dev_addr[1] = hi & 0xff;
13985 dev->dev_addr[0] = (hi >> 8) & 0xff;
13986 }
13987 }
13988
13989 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13990 #ifdef CONFIG_SPARC
13991 if (!tg3_get_default_macaddr_sparc(tp))
13992 return 0;
13993 #endif
13994 return -EINVAL;
13995 }
13996 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13997 return 0;
13998 }
13999
14000 #define BOUNDARY_SINGLE_CACHELINE 1
14001 #define BOUNDARY_MULTI_CACHELINE 2
14002
14003 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14004 {
14005 int cacheline_size;
14006 u8 byte;
14007 int goal;
14008
14009 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14010 if (byte == 0)
14011 cacheline_size = 1024;
14012 else
14013 cacheline_size = (int) byte * 4;
14014
14015 /* On 5703 and later chips, the boundary bits have no
14016 * effect.
14017 */
14018 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14019 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14020 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14021 goto out;
14022
14023 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14024 goal = BOUNDARY_MULTI_CACHELINE;
14025 #else
14026 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14027 goal = BOUNDARY_SINGLE_CACHELINE;
14028 #else
14029 goal = 0;
14030 #endif
14031 #endif
14032
14033 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14034 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14035 goto out;
14036 }
14037
14038 if (!goal)
14039 goto out;
14040
14041 /* PCI controllers on most RISC systems tend to disconnect
14042 * when a device tries to burst across a cache-line boundary.
14043 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14044 *
14045 * Unfortunately, for PCI-E there are only limited
14046 * write-side controls for this, and thus for reads
14047 * we will still get the disconnects. We'll also waste
14048 * these PCI cycles for both read and write for chips
14049 * other than 5700 and 5701 which do not implement the
14050 * boundary bits.
14051 */
14052 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14053 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14054 switch (cacheline_size) {
14055 case 16:
14056 case 32:
14057 case 64:
14058 case 128:
14059 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14060 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14061 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14062 } else {
14063 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14064 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14065 }
14066 break;
14067
14068 case 256:
14069 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14070 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14071 break;
14072
14073 default:
14074 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14075 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14076 break;
14077 }
14078 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14079 switch (cacheline_size) {
14080 case 16:
14081 case 32:
14082 case 64:
14083 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14084 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14085 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14086 break;
14087 }
14088 /* fallthrough */
14089 case 128:
14090 default:
14091 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14092 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14093 break;
14094 }
14095 } else {
14096 switch (cacheline_size) {
14097 case 16:
14098 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14099 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14100 DMA_RWCTRL_WRITE_BNDRY_16);
14101 break;
14102 }
14103 /* fallthrough */
14104 case 32:
14105 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14106 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14107 DMA_RWCTRL_WRITE_BNDRY_32);
14108 break;
14109 }
14110 /* fallthrough */
14111 case 64:
14112 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14113 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14114 DMA_RWCTRL_WRITE_BNDRY_64);
14115 break;
14116 }
14117 /* fallthrough */
14118 case 128:
14119 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14120 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14121 DMA_RWCTRL_WRITE_BNDRY_128);
14122 break;
14123 }
14124 /* fallthrough */
14125 case 256:
14126 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14127 DMA_RWCTRL_WRITE_BNDRY_256);
14128 break;
14129 case 512:
14130 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14131 DMA_RWCTRL_WRITE_BNDRY_512);
14132 break;
14133 case 1024:
14134 default:
14135 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14136 DMA_RWCTRL_WRITE_BNDRY_1024);
14137 break;
14138 }
14139 }
14140
14141 out:
14142 return val;
14143 }
14144
14145 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14146 {
14147 struct tg3_internal_buffer_desc test_desc;
14148 u32 sram_dma_descs;
14149 int i, ret;
14150
14151 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14152
14153 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14154 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14155 tw32(RDMAC_STATUS, 0);
14156 tw32(WDMAC_STATUS, 0);
14157
14158 tw32(BUFMGR_MODE, 0);
14159 tw32(FTQ_RESET, 0);
14160
14161 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14162 test_desc.addr_lo = buf_dma & 0xffffffff;
14163 test_desc.nic_mbuf = 0x00002100;
14164 test_desc.len = size;
14165
14166 /*
14167 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14168 * the *second* time the tg3 driver was getting loaded after an
14169 * initial scan.
14170 *
14171 * Broadcom tells me:
14172 * ...the DMA engine is connected to the GRC block and a DMA
14173 * reset may affect the GRC block in some unpredictable way...
14174 * The behavior of resets to individual blocks has not been tested.
14175 *
14176 * Broadcom noted the GRC reset will also reset all sub-components.
14177 */
14178 if (to_device) {
14179 test_desc.cqid_sqid = (13 << 8) | 2;
14180
14181 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14182 udelay(40);
14183 } else {
14184 test_desc.cqid_sqid = (16 << 8) | 7;
14185
14186 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14187 udelay(40);
14188 }
14189 test_desc.flags = 0x00000005;
14190
14191 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14192 u32 val;
14193
14194 val = *(((u32 *)&test_desc) + i);
14195 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14196 sram_dma_descs + (i * sizeof(u32)));
14197 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14198 }
14199 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14200
14201 if (to_device)
14202 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14203 else
14204 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14205
14206 ret = -ENODEV;
14207 for (i = 0; i < 40; i++) {
14208 u32 val;
14209
14210 if (to_device)
14211 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14212 else
14213 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14214 if ((val & 0xffff) == sram_dma_descs) {
14215 ret = 0;
14216 break;
14217 }
14218
14219 udelay(100);
14220 }
14221
14222 return ret;
14223 }
14224
14225 #define TEST_BUFFER_SIZE 0x2000
14226
14227 DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
14228 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14229 { },
14230 };
14231
14232 static int __devinit tg3_test_dma(struct tg3 *tp)
14233 {
14234 dma_addr_t buf_dma;
14235 u32 *buf, saved_dma_rwctrl;
14236 int ret = 0;
14237
14238 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14239 &buf_dma, GFP_KERNEL);
14240 if (!buf) {
14241 ret = -ENOMEM;
14242 goto out_nofree;
14243 }
14244
14245 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14246 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14247
14248 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14249
14250 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14251 goto out;
14252
14253 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14254 /* DMA read watermark not used on PCIE */
14255 tp->dma_rwctrl |= 0x00180000;
14256 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14258 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14259 tp->dma_rwctrl |= 0x003f0000;
14260 else
14261 tp->dma_rwctrl |= 0x003f000f;
14262 } else {
14263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14265 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14266 u32 read_water = 0x7;
14267
14268 /* If the 5704 is behind the EPB bridge, we can
14269 * do the less restrictive ONE_DMA workaround for
14270 * better performance.
14271 */
14272 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14274 tp->dma_rwctrl |= 0x8000;
14275 else if (ccval == 0x6 || ccval == 0x7)
14276 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14277
14278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14279 read_water = 4;
14280 /* Set bit 23 to enable PCIX hw bug fix */
14281 tp->dma_rwctrl |=
14282 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14283 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14284 (1 << 23);
14285 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14286 /* 5780 always in PCIX mode */
14287 tp->dma_rwctrl |= 0x00144000;
14288 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14289 /* 5714 always in PCIX mode */
14290 tp->dma_rwctrl |= 0x00148000;
14291 } else {
14292 tp->dma_rwctrl |= 0x001b000f;
14293 }
14294 }
14295
14296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14298 tp->dma_rwctrl &= 0xfffffff0;
14299
14300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14302 /* Remove this if it causes problems for some boards. */
14303 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14304
14305 /* On 5700/5701 chips, we need to set this bit.
14306 * Otherwise the chip will issue cacheline transactions
14307 * to streamable DMA memory with not all the byte
14308 * enables turned on. This is an error on several
14309 * RISC PCI controllers, in particular sparc64.
14310 *
14311 * On 5703/5704 chips, this bit has been reassigned
14312 * a different meaning. In particular, it is used
14313 * on those chips to enable a PCI-X workaround.
14314 */
14315 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14316 }
14317
14318 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14319
14320 #if 0
14321 /* Unneeded, already done by tg3_get_invariants. */
14322 tg3_switch_clocks(tp);
14323 #endif
14324
14325 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14326 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14327 goto out;
14328
14329 /* It is best to perform DMA test with maximum write burst size
14330 * to expose the 5700/5701 write DMA bug.
14331 */
14332 saved_dma_rwctrl = tp->dma_rwctrl;
14333 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14334 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14335
14336 while (1) {
14337 u32 *p = buf, i;
14338
14339 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14340 p[i] = i;
14341
14342 /* Send the buffer to the chip. */
14343 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14344 if (ret) {
14345 dev_err(&tp->pdev->dev,
14346 "%s: Buffer write failed. err = %d\n",
14347 __func__, ret);
14348 break;
14349 }
14350
14351 #if 0
14352 /* validate data reached card RAM correctly. */
14353 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14354 u32 val;
14355 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14356 if (le32_to_cpu(val) != p[i]) {
14357 dev_err(&tp->pdev->dev,
14358 "%s: Buffer corrupted on device! "
14359 "(%d != %d)\n", __func__, val, i);
14360 /* ret = -ENODEV here? */
14361 }
14362 p[i] = 0;
14363 }
14364 #endif
14365 /* Now read it back. */
14366 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14367 if (ret) {
14368 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14369 "err = %d\n", __func__, ret);
14370 break;
14371 }
14372
14373 /* Verify it. */
14374 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14375 if (p[i] == i)
14376 continue;
14377
14378 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14379 DMA_RWCTRL_WRITE_BNDRY_16) {
14380 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14381 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14382 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14383 break;
14384 } else {
14385 dev_err(&tp->pdev->dev,
14386 "%s: Buffer corrupted on read back! "
14387 "(%d != %d)\n", __func__, p[i], i);
14388 ret = -ENODEV;
14389 goto out;
14390 }
14391 }
14392
14393 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14394 /* Success. */
14395 ret = 0;
14396 break;
14397 }
14398 }
14399 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14400 DMA_RWCTRL_WRITE_BNDRY_16) {
14401
14402 /* DMA test passed without adjusting DMA boundary,
14403 * now look for chipsets that are known to expose the
14404 * DMA bug without failing the test.
14405 */
14406 if (pci_dev_present(dma_wait_state_chipsets)) {
14407 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14408 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14409 } else {
14410 /* Safe to use the calculated DMA boundary. */
14411 tp->dma_rwctrl = saved_dma_rwctrl;
14412 }
14413
14414 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14415 }
14416
14417 out:
14418 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14419 out_nofree:
14420 return ret;
14421 }
14422
14423 static void __devinit tg3_init_link_config(struct tg3 *tp)
14424 {
14425 tp->link_config.advertising =
14426 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14427 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14428 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14429 ADVERTISED_Autoneg | ADVERTISED_MII);
14430 tp->link_config.speed = SPEED_INVALID;
14431 tp->link_config.duplex = DUPLEX_INVALID;
14432 tp->link_config.autoneg = AUTONEG_ENABLE;
14433 tp->link_config.active_speed = SPEED_INVALID;
14434 tp->link_config.active_duplex = DUPLEX_INVALID;
14435 tp->link_config.orig_speed = SPEED_INVALID;
14436 tp->link_config.orig_duplex = DUPLEX_INVALID;
14437 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14438 }
14439
14440 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14441 {
14442 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14443 tp->bufmgr_config.mbuf_read_dma_low_water =
14444 DEFAULT_MB_RDMA_LOW_WATER_5705;
14445 tp->bufmgr_config.mbuf_mac_rx_low_water =
14446 DEFAULT_MB_MACRX_LOW_WATER_57765;
14447 tp->bufmgr_config.mbuf_high_water =
14448 DEFAULT_MB_HIGH_WATER_57765;
14449
14450 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14451 DEFAULT_MB_RDMA_LOW_WATER_5705;
14452 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14453 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14454 tp->bufmgr_config.mbuf_high_water_jumbo =
14455 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14456 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14457 tp->bufmgr_config.mbuf_read_dma_low_water =
14458 DEFAULT_MB_RDMA_LOW_WATER_5705;
14459 tp->bufmgr_config.mbuf_mac_rx_low_water =
14460 DEFAULT_MB_MACRX_LOW_WATER_5705;
14461 tp->bufmgr_config.mbuf_high_water =
14462 DEFAULT_MB_HIGH_WATER_5705;
14463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14464 tp->bufmgr_config.mbuf_mac_rx_low_water =
14465 DEFAULT_MB_MACRX_LOW_WATER_5906;
14466 tp->bufmgr_config.mbuf_high_water =
14467 DEFAULT_MB_HIGH_WATER_5906;
14468 }
14469
14470 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14471 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14472 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14473 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14474 tp->bufmgr_config.mbuf_high_water_jumbo =
14475 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14476 } else {
14477 tp->bufmgr_config.mbuf_read_dma_low_water =
14478 DEFAULT_MB_RDMA_LOW_WATER;
14479 tp->bufmgr_config.mbuf_mac_rx_low_water =
14480 DEFAULT_MB_MACRX_LOW_WATER;
14481 tp->bufmgr_config.mbuf_high_water =
14482 DEFAULT_MB_HIGH_WATER;
14483
14484 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14485 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14486 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14487 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14488 tp->bufmgr_config.mbuf_high_water_jumbo =
14489 DEFAULT_MB_HIGH_WATER_JUMBO;
14490 }
14491
14492 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14493 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14494 }
14495
14496 static char * __devinit tg3_phy_string(struct tg3 *tp)
14497 {
14498 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14499 case TG3_PHY_ID_BCM5400: return "5400";
14500 case TG3_PHY_ID_BCM5401: return "5401";
14501 case TG3_PHY_ID_BCM5411: return "5411";
14502 case TG3_PHY_ID_BCM5701: return "5701";
14503 case TG3_PHY_ID_BCM5703: return "5703";
14504 case TG3_PHY_ID_BCM5704: return "5704";
14505 case TG3_PHY_ID_BCM5705: return "5705";
14506 case TG3_PHY_ID_BCM5750: return "5750";
14507 case TG3_PHY_ID_BCM5752: return "5752";
14508 case TG3_PHY_ID_BCM5714: return "5714";
14509 case TG3_PHY_ID_BCM5780: return "5780";
14510 case TG3_PHY_ID_BCM5755: return "5755";
14511 case TG3_PHY_ID_BCM5787: return "5787";
14512 case TG3_PHY_ID_BCM5784: return "5784";
14513 case TG3_PHY_ID_BCM5756: return "5722/5756";
14514 case TG3_PHY_ID_BCM5906: return "5906";
14515 case TG3_PHY_ID_BCM5761: return "5761";
14516 case TG3_PHY_ID_BCM5718C: return "5718C";
14517 case TG3_PHY_ID_BCM5718S: return "5718S";
14518 case TG3_PHY_ID_BCM57765: return "57765";
14519 case TG3_PHY_ID_BCM5719C: return "5719C";
14520 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14521 case 0: return "serdes";
14522 default: return "unknown";
14523 }
14524 }
14525
14526 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14527 {
14528 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14529 strcpy(str, "PCI Express");
14530 return str;
14531 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14532 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14533
14534 strcpy(str, "PCIX:");
14535
14536 if ((clock_ctrl == 7) ||
14537 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14538 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14539 strcat(str, "133MHz");
14540 else if (clock_ctrl == 0)
14541 strcat(str, "33MHz");
14542 else if (clock_ctrl == 2)
14543 strcat(str, "50MHz");
14544 else if (clock_ctrl == 4)
14545 strcat(str, "66MHz");
14546 else if (clock_ctrl == 6)
14547 strcat(str, "100MHz");
14548 } else {
14549 strcpy(str, "PCI:");
14550 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14551 strcat(str, "66MHz");
14552 else
14553 strcat(str, "33MHz");
14554 }
14555 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14556 strcat(str, ":32-bit");
14557 else
14558 strcat(str, ":64-bit");
14559 return str;
14560 }
14561
14562 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14563 {
14564 struct pci_dev *peer;
14565 unsigned int func, devnr = tp->pdev->devfn & ~7;
14566
14567 for (func = 0; func < 8; func++) {
14568 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14569 if (peer && peer != tp->pdev)
14570 break;
14571 pci_dev_put(peer);
14572 }
14573 /* 5704 can be configured in single-port mode, set peer to
14574 * tp->pdev in that case.
14575 */
14576 if (!peer) {
14577 peer = tp->pdev;
14578 return peer;
14579 }
14580
14581 /*
14582 * We don't need to keep the refcount elevated; there's no way
14583 * to remove one half of this device without removing the other
14584 */
14585 pci_dev_put(peer);
14586
14587 return peer;
14588 }
14589
14590 static void __devinit tg3_init_coal(struct tg3 *tp)
14591 {
14592 struct ethtool_coalesce *ec = &tp->coal;
14593
14594 memset(ec, 0, sizeof(*ec));
14595 ec->cmd = ETHTOOL_GCOALESCE;
14596 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14597 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14598 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14599 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14600 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14601 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14602 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14603 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14604 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14605
14606 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14607 HOSTCC_MODE_CLRTICK_TXBD)) {
14608 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14609 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14610 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14611 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14612 }
14613
14614 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14615 ec->rx_coalesce_usecs_irq = 0;
14616 ec->tx_coalesce_usecs_irq = 0;
14617 ec->stats_block_coalesce_usecs = 0;
14618 }
14619 }
14620
14621 static const struct net_device_ops tg3_netdev_ops = {
14622 .ndo_open = tg3_open,
14623 .ndo_stop = tg3_close,
14624 .ndo_start_xmit = tg3_start_xmit,
14625 .ndo_get_stats64 = tg3_get_stats64,
14626 .ndo_validate_addr = eth_validate_addr,
14627 .ndo_set_multicast_list = tg3_set_rx_mode,
14628 .ndo_set_mac_address = tg3_set_mac_addr,
14629 .ndo_do_ioctl = tg3_ioctl,
14630 .ndo_tx_timeout = tg3_tx_timeout,
14631 .ndo_change_mtu = tg3_change_mtu,
14632 #if TG3_VLAN_TAG_USED
14633 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14634 #endif
14635 #ifdef CONFIG_NET_POLL_CONTROLLER
14636 .ndo_poll_controller = tg3_poll_controller,
14637 #endif
14638 };
14639
14640 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14641 .ndo_open = tg3_open,
14642 .ndo_stop = tg3_close,
14643 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14644 .ndo_get_stats64 = tg3_get_stats64,
14645 .ndo_validate_addr = eth_validate_addr,
14646 .ndo_set_multicast_list = tg3_set_rx_mode,
14647 .ndo_set_mac_address = tg3_set_mac_addr,
14648 .ndo_do_ioctl = tg3_ioctl,
14649 .ndo_tx_timeout = tg3_tx_timeout,
14650 .ndo_change_mtu = tg3_change_mtu,
14651 #if TG3_VLAN_TAG_USED
14652 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14653 #endif
14654 #ifdef CONFIG_NET_POLL_CONTROLLER
14655 .ndo_poll_controller = tg3_poll_controller,
14656 #endif
14657 };
14658
14659 static int __devinit tg3_init_one(struct pci_dev *pdev,
14660 const struct pci_device_id *ent)
14661 {
14662 struct net_device *dev;
14663 struct tg3 *tp;
14664 int i, err, pm_cap;
14665 u32 sndmbx, rcvmbx, intmbx;
14666 char str[40];
14667 u64 dma_mask, persist_dma_mask;
14668
14669 printk_once(KERN_INFO "%s\n", version);
14670
14671 err = pci_enable_device(pdev);
14672 if (err) {
14673 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14674 return err;
14675 }
14676
14677 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14678 if (err) {
14679 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14680 goto err_out_disable_pdev;
14681 }
14682
14683 pci_set_master(pdev);
14684
14685 /* Find power-management capability. */
14686 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14687 if (pm_cap == 0) {
14688 dev_err(&pdev->dev,
14689 "Cannot find Power Management capability, aborting\n");
14690 err = -EIO;
14691 goto err_out_free_res;
14692 }
14693
14694 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14695 if (!dev) {
14696 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14697 err = -ENOMEM;
14698 goto err_out_free_res;
14699 }
14700
14701 SET_NETDEV_DEV(dev, &pdev->dev);
14702
14703 #if TG3_VLAN_TAG_USED
14704 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14705 #endif
14706
14707 tp = netdev_priv(dev);
14708 tp->pdev = pdev;
14709 tp->dev = dev;
14710 tp->pm_cap = pm_cap;
14711 tp->rx_mode = TG3_DEF_RX_MODE;
14712 tp->tx_mode = TG3_DEF_TX_MODE;
14713
14714 if (tg3_debug > 0)
14715 tp->msg_enable = tg3_debug;
14716 else
14717 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14718
14719 /* The word/byte swap controls here control register access byte
14720 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14721 * setting below.
14722 */
14723 tp->misc_host_ctrl =
14724 MISC_HOST_CTRL_MASK_PCI_INT |
14725 MISC_HOST_CTRL_WORD_SWAP |
14726 MISC_HOST_CTRL_INDIR_ACCESS |
14727 MISC_HOST_CTRL_PCISTATE_RW;
14728
14729 /* The NONFRM (non-frame) byte/word swap controls take effect
14730 * on descriptor entries, anything which isn't packet data.
14731 *
14732 * The StrongARM chips on the board (one for tx, one for rx)
14733 * are running in big-endian mode.
14734 */
14735 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14736 GRC_MODE_WSWAP_NONFRM_DATA);
14737 #ifdef __BIG_ENDIAN
14738 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14739 #endif
14740 spin_lock_init(&tp->lock);
14741 spin_lock_init(&tp->indirect_lock);
14742 INIT_WORK(&tp->reset_task, tg3_reset_task);
14743
14744 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14745 if (!tp->regs) {
14746 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14747 err = -ENOMEM;
14748 goto err_out_free_dev;
14749 }
14750
14751 tg3_init_link_config(tp);
14752
14753 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14754 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14755
14756 dev->ethtool_ops = &tg3_ethtool_ops;
14757 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14758 dev->irq = pdev->irq;
14759
14760 err = tg3_get_invariants(tp);
14761 if (err) {
14762 dev_err(&pdev->dev,
14763 "Problem fetching invariants of chip, aborting\n");
14764 goto err_out_iounmap;
14765 }
14766
14767 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14768 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14769 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14770 dev->netdev_ops = &tg3_netdev_ops;
14771 else
14772 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14773
14774
14775 /* The EPB bridge inside 5714, 5715, and 5780 and any
14776 * device behind the EPB cannot support DMA addresses > 40-bit.
14777 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14778 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14779 * do DMA address check in tg3_start_xmit().
14780 */
14781 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14782 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14783 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14784 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14785 #ifdef CONFIG_HIGHMEM
14786 dma_mask = DMA_BIT_MASK(64);
14787 #endif
14788 } else
14789 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14790
14791 /* Configure DMA attributes. */
14792 if (dma_mask > DMA_BIT_MASK(32)) {
14793 err = pci_set_dma_mask(pdev, dma_mask);
14794 if (!err) {
14795 dev->features |= NETIF_F_HIGHDMA;
14796 err = pci_set_consistent_dma_mask(pdev,
14797 persist_dma_mask);
14798 if (err < 0) {
14799 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14800 "DMA for consistent allocations\n");
14801 goto err_out_iounmap;
14802 }
14803 }
14804 }
14805 if (err || dma_mask == DMA_BIT_MASK(32)) {
14806 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14807 if (err) {
14808 dev_err(&pdev->dev,
14809 "No usable DMA configuration, aborting\n");
14810 goto err_out_iounmap;
14811 }
14812 }
14813
14814 tg3_init_bufmgr_config(tp);
14815
14816 /* Selectively allow TSO based on operating conditions */
14817 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14818 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14819 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14820 else {
14821 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14822 tp->fw_needed = NULL;
14823 }
14824
14825 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14826 tp->fw_needed = FIRMWARE_TG3;
14827
14828 /* TSO is on by default on chips that support hardware TSO.
14829 * Firmware TSO on older chips gives lower performance, so it
14830 * is off by default, but can be enabled using ethtool.
14831 */
14832 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14833 (dev->features & NETIF_F_IP_CSUM)) {
14834 dev->features |= NETIF_F_TSO;
14835 vlan_features_add(dev, NETIF_F_TSO);
14836 }
14837 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14838 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14839 if (dev->features & NETIF_F_IPV6_CSUM) {
14840 dev->features |= NETIF_F_TSO6;
14841 vlan_features_add(dev, NETIF_F_TSO6);
14842 }
14843 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14845 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14846 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14849 dev->features |= NETIF_F_TSO_ECN;
14850 vlan_features_add(dev, NETIF_F_TSO_ECN);
14851 }
14852 }
14853
14854 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14855 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14856 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14857 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14858 tp->rx_pending = 63;
14859 }
14860
14861 err = tg3_get_device_address(tp);
14862 if (err) {
14863 dev_err(&pdev->dev,
14864 "Could not obtain valid ethernet address, aborting\n");
14865 goto err_out_iounmap;
14866 }
14867
14868 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14869 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14870 if (!tp->aperegs) {
14871 dev_err(&pdev->dev,
14872 "Cannot map APE registers, aborting\n");
14873 err = -ENOMEM;
14874 goto err_out_iounmap;
14875 }
14876
14877 tg3_ape_lock_init(tp);
14878
14879 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14880 tg3_read_dash_ver(tp);
14881 }
14882
14883 /*
14884 * Reset chip in case UNDI or EFI driver did not shutdown
14885 * DMA self test will enable WDMAC and we'll see (spurious)
14886 * pending DMA on the PCI bus at that point.
14887 */
14888 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14889 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14890 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14891 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14892 }
14893
14894 err = tg3_test_dma(tp);
14895 if (err) {
14896 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14897 goto err_out_apeunmap;
14898 }
14899
14900 /* flow control autonegotiation is default behavior */
14901 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14902 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14903
14904 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14905 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14906 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14907 for (i = 0; i < tp->irq_max; i++) {
14908 struct tg3_napi *tnapi = &tp->napi[i];
14909
14910 tnapi->tp = tp;
14911 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14912
14913 tnapi->int_mbox = intmbx;
14914 if (i < 4)
14915 intmbx += 0x8;
14916 else
14917 intmbx += 0x4;
14918
14919 tnapi->consmbox = rcvmbx;
14920 tnapi->prodmbox = sndmbx;
14921
14922 if (i)
14923 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14924 else
14925 tnapi->coal_now = HOSTCC_MODE_NOW;
14926
14927 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14928 break;
14929
14930 /*
14931 * If we support MSIX, we'll be using RSS. If we're using
14932 * RSS, the first vector only handles link interrupts and the
14933 * remaining vectors handle rx and tx interrupts. Reuse the
14934 * mailbox values for the next iteration. The values we setup
14935 * above are still useful for the single vectored mode.
14936 */
14937 if (!i)
14938 continue;
14939
14940 rcvmbx += 0x8;
14941
14942 if (sndmbx & 0x4)
14943 sndmbx -= 0x4;
14944 else
14945 sndmbx += 0xc;
14946 }
14947
14948 tg3_init_coal(tp);
14949
14950 pci_set_drvdata(pdev, dev);
14951
14952 err = register_netdev(dev);
14953 if (err) {
14954 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14955 goto err_out_apeunmap;
14956 }
14957
14958 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14959 tp->board_part_number,
14960 tp->pci_chip_rev_id,
14961 tg3_bus_string(tp, str),
14962 dev->dev_addr);
14963
14964 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14965 struct phy_device *phydev;
14966 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14967 netdev_info(dev,
14968 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14969 phydev->drv->name, dev_name(&phydev->dev));
14970 } else {
14971 char *ethtype;
14972
14973 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14974 ethtype = "10/100Base-TX";
14975 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14976 ethtype = "1000Base-SX";
14977 else
14978 ethtype = "10/100/1000Base-T";
14979
14980 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14981 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14982 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14983 }
14984
14985 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14986 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14987 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14988 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14989 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14990 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14991 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14992 tp->dma_rwctrl,
14993 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14994 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14995
14996 return 0;
14997
14998 err_out_apeunmap:
14999 if (tp->aperegs) {
15000 iounmap(tp->aperegs);
15001 tp->aperegs = NULL;
15002 }
15003
15004 err_out_iounmap:
15005 if (tp->regs) {
15006 iounmap(tp->regs);
15007 tp->regs = NULL;
15008 }
15009
15010 err_out_free_dev:
15011 free_netdev(dev);
15012
15013 err_out_free_res:
15014 pci_release_regions(pdev);
15015
15016 err_out_disable_pdev:
15017 pci_disable_device(pdev);
15018 pci_set_drvdata(pdev, NULL);
15019 return err;
15020 }
15021
15022 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15023 {
15024 struct net_device *dev = pci_get_drvdata(pdev);
15025
15026 if (dev) {
15027 struct tg3 *tp = netdev_priv(dev);
15028
15029 if (tp->fw)
15030 release_firmware(tp->fw);
15031
15032 cancel_work_sync(&tp->reset_task);
15033
15034 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15035 tg3_phy_fini(tp);
15036 tg3_mdio_fini(tp);
15037 }
15038
15039 unregister_netdev(dev);
15040 if (tp->aperegs) {
15041 iounmap(tp->aperegs);
15042 tp->aperegs = NULL;
15043 }
15044 if (tp->regs) {
15045 iounmap(tp->regs);
15046 tp->regs = NULL;
15047 }
15048 free_netdev(dev);
15049 pci_release_regions(pdev);
15050 pci_disable_device(pdev);
15051 pci_set_drvdata(pdev, NULL);
15052 }
15053 }
15054
15055 #ifdef CONFIG_PM_SLEEP
15056 static int tg3_suspend(struct device *device)
15057 {
15058 struct pci_dev *pdev = to_pci_dev(device);
15059 struct net_device *dev = pci_get_drvdata(pdev);
15060 struct tg3 *tp = netdev_priv(dev);
15061 int err;
15062
15063 if (!netif_running(dev))
15064 return 0;
15065
15066 flush_work_sync(&tp->reset_task);
15067 tg3_phy_stop(tp);
15068 tg3_netif_stop(tp);
15069
15070 del_timer_sync(&tp->timer);
15071
15072 tg3_full_lock(tp, 1);
15073 tg3_disable_ints(tp);
15074 tg3_full_unlock(tp);
15075
15076 netif_device_detach(dev);
15077
15078 tg3_full_lock(tp, 0);
15079 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15080 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15081 tg3_full_unlock(tp);
15082
15083 err = tg3_power_down_prepare(tp);
15084 if (err) {
15085 int err2;
15086
15087 tg3_full_lock(tp, 0);
15088
15089 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15090 err2 = tg3_restart_hw(tp, 1);
15091 if (err2)
15092 goto out;
15093
15094 tp->timer.expires = jiffies + tp->timer_offset;
15095 add_timer(&tp->timer);
15096
15097 netif_device_attach(dev);
15098 tg3_netif_start(tp);
15099
15100 out:
15101 tg3_full_unlock(tp);
15102
15103 if (!err2)
15104 tg3_phy_start(tp);
15105 }
15106
15107 return err;
15108 }
15109
15110 static int tg3_resume(struct device *device)
15111 {
15112 struct pci_dev *pdev = to_pci_dev(device);
15113 struct net_device *dev = pci_get_drvdata(pdev);
15114 struct tg3 *tp = netdev_priv(dev);
15115 int err;
15116
15117 if (!netif_running(dev))
15118 return 0;
15119
15120 netif_device_attach(dev);
15121
15122 tg3_full_lock(tp, 0);
15123
15124 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15125 err = tg3_restart_hw(tp, 1);
15126 if (err)
15127 goto out;
15128
15129 tp->timer.expires = jiffies + tp->timer_offset;
15130 add_timer(&tp->timer);
15131
15132 tg3_netif_start(tp);
15133
15134 out:
15135 tg3_full_unlock(tp);
15136
15137 if (!err)
15138 tg3_phy_start(tp);
15139
15140 return err;
15141 }
15142
15143 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15144 #define TG3_PM_OPS (&tg3_pm_ops)
15145
15146 #else
15147
15148 #define TG3_PM_OPS NULL
15149
15150 #endif /* CONFIG_PM_SLEEP */
15151
15152 static struct pci_driver tg3_driver = {
15153 .name = DRV_MODULE_NAME,
15154 .id_table = tg3_pci_tbl,
15155 .probe = tg3_init_one,
15156 .remove = __devexit_p(tg3_remove_one),
15157 .driver.pm = TG3_PM_OPS,
15158 };
15159
15160 static int __init tg3_init(void)
15161 {
15162 return pci_register_driver(&tg3_driver);
15163 }
15164
15165 static void __exit tg3_cleanup(void)
15166 {
15167 pci_unregister_driver(&tg3_driver);
15168 }
15169
15170 module_init(tg3_init);
15171 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree