x86, UV: Fix macros for multiple coherency domains
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / include / asm / uv / uv_hub.h
blob341070f7ad5cb62679f22f7b3fff7316c549b5d9
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
14 #ifdef CONFIG_X86_64
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
18 #include <asm/types.h>
19 #include <asm/percpu.h>
20 #include <asm/uv/uv_mmrs.h>
24 * Addressing Terminology
26 * M - The low M bits of a physical address represent the offset
27 * into the blade local memory. RAM memory on a blade is physically
28 * contiguous (although various IO spaces may punch holes in
29 * it)..
31 * N - Number of bits in the node portion of a socket physical
32 * address.
34 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
35 * routers always have low bit of 1, C/MBricks have low bit
36 * equal to 0. Most addressing macros that target UV hub chips
37 * right shift the NASID by 1 to exclude the always-zero bit.
38 * NASIDs contain up to 15 bits.
40 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
41 * of nasids.
43 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
44 * of the nasid for socket usage.
47 * NumaLink Global Physical Address Format:
48 * +--------------------------------+---------------------+
49 * |00..000| GNODE | NodeOffset |
50 * +--------------------------------+---------------------+
51 * |<-------53 - M bits --->|<--------M bits ----->
53 * M - number of node offset bits (35 .. 40)
56 * Memory/UV-HUB Processor Socket Address Format:
57 * +----------------+---------------+---------------------+
58 * |00..000000000000| PNODE | NodeOffset |
59 * +----------------+---------------+---------------------+
60 * <--- N bits --->|<--------M bits ----->
62 * M - number of node offset bits (35 .. 40)
63 * N - number of PNODE bits (0 .. 10)
65 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
66 * The actual values are configuration dependent and are set at
67 * boot time. M & N values are set by the hardware/BIOS at boot.
70 * APICID format
71 * NOTE!!!!!! This is the current format of the APICID. However, code
72 * should assume that this will change in the future. Use functions
73 * in this file for all APICID bit manipulations and conversion.
75 * 1111110000000000
76 * 5432109876543210
77 * pppppppppplc0cch
78 * sssssssssss
80 * p = pnode bits
81 * l = socket number on board
82 * c = core
83 * h = hyperthread
84 * s = bits that are in the SOCKET_ID CSR
86 * Note: Processor only supports 12 bits in the APICID register. The ACPI
87 * tables hold all 16 bits. Software needs to be aware of this.
89 * Unless otherwise specified, all references to APICID refer to
90 * the FULL value contained in ACPI tables, not the subset in the
91 * processor APICID register.
96 * Maximum number of bricks in all partitions and in all coherency domains.
97 * This is the total number of bricks accessible in the numalink fabric. It
98 * includes all C & M bricks. Routers are NOT included.
100 * This value is also the value of the maximum number of non-router NASIDs
101 * in the numalink fabric.
103 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
105 #define UV_MAX_NUMALINK_BLADES 16384
108 * Maximum number of C/Mbricks within a software SSI (hardware may support
109 * more).
111 #define UV_MAX_SSI_BLADES 256
114 * The largest possible NASID of a C or M brick (+ 2)
116 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
118 struct uv_scir_s {
119 struct timer_list timer;
120 unsigned long offset;
121 unsigned long last;
122 unsigned long idle_on;
123 unsigned long idle_off;
124 unsigned char state;
125 unsigned char enabled;
129 * The following defines attributes of the HUB chip. These attributes are
130 * frequently referenced and are kept in the per-cpu data areas of each cpu.
131 * They are kept together in a struct to minimize cache misses.
133 struct uv_hub_info_s {
134 unsigned long global_mmr_base;
135 unsigned long gpa_mask;
136 unsigned int gnode_extra;
137 unsigned long gnode_upper;
138 unsigned long lowmem_remap_top;
139 unsigned long lowmem_remap_base;
140 unsigned short pnode;
141 unsigned short pnode_mask;
142 unsigned short coherency_domain_number;
143 unsigned short numa_blade_id;
144 unsigned char blade_processor_id;
145 unsigned char m_val;
146 unsigned char n_val;
147 struct uv_scir_s scir;
150 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
151 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
152 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
155 * Local & Global MMR space macros.
156 * Note: macros are intended to be used ONLY by inline functions
157 * in this file - not by other kernel code.
158 * n - NASID (full 15-bit global nasid)
159 * g - GNODE (full 15-bit global nasid, right shifted 1)
160 * p - PNODE (local part of nsids, right shifted 1)
162 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
163 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
164 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
166 #define UV_LOCAL_MMR_BASE 0xf4000000UL
167 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
168 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
169 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
170 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
172 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
173 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
175 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
177 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
178 ((unsigned long)(UV_PNODE_TO_GNODE(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
180 #define UV_APIC_PNODE_SHIFT 6
182 /* Local Bus from cpu's perspective */
183 #define LOCAL_BUS_BASE 0x1c00000
184 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
187 * System Controller Interface Reg
189 * Note there are NO leds on a UV system. This register is only
190 * used by the system controller to monitor system-wide operation.
191 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
192 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
193 * a node.
195 * The window is located at top of ACPI MMR space
197 #define SCIR_WINDOW_COUNT 64
198 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
199 LOCAL_BUS_SIZE - \
200 SCIR_WINDOW_COUNT)
202 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
203 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
204 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
206 /* Loop through all installed blades */
207 #define for_each_possible_blade(bid) \
208 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
211 * Macros for converting between kernel virtual addresses, socket local physical
212 * addresses, and UV global physical addresses.
213 * Note: use the standard __pa() & __va() macros for converting
214 * between socket virtual and socket physical addresses.
217 /* socket phys RAM --> UV global physical address */
218 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
220 if (paddr < uv_hub_info->lowmem_remap_top)
221 paddr |= uv_hub_info->lowmem_remap_base;
222 return paddr | uv_hub_info->gnode_upper;
226 /* socket virtual --> UV global physical address */
227 static inline unsigned long uv_gpa(void *v)
229 return uv_soc_phys_ram_to_gpa(__pa(v));
232 /* pnode, offset --> socket virtual */
233 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
235 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
240 * Extract a PNODE from an APICID (full apicid, not processor subset)
242 static inline int uv_apicid_to_pnode(int apicid)
244 return (apicid >> UV_APIC_PNODE_SHIFT);
248 * Access global MMRs using the low memory MMR32 space. This region supports
249 * faster MMR access but not all MMRs are accessible in this space.
251 static inline unsigned long *uv_global_mmr32_address(int pnode,
252 unsigned long offset)
254 return __va(UV_GLOBAL_MMR32_BASE |
255 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
258 static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
259 unsigned long val)
261 *uv_global_mmr32_address(pnode, offset) = val;
264 static inline unsigned long uv_read_global_mmr32(int pnode,
265 unsigned long offset)
267 return *uv_global_mmr32_address(pnode, offset);
271 * Access Global MMR space using the MMR space located at the top of physical
272 * memory.
274 static inline unsigned long *uv_global_mmr64_address(int pnode,
275 unsigned long offset)
277 return __va(UV_GLOBAL_MMR64_BASE |
278 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
281 static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
282 unsigned long val)
284 *uv_global_mmr64_address(pnode, offset) = val;
287 static inline unsigned long uv_read_global_mmr64(int pnode,
288 unsigned long offset)
290 return *uv_global_mmr64_address(pnode, offset);
294 * Access hub local MMRs. Faster than using global space but only local MMRs
295 * are accessible.
297 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
299 return __va(UV_LOCAL_MMR_BASE | offset);
302 static inline unsigned long uv_read_local_mmr(unsigned long offset)
304 return *uv_local_mmr_address(offset);
307 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
309 *uv_local_mmr_address(offset) = val;
312 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
314 return *((unsigned char *)uv_local_mmr_address(offset));
317 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
319 *((unsigned char *)uv_local_mmr_address(offset)) = val;
323 * Structures and definitions for converting between cpu, node, pnode, and blade
324 * numbers.
326 struct uv_blade_info {
327 unsigned short nr_possible_cpus;
328 unsigned short nr_online_cpus;
329 unsigned short pnode;
331 extern struct uv_blade_info *uv_blade_info;
332 extern short *uv_node_to_blade;
333 extern short *uv_cpu_to_blade;
334 extern short uv_possible_blades;
336 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
337 static inline int uv_blade_processor_id(void)
339 return uv_hub_info->blade_processor_id;
342 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
343 static inline int uv_numa_blade_id(void)
345 return uv_hub_info->numa_blade_id;
348 /* Convert a cpu number to the the UV blade number */
349 static inline int uv_cpu_to_blade_id(int cpu)
351 return uv_cpu_to_blade[cpu];
354 /* Convert linux node number to the UV blade number */
355 static inline int uv_node_to_blade_id(int nid)
357 return uv_node_to_blade[nid];
360 /* Convert a blade id to the PNODE of the blade */
361 static inline int uv_blade_to_pnode(int bid)
363 return uv_blade_info[bid].pnode;
366 /* Determine the number of possible cpus on a blade */
367 static inline int uv_blade_nr_possible_cpus(int bid)
369 return uv_blade_info[bid].nr_possible_cpus;
372 /* Determine the number of online cpus on a blade */
373 static inline int uv_blade_nr_online_cpus(int bid)
375 return uv_blade_info[bid].nr_online_cpus;
378 /* Convert a cpu id to the PNODE of the blade containing the cpu */
379 static inline int uv_cpu_to_pnode(int cpu)
381 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
384 /* Convert a linux node number to the PNODE of the blade */
385 static inline int uv_node_to_pnode(int nid)
387 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
390 /* Maximum possible number of blades */
391 static inline int uv_num_possible_blades(void)
393 return uv_possible_blades;
396 /* Update SCIR state */
397 static inline void uv_set_scir_bits(unsigned char value)
399 if (uv_hub_info->scir.state != value) {
400 uv_hub_info->scir.state = value;
401 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
405 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
407 if (uv_cpu_hub_info(cpu)->scir.state != value) {
408 uv_cpu_hub_info(cpu)->scir.state = value;
409 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
413 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
415 unsigned long val;
417 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
418 ((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) |
419 (vector << UVH_IPI_INT_VECTOR_SHFT);
420 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
423 #endif /* CONFIG_X86_64 */
424 #endif /* _ASM_X86_UV_UV_HUB_H */