2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/config.h>
33 #include <linux/crc32.h>
34 #include <linux/kernel.h>
35 #include <linux/version.h>
36 #include <linux/module.h>
37 #include <linux/netdevice.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/etherdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/pci.h>
43 #include <linux/tcp.h>
45 #include <linux/delay.h>
46 #include <linux/workqueue.h>
47 #include <linux/if_vlan.h>
48 #include <linux/prefetch.h>
49 #include <linux/mii.h>
53 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54 #define SKY2_VLAN_TAG_USED 1
59 #define DRV_NAME "sky2"
60 #define DRV_VERSION "0.11"
61 #define PFX DRV_NAME " "
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
70 #define is_ec_a1(hw) \
71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
74 #define RX_LE_SIZE 512
75 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
76 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
77 #define RX_DEF_PENDING RX_MAX_PENDING
79 #define TX_RING_SIZE 512
80 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
81 #define TX_MIN_PENDING 64
82 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
84 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
85 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
86 #define ETH_JUMBO_MTU 9000
87 #define TX_WATCHDOG (5 * HZ)
88 #define NAPI_WEIGHT 64
89 #define PHY_RETRIES 1000
91 static const u32 default_msg
=
92 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
93 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
94 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
| NETIF_MSG_INTR
;
96 static int debug
= -1; /* defaults above */
97 module_param(debug
, int, 0);
98 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
100 static int copybreak __read_mostly
= 256;
101 module_param(copybreak
, int, 0);
102 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
104 static const struct pci_device_id sky2_id_table
[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
127 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
129 /* Avoid conditionals by using array */
130 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
131 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
133 /* This driver supports yukon2 chipset only */
134 static const char *yukon2_name
[] = {
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
147 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
148 gma_write16(hw
, port
, GM_SMI_CTRL
,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
151 for (i
= 0; i
< PHY_RETRIES
; i
++) {
152 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
157 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
161 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
165 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
166 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
168 for (i
= 0; i
< PHY_RETRIES
; i
++) {
169 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
170 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
180 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
184 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
185 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
189 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
196 pr_debug("sky2_set_power_state %d\n", state
);
197 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
199 pci_read_config_word(hw
->pdev
, hw
->pm_cap
+ PCI_PM_PMC
, &power_control
);
200 vaux
= (sky2_read8(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
201 (power_control
& PCI_PM_CAP_PME_D3cold
);
203 pci_read_config_word(hw
->pdev
, hw
->pm_cap
+ PCI_PM_CTRL
, &power_control
);
205 power_control
|= PCI_PM_CTRL_PME_STATUS
;
206 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw
, B0_POWER_CTRL
,
212 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
214 /* disable Core Clock Division, */
215 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
217 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
218 /* enable bits are inverted */
219 sky2_write8(hw
, B2_Y2_CLK_GATE
,
220 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
221 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
222 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
224 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
226 /* Turn off phy power saving */
227 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®1
);
228 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
230 /* looks like this XL is back asswards .. */
231 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
232 reg1
|= PCI_Y2_PHY1_COMA
;
234 reg1
|= PCI_Y2_PHY2_COMA
;
236 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg1
);
241 /* Turn on phy power saving */
242 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®1
);
243 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
244 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
246 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
247 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg1
);
249 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
250 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
252 /* enable bits are inverted */
253 sky2_write8(hw
, B2_Y2_CLK_GATE
,
254 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
255 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
256 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
258 /* switch power to VAUX */
259 if (vaux
&& state
!= PCI_D3cold
)
260 sky2_write8(hw
, B0_POWER_CTRL
,
261 (PC_VAUX_ENA
| PC_VCC_ENA
|
262 PC_VAUX_ON
| PC_VCC_OFF
));
265 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
269 pci_write_config_byte(hw
->pdev
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
270 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
274 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
278 /* disable all GMAC IRQ's */
279 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
280 /* disable PHY IRQs */
281 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
283 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
284 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
285 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
286 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
288 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
289 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
290 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
293 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
295 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
296 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
298 if (sky2
->autoneg
== AUTONEG_ENABLE
&& hw
->chip_id
!= CHIP_ID_YUKON_XL
) {
299 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
301 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
303 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
305 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
306 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
308 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
313 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
315 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
316 /* enable automatic crossover */
317 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
319 /* disable energy detect */
320 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
322 /* enable automatic crossover */
323 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
325 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
326 hw
->chip_id
== CHIP_ID_YUKON_XL
) {
327 ctrl
&= ~PHY_M_PC_DSC_MSK
;
328 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
331 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
333 /* workaround for deviation #4.88 (CRC errors) */
334 /* disable Automatic Crossover */
336 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
337 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
339 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
340 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
342 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
343 ctrl
&= ~PHY_M_MAC_MD_MSK
;
344 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
345 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
352 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
353 if (sky2
->autoneg
== AUTONEG_DISABLE
)
358 ctrl
|= PHY_CT_RESET
;
359 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
365 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
367 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
368 ct1000
|= PHY_M_1000C_AFD
;
369 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
370 ct1000
|= PHY_M_1000C_AHD
;
371 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
372 adv
|= PHY_M_AN_100_FD
;
373 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
374 adv
|= PHY_M_AN_100_HD
;
375 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
376 adv
|= PHY_M_AN_10_FD
;
377 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
378 adv
|= PHY_M_AN_10_HD
;
379 } else /* special defines for FIBER (88E1011S only) */
380 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
382 /* Set Flow-control capabilities */
383 if (sky2
->tx_pause
&& sky2
->rx_pause
)
384 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
385 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
386 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
387 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
388 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
390 /* Restart Auto-negotiation */
391 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
393 /* forced speed/duplex settings */
394 ct1000
= PHY_M_1000C_MSE
;
396 if (sky2
->duplex
== DUPLEX_FULL
)
397 ctrl
|= PHY_CT_DUP_MD
;
399 switch (sky2
->speed
) {
401 ctrl
|= PHY_CT_SP1000
;
404 ctrl
|= PHY_CT_SP100
;
408 ctrl
|= PHY_CT_RESET
;
411 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
412 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
414 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
415 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
417 /* Setup Phy LED's */
418 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
421 switch (hw
->chip_id
) {
422 case CHIP_ID_YUKON_FE
:
423 /* on 88E3082 these bits are at 11..9 (shifted left) */
424 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
426 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
428 /* delete ACT LED control bits */
429 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
430 /* change ACT LED control to blink mode */
431 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
432 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
435 case CHIP_ID_YUKON_XL
:
436 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
438 /* select page 3 to access LED control register */
439 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
441 /* set LED Function Control register */
442 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
447 /* set Polarity Control register */
448 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
449 (PHY_M_POLC_LS1_P_MIX(4) |
450 PHY_M_POLC_IS0_P_MIX(4) |
451 PHY_M_POLC_LOS_CTRL(2) |
452 PHY_M_POLC_INIT_CTRL(2) |
453 PHY_M_POLC_STA1_CTRL(2) |
454 PHY_M_POLC_STA0_CTRL(2)));
456 /* restore page register */
457 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
461 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
463 /* turn off the Rx LED (LED_RX) */
464 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
467 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
469 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
470 /* turn on 100 Mbps LED (LED_LINK100) */
471 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
475 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
477 /* Enable phy interrupt on auto-negotiation complete (or link up) */
478 if (sky2
->autoneg
== AUTONEG_ENABLE
)
479 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
481 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
484 /* Force a renegotiation */
485 static void sky2_phy_reinit(struct sky2_port
*sky2
)
487 down(&sky2
->phy_sema
);
488 sky2_phy_init(sky2
->hw
, sky2
->port
);
492 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
494 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
497 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
499 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
500 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
502 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
504 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
505 /* WA DEV_472 -- looks like crossed wires on port 2 */
506 /* clear GMAC 1 Control reset */
507 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
509 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
510 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
511 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
512 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
513 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
516 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
517 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
518 reg
|= GM_GPCR_AU_ALL_DIS
;
519 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
520 gma_read16(hw
, port
, GM_GP_CTRL
);
522 switch (sky2
->speed
) {
524 reg
|= GM_GPCR_SPEED_1000
;
527 reg
|= GM_GPCR_SPEED_100
;
530 if (sky2
->duplex
== DUPLEX_FULL
)
531 reg
|= GM_GPCR_DUP_FULL
;
533 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
535 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
536 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
538 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
539 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
540 /* disable Rx flow-control */
541 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
544 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
546 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
548 down(&sky2
->phy_sema
);
549 sky2_phy_init(hw
, port
);
553 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
554 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
556 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
557 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8 * i
);
558 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
560 /* transmit control */
561 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
563 /* receive control reg: unicast + multicast + no FCS */
564 gma_write16(hw
, port
, GM_RX_CTRL
,
565 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
567 /* transmit flow control */
568 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
570 /* transmit parameter */
571 gma_write16(hw
, port
, GM_TX_PARAM
,
572 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
573 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
574 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
575 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
577 /* serial mode register */
578 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
579 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
581 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
582 reg
|= GM_SMOD_JUMBO_ENA
;
584 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
586 /* virtual address for data */
587 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
589 /* physical address: used for pause frames */
590 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
592 /* ignore counter overflows */
593 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
594 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
595 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
597 /* Configure Rx MAC FIFO */
598 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
599 sky2_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
602 /* Flush Rx MAC FIFO on any flow control or error */
603 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
605 /* Set threshold to 0xa (64 bytes)
606 * ASF disabled so no need to do WA dev #4.30
608 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
610 /* Configure Tx MAC FIFO */
611 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
612 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
614 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
615 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
616 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
617 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
618 /* set Tx GMAC FIFO Almost Empty Threshold */
619 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
620 /* Disable Store & Forward mode for TX */
621 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
627 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, size_t len
)
633 end
= start
+ len
- 1;
635 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
636 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
637 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
638 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
639 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
641 if (q
== Q_R1
|| q
== Q_R2
) {
647 /* Set thresholds on receive queue's */
648 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), rxup
);
649 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), rxlo
);
651 /* Enable store & forward on Tx queue's because
652 * Tx FIFO is only 1K on Yukon
654 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
657 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
658 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
661 /* Setup Bus Memory Interface */
662 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
664 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
665 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
666 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
667 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
670 /* Setup prefetch unit registers. This is the interface between
671 * hardware and driver list elements
673 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
676 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
677 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
678 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
679 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
680 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
681 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
683 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
686 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
688 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
690 sky2
->tx_prod
= (sky2
->tx_prod
+ 1) % TX_RING_SIZE
;
695 * This is a workaround code taken from SysKonnect sk98lin driver
696 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
698 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
,
699 u16 idx
, u16
*last
, u16 size
)
701 if (is_ec_a1(hw
) && idx
< *last
) {
702 u16 hwget
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
705 /* Start prefetching again */
706 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 0xe0);
710 if (hwget
== size
- 1) {
711 /* set watermark to one list element */
712 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 8);
714 /* set put index to first list element */
715 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), 0);
716 } else /* have hardware go to end of list */
717 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
),
721 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
727 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
729 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
730 sky2
->rx_put
= (sky2
->rx_put
+ 1) % RX_LE_SIZE
;
734 /* Return high part of DMA address (could be 32 or 64 bit) */
735 static inline u32
high32(dma_addr_t a
)
737 return (a
>> 16) >> 16;
740 /* Build description to hardware about buffer */
741 static inline void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
743 struct sky2_rx_le
*le
;
744 u32 hi
= high32(map
);
745 u16 len
= sky2
->rx_bufsize
;
747 if (sky2
->rx_addr64
!= hi
) {
748 le
= sky2_next_rx(sky2
);
749 le
->addr
= cpu_to_le32(hi
);
751 le
->opcode
= OP_ADDR64
| HW_OWNER
;
752 sky2
->rx_addr64
= high32(map
+ len
);
755 le
= sky2_next_rx(sky2
);
756 le
->addr
= cpu_to_le32((u32
) map
);
757 le
->length
= cpu_to_le16(len
);
759 le
->opcode
= OP_PACKET
| HW_OWNER
;
763 /* Tell chip where to start receive checksum.
764 * Actually has two checksums, but set both same to avoid possible byte
767 static void rx_set_checksum(struct sky2_port
*sky2
)
769 struct sky2_rx_le
*le
;
771 le
= sky2_next_rx(sky2
);
772 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
774 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
776 sky2_write32(sky2
->hw
,
777 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
778 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
783 * The RX Stop command will not work for Yukon-2 if the BMU does not
784 * reach the end of packet and since we can't make sure that we have
785 * incoming data, we must reset the BMU while it is not doing a DMA
786 * transfer. Since it is possible that the RX path is still active,
787 * the RX RAM buffer will be stopped first, so any possible incoming
788 * data will not trigger a DMA. After the RAM buffer is stopped, the
789 * BMU is polled until any DMA in progress is ended and only then it
792 static void sky2_rx_stop(struct sky2_port
*sky2
)
794 struct sky2_hw
*hw
= sky2
->hw
;
795 unsigned rxq
= rxqaddr
[sky2
->port
];
798 /* disable the RAM Buffer receive queue */
799 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
801 for (i
= 0; i
< 0xffff; i
++)
802 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
803 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
806 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
809 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
811 /* reset the Rx prefetch unit */
812 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
815 /* Clean out receive buffer area, assumes receiver hardware stopped */
816 static void sky2_rx_clean(struct sky2_port
*sky2
)
820 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
821 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
822 struct ring_info
*re
= sky2
->rx_ring
+ i
;
825 pci_unmap_single(sky2
->hw
->pdev
,
826 re
->mapaddr
, sky2
->rx_bufsize
,
834 /* Basic MII support */
835 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
837 struct mii_ioctl_data
*data
= if_mii(ifr
);
838 struct sky2_port
*sky2
= netdev_priv(dev
);
839 struct sky2_hw
*hw
= sky2
->hw
;
840 int err
= -EOPNOTSUPP
;
842 if (!netif_running(dev
))
843 return -ENODEV
; /* Phy still in reset */
847 data
->phy_id
= PHY_ADDR_MARV
;
853 down(&sky2
->phy_sema
);
854 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
862 if (!capable(CAP_NET_ADMIN
))
865 down(&sky2
->phy_sema
);
866 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
874 #ifdef SKY2_VLAN_TAG_USED
875 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
877 struct sky2_port
*sky2
= netdev_priv(dev
);
878 struct sky2_hw
*hw
= sky2
->hw
;
879 u16 port
= sky2
->port
;
881 spin_lock(&sky2
->tx_lock
);
883 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
884 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
887 spin_unlock(&sky2
->tx_lock
);
890 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
892 struct sky2_port
*sky2
= netdev_priv(dev
);
893 struct sky2_hw
*hw
= sky2
->hw
;
894 u16 port
= sky2
->port
;
896 spin_lock(&sky2
->tx_lock
);
898 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
899 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
901 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
903 spin_unlock(&sky2
->tx_lock
);
908 * Allocate and setup receiver buffer pool.
909 * In case of 64 bit dma, there are 2X as many list elements
910 * available as ring entries
911 * and need to reserve one list element so we don't wrap around.
913 * It appears the hardware has a bug in the FIFO logic that
914 * cause it to hang if the FIFO gets overrun and the receive buffer
915 * is not aligned. This means we can't use skb_reserve to align
918 static int sky2_rx_start(struct sky2_port
*sky2
)
920 struct sky2_hw
*hw
= sky2
->hw
;
921 unsigned rxq
= rxqaddr
[sky2
->port
];
924 sky2
->rx_put
= sky2
->rx_next
= 0;
926 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
928 rx_set_checksum(sky2
);
929 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
930 struct ring_info
*re
= sky2
->rx_ring
+ i
;
932 re
->skb
= dev_alloc_skb(sky2
->rx_bufsize
);
936 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
937 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
938 sky2_rx_add(sky2
, re
->mapaddr
);
941 /* Tell chip about available buffers */
942 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
943 sky2
->rx_last_put
= sky2_read16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
));
950 /* Bring up network interface. */
951 static int sky2_up(struct net_device
*dev
)
953 struct sky2_port
*sky2
= netdev_priv(dev
);
954 struct sky2_hw
*hw
= sky2
->hw
;
955 unsigned port
= sky2
->port
;
956 u32 ramsize
, rxspace
;
959 if (netif_msg_ifup(sky2
))
960 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
962 /* must be power of 2 */
963 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
965 sizeof(struct sky2_tx_le
),
970 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
974 sky2
->tx_prod
= sky2
->tx_cons
= 0;
976 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
980 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
982 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
987 sky2_mac_init(hw
, port
);
989 /* Configure RAM buffers */
990 if (hw
->chip_id
== CHIP_ID_YUKON_FE
||
991 (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== 2))
994 u8 e0
= sky2_read8(hw
, B2_E_0
);
995 ramsize
= (e0
== 0) ? (128 * 1024) : (e0
* 4096);
999 rxspace
= (2 * ramsize
) / 3;
1000 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1001 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1003 /* Make sure SyncQ is disabled */
1004 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1007 sky2_qset(hw
, txqaddr
[port
]);
1008 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1009 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1012 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1015 err
= sky2_rx_start(sky2
);
1019 /* Enable interrupts from phy/mac for port */
1020 hw
->intr_mask
|= (port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1021 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1026 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1027 sky2
->rx_le
, sky2
->rx_le_map
);
1031 pci_free_consistent(hw
->pdev
,
1032 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1033 sky2
->tx_le
, sky2
->tx_le_map
);
1036 kfree(sky2
->tx_ring
);
1037 kfree(sky2
->rx_ring
);
1039 sky2
->tx_ring
= NULL
;
1040 sky2
->rx_ring
= NULL
;
1044 /* Modular subtraction in ring */
1045 static inline int tx_dist(unsigned tail
, unsigned head
)
1047 return (head
- tail
) % TX_RING_SIZE
;
1050 /* Number of list elements available for next tx */
1051 static inline int tx_avail(const struct sky2_port
*sky2
)
1053 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1056 /* Estimate of number of transmit list elements required */
1057 static inline unsigned tx_le_req(const struct sk_buff
*skb
)
1061 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1062 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1064 if (skb_shinfo(skb
)->tso_size
)
1067 if (skb
->ip_summed
== CHECKSUM_HW
)
1074 * Put one packet in ring for transmit.
1075 * A single packet can generate multiple list elements, and
1076 * the number of ring elements will probably be less than the number
1077 * of list elements used.
1079 * No BH disabling for tx_lock here (like tg3)
1081 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1083 struct sky2_port
*sky2
= netdev_priv(dev
);
1084 struct sky2_hw
*hw
= sky2
->hw
;
1085 struct sky2_tx_le
*le
= NULL
;
1086 struct tx_ring_info
*re
;
1093 if (!spin_trylock(&sky2
->tx_lock
))
1094 return NETDEV_TX_LOCKED
;
1096 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1097 /* There is a known but harmless race with lockless tx
1098 * and netif_stop_queue.
1100 if (!netif_queue_stopped(dev
)) {
1101 netif_stop_queue(dev
);
1102 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1105 spin_unlock(&sky2
->tx_lock
);
1107 return NETDEV_TX_BUSY
;
1110 if (unlikely(netif_msg_tx_queued(sky2
)))
1111 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1112 dev
->name
, sky2
->tx_prod
, skb
->len
);
1114 len
= skb_headlen(skb
);
1115 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1116 addr64
= high32(mapping
);
1118 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1120 /* Send high bits if changed or crosses boundary */
1121 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1122 le
= get_tx_le(sky2
);
1123 le
->tx
.addr
= cpu_to_le32(addr64
);
1125 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1126 sky2
->tx_addr64
= high32(mapping
+ len
);
1129 /* Check for TCP Segmentation Offload */
1130 mss
= skb_shinfo(skb
)->tso_size
;
1132 /* just drop the packet if non-linear expansion fails */
1133 if (skb_header_cloned(skb
) &&
1134 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1135 dev_kfree_skb_any(skb
);
1139 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1140 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1144 if (mss
!= sky2
->tx_last_mss
) {
1145 le
= get_tx_le(sky2
);
1146 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1147 le
->tx
.tso
.rsvd
= 0;
1148 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1150 sky2
->tx_last_mss
= mss
;
1154 #ifdef SKY2_VLAN_TAG_USED
1155 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1156 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1158 le
= get_tx_le(sky2
);
1160 le
->opcode
= OP_VLAN
|HW_OWNER
;
1163 le
->opcode
|= OP_VLAN
;
1164 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1169 /* Handle TCP checksum offload */
1170 if (skb
->ip_summed
== CHECKSUM_HW
) {
1171 u16 hdr
= skb
->h
.raw
- skb
->data
;
1172 u16 offset
= hdr
+ skb
->csum
;
1174 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1175 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1178 le
= get_tx_le(sky2
);
1179 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1180 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1181 le
->length
= 0; /* initial checksum value */
1182 le
->ctrl
= 1; /* one packet */
1183 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1186 le
= get_tx_le(sky2
);
1187 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1188 le
->length
= cpu_to_le16(len
);
1190 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1192 /* Record the transmit mapping info */
1194 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1196 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1197 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1198 struct tx_ring_info
*fre
;
1200 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1201 frag
->size
, PCI_DMA_TODEVICE
);
1202 addr64
= (mapping
>> 16) >> 16;
1203 if (addr64
!= sky2
->tx_addr64
) {
1204 le
= get_tx_le(sky2
);
1205 le
->tx
.addr
= cpu_to_le32(addr64
);
1207 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1208 sky2
->tx_addr64
= addr64
;
1211 le
= get_tx_le(sky2
);
1212 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1213 le
->length
= cpu_to_le16(frag
->size
);
1215 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1218 + ((re
- sky2
->tx_ring
) + i
+ 1) % TX_RING_SIZE
;
1219 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1222 re
->idx
= sky2
->tx_prod
;
1225 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
,
1226 &sky2
->tx_last_put
, TX_RING_SIZE
);
1228 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1229 netif_stop_queue(dev
);
1233 spin_unlock(&sky2
->tx_lock
);
1235 dev
->trans_start
= jiffies
;
1236 return NETDEV_TX_OK
;
1240 * Free ring elements from starting at tx_cons until "done"
1242 * NB: the hardware will tell us about partial completion of multi-part
1243 * buffers; these are deferred until completion.
1245 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1247 struct net_device
*dev
= sky2
->netdev
;
1248 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1252 BUG_ON(done
>= TX_RING_SIZE
);
1254 if (unlikely(netif_msg_tx_done(sky2
)))
1255 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1258 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1259 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1260 struct sk_buff
*skb
= re
->skb
;
1263 BUG_ON(nxt
>= TX_RING_SIZE
);
1264 prefetch(sky2
->tx_ring
+ nxt
);
1266 /* Check for partial status */
1267 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1271 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1272 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1274 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1275 struct tx_ring_info
*fre
;
1276 fre
= sky2
->tx_ring
+ (put
+ i
+ 1) % TX_RING_SIZE
;
1277 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1278 skb_shinfo(skb
)->frags
[i
].size
,
1282 dev_kfree_skb_any(skb
);
1285 spin_lock(&sky2
->tx_lock
);
1286 sky2
->tx_cons
= put
;
1287 if (netif_queue_stopped(dev
) && tx_avail(sky2
) > MAX_SKB_TX_LE
)
1288 netif_wake_queue(dev
);
1289 spin_unlock(&sky2
->tx_lock
);
1292 /* Cleanup all untransmitted buffers, assume transmitter not running */
1293 static void sky2_tx_clean(struct sky2_port
*sky2
)
1295 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1298 /* Network shutdown */
1299 static int sky2_down(struct net_device
*dev
)
1301 struct sky2_port
*sky2
= netdev_priv(dev
);
1302 struct sky2_hw
*hw
= sky2
->hw
;
1303 unsigned port
= sky2
->port
;
1306 /* Never really got started! */
1310 if (netif_msg_ifdown(sky2
))
1311 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1313 /* Stop more packets from being queued */
1314 netif_stop_queue(dev
);
1316 /* Disable port IRQ */
1317 local_irq_disable();
1318 hw
->intr_mask
&= ~((sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
1319 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1322 flush_scheduled_work();
1324 sky2_phy_reset(hw
, port
);
1326 /* Stop transmitter */
1327 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1328 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1330 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1331 RB_RST_SET
| RB_DIS_OP_MD
);
1333 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1334 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1335 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1337 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1339 /* Workaround shared GMAC reset */
1340 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1341 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1342 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1344 /* Disable Force Sync bit and Enable Alloc bit */
1345 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1346 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1348 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1349 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1350 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1352 /* Reset the PCI FIFO of the async Tx queue */
1353 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1354 BMU_RST_SET
| BMU_FIFO_RST
);
1356 /* Reset the Tx prefetch units */
1357 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1360 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1364 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1365 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1367 /* turn off LED's */
1368 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1370 synchronize_irq(hw
->pdev
->irq
);
1372 sky2_tx_clean(sky2
);
1373 sky2_rx_clean(sky2
);
1375 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1376 sky2
->rx_le
, sky2
->rx_le_map
);
1377 kfree(sky2
->rx_ring
);
1379 pci_free_consistent(hw
->pdev
,
1380 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1381 sky2
->tx_le
, sky2
->tx_le_map
);
1382 kfree(sky2
->tx_ring
);
1387 sky2
->rx_ring
= NULL
;
1388 sky2
->tx_ring
= NULL
;
1393 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1398 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1399 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1401 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1402 case PHY_M_PS_SPEED_1000
:
1404 case PHY_M_PS_SPEED_100
:
1411 static void sky2_link_up(struct sky2_port
*sky2
)
1413 struct sky2_hw
*hw
= sky2
->hw
;
1414 unsigned port
= sky2
->port
;
1417 /* Enable Transmit FIFO Underrun */
1418 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1420 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1421 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1422 reg
|= GM_GPCR_DUP_FULL
;
1425 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1426 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1427 gma_read16(hw
, port
, GM_GP_CTRL
);
1429 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1431 netif_carrier_on(sky2
->netdev
);
1432 netif_wake_queue(sky2
->netdev
);
1434 /* Turn on link LED */
1435 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1436 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1438 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1439 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1441 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1442 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1443 PHY_M_LEDC_INIT_CTRL(sky2
->speed
==
1445 PHY_M_LEDC_STA1_CTRL(sky2
->speed
==
1446 SPEED_100
? 7 : 0) |
1447 PHY_M_LEDC_STA0_CTRL(sky2
->speed
==
1448 SPEED_1000
? 7 : 0));
1449 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1452 if (netif_msg_link(sky2
))
1453 printk(KERN_INFO PFX
1454 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1455 sky2
->netdev
->name
, sky2
->speed
,
1456 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1457 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1458 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1461 static void sky2_link_down(struct sky2_port
*sky2
)
1463 struct sky2_hw
*hw
= sky2
->hw
;
1464 unsigned port
= sky2
->port
;
1467 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1469 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1470 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1471 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1472 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1474 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1475 /* restore Asymmetric Pause bit */
1476 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1477 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1481 netif_carrier_off(sky2
->netdev
);
1482 netif_stop_queue(sky2
->netdev
);
1484 /* Turn on link LED */
1485 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1487 if (netif_msg_link(sky2
))
1488 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1489 sky2_phy_init(hw
, port
);
1492 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1494 struct sky2_hw
*hw
= sky2
->hw
;
1495 unsigned port
= sky2
->port
;
1498 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1500 if (lpa
& PHY_M_AN_RF
) {
1501 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1505 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1506 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1507 printk(KERN_ERR PFX
"%s: master/slave fault",
1508 sky2
->netdev
->name
);
1512 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1513 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1514 sky2
->netdev
->name
);
1518 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1520 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1522 /* Pause bits are offset (9..8) */
1523 if (hw
->chip_id
== CHIP_ID_YUKON_XL
)
1526 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1527 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1529 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1530 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1531 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1533 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1539 * Interrupt from PHY are handled outside of interrupt context
1540 * because accessing phy registers requires spin wait which might
1541 * cause excess interrupt latency.
1543 static void sky2_phy_task(void *arg
)
1545 struct sky2_port
*sky2
= arg
;
1546 struct sky2_hw
*hw
= sky2
->hw
;
1547 u16 istatus
, phystat
;
1549 down(&sky2
->phy_sema
);
1550 istatus
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_INT_STAT
);
1551 phystat
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_PHY_STAT
);
1553 if (netif_msg_intr(sky2
))
1554 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1555 sky2
->netdev
->name
, istatus
, phystat
);
1557 if (istatus
& PHY_M_IS_AN_COMPL
) {
1558 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1563 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1564 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1566 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1568 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1570 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1571 if (phystat
& PHY_M_PS_LINK_UP
)
1574 sky2_link_down(sky2
);
1577 up(&sky2
->phy_sema
);
1579 local_irq_disable();
1580 hw
->intr_mask
|= (sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
;
1581 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1585 static void sky2_tx_timeout(struct net_device
*dev
)
1587 struct sky2_port
*sky2
= netdev_priv(dev
);
1588 struct sky2_hw
*hw
= sky2
->hw
;
1589 unsigned txq
= txqaddr
[sky2
->port
];
1591 if (netif_msg_timer(sky2
))
1592 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1594 netif_stop_queue(dev
);
1596 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1597 sky2_read32(hw
, Q_ADDR(txq
, Q_CSR
));
1599 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1601 sky2_tx_clean(sky2
);
1604 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1606 netif_wake_queue(dev
);
1610 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1611 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1612 static inline unsigned sky2_buf_size(int mtu
)
1614 return roundup(mtu
+ ETH_HLEN
+ 4, 8);
1617 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1619 struct sky2_port
*sky2
= netdev_priv(dev
);
1620 struct sky2_hw
*hw
= sky2
->hw
;
1624 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1627 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1630 if (!netif_running(dev
)) {
1635 sky2_write32(hw
, B0_IMSK
, 0);
1637 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1638 netif_stop_queue(dev
);
1639 netif_poll_disable(hw
->dev
[0]);
1641 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1642 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1644 sky2_rx_clean(sky2
);
1647 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1648 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1649 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1651 if (dev
->mtu
> ETH_DATA_LEN
)
1652 mode
|= GM_SMOD_JUMBO_ENA
;
1654 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1656 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1658 err
= sky2_rx_start(sky2
);
1659 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1664 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1666 netif_poll_enable(hw
->dev
[0]);
1667 netif_wake_queue(dev
);
1674 * Receive one packet.
1675 * For small packets or errors, just reuse existing skb.
1676 * For larger packets, get new buffer.
1678 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1679 u16 length
, u32 status
)
1681 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1682 struct sk_buff
*skb
= NULL
;
1684 if (unlikely(netif_msg_rx_status(sky2
)))
1685 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1686 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1688 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1689 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1691 if (status
& GMR_FS_ANY_ERR
)
1694 if (!(status
& GMR_FS_RX_OK
))
1697 if ((status
>> 16) != length
|| length
> sky2
->rx_bufsize
)
1700 if (length
< copybreak
) {
1701 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1705 skb_reserve(skb
, 2);
1706 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1707 length
, PCI_DMA_FROMDEVICE
);
1708 memcpy(skb
->data
, re
->skb
->data
, length
);
1709 skb
->ip_summed
= re
->skb
->ip_summed
;
1710 skb
->csum
= re
->skb
->csum
;
1711 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1712 length
, PCI_DMA_FROMDEVICE
);
1714 struct sk_buff
*nskb
;
1716 nskb
= dev_alloc_skb(sky2
->rx_bufsize
);
1722 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1723 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1724 prefetch(skb
->data
);
1726 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1727 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1730 skb_put(skb
, length
);
1732 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1733 sky2_rx_add(sky2
, re
->mapaddr
);
1735 /* Tell receiver about new buffers. */
1736 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
,
1737 &sky2
->rx_last_put
, RX_LE_SIZE
);
1742 ++sky2
->net_stats
.rx_over_errors
;
1746 ++sky2
->net_stats
.rx_errors
;
1748 if (netif_msg_rx_err(sky2
))
1749 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1750 sky2
->netdev
->name
, status
, length
);
1752 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1753 sky2
->net_stats
.rx_length_errors
++;
1754 if (status
& GMR_FS_FRAGMENT
)
1755 sky2
->net_stats
.rx_frame_errors
++;
1756 if (status
& GMR_FS_CRC_ERR
)
1757 sky2
->net_stats
.rx_crc_errors
++;
1758 if (status
& GMR_FS_RX_FF_OV
)
1759 sky2
->net_stats
.rx_fifo_errors
++;
1765 * Check for transmit complete
1767 #define TX_NO_STATUS 0xffff
1769 static inline void sky2_tx_check(struct sky2_hw
*hw
, int port
, u16 last
)
1771 if (last
!= TX_NO_STATUS
) {
1772 struct net_device
*dev
= hw
->dev
[port
];
1773 if (dev
&& netif_running(dev
)) {
1774 struct sky2_port
*sky2
= netdev_priv(dev
);
1775 sky2_tx_complete(sky2
, last
);
1781 * Both ports share the same status interrupt, therefore there is only
1784 static int sky2_poll(struct net_device
*dev0
, int *budget
)
1786 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
1787 unsigned int to_do
= min(dev0
->quota
, *budget
);
1788 unsigned int work_done
= 0;
1790 u16 tx_done
[2] = { TX_NO_STATUS
, TX_NO_STATUS
};
1792 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1793 BUG_ON(hwidx
>= STATUS_RING_SIZE
);
1796 while (hwidx
!= hw
->st_idx
) {
1797 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1798 struct net_device
*dev
;
1799 struct sky2_port
*sky2
;
1800 struct sk_buff
*skb
;
1805 le
= hw
->st_le
+ hw
->st_idx
;
1806 hw
->st_idx
= (hw
->st_idx
+ 1) % STATUS_RING_SIZE
;
1807 prefetch(hw
->st_le
+ hw
->st_idx
);
1809 BUG_ON(le
->link
>= 2);
1810 dev
= hw
->dev
[le
->link
];
1811 if (dev
== NULL
|| !netif_running(dev
))
1814 sky2
= netdev_priv(dev
);
1815 status
= le32_to_cpu(le
->status
);
1816 length
= le16_to_cpu(le
->length
);
1817 op
= le
->opcode
& ~HW_OWNER
;
1822 skb
= sky2_receive(sky2
, length
, status
);
1827 skb
->protocol
= eth_type_trans(skb
, dev
);
1828 dev
->last_rx
= jiffies
;
1830 #ifdef SKY2_VLAN_TAG_USED
1831 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1832 vlan_hwaccel_receive_skb(skb
,
1834 be16_to_cpu(sky2
->rx_tag
));
1837 netif_receive_skb(skb
);
1839 if (++work_done
>= to_do
)
1843 #ifdef SKY2_VLAN_TAG_USED
1845 sky2
->rx_tag
= length
;
1849 sky2
->rx_tag
= length
;
1853 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1854 skb
->ip_summed
= CHECKSUM_HW
;
1855 skb
->csum
= le16_to_cpu(status
);
1859 /* TX index reports status for both ports */
1860 tx_done
[0] = status
& 0xffff;
1861 tx_done
[1] = ((status
>> 24) & 0xff)
1862 | (u16
)(length
& 0xf) << 8;
1866 if (net_ratelimit())
1867 printk(KERN_WARNING PFX
1868 "unknown status opcode 0x%x\n", op
);
1874 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
1877 sky2_tx_check(hw
, 0, tx_done
[0]);
1878 sky2_tx_check(hw
, 1, tx_done
[1]);
1880 if (sky2_read16(hw
, STAT_PUT_IDX
) == hw
->st_idx
) {
1881 /* need to restart TX timer */
1883 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1884 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1887 netif_rx_complete(dev0
);
1888 hw
->intr_mask
|= Y2_IS_STAT_BMU
;
1889 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1893 *budget
-= work_done
;
1894 dev0
->quota
-= work_done
;
1899 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
1901 struct net_device
*dev
= hw
->dev
[port
];
1903 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
1906 if (status
& Y2_IS_PAR_RD1
) {
1907 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
1910 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
1913 if (status
& Y2_IS_PAR_WR1
) {
1914 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
1917 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
1920 if (status
& Y2_IS_PAR_MAC1
) {
1921 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
1922 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
1925 if (status
& Y2_IS_PAR_RX1
) {
1926 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
1927 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
1930 if (status
& Y2_IS_TCP_TXA1
) {
1931 printk(KERN_ERR PFX
"%s: TCP segmentation error\n", dev
->name
);
1932 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
1936 static void sky2_hw_intr(struct sky2_hw
*hw
)
1938 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
1940 if (status
& Y2_IS_TIST_OV
)
1941 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
1943 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
1946 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_err
);
1947 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
1948 pci_name(hw
->pdev
), pci_err
);
1950 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
1951 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
1952 pci_err
| PCI_STATUS_ERROR_BITS
);
1953 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
1956 if (status
& Y2_IS_PCI_EXP
) {
1957 /* PCI-Express uncorrectable Error occurred */
1960 pci_read_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
, &pex_err
);
1962 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
1963 pci_name(hw
->pdev
), pex_err
);
1965 /* clear the interrupt */
1966 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
1967 pci_write_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
,
1969 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
1971 if (pex_err
& PEX_FATAL_ERRORS
) {
1972 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
1973 hwmsk
&= ~Y2_IS_PCI_EXP
;
1974 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
1978 if (status
& Y2_HWE_L1_MASK
)
1979 sky2_hw_error(hw
, 0, status
);
1981 if (status
& Y2_HWE_L1_MASK
)
1982 sky2_hw_error(hw
, 1, status
);
1985 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
1987 struct net_device
*dev
= hw
->dev
[port
];
1988 struct sky2_port
*sky2
= netdev_priv(dev
);
1989 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
1991 if (netif_msg_intr(sky2
))
1992 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
1995 if (status
& GM_IS_RX_FF_OR
) {
1996 ++sky2
->net_stats
.rx_fifo_errors
;
1997 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2000 if (status
& GM_IS_TX_FF_UR
) {
2001 ++sky2
->net_stats
.tx_fifo_errors
;
2002 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2006 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2008 struct net_device
*dev
= hw
->dev
[port
];
2009 struct sky2_port
*sky2
= netdev_priv(dev
);
2011 hw
->intr_mask
&= ~(port
== 0 ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
2012 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2013 schedule_work(&sky2
->phy_task
);
2016 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2018 struct sky2_hw
*hw
= dev_id
;
2019 struct net_device
*dev0
= hw
->dev
[0];
2022 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2023 if (status
== 0 || status
== ~0)
2026 if (status
& Y2_IS_HW_ERR
)
2029 /* Do NAPI for Rx and Tx status */
2030 if (status
& Y2_IS_STAT_BMU
) {
2031 hw
->intr_mask
&= ~Y2_IS_STAT_BMU
;
2032 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2034 if (likely(__netif_rx_schedule_prep(dev0
))) {
2035 prefetch(&hw
->st_le
[hw
->st_idx
]);
2036 __netif_rx_schedule(dev0
);
2040 if (status
& Y2_IS_IRQ_PHY1
)
2041 sky2_phy_intr(hw
, 0);
2043 if (status
& Y2_IS_IRQ_PHY2
)
2044 sky2_phy_intr(hw
, 1);
2046 if (status
& Y2_IS_IRQ_MAC1
)
2047 sky2_mac_intr(hw
, 0);
2049 if (status
& Y2_IS_IRQ_MAC2
)
2050 sky2_mac_intr(hw
, 1);
2052 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
2054 sky2_read32(hw
, B0_IMSK
);
2059 #ifdef CONFIG_NET_POLL_CONTROLLER
2060 static void sky2_netpoll(struct net_device
*dev
)
2062 struct sky2_port
*sky2
= netdev_priv(dev
);
2064 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2068 /* Chip internal frequency for clock calculations */
2069 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2071 switch (hw
->chip_id
) {
2072 case CHIP_ID_YUKON_EC
:
2073 case CHIP_ID_YUKON_EC_U
:
2074 return 125; /* 125 Mhz */
2075 case CHIP_ID_YUKON_FE
:
2076 return 100; /* 100 Mhz */
2077 default: /* YUKON_XL */
2078 return 156; /* 156 Mhz */
2082 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2084 return sky2_mhz(hw
) * us
;
2087 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2089 return clk
/ sky2_mhz(hw
);
2093 static int sky2_reset(struct sky2_hw
*hw
)
2100 ctst
= sky2_read32(hw
, B0_CTST
);
2102 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2103 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2104 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2105 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2106 pci_name(hw
->pdev
), hw
->chip_id
);
2110 /* ring for status responses */
2111 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
2117 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2118 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2119 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2123 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2124 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2126 /* clear PCI errors, if any */
2127 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &status
);
2128 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2129 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
2130 status
| PCI_STATUS_ERROR_BITS
);
2132 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2134 /* clear any PEX errors */
2137 pci_write_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
,
2139 pci_read_config_word(hw
->pdev
, PEX_LNK_STAT
, &lstat
);
2142 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2143 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2146 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2147 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2148 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2151 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2153 sky2_set_power_state(hw
, PCI_D0
);
2155 for (i
= 0; i
< hw
->ports
; i
++) {
2156 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2157 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2160 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2162 /* Clear I2C IRQ noise */
2163 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2165 /* turn off hardware timer (unused) */
2166 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2167 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2169 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2171 /* Turn off descriptor polling */
2172 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2174 /* Turn off receive timestamp */
2175 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2176 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2178 /* enable the Tx Arbiters */
2179 for (i
= 0; i
< hw
->ports
; i
++)
2180 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2182 /* Initialize ram interface */
2183 for (i
= 0; i
< hw
->ports
; i
++) {
2184 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2186 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2187 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2188 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2189 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2190 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2191 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2192 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2193 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2194 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2195 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2196 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2197 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2200 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2202 for (i
= 0; i
< hw
->ports
; i
++)
2203 sky2_phy_reset(hw
, i
);
2205 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2208 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2209 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2211 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2212 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2214 /* Set the list last index */
2215 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2217 /* These status setup values are copied from SysKonnect's driver */
2219 /* WA for dev. #4.3 */
2220 sky2_write16(hw
, STAT_TX_IDX_TH
, 0xfff); /* Tx Threshold */
2222 /* set Status-FIFO watermark */
2223 sky2_write8(hw
, STAT_FIFO_WM
, 0x21); /* WA for dev. #4.18 */
2225 /* set Status-FIFO ISR watermark */
2226 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 0x07); /* WA for dev. #4.18 */
2227 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 10000));
2229 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2230 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2232 /* set Status-FIFO ISR watermark */
2233 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2234 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2236 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2238 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2239 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2240 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2243 /* enable status unit */
2244 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2246 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2247 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2248 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2253 static inline u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2257 modes
= SUPPORTED_10baseT_Half
2258 | SUPPORTED_10baseT_Full
2259 | SUPPORTED_100baseT_Half
2260 | SUPPORTED_100baseT_Full
2261 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2263 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2264 modes
|= SUPPORTED_1000baseT_Half
2265 | SUPPORTED_1000baseT_Full
;
2267 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2268 | SUPPORTED_Autoneg
;
2272 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2274 struct sky2_port
*sky2
= netdev_priv(dev
);
2275 struct sky2_hw
*hw
= sky2
->hw
;
2277 ecmd
->transceiver
= XCVR_INTERNAL
;
2278 ecmd
->supported
= sky2_supported_modes(hw
);
2279 ecmd
->phy_address
= PHY_ADDR_MARV
;
2281 ecmd
->supported
= SUPPORTED_10baseT_Half
2282 | SUPPORTED_10baseT_Full
2283 | SUPPORTED_100baseT_Half
2284 | SUPPORTED_100baseT_Full
2285 | SUPPORTED_1000baseT_Half
2286 | SUPPORTED_1000baseT_Full
2287 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2288 ecmd
->port
= PORT_TP
;
2290 ecmd
->port
= PORT_FIBRE
;
2292 ecmd
->advertising
= sky2
->advertising
;
2293 ecmd
->autoneg
= sky2
->autoneg
;
2294 ecmd
->speed
= sky2
->speed
;
2295 ecmd
->duplex
= sky2
->duplex
;
2299 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2301 struct sky2_port
*sky2
= netdev_priv(dev
);
2302 const struct sky2_hw
*hw
= sky2
->hw
;
2303 u32 supported
= sky2_supported_modes(hw
);
2305 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2306 ecmd
->advertising
= supported
;
2312 switch (ecmd
->speed
) {
2314 if (ecmd
->duplex
== DUPLEX_FULL
)
2315 setting
= SUPPORTED_1000baseT_Full
;
2316 else if (ecmd
->duplex
== DUPLEX_HALF
)
2317 setting
= SUPPORTED_1000baseT_Half
;
2322 if (ecmd
->duplex
== DUPLEX_FULL
)
2323 setting
= SUPPORTED_100baseT_Full
;
2324 else if (ecmd
->duplex
== DUPLEX_HALF
)
2325 setting
= SUPPORTED_100baseT_Half
;
2331 if (ecmd
->duplex
== DUPLEX_FULL
)
2332 setting
= SUPPORTED_10baseT_Full
;
2333 else if (ecmd
->duplex
== DUPLEX_HALF
)
2334 setting
= SUPPORTED_10baseT_Half
;
2342 if ((setting
& supported
) == 0)
2345 sky2
->speed
= ecmd
->speed
;
2346 sky2
->duplex
= ecmd
->duplex
;
2349 sky2
->autoneg
= ecmd
->autoneg
;
2350 sky2
->advertising
= ecmd
->advertising
;
2352 if (netif_running(dev
))
2353 sky2_phy_reinit(sky2
);
2358 static void sky2_get_drvinfo(struct net_device
*dev
,
2359 struct ethtool_drvinfo
*info
)
2361 struct sky2_port
*sky2
= netdev_priv(dev
);
2363 strcpy(info
->driver
, DRV_NAME
);
2364 strcpy(info
->version
, DRV_VERSION
);
2365 strcpy(info
->fw_version
, "N/A");
2366 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2369 static const struct sky2_stat
{
2370 char name
[ETH_GSTRING_LEN
];
2373 { "tx_bytes", GM_TXO_OK_HI
},
2374 { "rx_bytes", GM_RXO_OK_HI
},
2375 { "tx_broadcast", GM_TXF_BC_OK
},
2376 { "rx_broadcast", GM_RXF_BC_OK
},
2377 { "tx_multicast", GM_TXF_MC_OK
},
2378 { "rx_multicast", GM_RXF_MC_OK
},
2379 { "tx_unicast", GM_TXF_UC_OK
},
2380 { "rx_unicast", GM_RXF_UC_OK
},
2381 { "tx_mac_pause", GM_TXF_MPAUSE
},
2382 { "rx_mac_pause", GM_RXF_MPAUSE
},
2383 { "collisions", GM_TXF_SNG_COL
},
2384 { "late_collision",GM_TXF_LAT_COL
},
2385 { "aborted", GM_TXF_ABO_COL
},
2386 { "multi_collisions", GM_TXF_MUL_COL
},
2387 { "fifo_underrun", GM_TXE_FIFO_UR
},
2388 { "fifo_overflow", GM_RXE_FIFO_OV
},
2389 { "rx_toolong", GM_RXF_LNG_ERR
},
2390 { "rx_jabber", GM_RXF_JAB_PKT
},
2391 { "rx_runt", GM_RXE_FRAG
},
2392 { "rx_too_long", GM_RXF_LNG_ERR
},
2393 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2396 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2398 struct sky2_port
*sky2
= netdev_priv(dev
);
2400 return sky2
->rx_csum
;
2403 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2405 struct sky2_port
*sky2
= netdev_priv(dev
);
2407 sky2
->rx_csum
= data
;
2409 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2410 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2415 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2417 struct sky2_port
*sky2
= netdev_priv(netdev
);
2418 return sky2
->msg_enable
;
2421 static int sky2_nway_reset(struct net_device
*dev
)
2423 struct sky2_port
*sky2
= netdev_priv(dev
);
2425 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2428 sky2_phy_reinit(sky2
);
2433 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2435 struct sky2_hw
*hw
= sky2
->hw
;
2436 unsigned port
= sky2
->port
;
2439 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2440 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2441 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2442 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2444 for (i
= 2; i
< count
; i
++)
2445 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2448 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2450 struct sky2_port
*sky2
= netdev_priv(netdev
);
2451 sky2
->msg_enable
= value
;
2454 static int sky2_get_stats_count(struct net_device
*dev
)
2456 return ARRAY_SIZE(sky2_stats
);
2459 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2460 struct ethtool_stats
*stats
, u64
* data
)
2462 struct sky2_port
*sky2
= netdev_priv(dev
);
2464 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2467 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2471 switch (stringset
) {
2473 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2474 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2475 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2480 /* Use hardware MIB variables for critical path statistics and
2481 * transmit feedback not reported at interrupt.
2482 * Other errors are accounted for in interrupt handler.
2484 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2486 struct sky2_port
*sky2
= netdev_priv(dev
);
2489 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2491 sky2
->net_stats
.tx_bytes
= data
[0];
2492 sky2
->net_stats
.rx_bytes
= data
[1];
2493 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2494 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2495 sky2
->net_stats
.multicast
= data
[5] + data
[7];
2496 sky2
->net_stats
.collisions
= data
[10];
2497 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2499 return &sky2
->net_stats
;
2502 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2504 struct sky2_port
*sky2
= netdev_priv(dev
);
2505 struct sockaddr
*addr
= p
;
2507 if (!is_valid_ether_addr(addr
->sa_data
))
2508 return -EADDRNOTAVAIL
;
2510 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2511 memcpy_toio(sky2
->hw
->regs
+ B2_MAC_1
+ sky2
->port
* 8,
2512 dev
->dev_addr
, ETH_ALEN
);
2513 memcpy_toio(sky2
->hw
->regs
+ B2_MAC_2
+ sky2
->port
* 8,
2514 dev
->dev_addr
, ETH_ALEN
);
2516 if (netif_running(dev
))
2517 sky2_phy_reinit(sky2
);
2522 static void sky2_set_multicast(struct net_device
*dev
)
2524 struct sky2_port
*sky2
= netdev_priv(dev
);
2525 struct sky2_hw
*hw
= sky2
->hw
;
2526 unsigned port
= sky2
->port
;
2527 struct dev_mc_list
*list
= dev
->mc_list
;
2531 memset(filter
, 0, sizeof(filter
));
2533 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2534 reg
|= GM_RXCR_UCF_ENA
;
2536 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2537 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2538 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2539 memset(filter
, 0xff, sizeof(filter
));
2540 else if (dev
->mc_count
== 0) /* no multicast */
2541 reg
&= ~GM_RXCR_MCF_ENA
;
2544 reg
|= GM_RXCR_MCF_ENA
;
2546 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2547 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2548 filter
[bit
/ 8] |= 1 << (bit
% 8);
2552 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2553 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2554 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2555 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2556 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2557 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2558 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2559 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2561 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2564 /* Can have one global because blinking is controlled by
2565 * ethtool and that is always under RTNL mutex
2567 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2571 switch (hw
->chip_id
) {
2572 case CHIP_ID_YUKON_XL
:
2573 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2574 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2575 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2576 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2577 PHY_M_LEDC_INIT_CTRL(7) |
2578 PHY_M_LEDC_STA1_CTRL(7) |
2579 PHY_M_LEDC_STA0_CTRL(7))
2582 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2586 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2587 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2588 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2589 PHY_M_LED_MO_10(MO_LED_ON
) |
2590 PHY_M_LED_MO_100(MO_LED_ON
) |
2591 PHY_M_LED_MO_1000(MO_LED_ON
) |
2592 PHY_M_LED_MO_RX(MO_LED_ON
)
2593 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2594 PHY_M_LED_MO_10(MO_LED_OFF
) |
2595 PHY_M_LED_MO_100(MO_LED_OFF
) |
2596 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2597 PHY_M_LED_MO_RX(MO_LED_OFF
));
2602 /* blink LED's for finding board */
2603 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2605 struct sky2_port
*sky2
= netdev_priv(dev
);
2606 struct sky2_hw
*hw
= sky2
->hw
;
2607 unsigned port
= sky2
->port
;
2608 u16 ledctrl
, ledover
= 0;
2613 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2614 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2618 /* save initial values */
2619 down(&sky2
->phy_sema
);
2620 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2621 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2622 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2623 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2624 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2626 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2627 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2631 while (!interrupted
&& ms
> 0) {
2632 sky2_led(hw
, port
, onoff
);
2635 up(&sky2
->phy_sema
);
2636 interrupted
= msleep_interruptible(250);
2637 down(&sky2
->phy_sema
);
2642 /* resume regularly scheduled programming */
2643 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2644 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2645 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2646 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2647 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2649 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2650 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2652 up(&sky2
->phy_sema
);
2657 static void sky2_get_pauseparam(struct net_device
*dev
,
2658 struct ethtool_pauseparam
*ecmd
)
2660 struct sky2_port
*sky2
= netdev_priv(dev
);
2662 ecmd
->tx_pause
= sky2
->tx_pause
;
2663 ecmd
->rx_pause
= sky2
->rx_pause
;
2664 ecmd
->autoneg
= sky2
->autoneg
;
2667 static int sky2_set_pauseparam(struct net_device
*dev
,
2668 struct ethtool_pauseparam
*ecmd
)
2670 struct sky2_port
*sky2
= netdev_priv(dev
);
2673 sky2
->autoneg
= ecmd
->autoneg
;
2674 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2675 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2677 sky2_phy_reinit(sky2
);
2683 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2685 struct sky2_port
*sky2
= netdev_priv(dev
);
2687 wol
->supported
= WAKE_MAGIC
;
2688 wol
->wolopts
= sky2
->wol
? WAKE_MAGIC
: 0;
2691 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2693 struct sky2_port
*sky2
= netdev_priv(dev
);
2694 struct sky2_hw
*hw
= sky2
->hw
;
2696 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
2699 sky2
->wol
= wol
->wolopts
== WAKE_MAGIC
;
2702 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
2704 sky2_write16(hw
, WOL_CTRL_STAT
,
2705 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
2706 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
2708 sky2_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
2714 static int sky2_get_coalesce(struct net_device
*dev
,
2715 struct ethtool_coalesce
*ecmd
)
2717 struct sky2_port
*sky2
= netdev_priv(dev
);
2718 struct sky2_hw
*hw
= sky2
->hw
;
2720 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2721 ecmd
->tx_coalesce_usecs
= 0;
2723 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2724 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2726 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2728 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2729 ecmd
->rx_coalesce_usecs
= 0;
2731 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2732 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2734 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2736 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2737 ecmd
->rx_coalesce_usecs_irq
= 0;
2739 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2740 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2743 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2748 /* Note: this affect both ports */
2749 static int sky2_set_coalesce(struct net_device
*dev
,
2750 struct ethtool_coalesce
*ecmd
)
2752 struct sky2_port
*sky2
= netdev_priv(dev
);
2753 struct sky2_hw
*hw
= sky2
->hw
;
2754 const u32 tmin
= sky2_clk2us(hw
, 1);
2755 const u32 tmax
= 5000;
2757 if (ecmd
->tx_coalesce_usecs
!= 0 &&
2758 (ecmd
->tx_coalesce_usecs
< tmin
|| ecmd
->tx_coalesce_usecs
> tmax
))
2761 if (ecmd
->rx_coalesce_usecs
!= 0 &&
2762 (ecmd
->rx_coalesce_usecs
< tmin
|| ecmd
->rx_coalesce_usecs
> tmax
))
2765 if (ecmd
->rx_coalesce_usecs_irq
!= 0 &&
2766 (ecmd
->rx_coalesce_usecs_irq
< tmin
|| ecmd
->rx_coalesce_usecs_irq
> tmax
))
2769 if (ecmd
->tx_max_coalesced_frames
> 0xffff)
2771 if (ecmd
->rx_max_coalesced_frames
> 0xff)
2773 if (ecmd
->rx_max_coalesced_frames_irq
> 0xff)
2776 if (ecmd
->tx_coalesce_usecs
== 0)
2777 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2779 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2780 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2781 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2783 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2785 if (ecmd
->rx_coalesce_usecs
== 0)
2786 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2788 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2789 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2790 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2792 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2794 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2795 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2797 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2798 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2799 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2801 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2805 static void sky2_get_ringparam(struct net_device
*dev
,
2806 struct ethtool_ringparam
*ering
)
2808 struct sky2_port
*sky2
= netdev_priv(dev
);
2810 ering
->rx_max_pending
= RX_MAX_PENDING
;
2811 ering
->rx_mini_max_pending
= 0;
2812 ering
->rx_jumbo_max_pending
= 0;
2813 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2815 ering
->rx_pending
= sky2
->rx_pending
;
2816 ering
->rx_mini_pending
= 0;
2817 ering
->rx_jumbo_pending
= 0;
2818 ering
->tx_pending
= sky2
->tx_pending
;
2821 static int sky2_set_ringparam(struct net_device
*dev
,
2822 struct ethtool_ringparam
*ering
)
2824 struct sky2_port
*sky2
= netdev_priv(dev
);
2827 if (ering
->rx_pending
> RX_MAX_PENDING
||
2828 ering
->rx_pending
< 8 ||
2829 ering
->tx_pending
< MAX_SKB_TX_LE
||
2830 ering
->tx_pending
> TX_RING_SIZE
- 1)
2833 if (netif_running(dev
))
2836 sky2
->rx_pending
= ering
->rx_pending
;
2837 sky2
->tx_pending
= ering
->tx_pending
;
2839 if (netif_running(dev
)) {
2844 sky2_set_multicast(dev
);
2850 static int sky2_get_regs_len(struct net_device
*dev
)
2856 * Returns copy of control register region
2857 * Note: access to the RAM address register set will cause timeouts.
2859 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2862 const struct sky2_port
*sky2
= netdev_priv(dev
);
2863 const void __iomem
*io
= sky2
->hw
->regs
;
2865 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2867 memset(p
, 0, regs
->len
);
2869 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2871 memcpy_fromio(p
+ B3_RI_WTO_R1
,
2873 regs
->len
- B3_RI_WTO_R1
);
2876 static struct ethtool_ops sky2_ethtool_ops
= {
2877 .get_settings
= sky2_get_settings
,
2878 .set_settings
= sky2_set_settings
,
2879 .get_drvinfo
= sky2_get_drvinfo
,
2880 .get_msglevel
= sky2_get_msglevel
,
2881 .set_msglevel
= sky2_set_msglevel
,
2882 .nway_reset
= sky2_nway_reset
,
2883 .get_regs_len
= sky2_get_regs_len
,
2884 .get_regs
= sky2_get_regs
,
2885 .get_link
= ethtool_op_get_link
,
2886 .get_sg
= ethtool_op_get_sg
,
2887 .set_sg
= ethtool_op_set_sg
,
2888 .get_tx_csum
= ethtool_op_get_tx_csum
,
2889 .set_tx_csum
= ethtool_op_set_tx_csum
,
2890 .get_tso
= ethtool_op_get_tso
,
2891 .set_tso
= ethtool_op_set_tso
,
2892 .get_rx_csum
= sky2_get_rx_csum
,
2893 .set_rx_csum
= sky2_set_rx_csum
,
2894 .get_strings
= sky2_get_strings
,
2895 .get_coalesce
= sky2_get_coalesce
,
2896 .set_coalesce
= sky2_set_coalesce
,
2897 .get_ringparam
= sky2_get_ringparam
,
2898 .set_ringparam
= sky2_set_ringparam
,
2899 .get_pauseparam
= sky2_get_pauseparam
,
2900 .set_pauseparam
= sky2_set_pauseparam
,
2902 .get_wol
= sky2_get_wol
,
2903 .set_wol
= sky2_set_wol
,
2905 .phys_id
= sky2_phys_id
,
2906 .get_stats_count
= sky2_get_stats_count
,
2907 .get_ethtool_stats
= sky2_get_ethtool_stats
,
2908 .get_perm_addr
= ethtool_op_get_perm_addr
,
2911 /* Initialize network device */
2912 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
2913 unsigned port
, int highmem
)
2915 struct sky2_port
*sky2
;
2916 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
2919 printk(KERN_ERR
"sky2 etherdev alloc failed");
2923 SET_MODULE_OWNER(dev
);
2924 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
2925 dev
->irq
= hw
->pdev
->irq
;
2926 dev
->open
= sky2_up
;
2927 dev
->stop
= sky2_down
;
2928 dev
->do_ioctl
= sky2_ioctl
;
2929 dev
->hard_start_xmit
= sky2_xmit_frame
;
2930 dev
->get_stats
= sky2_get_stats
;
2931 dev
->set_multicast_list
= sky2_set_multicast
;
2932 dev
->set_mac_address
= sky2_set_mac_address
;
2933 dev
->change_mtu
= sky2_change_mtu
;
2934 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
2935 dev
->tx_timeout
= sky2_tx_timeout
;
2936 dev
->watchdog_timeo
= TX_WATCHDOG
;
2938 dev
->poll
= sky2_poll
;
2939 dev
->weight
= NAPI_WEIGHT
;
2940 #ifdef CONFIG_NET_POLL_CONTROLLER
2941 dev
->poll_controller
= sky2_netpoll
;
2944 sky2
= netdev_priv(dev
);
2947 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
2949 spin_lock_init(&sky2
->tx_lock
);
2950 /* Auto speed and flow control */
2951 sky2
->autoneg
= AUTONEG_ENABLE
;
2956 sky2
->advertising
= sky2_supported_modes(hw
);
2958 /* Receive checksum disabled for Yukon XL
2959 * because of observed problems with incorrect
2960 * values when multiple packets are received in one interrupt
2962 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
2964 INIT_WORK(&sky2
->phy_task
, sky2_phy_task
, sky2
);
2965 init_MUTEX(&sky2
->phy_sema
);
2966 sky2
->tx_pending
= TX_DEF_PENDING
;
2967 sky2
->rx_pending
= is_ec_a1(hw
) ? 8 : RX_DEF_PENDING
;
2968 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
2970 hw
->dev
[port
] = dev
;
2974 dev
->features
|= NETIF_F_LLTX
;
2975 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
2976 dev
->features
|= NETIF_F_TSO
;
2978 dev
->features
|= NETIF_F_HIGHDMA
;
2979 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
2981 #ifdef SKY2_VLAN_TAG_USED
2982 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2983 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
2984 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
2987 /* read the mac address */
2988 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
2989 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2991 /* device is off until link detection */
2992 netif_carrier_off(dev
);
2993 netif_stop_queue(dev
);
2998 static inline void sky2_show_addr(struct net_device
*dev
)
3000 const struct sky2_port
*sky2
= netdev_priv(dev
);
3002 if (netif_msg_probe(sky2
))
3003 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3005 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3006 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3009 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3010 const struct pci_device_id
*ent
)
3012 struct net_device
*dev
, *dev1
= NULL
;
3014 int err
, pm_cap
, using_dac
= 0;
3016 err
= pci_enable_device(pdev
);
3018 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3023 err
= pci_request_regions(pdev
, DRV_NAME
);
3025 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3030 pci_set_master(pdev
);
3032 /* Find power-management capability. */
3033 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3035 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3038 goto err_out_free_regions
;
3041 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
3042 err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
3048 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3050 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3052 goto err_out_free_regions
;
3056 /* byte swap descriptors in hardware */
3060 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3061 reg
|= PCI_REV_DESC
;
3062 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3067 hw
= kmalloc(sizeof(*hw
), GFP_KERNEL
);
3069 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3071 goto err_out_free_regions
;
3074 memset(hw
, 0, sizeof(*hw
));
3077 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3079 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3081 goto err_out_free_hw
;
3083 hw
->pm_cap
= pm_cap
;
3085 err
= sky2_reset(hw
);
3087 goto err_out_iounmap
;
3089 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3090 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3091 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3092 hw
->chip_id
, hw
->chip_rev
);
3094 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3096 goto err_out_free_pci
;
3098 err
= register_netdev(dev
);
3100 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3102 goto err_out_free_netdev
;
3105 sky2_show_addr(dev
);
3107 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3108 if (register_netdev(dev1
) == 0)
3109 sky2_show_addr(dev1
);
3111 /* Failure to register second port need not be fatal */
3112 printk(KERN_WARNING PFX
3113 "register of second port failed\n");
3119 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3121 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3122 pci_name(pdev
), pdev
->irq
);
3123 goto err_out_unregister
;
3126 hw
->intr_mask
= Y2_IS_BASE
;
3127 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3129 pci_set_drvdata(pdev
, hw
);
3135 unregister_netdev(dev1
);
3138 unregister_netdev(dev
);
3139 err_out_free_netdev
:
3142 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3143 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3148 err_out_free_regions
:
3149 pci_release_regions(pdev
);
3150 pci_disable_device(pdev
);
3155 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3157 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3158 struct net_device
*dev0
, *dev1
;
3166 unregister_netdev(dev1
);
3167 unregister_netdev(dev0
);
3169 sky2_write32(hw
, B0_IMSK
, 0);
3170 sky2_set_power_state(hw
, PCI_D3hot
);
3171 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3172 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3173 sky2_read8(hw
, B0_CTST
);
3175 free_irq(pdev
->irq
, hw
);
3176 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3177 pci_release_regions(pdev
);
3178 pci_disable_device(pdev
);
3186 pci_set_drvdata(pdev
, NULL
);
3190 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3192 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3195 for (i
= 0; i
< 2; i
++) {
3196 struct net_device
*dev
= hw
->dev
[i
];
3199 if (!netif_running(dev
))
3203 netif_device_detach(dev
);
3207 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3210 static int sky2_resume(struct pci_dev
*pdev
)
3212 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3215 pci_restore_state(pdev
);
3216 pci_enable_wake(pdev
, PCI_D0
, 0);
3217 sky2_set_power_state(hw
, PCI_D0
);
3221 for (i
= 0; i
< 2; i
++) {
3222 struct net_device
*dev
= hw
->dev
[i
];
3224 if (netif_running(dev
)) {
3225 netif_device_attach(dev
);
3235 static struct pci_driver sky2_driver
= {
3237 .id_table
= sky2_id_table
,
3238 .probe
= sky2_probe
,
3239 .remove
= __devexit_p(sky2_remove
),
3241 .suspend
= sky2_suspend
,
3242 .resume
= sky2_resume
,
3246 static int __init
sky2_init_module(void)
3248 return pci_register_driver(&sky2_driver
);
3251 static void __exit
sky2_cleanup_module(void)
3253 pci_unregister_driver(&sky2_driver
);
3256 module_init(sky2_init_module
);
3257 module_exit(sky2_cleanup_module
);
3259 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3260 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3261 MODULE_LICENSE("GPL");
3262 MODULE_VERSION(DRV_VERSION
);