2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/via-core.h>
25 * Figure out an appropriate bytes-per-pixel setting.
27 static int viafb_set_bpp(void __iomem
*engine
, u8 bpp
)
31 /* Preserve the reserved bits */
32 /* Lowest 2 bits to zero gives us no rotation */
33 gemode
= readl(engine
+ VIA_REG_GEMODE
) & 0xfffffcfc;
36 gemode
|= VIA_GEM_8bpp
;
39 gemode
|= VIA_GEM_16bpp
;
42 gemode
|= VIA_GEM_32bpp
;
45 printk(KERN_WARNING
"viafb_set_bpp: Unsupported bpp %d\n", bpp
);
48 writel(gemode
, engine
+ VIA_REG_GEMODE
);
53 static int hw_bitblt_1(void __iomem
*engine
, u8 op
, u32 width
, u32 height
,
54 u8 dst_bpp
, u32 dst_addr
, u32 dst_pitch
, u32 dst_x
, u32 dst_y
,
55 u32
*src_mem
, u32 src_addr
, u32 src_pitch
, u32 src_x
, u32 src_y
,
56 u32 fg_color
, u32 bg_color
, u8 fill_rop
)
58 u32 ge_cmd
= 0, tmp
, i
;
62 printk(KERN_WARNING
"hw_bitblt_1: Invalid operation: %d\n", op
);
66 if (op
!= VIA_BITBLT_FILL
&& !src_mem
&& src_addr
== dst_addr
) {
79 if (op
== VIA_BITBLT_FILL
) {
81 case 0x00: /* blackness */
82 case 0x5A: /* pattern inversion */
83 case 0xF0: /* pattern copy */
84 case 0xFF: /* whiteness */
87 printk(KERN_WARNING
"hw_bitblt_1: Invalid fill rop: "
93 ret
= viafb_set_bpp(engine
, dst_bpp
);
97 if (op
!= VIA_BITBLT_FILL
) {
98 if (src_x
& (op
== VIA_BITBLT_MONO
? 0xFFFF8000 : 0xFFFFF000)
99 || src_y
& 0xFFFFF000) {
100 printk(KERN_WARNING
"hw_bitblt_1: Unsupported source "
101 "x/y %d %d\n", src_x
, src_y
);
104 tmp
= src_x
| (src_y
<< 16);
105 writel(tmp
, engine
+ 0x08);
108 if (dst_x
& 0xFFFFF000 || dst_y
& 0xFFFFF000) {
109 printk(KERN_WARNING
"hw_bitblt_1: Unsupported destination x/y "
110 "%d %d\n", dst_x
, dst_y
);
113 tmp
= dst_x
| (dst_y
<< 16);
114 writel(tmp
, engine
+ 0x0C);
116 if ((width
- 1) & 0xFFFFF000 || (height
- 1) & 0xFFFFF000) {
117 printk(KERN_WARNING
"hw_bitblt_1: Unsupported width/height "
118 "%d %d\n", width
, height
);
121 tmp
= (width
- 1) | ((height
- 1) << 16);
122 writel(tmp
, engine
+ 0x10);
124 if (op
!= VIA_BITBLT_COLOR
)
125 writel(fg_color
, engine
+ 0x18);
127 if (op
== VIA_BITBLT_MONO
)
128 writel(bg_color
, engine
+ 0x1C);
130 if (op
!= VIA_BITBLT_FILL
) {
131 tmp
= src_mem
? 0 : src_addr
;
132 if (dst_addr
& 0xE0000007) {
133 printk(KERN_WARNING
"hw_bitblt_1: Unsupported source "
134 "address %X\n", tmp
);
138 writel(tmp
, engine
+ 0x30);
141 if (dst_addr
& 0xE0000007) {
142 printk(KERN_WARNING
"hw_bitblt_1: Unsupported destination "
143 "address %X\n", dst_addr
);
147 writel(tmp
, engine
+ 0x34);
149 if (op
== VIA_BITBLT_FILL
)
153 if (tmp
& 0xFFFFC007 || dst_pitch
& 0xFFFFC007) {
154 printk(KERN_WARNING
"hw_bitblt_1: Unsupported pitch %X %X\n",
158 tmp
= VIA_PITCH_ENABLE
| (tmp
>> 3) | (dst_pitch
<< (16 - 3));
159 writel(tmp
, engine
+ 0x38);
161 if (op
== VIA_BITBLT_FILL
)
162 ge_cmd
|= fill_rop
<< 24 | 0x00002000 | 0x00000001;
164 ge_cmd
|= 0xCC000000; /* ROP=SRCCOPY */
166 ge_cmd
|= 0x00000040;
167 if (op
== VIA_BITBLT_MONO
)
168 ge_cmd
|= 0x00000002 | 0x00000100 | 0x00020000;
170 ge_cmd
|= 0x00000001;
172 writel(ge_cmd
, engine
);
174 if (op
== VIA_BITBLT_FILL
|| !src_mem
)
177 tmp
= (width
* height
* (op
== VIA_BITBLT_MONO
? 1 : (dst_bpp
>> 3)) +
180 for (i
= 0; i
< tmp
; i
++)
181 writel(src_mem
[i
], engine
+ VIA_MMIO_BLTBASE
);
186 static int hw_bitblt_2(void __iomem
*engine
, u8 op
, u32 width
, u32 height
,
187 u8 dst_bpp
, u32 dst_addr
, u32 dst_pitch
, u32 dst_x
, u32 dst_y
,
188 u32
*src_mem
, u32 src_addr
, u32 src_pitch
, u32 src_x
, u32 src_y
,
189 u32 fg_color
, u32 bg_color
, u8 fill_rop
)
191 u32 ge_cmd
= 0, tmp
, i
;
195 printk(KERN_WARNING
"hw_bitblt_2: Invalid operation: %d\n", op
);
199 if (op
!= VIA_BITBLT_FILL
&& !src_mem
&& src_addr
== dst_addr
) {
201 ge_cmd
|= 0x00008000;
206 ge_cmd
|= 0x00004000;
212 if (op
== VIA_BITBLT_FILL
) {
214 case 0x00: /* blackness */
215 case 0x5A: /* pattern inversion */
216 case 0xF0: /* pattern copy */
217 case 0xFF: /* whiteness */
220 printk(KERN_WARNING
"hw_bitblt_2: Invalid fill rop: "
226 ret
= viafb_set_bpp(engine
, dst_bpp
);
230 if (op
== VIA_BITBLT_FILL
)
234 if (tmp
& 0xFFFFC007 || dst_pitch
& 0xFFFFC007) {
235 printk(KERN_WARNING
"hw_bitblt_2: Unsupported pitch %X %X\n",
239 tmp
= (tmp
>> 3) | (dst_pitch
<< (16 - 3));
240 writel(tmp
, engine
+ 0x08);
242 if ((width
- 1) & 0xFFFFF000 || (height
- 1) & 0xFFFFF000) {
243 printk(KERN_WARNING
"hw_bitblt_2: Unsupported width/height "
244 "%d %d\n", width
, height
);
247 tmp
= (width
- 1) | ((height
- 1) << 16);
248 writel(tmp
, engine
+ 0x0C);
250 if (dst_x
& 0xFFFFF000 || dst_y
& 0xFFFFF000) {
251 printk(KERN_WARNING
"hw_bitblt_2: Unsupported destination x/y "
252 "%d %d\n", dst_x
, dst_y
);
255 tmp
= dst_x
| (dst_y
<< 16);
256 writel(tmp
, engine
+ 0x10);
258 if (dst_addr
& 0xE0000007) {
259 printk(KERN_WARNING
"hw_bitblt_2: Unsupported destination "
260 "address %X\n", dst_addr
);
264 writel(tmp
, engine
+ 0x14);
266 if (op
!= VIA_BITBLT_FILL
) {
267 if (src_x
& (op
== VIA_BITBLT_MONO
? 0xFFFF8000 : 0xFFFFF000)
268 || src_y
& 0xFFFFF000) {
269 printk(KERN_WARNING
"hw_bitblt_2: Unsupported source "
270 "x/y %d %d\n", src_x
, src_y
);
273 tmp
= src_x
| (src_y
<< 16);
274 writel(tmp
, engine
+ 0x18);
276 tmp
= src_mem
? 0 : src_addr
;
277 if (dst_addr
& 0xE0000007) {
278 printk(KERN_WARNING
"hw_bitblt_2: Unsupported source "
279 "address %X\n", tmp
);
283 writel(tmp
, engine
+ 0x1C);
286 if (op
!= VIA_BITBLT_COLOR
)
287 writel(fg_color
, engine
+ 0x4C);
289 if (op
== VIA_BITBLT_MONO
)
290 writel(bg_color
, engine
+ 0x50);
292 if (op
== VIA_BITBLT_FILL
)
293 ge_cmd
|= fill_rop
<< 24 | 0x00002000 | 0x00000001;
295 ge_cmd
|= 0xCC000000; /* ROP=SRCCOPY */
297 ge_cmd
|= 0x00000040;
298 if (op
== VIA_BITBLT_MONO
)
299 ge_cmd
|= 0x00000002 | 0x00000100 | 0x00020000;
301 ge_cmd
|= 0x00000001;
303 writel(ge_cmd
, engine
);
305 if (op
== VIA_BITBLT_FILL
|| !src_mem
)
308 tmp
= (width
* height
* (op
== VIA_BITBLT_MONO
? 1 : (dst_bpp
>> 3)) +
311 for (i
= 0; i
< tmp
; i
++)
312 writel(src_mem
[i
], engine
+ VIA_MMIO_BLTBASE
);
317 int viafb_init_engine(struct fb_info
*info
)
319 struct viafb_par
*viapar
= info
->par
;
320 void __iomem
*engine
;
322 u32 vq_start_addr
, vq_end_addr
, vq_start_low
, vq_end_low
, vq_high
,
323 vq_len
, chip_name
= viapar
->shared
->chip_info
.gfx_chip_name
;
325 engine
= viapar
->shared
->vdev
->engine_mmio
;
327 printk(KERN_WARNING
"viafb_init_accel: ioremap failed, "
328 "hardware acceleration disabled\n");
332 /* Initialize registers to reset the 2D engine */
333 switch (viapar
->shared
->chip_info
.twod_engine
) {
341 for (i
= 0; i
<= highest_reg
; i
+= 4)
342 writel(0x0, engine
+ i
);
345 case UNICHROME_CLE266
:
348 case UNICHROME_PM800
:
349 case UNICHROME_CN700
:
350 case UNICHROME_CX700
:
351 case UNICHROME_CN750
:
352 case UNICHROME_K8M890
:
353 case UNICHROME_P4M890
:
354 case UNICHROME_P4M900
:
355 viapar
->shared
->hw_bitblt
= hw_bitblt_1
;
357 case UNICHROME_VX800
:
358 case UNICHROME_VX855
:
359 viapar
->shared
->hw_bitblt
= hw_bitblt_2
;
362 viapar
->shared
->hw_bitblt
= NULL
;
365 viapar
->fbmem_free
-= CURSOR_SIZE
;
366 viapar
->shared
->cursor_vram_addr
= viapar
->fbmem_free
;
367 viapar
->fbmem_used
+= CURSOR_SIZE
;
369 viapar
->fbmem_free
-= VQ_SIZE
;
370 viapar
->shared
->vq_vram_addr
= viapar
->fbmem_free
;
371 viapar
->fbmem_used
+= VQ_SIZE
;
373 #if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
375 * Set aside a chunk of framebuffer memory for the camera
376 * driver. Someday this driver probably needs a proper allocator
377 * for fbmem; for now, we just have to do this before the
378 * framebuffer initializes itself.
380 * As for the size: the engine can handle three frames,
381 * 16 bits deep, up to VGA resolution.
383 viapar
->shared
->vdev
->camera_fbmem_size
= 3*VGA_HEIGHT
*VGA_WIDTH
*2;
384 viapar
->fbmem_free
-= viapar
->shared
->vdev
->camera_fbmem_size
;
385 viapar
->fbmem_used
+= viapar
->shared
->vdev
->camera_fbmem_size
;
386 viapar
->shared
->vdev
->camera_fbmem_offset
= viapar
->fbmem_free
;
389 /* Init AGP and VQ regs */
391 case UNICHROME_K8M890
:
392 case UNICHROME_P4M900
:
393 case UNICHROME_VX800
:
394 case UNICHROME_VX855
:
395 writel(0x00100000, engine
+ VIA_REG_CR_TRANSET
);
396 writel(0x680A0000, engine
+ VIA_REG_CR_TRANSPACE
);
397 writel(0x02000000, engine
+ VIA_REG_CR_TRANSPACE
);
401 writel(0x00100000, engine
+ VIA_REG_TRANSET
);
402 writel(0x00000000, engine
+ VIA_REG_TRANSPACE
);
403 writel(0x00333004, engine
+ VIA_REG_TRANSPACE
);
404 writel(0x60000000, engine
+ VIA_REG_TRANSPACE
);
405 writel(0x61000000, engine
+ VIA_REG_TRANSPACE
);
406 writel(0x62000000, engine
+ VIA_REG_TRANSPACE
);
407 writel(0x63000000, engine
+ VIA_REG_TRANSPACE
);
408 writel(0x64000000, engine
+ VIA_REG_TRANSPACE
);
409 writel(0x7D000000, engine
+ VIA_REG_TRANSPACE
);
411 writel(0xFE020000, engine
+ VIA_REG_TRANSET
);
412 writel(0x00000000, engine
+ VIA_REG_TRANSPACE
);
417 vq_start_addr
= viapar
->shared
->vq_vram_addr
;
418 vq_end_addr
= viapar
->shared
->vq_vram_addr
+ VQ_SIZE
- 1;
420 vq_start_low
= 0x50000000 | (vq_start_addr
& 0xFFFFFF);
421 vq_end_low
= 0x51000000 | (vq_end_addr
& 0xFFFFFF);
422 vq_high
= 0x52000000 | ((vq_start_addr
& 0xFF000000) >> 24) |
423 ((vq_end_addr
& 0xFF000000) >> 16);
424 vq_len
= 0x53000000 | (VQ_SIZE
>> 3);
427 case UNICHROME_K8M890
:
428 case UNICHROME_P4M900
:
429 case UNICHROME_VX800
:
430 case UNICHROME_VX855
:
431 vq_start_low
|= 0x20000000;
432 vq_end_low
|= 0x20000000;
433 vq_high
|= 0x20000000;
434 vq_len
|= 0x20000000;
436 writel(0x00100000, engine
+ VIA_REG_CR_TRANSET
);
437 writel(vq_high
, engine
+ VIA_REG_CR_TRANSPACE
);
438 writel(vq_start_low
, engine
+ VIA_REG_CR_TRANSPACE
);
439 writel(vq_end_low
, engine
+ VIA_REG_CR_TRANSPACE
);
440 writel(vq_len
, engine
+ VIA_REG_CR_TRANSPACE
);
441 writel(0x74301001, engine
+ VIA_REG_CR_TRANSPACE
);
442 writel(0x00000000, engine
+ VIA_REG_CR_TRANSPACE
);
445 writel(0x00FE0000, engine
+ VIA_REG_TRANSET
);
446 writel(0x080003FE, engine
+ VIA_REG_TRANSPACE
);
447 writel(0x0A00027C, engine
+ VIA_REG_TRANSPACE
);
448 writel(0x0B000260, engine
+ VIA_REG_TRANSPACE
);
449 writel(0x0C000274, engine
+ VIA_REG_TRANSPACE
);
450 writel(0x0D000264, engine
+ VIA_REG_TRANSPACE
);
451 writel(0x0E000000, engine
+ VIA_REG_TRANSPACE
);
452 writel(0x0F000020, engine
+ VIA_REG_TRANSPACE
);
453 writel(0x1000027E, engine
+ VIA_REG_TRANSPACE
);
454 writel(0x110002FE, engine
+ VIA_REG_TRANSPACE
);
455 writel(0x200F0060, engine
+ VIA_REG_TRANSPACE
);
457 writel(0x00000006, engine
+ VIA_REG_TRANSPACE
);
458 writel(0x40008C0F, engine
+ VIA_REG_TRANSPACE
);
459 writel(0x44000000, engine
+ VIA_REG_TRANSPACE
);
460 writel(0x45080C04, engine
+ VIA_REG_TRANSPACE
);
461 writel(0x46800408, engine
+ VIA_REG_TRANSPACE
);
463 writel(vq_high
, engine
+ VIA_REG_TRANSPACE
);
464 writel(vq_start_low
, engine
+ VIA_REG_TRANSPACE
);
465 writel(vq_end_low
, engine
+ VIA_REG_TRANSPACE
);
466 writel(vq_len
, engine
+ VIA_REG_TRANSPACE
);
470 /* Set Cursor Image Base Address */
471 writel(viapar
->shared
->cursor_vram_addr
, engine
+ VIA_REG_CURSOR_MODE
);
472 writel(0x0, engine
+ VIA_REG_CURSOR_POS
);
473 writel(0x0, engine
+ VIA_REG_CURSOR_ORG
);
474 writel(0x0, engine
+ VIA_REG_CURSOR_BG
);
475 writel(0x0, engine
+ VIA_REG_CURSOR_FG
);
479 void viafb_show_hw_cursor(struct fb_info
*info
, int Status
)
481 struct viafb_par
*viapar
= info
->par
;
482 u32 temp
, iga_path
= viapar
->iga_path
;
484 temp
= readl(viapar
->shared
->vdev
->engine_mmio
+ VIA_REG_CURSOR_MODE
);
501 writel(temp
, viapar
->shared
->vdev
->engine_mmio
+ VIA_REG_CURSOR_MODE
);
504 void viafb_wait_engine_idle(struct fb_info
*info
)
506 struct viafb_par
*viapar
= info
->par
;
509 void __iomem
*engine
= viapar
->shared
->vdev
->engine_mmio
;
511 switch (viapar
->shared
->chip_info
.twod_engine
) {
514 mask
= VIA_CMD_RGTR_BUSY_M1
| VIA_2D_ENG_BUSY_M1
|
518 while (!(readl(engine
+ VIA_REG_STATUS
) &
519 VIA_VR_QUEUE_BUSY
) && (loop
< MAXLOOP
)) {
523 mask
= VIA_CMD_RGTR_BUSY
| VIA_2D_ENG_BUSY
| VIA_3D_ENG_BUSY
;
527 while ((readl(engine
+ VIA_REG_STATUS
) & mask
) && (loop
< MAXLOOP
)) {
533 printk(KERN_ERR
"viafb_wait_engine_idle: not syncing\n");