2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 * Original release 01/11/99
16 * This code is released under the GNU General Public License (GPL)
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
55 # define BREAKPOINT() asm(" int $3");
57 # define BREAKPOINT() { }
60 #define MAX_ISA_DEVICES 10
61 #define MAX_PCI_DEVICES 10
62 #define MAX_TOTAL_DEVICES 20
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/signal.h>
67 #include <linux/sched.h>
68 #include <linux/timer.h>
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/tty.h>
72 #include <linux/tty_flip.h>
73 #include <linux/serial.h>
74 #include <linux/major.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
80 #include <linux/seq_file.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/vmalloc.h>
85 #include <linux/init.h>
86 #include <linux/ioctl.h>
87 #include <linux/synclink.h>
92 #include <linux/bitops.h>
93 #include <asm/types.h>
94 #include <linux/termios.h>
95 #include <linux/workqueue.h>
96 #include <linux/hdlc.h>
97 #include <linux/dma-mapping.h>
99 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100 #define SYNCLINK_GENERIC_HDLC 1
102 #define SYNCLINK_GENERIC_HDLC 0
105 #define GET_USER(error,value,addr) error = get_user(value,addr)
106 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107 #define PUT_USER(error,value,addr) error = put_user(value,addr)
108 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
110 #include <asm/uaccess.h>
112 #define RCLRVALUE 0xffff
114 static MGSL_PARAMS default_params
= {
115 MGSL_MODE_HDLC
, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE
/* unsigned char parity; */
130 #define SHARED_MEM_ADDRESS_SIZE 0x40000
131 #define BUFFERLISTSIZE 4096
132 #define DMABUFFERSIZE 4096
133 #define MAXRXFRAMES 7
135 typedef struct _DMABUFFERENTRY
137 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
138 volatile u16 count
; /* buffer size/data count */
139 volatile u16 status
; /* Control/status field */
140 volatile u16 rcc
; /* character count field */
141 u16 reserved
; /* padding required by 16C32 */
142 u32 link
; /* 32-bit flat link to next buffer entry */
143 char *virt_addr
; /* virtual address of data buffer */
144 u32 phys_entry
; /* physical address of this buffer entry */
146 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
148 /* The queue of BH actions to be performed */
151 #define BH_TRANSMIT 2
154 #define IO_PIN_SHUTDOWN_LIMIT 100
156 struct _input_signal_events
{
167 /* transmit holding buffer definitions*/
168 #define MAX_TX_HOLDING_BUFFERS 5
169 struct tx_holding_buffer
{
171 unsigned char * buffer
;
176 * Device instance data structure
181 struct tty_port port
;
185 struct mgsl_icount icount
;
188 int x_char
; /* xon/xoff character */
189 u16 read_status_mask
;
190 u16 ignore_status_mask
;
191 unsigned char *xmit_buf
;
196 wait_queue_head_t status_event_wait_q
;
197 wait_queue_head_t event_wait_q
;
198 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
199 struct mgsl_struct
*next_device
; /* device list link */
201 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
202 struct work_struct task
; /* task structure for scheduling bh */
204 u32 EventMask
; /* event trigger mask */
205 u32 RecordedEvents
; /* pending events */
207 u32 max_frame_size
; /* as set by device config */
211 bool bh_running
; /* Protection from multiple */
215 int dcd_chkcount
; /* check counts to prevent */
216 int cts_chkcount
; /* too many IRQs if a signal */
217 int dsr_chkcount
; /* is floating */
220 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
221 u32 buffer_list_phys
;
222 dma_addr_t buffer_list_dma_addr
;
224 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
226 unsigned int current_rx_buffer
;
228 int num_tx_dma_buffers
; /* number of tx dma frames required */
229 int tx_dma_buffers_used
;
230 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
232 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer
; /* next tx dma buffer to be loaded */
235 unsigned char *intermediate_rxbuffer
;
237 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
238 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index
; /* next tx holding buffer to store user request */
240 int tx_holding_count
; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
245 bool rx_rcc_underrun
;
254 char device_name
[25]; /* device instance name */
256 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus
; /* expansion bus number (zero based) */
258 unsigned char function
; /* PCI device number */
260 unsigned int io_base
; /* base I/O address of adapter */
261 unsigned int io_addr_size
; /* size of the I/O address range */
262 bool io_addr_requested
; /* true if I/O address requested */
264 unsigned int irq_level
; /* interrupt level */
265 unsigned long irq_flags
;
266 bool irq_requested
; /* true if IRQ requested */
268 unsigned int dma_level
; /* DMA channel */
269 bool dma_requested
; /* true if dma channel requested */
275 MGSL_PARAMS params
; /* communications parameters */
277 unsigned char serial_signals
; /* current serial signal states */
279 bool irq_occurred
; /* for diagnostics use */
280 unsigned int init_error
; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
284 unsigned char* memory_base
; /* shared memory address (PCI only) */
285 u32 phys_memory_base
;
286 bool shared_mem_requested
;
288 unsigned char* lcr_base
; /* local config registers (PCI only) */
291 bool lcr_mem_requested
;
294 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
295 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
296 bool drop_rts_on_tx_done
;
298 bool loopmode_insert_requested
;
299 bool loopmode_send_done_requested
;
301 struct _input_signal_events input_signal_events
;
303 /* generic HDLC device parts */
307 #if SYNCLINK_GENERIC_HDLC
308 struct net_device
*netdev
;
312 #define MGSL_MAGIC 0x5401
315 * The size of the serial xmit buffer is 1 page, or 4096 bytes
317 #ifndef SERIAL_XMIT_SIZE
318 #define SERIAL_XMIT_SIZE 4096
322 * These macros define the offsets used in calculating the
323 * I/O address of the specified USC registers.
327 #define DCPIN 2 /* Bit 1 of I/O address */
328 #define SDPIN 4 /* Bit 2 of I/O address */
330 #define DCAR 0 /* DMA command/address register */
331 #define CCAR SDPIN /* channel command/address register */
332 #define DATAREG DCPIN + SDPIN /* serial data register */
337 * These macros define the register address (ordinal number)
338 * used for writing address/value pairs to the USC.
341 #define CMR 0x02 /* Channel mode Register */
342 #define CCSR 0x04 /* Channel Command/status Register */
343 #define CCR 0x06 /* Channel Control Register */
344 #define PSR 0x08 /* Port status Register */
345 #define PCR 0x0a /* Port Control Register */
346 #define TMDR 0x0c /* Test mode Data Register */
347 #define TMCR 0x0e /* Test mode Control Register */
348 #define CMCR 0x10 /* Clock mode Control Register */
349 #define HCR 0x12 /* Hardware Configuration Register */
350 #define IVR 0x14 /* Interrupt Vector Register */
351 #define IOCR 0x16 /* Input/Output Control Register */
352 #define ICR 0x18 /* Interrupt Control Register */
353 #define DCCR 0x1a /* Daisy Chain Control Register */
354 #define MISR 0x1c /* Misc Interrupt status Register */
355 #define SICR 0x1e /* status Interrupt Control Register */
356 #define RDR 0x20 /* Receive Data Register */
357 #define RMR 0x22 /* Receive mode Register */
358 #define RCSR 0x24 /* Receive Command/status Register */
359 #define RICR 0x26 /* Receive Interrupt Control Register */
360 #define RSR 0x28 /* Receive Sync Register */
361 #define RCLR 0x2a /* Receive count Limit Register */
362 #define RCCR 0x2c /* Receive Character count Register */
363 #define TC0R 0x2e /* Time Constant 0 Register */
364 #define TDR 0x30 /* Transmit Data Register */
365 #define TMR 0x32 /* Transmit mode Register */
366 #define TCSR 0x34 /* Transmit Command/status Register */
367 #define TICR 0x36 /* Transmit Interrupt Control Register */
368 #define TSR 0x38 /* Transmit Sync Register */
369 #define TCLR 0x3a /* Transmit count Limit Register */
370 #define TCCR 0x3c /* Transmit Character count Register */
371 #define TC1R 0x3e /* Time Constant 1 Register */
375 * MACRO DEFINITIONS FOR DMA REGISTERS
378 #define DCR 0x06 /* DMA Control Register (shared) */
379 #define DACR 0x08 /* DMA Array count Register (shared) */
380 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
381 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
382 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
383 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
384 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
386 #define TDMR 0x02 /* Transmit DMA mode Register */
387 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
388 #define TBCR 0x2a /* Transmit Byte count Register */
389 #define TARL 0x2c /* Transmit Address Register (low) */
390 #define TARU 0x2e /* Transmit Address Register (high) */
391 #define NTBCR 0x3a /* Next Transmit Byte count Register */
392 #define NTARL 0x3c /* Next Transmit Address Register (low) */
393 #define NTARU 0x3e /* Next Transmit Address Register (high) */
395 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
396 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
397 #define RBCR 0xaa /* Receive Byte count Register */
398 #define RARL 0xac /* Receive Address Register (low) */
399 #define RARU 0xae /* Receive Address Register (high) */
400 #define NRBCR 0xba /* Next Receive Byte count Register */
401 #define NRARL 0xbc /* Next Receive Address Register (low) */
402 #define NRARU 0xbe /* Next Receive Address Register (high) */
406 * MACRO DEFINITIONS FOR MODEM STATUS BITS
409 #define MODEMSTATUS_DTR 0x80
410 #define MODEMSTATUS_DSR 0x40
411 #define MODEMSTATUS_RTS 0x20
412 #define MODEMSTATUS_CTS 0x10
413 #define MODEMSTATUS_RI 0x04
414 #define MODEMSTATUS_DCD 0x01
418 * Channel Command/Address Register (CCAR) Command Codes
421 #define RTCmd_Null 0x0000
422 #define RTCmd_ResetHighestIus 0x1000
423 #define RTCmd_TriggerChannelLoadDma 0x2000
424 #define RTCmd_TriggerRxDma 0x2800
425 #define RTCmd_TriggerTxDma 0x3000
426 #define RTCmd_TriggerRxAndTxDma 0x3800
427 #define RTCmd_PurgeRxFifo 0x4800
428 #define RTCmd_PurgeTxFifo 0x5000
429 #define RTCmd_PurgeRxAndTxFifo 0x5800
430 #define RTCmd_LoadRcc 0x6800
431 #define RTCmd_LoadTcc 0x7000
432 #define RTCmd_LoadRccAndTcc 0x7800
433 #define RTCmd_LoadTC0 0x8800
434 #define RTCmd_LoadTC1 0x9000
435 #define RTCmd_LoadTC0AndTC1 0x9800
436 #define RTCmd_SerialDataLSBFirst 0xa000
437 #define RTCmd_SerialDataMSBFirst 0xa800
438 #define RTCmd_SelectBigEndian 0xb000
439 #define RTCmd_SelectLittleEndian 0xb800
443 * DMA Command/Address Register (DCAR) Command Codes
446 #define DmaCmd_Null 0x0000
447 #define DmaCmd_ResetTxChannel 0x1000
448 #define DmaCmd_ResetRxChannel 0x1200
449 #define DmaCmd_StartTxChannel 0x2000
450 #define DmaCmd_StartRxChannel 0x2200
451 #define DmaCmd_ContinueTxChannel 0x3000
452 #define DmaCmd_ContinueRxChannel 0x3200
453 #define DmaCmd_PauseTxChannel 0x4000
454 #define DmaCmd_PauseRxChannel 0x4200
455 #define DmaCmd_AbortTxChannel 0x5000
456 #define DmaCmd_AbortRxChannel 0x5200
457 #define DmaCmd_InitTxChannel 0x7000
458 #define DmaCmd_InitRxChannel 0x7200
459 #define DmaCmd_ResetHighestDmaIus 0x8000
460 #define DmaCmd_ResetAllChannels 0x9000
461 #define DmaCmd_StartAllChannels 0xa000
462 #define DmaCmd_ContinueAllChannels 0xb000
463 #define DmaCmd_PauseAllChannels 0xc000
464 #define DmaCmd_AbortAllChannels 0xd000
465 #define DmaCmd_InitAllChannels 0xf000
467 #define TCmd_Null 0x0000
468 #define TCmd_ClearTxCRC 0x2000
469 #define TCmd_SelectTicrTtsaData 0x4000
470 #define TCmd_SelectTicrTxFifostatus 0x5000
471 #define TCmd_SelectTicrIntLevel 0x6000
472 #define TCmd_SelectTicrdma_level 0x7000
473 #define TCmd_SendFrame 0x8000
474 #define TCmd_SendAbort 0x9000
475 #define TCmd_EnableDleInsertion 0xc000
476 #define TCmd_DisableDleInsertion 0xd000
477 #define TCmd_ClearEofEom 0xe000
478 #define TCmd_SetEofEom 0xf000
480 #define RCmd_Null 0x0000
481 #define RCmd_ClearRxCRC 0x2000
482 #define RCmd_EnterHuntmode 0x3000
483 #define RCmd_SelectRicrRtsaData 0x4000
484 #define RCmd_SelectRicrRxFifostatus 0x5000
485 #define RCmd_SelectRicrIntLevel 0x6000
486 #define RCmd_SelectRicrdma_level 0x7000
489 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
492 #define RECEIVE_STATUS BIT5
493 #define RECEIVE_DATA BIT4
494 #define TRANSMIT_STATUS BIT3
495 #define TRANSMIT_DATA BIT2
501 * Receive status Bits in Receive Command/status Register RCSR
504 #define RXSTATUS_SHORT_FRAME BIT8
505 #define RXSTATUS_CODE_VIOLATION BIT8
506 #define RXSTATUS_EXITED_HUNT BIT7
507 #define RXSTATUS_IDLE_RECEIVED BIT6
508 #define RXSTATUS_BREAK_RECEIVED BIT5
509 #define RXSTATUS_ABORT_RECEIVED BIT5
510 #define RXSTATUS_RXBOUND BIT4
511 #define RXSTATUS_CRC_ERROR BIT3
512 #define RXSTATUS_FRAMING_ERROR BIT3
513 #define RXSTATUS_ABORT BIT2
514 #define RXSTATUS_PARITY_ERROR BIT2
515 #define RXSTATUS_OVERRUN BIT1
516 #define RXSTATUS_DATA_AVAILABLE BIT0
517 #define RXSTATUS_ALL 0x01f6
518 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
521 * Values for setting transmit idle mode in
522 * Transmit Control/status Register (TCSR)
524 #define IDLEMODE_FLAGS 0x0000
525 #define IDLEMODE_ALT_ONE_ZERO 0x0100
526 #define IDLEMODE_ZERO 0x0200
527 #define IDLEMODE_ONE 0x0300
528 #define IDLEMODE_ALT_MARK_SPACE 0x0500
529 #define IDLEMODE_SPACE 0x0600
530 #define IDLEMODE_MARK 0x0700
531 #define IDLEMODE_MASK 0x0700
534 * IUSC revision identifiers
536 #define IUSC_SL1660 0x4d44
537 #define IUSC_PRE_SL1660 0x4553
540 * Transmit status Bits in Transmit Command/status Register (TCSR)
543 #define TCSR_PRESERVE 0x0F00
545 #define TCSR_UNDERWAIT BIT11
546 #define TXSTATUS_PREAMBLE_SENT BIT7
547 #define TXSTATUS_IDLE_SENT BIT6
548 #define TXSTATUS_ABORT_SENT BIT5
549 #define TXSTATUS_EOF_SENT BIT4
550 #define TXSTATUS_EOM_SENT BIT4
551 #define TXSTATUS_CRC_SENT BIT3
552 #define TXSTATUS_ALL_SENT BIT2
553 #define TXSTATUS_UNDERRUN BIT1
554 #define TXSTATUS_FIFO_EMPTY BIT0
555 #define TXSTATUS_ALL 0x00fa
556 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
559 #define MISCSTATUS_RXC_LATCHED BIT15
560 #define MISCSTATUS_RXC BIT14
561 #define MISCSTATUS_TXC_LATCHED BIT13
562 #define MISCSTATUS_TXC BIT12
563 #define MISCSTATUS_RI_LATCHED BIT11
564 #define MISCSTATUS_RI BIT10
565 #define MISCSTATUS_DSR_LATCHED BIT9
566 #define MISCSTATUS_DSR BIT8
567 #define MISCSTATUS_DCD_LATCHED BIT7
568 #define MISCSTATUS_DCD BIT6
569 #define MISCSTATUS_CTS_LATCHED BIT5
570 #define MISCSTATUS_CTS BIT4
571 #define MISCSTATUS_RCC_UNDERRUN BIT3
572 #define MISCSTATUS_DPLL_NO_SYNC BIT2
573 #define MISCSTATUS_BRG1_ZERO BIT1
574 #define MISCSTATUS_BRG0_ZERO BIT0
576 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
577 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
579 #define SICR_RXC_ACTIVE BIT15
580 #define SICR_RXC_INACTIVE BIT14
581 #define SICR_RXC (BIT15+BIT14)
582 #define SICR_TXC_ACTIVE BIT13
583 #define SICR_TXC_INACTIVE BIT12
584 #define SICR_TXC (BIT13+BIT12)
585 #define SICR_RI_ACTIVE BIT11
586 #define SICR_RI_INACTIVE BIT10
587 #define SICR_RI (BIT11+BIT10)
588 #define SICR_DSR_ACTIVE BIT9
589 #define SICR_DSR_INACTIVE BIT8
590 #define SICR_DSR (BIT9+BIT8)
591 #define SICR_DCD_ACTIVE BIT7
592 #define SICR_DCD_INACTIVE BIT6
593 #define SICR_DCD (BIT7+BIT6)
594 #define SICR_CTS_ACTIVE BIT5
595 #define SICR_CTS_INACTIVE BIT4
596 #define SICR_CTS (BIT5+BIT4)
597 #define SICR_RCC_UNDERFLOW BIT3
598 #define SICR_DPLL_NO_SYNC BIT2
599 #define SICR_BRG1_ZERO BIT1
600 #define SICR_BRG0_ZERO BIT0
602 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
603 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
604 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
605 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
606 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
608 #define usc_EnableInterrupts( a, b ) \
609 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
611 #define usc_DisableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
614 #define usc_EnableMasterIrqBit(a) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
617 #define usc_DisableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
620 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
623 * Transmit status Bits in Transmit Control status Register (TCSR)
624 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
627 #define TXSTATUS_PREAMBLE_SENT BIT7
628 #define TXSTATUS_IDLE_SENT BIT6
629 #define TXSTATUS_ABORT_SENT BIT5
630 #define TXSTATUS_EOF BIT4
631 #define TXSTATUS_CRC_SENT BIT3
632 #define TXSTATUS_ALL_SENT BIT2
633 #define TXSTATUS_UNDERRUN BIT1
634 #define TXSTATUS_FIFO_EMPTY BIT0
636 #define DICR_MASTER BIT15
637 #define DICR_TRANSMIT BIT0
638 #define DICR_RECEIVE BIT1
640 #define usc_EnableDmaInterrupts(a,b) \
641 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
643 #define usc_DisableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
646 #define usc_EnableStatusIrqs(a,b) \
647 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
649 #define usc_DisablestatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
652 /* Transmit status Bits in Transmit Control status Register (TCSR) */
653 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
656 #define DISABLE_UNCONDITIONAL 0
657 #define DISABLE_END_OF_FRAME 1
658 #define ENABLE_UNCONDITIONAL 2
659 #define ENABLE_AUTO_CTS 3
660 #define ENABLE_AUTO_DCD 3
661 #define usc_EnableTransmitter(a,b) \
662 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
663 #define usc_EnableReceiver(a,b) \
664 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
666 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
667 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
668 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
670 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
671 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
672 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
673 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
674 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
676 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
677 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
679 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
681 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
682 static void usc_start_receiver( struct mgsl_struct
*info
);
683 static void usc_stop_receiver( struct mgsl_struct
*info
);
685 static void usc_start_transmitter( struct mgsl_struct
*info
);
686 static void usc_stop_transmitter( struct mgsl_struct
*info
);
687 static void usc_set_txidle( struct mgsl_struct
*info
);
688 static void usc_load_txfifo( struct mgsl_struct
*info
);
690 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
691 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
693 static void usc_get_serial_signals( struct mgsl_struct
*info
);
694 static void usc_set_serial_signals( struct mgsl_struct
*info
);
696 static void usc_reset( struct mgsl_struct
*info
);
698 static void usc_set_sync_mode( struct mgsl_struct
*info
);
699 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
700 static void usc_set_async_mode( struct mgsl_struct
*info
);
701 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
703 static void usc_loopback_frame( struct mgsl_struct
*info
);
705 static void mgsl_tx_timeout(unsigned long context
);
708 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
709 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
710 static int usc_loopmode_active( struct mgsl_struct
* info
);
711 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
713 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
715 #if SYNCLINK_GENERIC_HDLC
716 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
717 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
718 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
719 static int hdlcdev_init(struct mgsl_struct
*info
);
720 static void hdlcdev_exit(struct mgsl_struct
*info
);
724 * Defines a BUS descriptor value for the PCI adapter
725 * local bus address ranges.
728 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
739 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
742 * Adapter diagnostic routines
744 static bool mgsl_register_test( struct mgsl_struct
*info
);
745 static bool mgsl_irq_test( struct mgsl_struct
*info
);
746 static bool mgsl_dma_test( struct mgsl_struct
*info
);
747 static bool mgsl_memory_test( struct mgsl_struct
*info
);
748 static int mgsl_adapter_test( struct mgsl_struct
*info
);
751 * device and resource management routines
753 static int mgsl_claim_resources(struct mgsl_struct
*info
);
754 static void mgsl_release_resources(struct mgsl_struct
*info
);
755 static void mgsl_add_device(struct mgsl_struct
*info
);
756 static struct mgsl_struct
* mgsl_allocate_device(void);
759 * DMA buffer manupulation functions.
761 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
762 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
763 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
764 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
765 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
766 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
767 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
768 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
771 * DMA and Shared Memory buffer allocation and formatting
773 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
774 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
775 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
776 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
777 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
778 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
779 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
780 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
781 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
782 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
783 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
784 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
787 * Bottom half interrupt handlers
789 static void mgsl_bh_handler(struct work_struct
*work
);
790 static void mgsl_bh_receive(struct mgsl_struct
*info
);
791 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
792 static void mgsl_bh_status(struct mgsl_struct
*info
);
795 * Interrupt handler routines and dispatch table.
797 static void mgsl_isr_null( struct mgsl_struct
*info
);
798 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
799 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
800 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
801 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
802 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
803 static void mgsl_isr_misc( struct mgsl_struct
*info
);
804 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
805 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
807 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
809 static isr_dispatch_func UscIsrTable
[7] =
814 mgsl_isr_transmit_data
,
815 mgsl_isr_transmit_status
,
816 mgsl_isr_receive_data
,
817 mgsl_isr_receive_status
821 * ioctl call handlers
823 static int tiocmget(struct tty_struct
*tty
);
824 static int tiocmset(struct tty_struct
*tty
,
825 unsigned int set
, unsigned int clear
);
826 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
827 __user
*user_icount
);
828 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
829 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
830 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
831 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
832 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
833 static int mgsl_txabort(struct mgsl_struct
* info
);
834 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
835 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
836 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
838 /* set non-zero on successful registration with PCI subsystem */
839 static bool pci_registered
;
842 * Global linked list of SyncLink devices
844 static struct mgsl_struct
*mgsl_device_list
;
845 static int mgsl_device_count
;
848 * Set this param to non-zero to load eax with the
849 * .text section address and breakpoint on module load.
850 * This is useful for use with gdb and add-symbol-file command.
852 static bool break_on_load
;
855 * Driver major number, defaults to zero to get auto
856 * assigned major number. May be forced as module parameter.
861 * Array of user specified options for ISA adapters.
863 static int io
[MAX_ISA_DEVICES
];
864 static int irq
[MAX_ISA_DEVICES
];
865 static int dma
[MAX_ISA_DEVICES
];
866 static int debug_level
;
867 static int maxframe
[MAX_TOTAL_DEVICES
];
868 static int txdmabufs
[MAX_TOTAL_DEVICES
];
869 static int txholdbufs
[MAX_TOTAL_DEVICES
];
871 module_param(break_on_load
, bool, 0);
872 module_param(ttymajor
, int, 0);
873 module_param_array(io
, int, NULL
, 0);
874 module_param_array(irq
, int, NULL
, 0);
875 module_param_array(dma
, int, NULL
, 0);
876 module_param(debug_level
, int, 0);
877 module_param_array(maxframe
, int, NULL
, 0);
878 module_param_array(txdmabufs
, int, NULL
, 0);
879 module_param_array(txholdbufs
, int, NULL
, 0);
881 static char *driver_name
= "SyncLink serial driver";
882 static char *driver_version
= "$Revision: 4.38 $";
884 static int synclink_init_one (struct pci_dev
*dev
,
885 const struct pci_device_id
*ent
);
886 static void synclink_remove_one (struct pci_dev
*dev
);
888 static struct pci_device_id synclink_pci_tbl
[] = {
889 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
890 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
891 { 0, }, /* terminate list */
893 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
895 MODULE_LICENSE("GPL");
897 static struct pci_driver synclink_pci_driver
= {
899 .id_table
= synclink_pci_tbl
,
900 .probe
= synclink_init_one
,
901 .remove
= __devexit_p(synclink_remove_one
),
904 static struct tty_driver
*serial_driver
;
906 /* number of characters left in xmit buffer before we ask for more */
907 #define WAKEUP_CHARS 256
910 static void mgsl_change_params(struct mgsl_struct
*info
);
911 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
914 * 1st function defined in .text section. Calling this function in
915 * init_module() followed by a breakpoint allows a remote debugger
916 * (gdb) to get the .text address for the add-symbol-file command.
917 * This allows remote debugging of dynamically loadable modules.
919 static void* mgsl_get_text_ptr(void)
921 return mgsl_get_text_ptr
;
924 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
925 char *name
, const char *routine
)
927 #ifdef MGSL_PARANOIA_CHECK
928 static const char *badmagic
=
929 "Warning: bad magic number for mgsl struct (%s) in %s\n";
930 static const char *badinfo
=
931 "Warning: null mgsl_struct for (%s) in %s\n";
934 printk(badinfo
, name
, routine
);
937 if (info
->magic
!= MGSL_MAGIC
) {
938 printk(badmagic
, name
, routine
);
949 * line discipline callback wrappers
951 * The wrappers maintain line discipline references
952 * while calling into the line discipline.
954 * ldisc_receive_buf - pass receive data to line discipline
957 static void ldisc_receive_buf(struct tty_struct
*tty
,
958 const __u8
*data
, char *flags
, int count
)
960 struct tty_ldisc
*ld
;
963 ld
= tty_ldisc_ref(tty
);
965 if (ld
->ops
->receive_buf
)
966 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
971 /* mgsl_stop() throttle (stop) transmitter
973 * Arguments: tty pointer to tty info structure
976 static void mgsl_stop(struct tty_struct
*tty
)
978 struct mgsl_struct
*info
= tty
->driver_data
;
981 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
984 if ( debug_level
>= DEBUG_LEVEL_INFO
)
985 printk("mgsl_stop(%s)\n",info
->device_name
);
987 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
988 if (info
->tx_enabled
)
989 usc_stop_transmitter(info
);
990 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
992 } /* end of mgsl_stop() */
994 /* mgsl_start() release (start) transmitter
996 * Arguments: tty pointer to tty info structure
999 static void mgsl_start(struct tty_struct
*tty
)
1001 struct mgsl_struct
*info
= tty
->driver_data
;
1002 unsigned long flags
;
1004 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1007 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1008 printk("mgsl_start(%s)\n",info
->device_name
);
1010 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1011 if (!info
->tx_enabled
)
1012 usc_start_transmitter(info
);
1013 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1015 } /* end of mgsl_start() */
1018 * Bottom half work queue access functions
1021 /* mgsl_bh_action() Return next bottom half action to perform.
1022 * Return Value: BH action code or 0 if nothing to do.
1024 static int mgsl_bh_action(struct mgsl_struct
*info
)
1026 unsigned long flags
;
1029 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1031 if (info
->pending_bh
& BH_RECEIVE
) {
1032 info
->pending_bh
&= ~BH_RECEIVE
;
1034 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1035 info
->pending_bh
&= ~BH_TRANSMIT
;
1037 } else if (info
->pending_bh
& BH_STATUS
) {
1038 info
->pending_bh
&= ~BH_STATUS
;
1043 /* Mark BH routine as complete */
1044 info
->bh_running
= false;
1045 info
->bh_requested
= false;
1048 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1054 * Perform bottom half processing of work items queued by ISR.
1056 static void mgsl_bh_handler(struct work_struct
*work
)
1058 struct mgsl_struct
*info
=
1059 container_of(work
, struct mgsl_struct
, task
);
1065 if ( debug_level
>= DEBUG_LEVEL_BH
)
1066 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1067 __FILE__
,__LINE__
,info
->device_name
);
1069 info
->bh_running
= true;
1071 while((action
= mgsl_bh_action(info
)) != 0) {
1073 /* Process work item */
1074 if ( debug_level
>= DEBUG_LEVEL_BH
)
1075 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1076 __FILE__
,__LINE__
,action
);
1081 mgsl_bh_receive(info
);
1084 mgsl_bh_transmit(info
);
1087 mgsl_bh_status(info
);
1090 /* unknown work item ID */
1091 printk("Unknown work item ID=%08X!\n", action
);
1096 if ( debug_level
>= DEBUG_LEVEL_BH
)
1097 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1098 __FILE__
,__LINE__
,info
->device_name
);
1101 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1103 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1104 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1106 if ( debug_level
>= DEBUG_LEVEL_BH
)
1107 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1108 __FILE__
,__LINE__
,info
->device_name
);
1112 if (info
->rx_rcc_underrun
) {
1113 unsigned long flags
;
1114 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1115 usc_start_receiver(info
);
1116 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1119 } while(get_rx_frame(info
));
1122 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1124 struct tty_struct
*tty
= info
->port
.tty
;
1125 unsigned long flags
;
1127 if ( debug_level
>= DEBUG_LEVEL_BH
)
1128 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1129 __FILE__
,__LINE__
,info
->device_name
);
1134 /* if transmitter idle and loopmode_send_done_requested
1135 * then start echoing RxD to TxD
1137 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1138 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1139 usc_loopmode_send_done( info
);
1140 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1143 static void mgsl_bh_status(struct mgsl_struct
*info
)
1145 if ( debug_level
>= DEBUG_LEVEL_BH
)
1146 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1147 __FILE__
,__LINE__
,info
->device_name
);
1149 info
->ri_chkcount
= 0;
1150 info
->dsr_chkcount
= 0;
1151 info
->dcd_chkcount
= 0;
1152 info
->cts_chkcount
= 0;
1155 /* mgsl_isr_receive_status()
1157 * Service a receive status interrupt. The type of status
1158 * interrupt is indicated by the state of the RCSR.
1159 * This is only used for HDLC mode.
1161 * Arguments: info pointer to device instance data
1162 * Return Value: None
1164 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1166 u16 status
= usc_InReg( info
, RCSR
);
1168 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1169 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1170 __FILE__
,__LINE__
,status
);
1172 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1173 info
->loopmode_insert_requested
&&
1174 usc_loopmode_active(info
) )
1176 ++info
->icount
.rxabort
;
1177 info
->loopmode_insert_requested
= false;
1179 /* clear CMR:13 to start echoing RxD to TxD */
1180 info
->cmr_value
&= ~BIT13
;
1181 usc_OutReg(info
, CMR
, info
->cmr_value
);
1183 /* disable received abort irq (no longer required) */
1184 usc_OutReg(info
, RICR
,
1185 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1188 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1189 if (status
& RXSTATUS_EXITED_HUNT
)
1190 info
->icount
.exithunt
++;
1191 if (status
& RXSTATUS_IDLE_RECEIVED
)
1192 info
->icount
.rxidle
++;
1193 wake_up_interruptible(&info
->event_wait_q
);
1196 if (status
& RXSTATUS_OVERRUN
){
1197 info
->icount
.rxover
++;
1198 usc_process_rxoverrun_sync( info
);
1201 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1202 usc_UnlatchRxstatusBits( info
, status
);
1204 } /* end of mgsl_isr_receive_status() */
1206 /* mgsl_isr_transmit_status()
1208 * Service a transmit status interrupt
1209 * HDLC mode :end of transmit frame
1210 * Async mode:all data is sent
1211 * transmit status is indicated by bits in the TCSR.
1213 * Arguments: info pointer to device instance data
1214 * Return Value: None
1216 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1218 u16 status
= usc_InReg( info
, TCSR
);
1220 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1221 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1222 __FILE__
,__LINE__
,status
);
1224 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1225 usc_UnlatchTxstatusBits( info
, status
);
1227 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1229 /* finished sending HDLC abort. This may leave */
1230 /* the TxFifo with data from the aborted frame */
1231 /* so purge the TxFifo. Also shutdown the DMA */
1232 /* channel in case there is data remaining in */
1233 /* the DMA buffer */
1234 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1235 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1238 if ( status
& TXSTATUS_EOF_SENT
)
1239 info
->icount
.txok
++;
1240 else if ( status
& TXSTATUS_UNDERRUN
)
1241 info
->icount
.txunder
++;
1242 else if ( status
& TXSTATUS_ABORT_SENT
)
1243 info
->icount
.txabort
++;
1245 info
->icount
.txunder
++;
1247 info
->tx_active
= false;
1248 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1249 del_timer(&info
->tx_timer
);
1251 if ( info
->drop_rts_on_tx_done
) {
1252 usc_get_serial_signals( info
);
1253 if ( info
->serial_signals
& SerialSignal_RTS
) {
1254 info
->serial_signals
&= ~SerialSignal_RTS
;
1255 usc_set_serial_signals( info
);
1257 info
->drop_rts_on_tx_done
= false;
1260 #if SYNCLINK_GENERIC_HDLC
1262 hdlcdev_tx_done(info
);
1266 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1267 usc_stop_transmitter(info
);
1270 info
->pending_bh
|= BH_TRANSMIT
;
1273 } /* end of mgsl_isr_transmit_status() */
1275 /* mgsl_isr_io_pin()
1277 * Service an Input/Output pin interrupt. The type of
1278 * interrupt is indicated by bits in the MISR
1280 * Arguments: info pointer to device instance data
1281 * Return Value: None
1283 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1285 struct mgsl_icount
*icount
;
1286 u16 status
= usc_InReg( info
, MISR
);
1288 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1289 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1290 __FILE__
,__LINE__
,status
);
1292 usc_ClearIrqPendingBits( info
, IO_PIN
);
1293 usc_UnlatchIostatusBits( info
, status
);
1295 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1296 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1297 icount
= &info
->icount
;
1298 /* update input line counters */
1299 if (status
& MISCSTATUS_RI_LATCHED
) {
1300 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1301 usc_DisablestatusIrqs(info
,SICR_RI
);
1303 if ( status
& MISCSTATUS_RI
)
1304 info
->input_signal_events
.ri_up
++;
1306 info
->input_signal_events
.ri_down
++;
1308 if (status
& MISCSTATUS_DSR_LATCHED
) {
1309 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1310 usc_DisablestatusIrqs(info
,SICR_DSR
);
1312 if ( status
& MISCSTATUS_DSR
)
1313 info
->input_signal_events
.dsr_up
++;
1315 info
->input_signal_events
.dsr_down
++;
1317 if (status
& MISCSTATUS_DCD_LATCHED
) {
1318 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1319 usc_DisablestatusIrqs(info
,SICR_DCD
);
1321 if (status
& MISCSTATUS_DCD
) {
1322 info
->input_signal_events
.dcd_up
++;
1324 info
->input_signal_events
.dcd_down
++;
1325 #if SYNCLINK_GENERIC_HDLC
1326 if (info
->netcount
) {
1327 if (status
& MISCSTATUS_DCD
)
1328 netif_carrier_on(info
->netdev
);
1330 netif_carrier_off(info
->netdev
);
1334 if (status
& MISCSTATUS_CTS_LATCHED
)
1336 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1337 usc_DisablestatusIrqs(info
,SICR_CTS
);
1339 if ( status
& MISCSTATUS_CTS
)
1340 info
->input_signal_events
.cts_up
++;
1342 info
->input_signal_events
.cts_down
++;
1344 wake_up_interruptible(&info
->status_event_wait_q
);
1345 wake_up_interruptible(&info
->event_wait_q
);
1347 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
1348 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1349 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1350 printk("%s CD now %s...", info
->device_name
,
1351 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1352 if (status
& MISCSTATUS_DCD
)
1353 wake_up_interruptible(&info
->port
.open_wait
);
1355 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1356 printk("doing serial hangup...");
1358 tty_hangup(info
->port
.tty
);
1362 if (tty_port_cts_enabled(&info
->port
) &&
1363 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1364 if (info
->port
.tty
->hw_stopped
) {
1365 if (status
& MISCSTATUS_CTS
) {
1366 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1367 printk("CTS tx start...");
1369 info
->port
.tty
->hw_stopped
= 0;
1370 usc_start_transmitter(info
);
1371 info
->pending_bh
|= BH_TRANSMIT
;
1375 if (!(status
& MISCSTATUS_CTS
)) {
1376 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1377 printk("CTS tx stop...");
1379 info
->port
.tty
->hw_stopped
= 1;
1380 usc_stop_transmitter(info
);
1386 info
->pending_bh
|= BH_STATUS
;
1388 /* for diagnostics set IRQ flag */
1389 if ( status
& MISCSTATUS_TXC_LATCHED
){
1390 usc_OutReg( info
, SICR
,
1391 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1392 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1393 info
->irq_occurred
= true;
1396 } /* end of mgsl_isr_io_pin() */
1398 /* mgsl_isr_transmit_data()
1400 * Service a transmit data interrupt (async mode only).
1402 * Arguments: info pointer to device instance data
1403 * Return Value: None
1405 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1407 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1408 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1409 __FILE__
,__LINE__
,info
->xmit_cnt
);
1411 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1413 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1414 usc_stop_transmitter(info
);
1418 if ( info
->xmit_cnt
)
1419 usc_load_txfifo( info
);
1421 info
->tx_active
= false;
1423 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1424 info
->pending_bh
|= BH_TRANSMIT
;
1426 } /* end of mgsl_isr_transmit_data() */
1428 /* mgsl_isr_receive_data()
1430 * Service a receive data interrupt. This occurs
1431 * when operating in asynchronous interrupt transfer mode.
1432 * The receive data FIFO is flushed to the receive data buffers.
1434 * Arguments: info pointer to device instance data
1435 * Return Value: None
1437 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1442 unsigned char DataByte
;
1443 struct tty_struct
*tty
= info
->port
.tty
;
1444 struct mgsl_icount
*icount
= &info
->icount
;
1446 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1447 printk("%s(%d):mgsl_isr_receive_data\n",
1450 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1452 /* select FIFO status for RICR readback */
1453 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1455 /* clear the Wordstatus bit so that status readback */
1456 /* only reflects the status of this byte */
1457 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1459 /* flush the receive FIFO */
1461 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1464 /* read one byte from RxFIFO */
1465 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1466 info
->io_base
+ CCAR
);
1467 DataByte
= inb( info
->io_base
+ CCAR
);
1469 /* get the status of the received byte */
1470 status
= usc_InReg(info
, RCSR
);
1471 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1472 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1473 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1478 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1479 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1480 printk("rxerr=%04X\n",status
);
1481 /* update error statistics */
1482 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1483 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1485 } else if (status
& RXSTATUS_PARITY_ERROR
)
1487 else if (status
& RXSTATUS_FRAMING_ERROR
)
1489 else if (status
& RXSTATUS_OVERRUN
) {
1490 /* must issue purge fifo cmd before */
1491 /* 16C32 accepts more receive chars */
1492 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1496 /* discard char if tty control flags say so */
1497 if (status
& info
->ignore_status_mask
)
1500 status
&= info
->read_status_mask
;
1502 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1504 if (info
->port
.flags
& ASYNC_SAK
)
1506 } else if (status
& RXSTATUS_PARITY_ERROR
)
1508 else if (status
& RXSTATUS_FRAMING_ERROR
)
1510 } /* end of if (error) */
1511 tty_insert_flip_char(tty
, DataByte
, flag
);
1512 if (status
& RXSTATUS_OVERRUN
) {
1513 /* Overrun is special, since it's
1514 * reported immediately, and doesn't
1515 * affect the current character
1517 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1521 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1522 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1523 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1524 icount
->parity
,icount
->frame
,icount
->overrun
);
1528 tty_flip_buffer_push(tty
);
1533 * Service a miscellaneous interrupt source.
1535 * Arguments: info pointer to device extension (instance data)
1536 * Return Value: None
1538 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1540 u16 status
= usc_InReg( info
, MISR
);
1542 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1543 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1544 __FILE__
,__LINE__
,status
);
1546 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1547 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1549 /* turn off receiver and rx DMA */
1550 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1551 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1552 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1553 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1554 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1556 /* schedule BH handler to restart receiver */
1557 info
->pending_bh
|= BH_RECEIVE
;
1558 info
->rx_rcc_underrun
= true;
1561 usc_ClearIrqPendingBits( info
, MISC
);
1562 usc_UnlatchMiscstatusBits( info
, status
);
1564 } /* end of mgsl_isr_misc() */
1568 * Services undefined interrupt vectors from the
1569 * USC. (hence this function SHOULD never be called)
1571 * Arguments: info pointer to device extension (instance data)
1572 * Return Value: None
1574 static void mgsl_isr_null( struct mgsl_struct
*info
)
1577 } /* end of mgsl_isr_null() */
1579 /* mgsl_isr_receive_dma()
1581 * Service a receive DMA channel interrupt.
1582 * For this driver there are two sources of receive DMA interrupts
1583 * as identified in the Receive DMA mode Register (RDMR):
1585 * BIT3 EOA/EOL End of List, all receive buffers in receive
1586 * buffer list have been filled (no more free buffers
1587 * available). The DMA controller has shut down.
1589 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1590 * DMA buffer is terminated in response to completion
1591 * of a good frame or a frame with errors. The status
1592 * of the frame is stored in the buffer entry in the
1593 * list of receive buffer entries.
1595 * Arguments: info pointer to device instance data
1596 * Return Value: None
1598 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1602 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1603 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1605 /* Read the receive DMA status to identify interrupt type. */
1606 /* This also clears the status bits. */
1607 status
= usc_InDmaReg( info
, RDMR
);
1609 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1610 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1611 __FILE__
,__LINE__
,info
->device_name
,status
);
1613 info
->pending_bh
|= BH_RECEIVE
;
1615 if ( status
& BIT3
) {
1616 info
->rx_overflow
= true;
1617 info
->icount
.buf_overrun
++;
1620 } /* end of mgsl_isr_receive_dma() */
1622 /* mgsl_isr_transmit_dma()
1624 * This function services a transmit DMA channel interrupt.
1626 * For this driver there is one source of transmit DMA interrupts
1627 * as identified in the Transmit DMA Mode Register (TDMR):
1629 * BIT2 EOB End of Buffer. This interrupt occurs when a
1630 * transmit DMA buffer has been emptied.
1632 * The driver maintains enough transmit DMA buffers to hold at least
1633 * one max frame size transmit frame. When operating in a buffered
1634 * transmit mode, there may be enough transmit DMA buffers to hold at
1635 * least two or more max frame size frames. On an EOB condition,
1636 * determine if there are any queued transmit buffers and copy into
1637 * transmit DMA buffers if we have room.
1639 * Arguments: info pointer to device instance data
1640 * Return Value: None
1642 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1646 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1647 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1649 /* Read the transmit DMA status to identify interrupt type. */
1650 /* This also clears the status bits. */
1652 status
= usc_InDmaReg( info
, TDMR
);
1654 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1655 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1656 __FILE__
,__LINE__
,info
->device_name
,status
);
1658 if ( status
& BIT2
) {
1659 --info
->tx_dma_buffers_used
;
1661 /* if there are transmit frames queued,
1662 * try to load the next one
1664 if ( load_next_tx_holding_buffer(info
) ) {
1665 /* if call returns non-zero value, we have
1666 * at least one free tx holding buffer
1668 info
->pending_bh
|= BH_TRANSMIT
;
1672 } /* end of mgsl_isr_transmit_dma() */
1676 * Interrupt service routine entry point.
1680 * irq interrupt number that caused interrupt
1681 * dev_id device ID supplied during interrupt registration
1683 * Return Value: None
1685 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1687 struct mgsl_struct
*info
= dev_id
;
1691 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1692 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1693 __FILE__
, __LINE__
, info
->irq_level
);
1695 spin_lock(&info
->irq_spinlock
);
1698 /* Read the interrupt vectors from hardware. */
1699 UscVector
= usc_InReg(info
, IVR
) >> 9;
1700 DmaVector
= usc_InDmaReg(info
, DIVR
);
1702 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1703 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1704 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1706 if ( !UscVector
&& !DmaVector
)
1709 /* Dispatch interrupt vector */
1711 (*UscIsrTable
[UscVector
])(info
);
1712 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1713 mgsl_isr_transmit_dma(info
);
1715 mgsl_isr_receive_dma(info
);
1717 if ( info
->isr_overflow
) {
1718 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1719 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1720 usc_DisableMasterIrqBit(info
);
1721 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1726 /* Request bottom half processing if there's something
1727 * for it to do and the bh is not already running
1730 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1731 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1732 printk("%s(%d):%s queueing bh task.\n",
1733 __FILE__
,__LINE__
,info
->device_name
);
1734 schedule_work(&info
->task
);
1735 info
->bh_requested
= true;
1738 spin_unlock(&info
->irq_spinlock
);
1740 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1741 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1742 __FILE__
, __LINE__
, info
->irq_level
);
1745 } /* end of mgsl_interrupt() */
1749 * Initialize and start device.
1751 * Arguments: info pointer to device instance data
1752 * Return Value: 0 if success, otherwise error code
1754 static int startup(struct mgsl_struct
* info
)
1758 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1759 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1761 if (info
->port
.flags
& ASYNC_INITIALIZED
)
1764 if (!info
->xmit_buf
) {
1765 /* allocate a page of memory for a transmit buffer */
1766 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1767 if (!info
->xmit_buf
) {
1768 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1769 __FILE__
,__LINE__
,info
->device_name
);
1774 info
->pending_bh
= 0;
1776 memset(&info
->icount
, 0, sizeof(info
->icount
));
1778 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1780 /* Allocate and claim adapter resources */
1781 retval
= mgsl_claim_resources(info
);
1783 /* perform existence check and diagnostics */
1785 retval
= mgsl_adapter_test(info
);
1788 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1789 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1790 mgsl_release_resources(info
);
1794 /* program hardware for current parameters */
1795 mgsl_change_params(info
);
1798 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1800 info
->port
.flags
|= ASYNC_INITIALIZED
;
1804 } /* end of startup() */
1808 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1810 * Arguments: info pointer to device instance data
1811 * Return Value: None
1813 static void shutdown(struct mgsl_struct
* info
)
1815 unsigned long flags
;
1817 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1820 if (debug_level
>= DEBUG_LEVEL_INFO
)
1821 printk("%s(%d):mgsl_shutdown(%s)\n",
1822 __FILE__
,__LINE__
, info
->device_name
);
1824 /* clear status wait queue because status changes */
1825 /* can't happen after shutting down the hardware */
1826 wake_up_interruptible(&info
->status_event_wait_q
);
1827 wake_up_interruptible(&info
->event_wait_q
);
1829 del_timer_sync(&info
->tx_timer
);
1831 if (info
->xmit_buf
) {
1832 free_page((unsigned long) info
->xmit_buf
);
1833 info
->xmit_buf
= NULL
;
1836 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1837 usc_DisableMasterIrqBit(info
);
1838 usc_stop_receiver(info
);
1839 usc_stop_transmitter(info
);
1840 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1841 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1842 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1844 /* Disable DMAEN (Port 7, Bit 14) */
1845 /* This disconnects the DMA request signal from the ISA bus */
1846 /* on the ISA adapter. This has no effect for the PCI adapter */
1847 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1849 /* Disable INTEN (Port 6, Bit12) */
1850 /* This disconnects the IRQ request signal to the ISA bus */
1851 /* on the ISA adapter. This has no effect for the PCI adapter */
1852 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1854 if (!info
->port
.tty
|| info
->port
.tty
->termios
.c_cflag
& HUPCL
) {
1855 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1856 usc_set_serial_signals(info
);
1859 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1861 mgsl_release_resources(info
);
1864 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1866 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
1868 } /* end of shutdown() */
1870 static void mgsl_program_hw(struct mgsl_struct
*info
)
1872 unsigned long flags
;
1874 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1876 usc_stop_receiver(info
);
1877 usc_stop_transmitter(info
);
1878 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1880 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1881 info
->params
.mode
== MGSL_MODE_RAW
||
1883 usc_set_sync_mode(info
);
1885 usc_set_async_mode(info
);
1887 usc_set_serial_signals(info
);
1889 info
->dcd_chkcount
= 0;
1890 info
->cts_chkcount
= 0;
1891 info
->ri_chkcount
= 0;
1892 info
->dsr_chkcount
= 0;
1894 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1895 usc_EnableInterrupts(info
, IO_PIN
);
1896 usc_get_serial_signals(info
);
1898 if (info
->netcount
|| info
->port
.tty
->termios
.c_cflag
& CREAD
)
1899 usc_start_receiver(info
);
1901 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1904 /* Reconfigure adapter based on new parameters
1906 static void mgsl_change_params(struct mgsl_struct
*info
)
1911 if (!info
->port
.tty
)
1914 if (debug_level
>= DEBUG_LEVEL_INFO
)
1915 printk("%s(%d):mgsl_change_params(%s)\n",
1916 __FILE__
,__LINE__
, info
->device_name
);
1918 cflag
= info
->port
.tty
->termios
.c_cflag
;
1920 /* if B0 rate (hangup) specified then negate DTR and RTS */
1921 /* otherwise assert DTR and RTS */
1923 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1925 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1927 /* byte size and parity */
1929 switch (cflag
& CSIZE
) {
1930 case CS5
: info
->params
.data_bits
= 5; break;
1931 case CS6
: info
->params
.data_bits
= 6; break;
1932 case CS7
: info
->params
.data_bits
= 7; break;
1933 case CS8
: info
->params
.data_bits
= 8; break;
1934 /* Never happens, but GCC is too dumb to figure it out */
1935 default: info
->params
.data_bits
= 7; break;
1939 info
->params
.stop_bits
= 2;
1941 info
->params
.stop_bits
= 1;
1943 info
->params
.parity
= ASYNC_PARITY_NONE
;
1944 if (cflag
& PARENB
) {
1946 info
->params
.parity
= ASYNC_PARITY_ODD
;
1948 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1951 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1955 /* calculate number of jiffies to transmit a full
1956 * FIFO (32 bytes) at specified data rate
1958 bits_per_char
= info
->params
.data_bits
+
1959 info
->params
.stop_bits
+ 1;
1961 /* if port data rate is set to 460800 or less then
1962 * allow tty settings to override, otherwise keep the
1963 * current data rate.
1965 if (info
->params
.data_rate
<= 460800)
1966 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1968 if ( info
->params
.data_rate
) {
1969 info
->timeout
= (32*HZ
*bits_per_char
) /
1970 info
->params
.data_rate
;
1972 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1974 if (cflag
& CRTSCTS
)
1975 info
->port
.flags
|= ASYNC_CTS_FLOW
;
1977 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
1980 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
1982 info
->port
.flags
|= ASYNC_CHECK_CD
;
1984 /* process tty input control flags */
1986 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1987 if (I_INPCK(info
->port
.tty
))
1988 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1989 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1990 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1992 if (I_IGNPAR(info
->port
.tty
))
1993 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1994 if (I_IGNBRK(info
->port
.tty
)) {
1995 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1996 /* If ignoring parity and break indicators, ignore
1997 * overruns too. (For real raw support).
1999 if (I_IGNPAR(info
->port
.tty
))
2000 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2003 mgsl_program_hw(info
);
2005 } /* end of mgsl_change_params() */
2009 * Add a character to the transmit buffer.
2011 * Arguments: tty pointer to tty information structure
2012 * ch character to add to transmit buffer
2014 * Return Value: None
2016 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2018 struct mgsl_struct
*info
= tty
->driver_data
;
2019 unsigned long flags
;
2022 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2023 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2024 __FILE__
, __LINE__
, ch
, info
->device_name
);
2027 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2030 if (!info
->xmit_buf
)
2033 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2035 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2036 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2037 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2038 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2043 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2046 } /* end of mgsl_put_char() */
2048 /* mgsl_flush_chars()
2050 * Enable transmitter so remaining characters in the
2051 * transmit buffer are sent.
2053 * Arguments: tty pointer to tty information structure
2054 * Return Value: None
2056 static void mgsl_flush_chars(struct tty_struct
*tty
)
2058 struct mgsl_struct
*info
= tty
->driver_data
;
2059 unsigned long flags
;
2061 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2062 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2063 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2065 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2068 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2072 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2073 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2074 __FILE__
,__LINE__
,info
->device_name
);
2076 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2078 if (!info
->tx_active
) {
2079 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2080 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2081 /* operating in synchronous (frame oriented) mode */
2082 /* copy data from circular xmit_buf to */
2083 /* transmit DMA buffer. */
2084 mgsl_load_tx_dma_buffer(info
,
2085 info
->xmit_buf
,info
->xmit_cnt
);
2087 usc_start_transmitter(info
);
2090 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2092 } /* end of mgsl_flush_chars() */
2096 * Send a block of data
2100 * tty pointer to tty information structure
2101 * buf pointer to buffer containing send data
2102 * count size of send data in bytes
2104 * Return Value: number of characters written
2106 static int mgsl_write(struct tty_struct
* tty
,
2107 const unsigned char *buf
, int count
)
2110 struct mgsl_struct
*info
= tty
->driver_data
;
2111 unsigned long flags
;
2113 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2114 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2115 __FILE__
,__LINE__
,info
->device_name
,count
);
2117 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2120 if (!info
->xmit_buf
)
2123 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2124 info
->params
.mode
== MGSL_MODE_RAW
) {
2125 /* operating in synchronous (frame oriented) mode */
2126 if (info
->tx_active
) {
2128 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2132 /* transmitter is actively sending data -
2133 * if we have multiple transmit dma and
2134 * holding buffers, attempt to queue this
2135 * frame for transmission at a later time.
2137 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2138 /* no tx holding buffers available */
2143 /* queue transmit frame request */
2145 save_tx_buffer_request(info
,buf
,count
);
2147 /* if we have sufficient tx dma buffers,
2148 * load the next buffered tx request
2150 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2151 load_next_tx_holding_buffer(info
);
2152 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2156 /* if operating in HDLC LoopMode and the adapter */
2157 /* has yet to be inserted into the loop, we can't */
2160 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2161 !usc_loopmode_active(info
) )
2167 if ( info
->xmit_cnt
) {
2168 /* Send accumulated from send_char() calls */
2169 /* as frame and wait before accepting more data. */
2172 /* copy data from circular xmit_buf to */
2173 /* transmit DMA buffer. */
2174 mgsl_load_tx_dma_buffer(info
,
2175 info
->xmit_buf
,info
->xmit_cnt
);
2176 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2177 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2178 __FILE__
,__LINE__
,info
->device_name
);
2180 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2181 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2182 __FILE__
,__LINE__
,info
->device_name
);
2184 info
->xmit_cnt
= count
;
2185 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2189 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2190 c
= min_t(int, count
,
2191 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2192 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2194 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2197 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2198 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2199 (SERIAL_XMIT_SIZE
-1));
2200 info
->xmit_cnt
+= c
;
2201 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2208 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2209 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2210 if (!info
->tx_active
)
2211 usc_start_transmitter(info
);
2212 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2215 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2216 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2217 __FILE__
,__LINE__
,info
->device_name
,ret
);
2221 } /* end of mgsl_write() */
2223 /* mgsl_write_room()
2225 * Return the count of free bytes in transmit buffer
2227 * Arguments: tty pointer to tty info structure
2228 * Return Value: None
2230 static int mgsl_write_room(struct tty_struct
*tty
)
2232 struct mgsl_struct
*info
= tty
->driver_data
;
2235 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2237 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2241 if (debug_level
>= DEBUG_LEVEL_INFO
)
2242 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2243 __FILE__
,__LINE__
, info
->device_name
,ret
);
2245 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2246 info
->params
.mode
== MGSL_MODE_RAW
) {
2247 /* operating in synchronous (frame oriented) mode */
2248 if ( info
->tx_active
)
2251 return HDLC_MAX_FRAME_SIZE
;
2256 } /* end of mgsl_write_room() */
2258 /* mgsl_chars_in_buffer()
2260 * Return the count of bytes in transmit buffer
2262 * Arguments: tty pointer to tty info structure
2263 * Return Value: None
2265 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2267 struct mgsl_struct
*info
= tty
->driver_data
;
2269 if (debug_level
>= DEBUG_LEVEL_INFO
)
2270 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2271 __FILE__
,__LINE__
, info
->device_name
);
2273 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2276 if (debug_level
>= DEBUG_LEVEL_INFO
)
2277 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2278 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2280 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2281 info
->params
.mode
== MGSL_MODE_RAW
) {
2282 /* operating in synchronous (frame oriented) mode */
2283 if ( info
->tx_active
)
2284 return info
->max_frame_size
;
2289 return info
->xmit_cnt
;
2290 } /* end of mgsl_chars_in_buffer() */
2292 /* mgsl_flush_buffer()
2294 * Discard all data in the send buffer
2296 * Arguments: tty pointer to tty info structure
2297 * Return Value: None
2299 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2301 struct mgsl_struct
*info
= tty
->driver_data
;
2302 unsigned long flags
;
2304 if (debug_level
>= DEBUG_LEVEL_INFO
)
2305 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2306 __FILE__
,__LINE__
, info
->device_name
);
2308 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2311 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2312 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2313 del_timer(&info
->tx_timer
);
2314 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2319 /* mgsl_send_xchar()
2321 * Send a high-priority XON/XOFF character
2323 * Arguments: tty pointer to tty info structure
2324 * ch character to send
2325 * Return Value: None
2327 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2329 struct mgsl_struct
*info
= tty
->driver_data
;
2330 unsigned long flags
;
2332 if (debug_level
>= DEBUG_LEVEL_INFO
)
2333 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2334 __FILE__
,__LINE__
, info
->device_name
, ch
);
2336 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2341 /* Make sure transmit interrupts are on */
2342 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2343 if (!info
->tx_enabled
)
2344 usc_start_transmitter(info
);
2345 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2347 } /* end of mgsl_send_xchar() */
2351 * Signal remote device to throttle send data (our receive data)
2353 * Arguments: tty pointer to tty info structure
2354 * Return Value: None
2356 static void mgsl_throttle(struct tty_struct
* tty
)
2358 struct mgsl_struct
*info
= tty
->driver_data
;
2359 unsigned long flags
;
2361 if (debug_level
>= DEBUG_LEVEL_INFO
)
2362 printk("%s(%d):mgsl_throttle(%s) entry\n",
2363 __FILE__
,__LINE__
, info
->device_name
);
2365 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2369 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2371 if (tty
->termios
.c_cflag
& CRTSCTS
) {
2372 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2373 info
->serial_signals
&= ~SerialSignal_RTS
;
2374 usc_set_serial_signals(info
);
2375 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2377 } /* end of mgsl_throttle() */
2379 /* mgsl_unthrottle()
2381 * Signal remote device to stop throttling send data (our receive data)
2383 * Arguments: tty pointer to tty info structure
2384 * Return Value: None
2386 static void mgsl_unthrottle(struct tty_struct
* tty
)
2388 struct mgsl_struct
*info
= tty
->driver_data
;
2389 unsigned long flags
;
2391 if (debug_level
>= DEBUG_LEVEL_INFO
)
2392 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2393 __FILE__
,__LINE__
, info
->device_name
);
2395 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2402 mgsl_send_xchar(tty
, START_CHAR(tty
));
2405 if (tty
->termios
.c_cflag
& CRTSCTS
) {
2406 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2407 info
->serial_signals
|= SerialSignal_RTS
;
2408 usc_set_serial_signals(info
);
2409 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2412 } /* end of mgsl_unthrottle() */
2416 * get the current serial parameters information
2418 * Arguments: info pointer to device instance data
2419 * user_icount pointer to buffer to hold returned stats
2421 * Return Value: 0 if success, otherwise error code
2423 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2427 if (debug_level
>= DEBUG_LEVEL_INFO
)
2428 printk("%s(%d):mgsl_get_params(%s)\n",
2429 __FILE__
,__LINE__
, info
->device_name
);
2432 memset(&info
->icount
, 0, sizeof(info
->icount
));
2434 mutex_lock(&info
->port
.mutex
);
2435 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2436 mutex_unlock(&info
->port
.mutex
);
2443 } /* end of mgsl_get_stats() */
2445 /* mgsl_get_params()
2447 * get the current serial parameters information
2449 * Arguments: info pointer to device instance data
2450 * user_params pointer to buffer to hold returned params
2452 * Return Value: 0 if success, otherwise error code
2454 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2457 if (debug_level
>= DEBUG_LEVEL_INFO
)
2458 printk("%s(%d):mgsl_get_params(%s)\n",
2459 __FILE__
,__LINE__
, info
->device_name
);
2461 mutex_lock(&info
->port
.mutex
);
2462 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2463 mutex_unlock(&info
->port
.mutex
);
2465 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2466 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2467 __FILE__
,__LINE__
,info
->device_name
);
2473 } /* end of mgsl_get_params() */
2475 /* mgsl_set_params()
2477 * set the serial parameters
2481 * info pointer to device instance data
2482 * new_params user buffer containing new serial params
2484 * Return Value: 0 if success, otherwise error code
2486 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2488 unsigned long flags
;
2489 MGSL_PARAMS tmp_params
;
2492 if (debug_level
>= DEBUG_LEVEL_INFO
)
2493 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2494 info
->device_name
);
2495 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2497 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2498 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2499 __FILE__
,__LINE__
,info
->device_name
);
2503 mutex_lock(&info
->port
.mutex
);
2504 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2505 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2506 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2508 mgsl_change_params(info
);
2509 mutex_unlock(&info
->port
.mutex
);
2513 } /* end of mgsl_set_params() */
2515 /* mgsl_get_txidle()
2517 * get the current transmit idle mode
2519 * Arguments: info pointer to device instance data
2520 * idle_mode pointer to buffer to hold returned idle mode
2522 * Return Value: 0 if success, otherwise error code
2524 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2528 if (debug_level
>= DEBUG_LEVEL_INFO
)
2529 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2530 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2532 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2534 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2535 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2536 __FILE__
,__LINE__
,info
->device_name
);
2542 } /* end of mgsl_get_txidle() */
2544 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2546 * Arguments: info pointer to device instance data
2547 * idle_mode new idle mode
2549 * Return Value: 0 if success, otherwise error code
2551 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2553 unsigned long flags
;
2555 if (debug_level
>= DEBUG_LEVEL_INFO
)
2556 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2557 info
->device_name
, idle_mode
);
2559 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2560 info
->idle_mode
= idle_mode
;
2561 usc_set_txidle( info
);
2562 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2565 } /* end of mgsl_set_txidle() */
2569 * enable or disable the transmitter
2573 * info pointer to device instance data
2574 * enable 1 = enable, 0 = disable
2576 * Return Value: 0 if success, otherwise error code
2578 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2580 unsigned long flags
;
2582 if (debug_level
>= DEBUG_LEVEL_INFO
)
2583 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2584 info
->device_name
, enable
);
2586 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2588 if ( !info
->tx_enabled
) {
2590 usc_start_transmitter(info
);
2591 /*--------------------------------------------------
2592 * if HDLC/SDLC Loop mode, attempt to insert the
2593 * station in the 'loop' by setting CMR:13. Upon
2594 * receipt of the next GoAhead (RxAbort) sequence,
2595 * the OnLoop indicator (CCSR:7) should go active
2596 * to indicate that we are on the loop
2597 *--------------------------------------------------*/
2598 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2599 usc_loopmode_insert_request( info
);
2602 if ( info
->tx_enabled
)
2603 usc_stop_transmitter(info
);
2605 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2608 } /* end of mgsl_txenable() */
2610 /* mgsl_txabort() abort send HDLC frame
2612 * Arguments: info pointer to device instance data
2613 * Return Value: 0 if success, otherwise error code
2615 static int mgsl_txabort(struct mgsl_struct
* info
)
2617 unsigned long flags
;
2619 if (debug_level
>= DEBUG_LEVEL_INFO
)
2620 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2623 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2624 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2626 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2627 usc_loopmode_cancel_transmit( info
);
2629 usc_TCmd(info
,TCmd_SendAbort
);
2631 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2634 } /* end of mgsl_txabort() */
2636 /* mgsl_rxenable() enable or disable the receiver
2638 * Arguments: info pointer to device instance data
2639 * enable 1 = enable, 0 = disable
2640 * Return Value: 0 if success, otherwise error code
2642 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2644 unsigned long flags
;
2646 if (debug_level
>= DEBUG_LEVEL_INFO
)
2647 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2648 info
->device_name
, enable
);
2650 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2652 if ( !info
->rx_enabled
)
2653 usc_start_receiver(info
);
2655 if ( info
->rx_enabled
)
2656 usc_stop_receiver(info
);
2658 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2661 } /* end of mgsl_rxenable() */
2663 /* mgsl_wait_event() wait for specified event to occur
2665 * Arguments: info pointer to device instance data
2666 * mask pointer to bitmask of events to wait for
2667 * Return Value: 0 if successful and bit mask updated with
2668 * of events triggerred,
2669 * otherwise error code
2671 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2673 unsigned long flags
;
2676 struct mgsl_icount cprev
, cnow
;
2679 struct _input_signal_events oldsigs
, newsigs
;
2680 DECLARE_WAITQUEUE(wait
, current
);
2682 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2687 if (debug_level
>= DEBUG_LEVEL_INFO
)
2688 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2689 info
->device_name
, mask
);
2691 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2693 /* return immediately if state matches requested events */
2694 usc_get_serial_signals(info
);
2695 s
= info
->serial_signals
;
2697 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2698 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2699 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2700 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2702 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2706 /* save current irq counts */
2707 cprev
= info
->icount
;
2708 oldsigs
= info
->input_signal_events
;
2710 /* enable hunt and idle irqs if needed */
2711 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2712 u16 oldreg
= usc_InReg(info
,RICR
);
2713 u16 newreg
= oldreg
+
2714 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2715 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2716 if (oldreg
!= newreg
)
2717 usc_OutReg(info
, RICR
, newreg
);
2720 set_current_state(TASK_INTERRUPTIBLE
);
2721 add_wait_queue(&info
->event_wait_q
, &wait
);
2723 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2728 if (signal_pending(current
)) {
2733 /* get current irq counts */
2734 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2735 cnow
= info
->icount
;
2736 newsigs
= info
->input_signal_events
;
2737 set_current_state(TASK_INTERRUPTIBLE
);
2738 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2740 /* if no change, wait aborted for some reason */
2741 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2742 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2743 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2744 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2745 newsigs
.cts_up
== oldsigs
.cts_up
&&
2746 newsigs
.cts_down
== oldsigs
.cts_down
&&
2747 newsigs
.ri_up
== oldsigs
.ri_up
&&
2748 newsigs
.ri_down
== oldsigs
.ri_down
&&
2749 cnow
.exithunt
== cprev
.exithunt
&&
2750 cnow
.rxidle
== cprev
.rxidle
) {
2756 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2757 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2758 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2759 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2760 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2761 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2762 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2763 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2764 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2765 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2773 remove_wait_queue(&info
->event_wait_q
, &wait
);
2774 set_current_state(TASK_RUNNING
);
2776 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2777 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2778 if (!waitqueue_active(&info
->event_wait_q
)) {
2779 /* disable enable exit hunt mode/idle rcvd IRQs */
2780 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2781 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2783 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2787 PUT_USER(rc
, events
, mask_ptr
);
2791 } /* end of mgsl_wait_event() */
2793 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2795 unsigned long flags
;
2797 struct mgsl_icount cprev
, cnow
;
2798 DECLARE_WAITQUEUE(wait
, current
);
2800 /* save current irq counts */
2801 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2802 cprev
= info
->icount
;
2803 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2804 set_current_state(TASK_INTERRUPTIBLE
);
2805 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2809 if (signal_pending(current
)) {
2814 /* get new irq counts */
2815 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2816 cnow
= info
->icount
;
2817 set_current_state(TASK_INTERRUPTIBLE
);
2818 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2820 /* if no change, wait aborted for some reason */
2821 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2822 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2827 /* check for change in caller specified modem input */
2828 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2829 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2830 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2831 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2838 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2839 set_current_state(TASK_RUNNING
);
2843 /* return the state of the serial control and status signals
2845 static int tiocmget(struct tty_struct
*tty
)
2847 struct mgsl_struct
*info
= tty
->driver_data
;
2848 unsigned int result
;
2849 unsigned long flags
;
2851 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2852 usc_get_serial_signals(info
);
2853 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2855 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2856 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2857 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2858 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2859 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2860 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2862 if (debug_level
>= DEBUG_LEVEL_INFO
)
2863 printk("%s(%d):%s tiocmget() value=%08X\n",
2864 __FILE__
,__LINE__
, info
->device_name
, result
);
2868 /* set modem control signals (DTR/RTS)
2870 static int tiocmset(struct tty_struct
*tty
,
2871 unsigned int set
, unsigned int clear
)
2873 struct mgsl_struct
*info
= tty
->driver_data
;
2874 unsigned long flags
;
2876 if (debug_level
>= DEBUG_LEVEL_INFO
)
2877 printk("%s(%d):%s tiocmset(%x,%x)\n",
2878 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2880 if (set
& TIOCM_RTS
)
2881 info
->serial_signals
|= SerialSignal_RTS
;
2882 if (set
& TIOCM_DTR
)
2883 info
->serial_signals
|= SerialSignal_DTR
;
2884 if (clear
& TIOCM_RTS
)
2885 info
->serial_signals
&= ~SerialSignal_RTS
;
2886 if (clear
& TIOCM_DTR
)
2887 info
->serial_signals
&= ~SerialSignal_DTR
;
2889 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2890 usc_set_serial_signals(info
);
2891 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2896 /* mgsl_break() Set or clear transmit break condition
2898 * Arguments: tty pointer to tty instance data
2899 * break_state -1=set break condition, 0=clear
2900 * Return Value: error code
2902 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2904 struct mgsl_struct
* info
= tty
->driver_data
;
2905 unsigned long flags
;
2907 if (debug_level
>= DEBUG_LEVEL_INFO
)
2908 printk("%s(%d):mgsl_break(%s,%d)\n",
2909 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2911 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2914 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2915 if (break_state
== -1)
2916 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2918 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2919 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2922 } /* end of mgsl_break() */
2925 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2926 * Return: write counters to the user passed counter struct
2927 * NB: both 1->0 and 0->1 transitions are counted except for
2928 * RI where only 0->1 is counted.
2930 static int msgl_get_icount(struct tty_struct
*tty
,
2931 struct serial_icounter_struct
*icount
)
2934 struct mgsl_struct
* info
= tty
->driver_data
;
2935 struct mgsl_icount cnow
; /* kernel counter temps */
2936 unsigned long flags
;
2938 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2939 cnow
= info
->icount
;
2940 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2942 icount
->cts
= cnow
.cts
;
2943 icount
->dsr
= cnow
.dsr
;
2944 icount
->rng
= cnow
.rng
;
2945 icount
->dcd
= cnow
.dcd
;
2946 icount
->rx
= cnow
.rx
;
2947 icount
->tx
= cnow
.tx
;
2948 icount
->frame
= cnow
.frame
;
2949 icount
->overrun
= cnow
.overrun
;
2950 icount
->parity
= cnow
.parity
;
2951 icount
->brk
= cnow
.brk
;
2952 icount
->buf_overrun
= cnow
.buf_overrun
;
2956 /* mgsl_ioctl() Service an IOCTL request
2960 * tty pointer to tty instance data
2961 * cmd IOCTL command code
2962 * arg command argument/context
2964 * Return Value: 0 if success, otherwise error code
2966 static int mgsl_ioctl(struct tty_struct
*tty
,
2967 unsigned int cmd
, unsigned long arg
)
2969 struct mgsl_struct
* info
= tty
->driver_data
;
2971 if (debug_level
>= DEBUG_LEVEL_INFO
)
2972 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2973 info
->device_name
, cmd
);
2975 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2978 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2979 (cmd
!= TIOCMIWAIT
)) {
2980 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2984 return mgsl_ioctl_common(info
, cmd
, arg
);
2987 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2989 void __user
*argp
= (void __user
*)arg
;
2992 case MGSL_IOCGPARAMS
:
2993 return mgsl_get_params(info
, argp
);
2994 case MGSL_IOCSPARAMS
:
2995 return mgsl_set_params(info
, argp
);
2996 case MGSL_IOCGTXIDLE
:
2997 return mgsl_get_txidle(info
, argp
);
2998 case MGSL_IOCSTXIDLE
:
2999 return mgsl_set_txidle(info
,(int)arg
);
3000 case MGSL_IOCTXENABLE
:
3001 return mgsl_txenable(info
,(int)arg
);
3002 case MGSL_IOCRXENABLE
:
3003 return mgsl_rxenable(info
,(int)arg
);
3004 case MGSL_IOCTXABORT
:
3005 return mgsl_txabort(info
);
3006 case MGSL_IOCGSTATS
:
3007 return mgsl_get_stats(info
, argp
);
3008 case MGSL_IOCWAITEVENT
:
3009 return mgsl_wait_event(info
, argp
);
3010 case MGSL_IOCLOOPTXDONE
:
3011 return mgsl_loopmode_send_done(info
);
3012 /* Wait for modem input (DCD,RI,DSR,CTS) change
3013 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3016 return modem_input_wait(info
,(int)arg
);
3019 return -ENOIOCTLCMD
;
3024 /* mgsl_set_termios()
3026 * Set new termios settings
3030 * tty pointer to tty structure
3031 * termios pointer to buffer to hold returned old termios
3033 * Return Value: None
3035 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3037 struct mgsl_struct
*info
= tty
->driver_data
;
3038 unsigned long flags
;
3040 if (debug_level
>= DEBUG_LEVEL_INFO
)
3041 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3042 tty
->driver
->name
);
3044 mgsl_change_params(info
);
3046 /* Handle transition to B0 status */
3047 if (old_termios
->c_cflag
& CBAUD
&&
3048 !(tty
->termios
.c_cflag
& CBAUD
)) {
3049 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3050 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3051 usc_set_serial_signals(info
);
3052 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3055 /* Handle transition away from B0 status */
3056 if (!(old_termios
->c_cflag
& CBAUD
) &&
3057 tty
->termios
.c_cflag
& CBAUD
) {
3058 info
->serial_signals
|= SerialSignal_DTR
;
3059 if (!(tty
->termios
.c_cflag
& CRTSCTS
) ||
3060 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3061 info
->serial_signals
|= SerialSignal_RTS
;
3063 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3064 usc_set_serial_signals(info
);
3065 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3068 /* Handle turning off CRTSCTS */
3069 if (old_termios
->c_cflag
& CRTSCTS
&&
3070 !(tty
->termios
.c_cflag
& CRTSCTS
)) {
3071 tty
->hw_stopped
= 0;
3075 } /* end of mgsl_set_termios() */
3079 * Called when port is closed. Wait for remaining data to be
3080 * sent. Disable port and free resources.
3084 * tty pointer to open tty structure
3085 * filp pointer to open file object
3087 * Return Value: None
3089 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3091 struct mgsl_struct
* info
= tty
->driver_data
;
3093 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3096 if (debug_level
>= DEBUG_LEVEL_INFO
)
3097 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3098 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3100 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
3103 mutex_lock(&info
->port
.mutex
);
3104 if (info
->port
.flags
& ASYNC_INITIALIZED
)
3105 mgsl_wait_until_sent(tty
, info
->timeout
);
3106 mgsl_flush_buffer(tty
);
3107 tty_ldisc_flush(tty
);
3109 mutex_unlock(&info
->port
.mutex
);
3111 tty_port_close_end(&info
->port
, tty
);
3112 info
->port
.tty
= NULL
;
3114 if (debug_level
>= DEBUG_LEVEL_INFO
)
3115 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3116 tty
->driver
->name
, info
->port
.count
);
3118 } /* end of mgsl_close() */
3120 /* mgsl_wait_until_sent()
3122 * Wait until the transmitter is empty.
3126 * tty pointer to tty info structure
3127 * timeout time to wait for send completion
3129 * Return Value: None
3131 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3133 struct mgsl_struct
* info
= tty
->driver_data
;
3134 unsigned long orig_jiffies
, char_time
;
3139 if (debug_level
>= DEBUG_LEVEL_INFO
)
3140 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3141 __FILE__
,__LINE__
, info
->device_name
);
3143 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3146 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
3149 orig_jiffies
= jiffies
;
3151 /* Set check interval to 1/5 of estimated time to
3152 * send a character, and make it at least 1. The check
3153 * interval should also be less than the timeout.
3154 * Note: use tight timings here to satisfy the NIST-PCTS.
3157 if ( info
->params
.data_rate
) {
3158 char_time
= info
->timeout
/(32 * 5);
3165 char_time
= min_t(unsigned long, char_time
, timeout
);
3167 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3168 info
->params
.mode
== MGSL_MODE_RAW
) {
3169 while (info
->tx_active
) {
3170 msleep_interruptible(jiffies_to_msecs(char_time
));
3171 if (signal_pending(current
))
3173 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3177 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3179 msleep_interruptible(jiffies_to_msecs(char_time
));
3180 if (signal_pending(current
))
3182 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3188 if (debug_level
>= DEBUG_LEVEL_INFO
)
3189 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3190 __FILE__
,__LINE__
, info
->device_name
);
3192 } /* end of mgsl_wait_until_sent() */
3196 * Called by tty_hangup() when a hangup is signaled.
3197 * This is the same as to closing all open files for the port.
3199 * Arguments: tty pointer to associated tty object
3200 * Return Value: None
3202 static void mgsl_hangup(struct tty_struct
*tty
)
3204 struct mgsl_struct
* info
= tty
->driver_data
;
3206 if (debug_level
>= DEBUG_LEVEL_INFO
)
3207 printk("%s(%d):mgsl_hangup(%s)\n",
3208 __FILE__
,__LINE__
, info
->device_name
);
3210 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3213 mgsl_flush_buffer(tty
);
3216 info
->port
.count
= 0;
3217 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
3218 info
->port
.tty
= NULL
;
3220 wake_up_interruptible(&info
->port
.open_wait
);
3222 } /* end of mgsl_hangup() */
3227 * Return true if carrier is raised
3230 static int carrier_raised(struct tty_port
*port
)
3232 unsigned long flags
;
3233 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3235 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3236 usc_get_serial_signals(info
);
3237 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3238 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3241 static void dtr_rts(struct tty_port
*port
, int on
)
3243 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3244 unsigned long flags
;
3246 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3248 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3250 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3251 usc_set_serial_signals(info
);
3252 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3256 /* block_til_ready()
3258 * Block the current process until the specified port
3259 * is ready to be opened.
3263 * tty pointer to tty info structure
3264 * filp pointer to open file object
3265 * info pointer to device instance data
3267 * Return Value: 0 if success, otherwise error code
3269 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3270 struct mgsl_struct
*info
)
3272 DECLARE_WAITQUEUE(wait
, current
);
3274 bool do_clocal
= false;
3275 bool extra_count
= false;
3276 unsigned long flags
;
3278 struct tty_port
*port
= &info
->port
;
3280 if (debug_level
>= DEBUG_LEVEL_INFO
)
3281 printk("%s(%d):block_til_ready on %s\n",
3282 __FILE__
,__LINE__
, tty
->driver
->name
);
3284 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3285 /* nonblock mode is set or port is not enabled */
3286 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3290 if (tty
->termios
.c_cflag
& CLOCAL
)
3293 /* Wait for carrier detect and the line to become
3294 * free (i.e., not in use by the callout). While we are in
3295 * this loop, port->count is dropped by one, so that
3296 * mgsl_close() knows when to free things. We restore it upon
3297 * exit, either normal or abnormal.
3301 add_wait_queue(&port
->open_wait
, &wait
);
3303 if (debug_level
>= DEBUG_LEVEL_INFO
)
3304 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3305 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3307 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3308 if (!tty_hung_up_p(filp
)) {
3312 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3313 port
->blocked_open
++;
3316 if (tty
->termios
.c_cflag
& CBAUD
)
3317 tty_port_raise_dtr_rts(port
);
3319 set_current_state(TASK_INTERRUPTIBLE
);
3321 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3322 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3323 -EAGAIN
: -ERESTARTSYS
;
3327 dcd
= tty_port_carrier_raised(&info
->port
);
3329 if (!(port
->flags
& ASYNC_CLOSING
) && (do_clocal
|| dcd
))
3332 if (signal_pending(current
)) {
3333 retval
= -ERESTARTSYS
;
3337 if (debug_level
>= DEBUG_LEVEL_INFO
)
3338 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3339 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3346 set_current_state(TASK_RUNNING
);
3347 remove_wait_queue(&port
->open_wait
, &wait
);
3349 /* FIXME: Racy on hangup during close wait */
3352 port
->blocked_open
--;
3354 if (debug_level
>= DEBUG_LEVEL_INFO
)
3355 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3356 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3359 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3363 } /* end of block_til_ready() */
3365 static int mgsl_install(struct tty_driver
*driver
, struct tty_struct
*tty
)
3367 struct mgsl_struct
*info
;
3368 int line
= tty
->index
;
3370 /* verify range of specified line number */
3371 if (line
>= mgsl_device_count
) {
3372 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3373 __FILE__
, __LINE__
, line
);
3377 /* find the info structure for the specified line */
3378 info
= mgsl_device_list
;
3379 while (info
&& info
->line
!= line
)
3380 info
= info
->next_device
;
3381 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3383 tty
->driver_data
= info
;
3385 return tty_port_install(&info
->port
, driver
, tty
);
3390 * Called when a port is opened. Init and enable port.
3391 * Perform serial-specific initialization for the tty structure.
3393 * Arguments: tty pointer to tty info structure
3394 * filp associated file pointer
3396 * Return Value: 0 if success, otherwise error code
3398 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3400 struct mgsl_struct
*info
= tty
->driver_data
;
3401 unsigned long flags
;
3404 info
->port
.tty
= tty
;
3406 if (debug_level
>= DEBUG_LEVEL_INFO
)
3407 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3408 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3410 /* If port is closing, signal caller to try again */
3411 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
3412 if (info
->port
.flags
& ASYNC_CLOSING
)
3413 interruptible_sleep_on(&info
->port
.close_wait
);
3414 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
3415 -EAGAIN
: -ERESTARTSYS
);
3419 info
->port
.tty
->low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3421 spin_lock_irqsave(&info
->netlock
, flags
);
3422 if (info
->netcount
) {
3424 spin_unlock_irqrestore(&info
->netlock
, flags
);
3428 spin_unlock_irqrestore(&info
->netlock
, flags
);
3430 if (info
->port
.count
== 1) {
3431 /* 1st open on this device, init hardware */
3432 retval
= startup(info
);
3437 retval
= block_til_ready(tty
, filp
, info
);
3439 if (debug_level
>= DEBUG_LEVEL_INFO
)
3440 printk("%s(%d):block_til_ready(%s) returned %d\n",
3441 __FILE__
,__LINE__
, info
->device_name
, retval
);
3445 if (debug_level
>= DEBUG_LEVEL_INFO
)
3446 printk("%s(%d):mgsl_open(%s) success\n",
3447 __FILE__
,__LINE__
, info
->device_name
);
3452 if (tty
->count
== 1)
3453 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3454 if(info
->port
.count
)
3460 } /* end of mgsl_open() */
3463 * /proc fs routines....
3466 static inline void line_info(struct seq_file
*m
, struct mgsl_struct
*info
)
3469 unsigned long flags
;
3471 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3472 seq_printf(m
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3473 info
->device_name
, info
->io_base
, info
->irq_level
,
3474 info
->phys_memory_base
, info
->phys_lcr_base
);
3476 seq_printf(m
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3477 info
->device_name
, info
->io_base
,
3478 info
->irq_level
, info
->dma_level
);
3481 /* output current serial signal states */
3482 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3483 usc_get_serial_signals(info
);
3484 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3488 if (info
->serial_signals
& SerialSignal_RTS
)
3489 strcat(stat_buf
, "|RTS");
3490 if (info
->serial_signals
& SerialSignal_CTS
)
3491 strcat(stat_buf
, "|CTS");
3492 if (info
->serial_signals
& SerialSignal_DTR
)
3493 strcat(stat_buf
, "|DTR");
3494 if (info
->serial_signals
& SerialSignal_DSR
)
3495 strcat(stat_buf
, "|DSR");
3496 if (info
->serial_signals
& SerialSignal_DCD
)
3497 strcat(stat_buf
, "|CD");
3498 if (info
->serial_signals
& SerialSignal_RI
)
3499 strcat(stat_buf
, "|RI");
3501 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3502 info
->params
.mode
== MGSL_MODE_RAW
) {
3503 seq_printf(m
, " HDLC txok:%d rxok:%d",
3504 info
->icount
.txok
, info
->icount
.rxok
);
3505 if (info
->icount
.txunder
)
3506 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
3507 if (info
->icount
.txabort
)
3508 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
3509 if (info
->icount
.rxshort
)
3510 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
3511 if (info
->icount
.rxlong
)
3512 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
3513 if (info
->icount
.rxover
)
3514 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
3515 if (info
->icount
.rxcrc
)
3516 seq_printf(m
, " rxcrc:%d", info
->icount
.rxcrc
);
3518 seq_printf(m
, " ASYNC tx:%d rx:%d",
3519 info
->icount
.tx
, info
->icount
.rx
);
3520 if (info
->icount
.frame
)
3521 seq_printf(m
, " fe:%d", info
->icount
.frame
);
3522 if (info
->icount
.parity
)
3523 seq_printf(m
, " pe:%d", info
->icount
.parity
);
3524 if (info
->icount
.brk
)
3525 seq_printf(m
, " brk:%d", info
->icount
.brk
);
3526 if (info
->icount
.overrun
)
3527 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
3530 /* Append serial signal status to end */
3531 seq_printf(m
, " %s\n", stat_buf
+1);
3533 seq_printf(m
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3534 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3537 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3539 u16 Tcsr
= usc_InReg( info
, TCSR
);
3540 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3541 u16 Ticr
= usc_InReg( info
, TICR
);
3542 u16 Rscr
= usc_InReg( info
, RCSR
);
3543 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3544 u16 Ricr
= usc_InReg( info
, RICR
);
3545 u16 Icr
= usc_InReg( info
, ICR
);
3546 u16 Dccr
= usc_InReg( info
, DCCR
);
3547 u16 Tmr
= usc_InReg( info
, TMR
);
3548 u16 Tccr
= usc_InReg( info
, TCCR
);
3549 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3550 seq_printf(m
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3551 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3552 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3554 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3557 /* Called to print information about devices */
3558 static int mgsl_proc_show(struct seq_file
*m
, void *v
)
3560 struct mgsl_struct
*info
;
3562 seq_printf(m
, "synclink driver:%s\n", driver_version
);
3564 info
= mgsl_device_list
;
3567 info
= info
->next_device
;
3572 static int mgsl_proc_open(struct inode
*inode
, struct file
*file
)
3574 return single_open(file
, mgsl_proc_show
, NULL
);
3577 static const struct file_operations mgsl_proc_fops
= {
3578 .owner
= THIS_MODULE
,
3579 .open
= mgsl_proc_open
,
3581 .llseek
= seq_lseek
,
3582 .release
= single_release
,
3585 /* mgsl_allocate_dma_buffers()
3587 * Allocate and format DMA buffers (ISA adapter)
3588 * or format shared memory buffers (PCI adapter).
3590 * Arguments: info pointer to device instance data
3591 * Return Value: 0 if success, otherwise error
3593 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3595 unsigned short BuffersPerFrame
;
3597 info
->last_mem_alloc
= 0;
3599 /* Calculate the number of DMA buffers necessary to hold the */
3600 /* largest allowable frame size. Note: If the max frame size is */
3601 /* not an even multiple of the DMA buffer size then we need to */
3602 /* round the buffer count per frame up one. */
3604 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3605 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3608 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3610 * The PCI adapter has 256KBytes of shared memory to use.
3611 * This is 64 PAGE_SIZE buffers.
3613 * The first page is used for padding at this time so the
3614 * buffer list does not begin at offset 0 of the PCI
3615 * adapter's shared memory.
3617 * The 2nd page is used for the buffer list. A 4K buffer
3618 * list can hold 128 DMA_BUFFER structures at 32 bytes
3621 * This leaves 62 4K pages.
3623 * The next N pages are used for transmit frame(s). We
3624 * reserve enough 4K page blocks to hold the required
3625 * number of transmit dma buffers (num_tx_dma_buffers),
3626 * each of MaxFrameSize size.
3628 * Of the remaining pages (62-N), determine how many can
3629 * be used to receive full MaxFrameSize inbound frames
3631 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3632 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3634 /* Calculate the number of PAGE_SIZE buffers needed for */
3635 /* receive and transmit DMA buffers. */
3638 /* Calculate the number of DMA buffers necessary to */
3639 /* hold 7 max size receive frames and one max size transmit frame. */
3640 /* The receive buffer count is bumped by one so we avoid an */
3641 /* End of List condition if all receive buffers are used when */
3642 /* using linked list DMA buffers. */
3644 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3645 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3648 * limit total TxBuffers & RxBuffers to 62 4K total
3649 * (ala PCI Allocation)
3652 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3653 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3657 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3658 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3659 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3661 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3662 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3663 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3664 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3665 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3666 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3670 mgsl_reset_rx_dma_buffers( info
);
3671 mgsl_reset_tx_dma_buffers( info
);
3675 } /* end of mgsl_allocate_dma_buffers() */
3678 * mgsl_alloc_buffer_list_memory()
3680 * Allocate a common DMA buffer for use as the
3681 * receive and transmit buffer lists.
3683 * A buffer list is a set of buffer entries where each entry contains
3684 * a pointer to an actual buffer and a pointer to the next buffer entry
3685 * (plus some other info about the buffer).
3687 * The buffer entries for a list are built to form a circular list so
3688 * that when the entire list has been traversed you start back at the
3691 * This function allocates memory for just the buffer entries.
3692 * The links (pointer to next entry) are filled in with the physical
3693 * address of the next entry so the adapter can navigate the list
3694 * using bus master DMA. The pointers to the actual buffers are filled
3695 * out later when the actual buffers are allocated.
3697 * Arguments: info pointer to device instance data
3698 * Return Value: 0 if success, otherwise error
3700 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3704 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3705 /* PCI adapter uses shared memory. */
3706 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3707 info
->buffer_list_phys
= info
->last_mem_alloc
;
3708 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3710 /* ISA adapter uses system memory. */
3711 /* The buffer lists are allocated as a common buffer that both */
3712 /* the processor and adapter can access. This allows the driver to */
3713 /* inspect portions of the buffer while other portions are being */
3714 /* updated by the adapter using Bus Master DMA. */
3716 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3717 if (info
->buffer_list
== NULL
)
3719 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3722 /* We got the memory for the buffer entry lists. */
3723 /* Initialize the memory block to all zeros. */
3724 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3726 /* Save virtual address pointers to the receive and */
3727 /* transmit buffer lists. (Receive 1st). These pointers will */
3728 /* be used by the processor to access the lists. */
3729 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3730 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3731 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3734 * Build the links for the buffer entry lists such that
3735 * two circular lists are built. (Transmit and Receive).
3737 * Note: the links are physical addresses
3738 * which are read by the adapter to determine the next
3739 * buffer entry to use.
3742 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3743 /* calculate and store physical address of this buffer entry */
3744 info
->rx_buffer_list
[i
].phys_entry
=
3745 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3747 /* calculate and store physical address of */
3748 /* next entry in cirular list of entries */
3750 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3752 if ( i
< info
->rx_buffer_count
- 1 )
3753 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3756 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3757 /* calculate and store physical address of this buffer entry */
3758 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3759 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3761 /* calculate and store physical address of */
3762 /* next entry in cirular list of entries */
3764 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3765 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3767 if ( i
< info
->tx_buffer_count
- 1 )
3768 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3773 } /* end of mgsl_alloc_buffer_list_memory() */
3775 /* Free DMA buffers allocated for use as the
3776 * receive and transmit buffer lists.
3779 * The data transfer buffers associated with the buffer list
3780 * MUST be freed before freeing the buffer list itself because
3781 * the buffer list contains the information necessary to free
3782 * the individual buffers!
3784 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3786 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3787 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3789 info
->buffer_list
= NULL
;
3790 info
->rx_buffer_list
= NULL
;
3791 info
->tx_buffer_list
= NULL
;
3793 } /* end of mgsl_free_buffer_list_memory() */
3796 * mgsl_alloc_frame_memory()
3798 * Allocate the frame DMA buffers used by the specified buffer list.
3799 * Each DMA buffer will be one memory page in size. This is necessary
3800 * because memory can fragment enough that it may be impossible
3805 * info pointer to device instance data
3806 * BufferList pointer to list of buffer entries
3807 * Buffercount count of buffer entries in buffer list
3809 * Return Value: 0 if success, otherwise -ENOMEM
3811 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3816 /* Allocate page sized buffers for the receive buffer list */
3818 for ( i
= 0; i
< Buffercount
; i
++ ) {
3819 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3820 /* PCI adapter uses shared memory buffers. */
3821 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3822 phys_addr
= info
->last_mem_alloc
;
3823 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3825 /* ISA adapter uses system memory. */
3826 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3827 if (BufferList
[i
].virt_addr
== NULL
)
3829 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3831 BufferList
[i
].phys_addr
= phys_addr
;
3836 } /* end of mgsl_alloc_frame_memory() */
3839 * mgsl_free_frame_memory()
3841 * Free the buffers associated with
3842 * each buffer entry of a buffer list.
3846 * info pointer to device instance data
3847 * BufferList pointer to list of buffer entries
3848 * Buffercount count of buffer entries in buffer list
3850 * Return Value: None
3852 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3857 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3858 if ( BufferList
[i
].virt_addr
) {
3859 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3860 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3861 BufferList
[i
].virt_addr
= NULL
;
3866 } /* end of mgsl_free_frame_memory() */
3868 /* mgsl_free_dma_buffers()
3872 * Arguments: info pointer to device instance data
3873 * Return Value: None
3875 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3877 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3878 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3879 mgsl_free_buffer_list_memory( info
);
3881 } /* end of mgsl_free_dma_buffers() */
3885 * mgsl_alloc_intermediate_rxbuffer_memory()
3887 * Allocate a buffer large enough to hold max_frame_size. This buffer
3888 * is used to pass an assembled frame to the line discipline.
3892 * info pointer to device instance data
3894 * Return Value: 0 if success, otherwise -ENOMEM
3896 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3898 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3899 if ( info
->intermediate_rxbuffer
== NULL
)
3904 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3907 * mgsl_free_intermediate_rxbuffer_memory()
3912 * info pointer to device instance data
3914 * Return Value: None
3916 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3918 kfree(info
->intermediate_rxbuffer
);
3919 info
->intermediate_rxbuffer
= NULL
;
3921 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3924 * mgsl_alloc_intermediate_txbuffer_memory()
3926 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3927 * This buffer is used to load transmit frames into the adapter's dma transfer
3928 * buffers when there is sufficient space.
3932 * info pointer to device instance data
3934 * Return Value: 0 if success, otherwise -ENOMEM
3936 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3940 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3941 printk("%s %s(%d) allocating %d tx holding buffers\n",
3942 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3944 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3946 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3947 info
->tx_holding_buffers
[i
].buffer
=
3948 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3949 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3950 for (--i
; i
>= 0; i
--) {
3951 kfree(info
->tx_holding_buffers
[i
].buffer
);
3952 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3960 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3963 * mgsl_free_intermediate_txbuffer_memory()
3968 * info pointer to device instance data
3970 * Return Value: None
3972 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3976 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3977 kfree(info
->tx_holding_buffers
[i
].buffer
);
3978 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3981 info
->get_tx_holding_index
= 0;
3982 info
->put_tx_holding_index
= 0;
3983 info
->tx_holding_count
= 0;
3985 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3989 * load_next_tx_holding_buffer()
3991 * attempts to load the next buffered tx request into the
3996 * info pointer to device instance data
3998 * Return Value: true if next buffered tx request loaded
3999 * into adapter's tx dma buffer,
4002 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4006 if ( info
->tx_holding_count
) {
4007 /* determine if we have enough tx dma buffers
4008 * to accommodate the next tx frame
4010 struct tx_holding_buffer
*ptx
=
4011 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4012 int num_free
= num_free_tx_dma_buffers(info
);
4013 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4014 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4017 if (num_needed
<= num_free
) {
4018 info
->xmit_cnt
= ptx
->buffer_size
;
4019 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4021 --info
->tx_holding_count
;
4022 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4023 info
->get_tx_holding_index
=0;
4025 /* restart transmit timer */
4026 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4036 * save_tx_buffer_request()
4038 * attempt to store transmit frame request for later transmission
4042 * info pointer to device instance data
4043 * Buffer pointer to buffer containing frame to load
4044 * BufferSize size in bytes of frame in Buffer
4046 * Return Value: 1 if able to store, 0 otherwise
4048 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4050 struct tx_holding_buffer
*ptx
;
4052 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4053 return 0; /* all buffers in use */
4056 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4057 ptx
->buffer_size
= BufferSize
;
4058 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4060 ++info
->tx_holding_count
;
4061 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4062 info
->put_tx_holding_index
=0;
4067 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4069 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4070 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4071 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4074 info
->io_addr_requested
= true;
4076 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4077 info
->device_name
, info
) < 0 ) {
4078 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4079 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4082 info
->irq_requested
= true;
4084 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4085 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4086 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4087 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4090 info
->shared_mem_requested
= true;
4091 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4092 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4093 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4096 info
->lcr_mem_requested
= true;
4098 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4100 if (!info
->memory_base
) {
4101 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4102 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4106 if ( !mgsl_memory_test(info
) ) {
4107 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4108 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4112 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4114 if (!info
->lcr_base
) {
4115 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4116 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4119 info
->lcr_base
+= info
->lcr_offset
;
4122 /* claim DMA channel */
4124 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4125 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4126 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4127 mgsl_release_resources( info
);
4130 info
->dma_requested
= true;
4132 /* ISA adapter uses bus master DMA */
4133 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4134 enable_dma(info
->dma_level
);
4137 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4138 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4139 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4145 mgsl_release_resources(info
);
4148 } /* end of mgsl_claim_resources() */
4150 static void mgsl_release_resources(struct mgsl_struct
*info
)
4152 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4153 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4154 __FILE__
,__LINE__
,info
->device_name
);
4156 if ( info
->irq_requested
) {
4157 free_irq(info
->irq_level
, info
);
4158 info
->irq_requested
= false;
4160 if ( info
->dma_requested
) {
4161 disable_dma(info
->dma_level
);
4162 free_dma(info
->dma_level
);
4163 info
->dma_requested
= false;
4165 mgsl_free_dma_buffers(info
);
4166 mgsl_free_intermediate_rxbuffer_memory(info
);
4167 mgsl_free_intermediate_txbuffer_memory(info
);
4169 if ( info
->io_addr_requested
) {
4170 release_region(info
->io_base
,info
->io_addr_size
);
4171 info
->io_addr_requested
= false;
4173 if ( info
->shared_mem_requested
) {
4174 release_mem_region(info
->phys_memory_base
,0x40000);
4175 info
->shared_mem_requested
= false;
4177 if ( info
->lcr_mem_requested
) {
4178 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4179 info
->lcr_mem_requested
= false;
4181 if (info
->memory_base
){
4182 iounmap(info
->memory_base
);
4183 info
->memory_base
= NULL
;
4185 if (info
->lcr_base
){
4186 iounmap(info
->lcr_base
- info
->lcr_offset
);
4187 info
->lcr_base
= NULL
;
4190 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4191 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4192 __FILE__
,__LINE__
,info
->device_name
);
4194 } /* end of mgsl_release_resources() */
4196 /* mgsl_add_device()
4198 * Add the specified device instance data structure to the
4199 * global linked list of devices and increment the device count.
4201 * Arguments: info pointer to device instance data
4202 * Return Value: None
4204 static void mgsl_add_device( struct mgsl_struct
*info
)
4206 info
->next_device
= NULL
;
4207 info
->line
= mgsl_device_count
;
4208 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4210 if (info
->line
< MAX_TOTAL_DEVICES
) {
4211 if (maxframe
[info
->line
])
4212 info
->max_frame_size
= maxframe
[info
->line
];
4214 if (txdmabufs
[info
->line
]) {
4215 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4216 if (info
->num_tx_dma_buffers
< 1)
4217 info
->num_tx_dma_buffers
= 1;
4220 if (txholdbufs
[info
->line
]) {
4221 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4222 if (info
->num_tx_holding_buffers
< 1)
4223 info
->num_tx_holding_buffers
= 1;
4224 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4225 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4229 mgsl_device_count
++;
4231 if ( !mgsl_device_list
)
4232 mgsl_device_list
= info
;
4234 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4235 while( current_dev
->next_device
)
4236 current_dev
= current_dev
->next_device
;
4237 current_dev
->next_device
= info
;
4240 if ( info
->max_frame_size
< 4096 )
4241 info
->max_frame_size
= 4096;
4242 else if ( info
->max_frame_size
> 65535 )
4243 info
->max_frame_size
= 65535;
4245 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4246 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4247 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4248 info
->phys_memory_base
, info
->phys_lcr_base
,
4249 info
->max_frame_size
);
4251 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4252 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4253 info
->max_frame_size
);
4256 #if SYNCLINK_GENERIC_HDLC
4260 } /* end of mgsl_add_device() */
4262 static const struct tty_port_operations mgsl_port_ops
= {
4263 .carrier_raised
= carrier_raised
,
4268 /* mgsl_allocate_device()
4270 * Allocate and initialize a device instance structure
4273 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4275 static struct mgsl_struct
* mgsl_allocate_device(void)
4277 struct mgsl_struct
*info
;
4279 info
= kzalloc(sizeof(struct mgsl_struct
),
4283 printk("Error can't allocate device instance data\n");
4285 tty_port_init(&info
->port
);
4286 info
->port
.ops
= &mgsl_port_ops
;
4287 info
->magic
= MGSL_MAGIC
;
4288 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4289 info
->max_frame_size
= 4096;
4290 info
->port
.close_delay
= 5*HZ
/10;
4291 info
->port
.closing_wait
= 30*HZ
;
4292 init_waitqueue_head(&info
->status_event_wait_q
);
4293 init_waitqueue_head(&info
->event_wait_q
);
4294 spin_lock_init(&info
->irq_spinlock
);
4295 spin_lock_init(&info
->netlock
);
4296 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4297 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4298 info
->num_tx_dma_buffers
= 1;
4299 info
->num_tx_holding_buffers
= 0;
4304 } /* end of mgsl_allocate_device()*/
4306 static const struct tty_operations mgsl_ops
= {
4307 .install
= mgsl_install
,
4309 .close
= mgsl_close
,
4310 .write
= mgsl_write
,
4311 .put_char
= mgsl_put_char
,
4312 .flush_chars
= mgsl_flush_chars
,
4313 .write_room
= mgsl_write_room
,
4314 .chars_in_buffer
= mgsl_chars_in_buffer
,
4315 .flush_buffer
= mgsl_flush_buffer
,
4316 .ioctl
= mgsl_ioctl
,
4317 .throttle
= mgsl_throttle
,
4318 .unthrottle
= mgsl_unthrottle
,
4319 .send_xchar
= mgsl_send_xchar
,
4320 .break_ctl
= mgsl_break
,
4321 .wait_until_sent
= mgsl_wait_until_sent
,
4322 .set_termios
= mgsl_set_termios
,
4324 .start
= mgsl_start
,
4325 .hangup
= mgsl_hangup
,
4326 .tiocmget
= tiocmget
,
4327 .tiocmset
= tiocmset
,
4328 .get_icount
= msgl_get_icount
,
4329 .proc_fops
= &mgsl_proc_fops
,
4333 * perform tty device initialization
4335 static int mgsl_init_tty(void)
4339 serial_driver
= alloc_tty_driver(128);
4343 serial_driver
->driver_name
= "synclink";
4344 serial_driver
->name
= "ttySL";
4345 serial_driver
->major
= ttymajor
;
4346 serial_driver
->minor_start
= 64;
4347 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4348 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4349 serial_driver
->init_termios
= tty_std_termios
;
4350 serial_driver
->init_termios
.c_cflag
=
4351 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4352 serial_driver
->init_termios
.c_ispeed
= 9600;
4353 serial_driver
->init_termios
.c_ospeed
= 9600;
4354 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4355 tty_set_operations(serial_driver
, &mgsl_ops
);
4356 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4357 printk("%s(%d):Couldn't register serial driver\n",
4359 put_tty_driver(serial_driver
);
4360 serial_driver
= NULL
;
4364 printk("%s %s, tty major#%d\n",
4365 driver_name
, driver_version
,
4366 serial_driver
->major
);
4370 /* enumerate user specified ISA adapters
4372 static void mgsl_enum_isa_devices(void)
4374 struct mgsl_struct
*info
;
4377 /* Check for user specified ISA devices */
4379 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4380 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4381 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4382 io
[i
], irq
[i
], dma
[i
] );
4384 info
= mgsl_allocate_device();
4386 /* error allocating device instance data */
4387 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4388 printk( "can't allocate device instance data.\n");
4392 /* Copy user configuration info to device instance data */
4393 info
->io_base
= (unsigned int)io
[i
];
4394 info
->irq_level
= (unsigned int)irq
[i
];
4395 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4396 info
->dma_level
= (unsigned int)dma
[i
];
4397 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4398 info
->io_addr_size
= 16;
4399 info
->irq_flags
= 0;
4401 mgsl_add_device( info
);
4405 static void synclink_cleanup(void)
4408 struct mgsl_struct
*info
;
4409 struct mgsl_struct
*tmp
;
4411 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4413 if (serial_driver
) {
4414 if ((rc
= tty_unregister_driver(serial_driver
)))
4415 printk("%s(%d) failed to unregister tty driver err=%d\n",
4416 __FILE__
,__LINE__
,rc
);
4417 put_tty_driver(serial_driver
);
4420 info
= mgsl_device_list
;
4422 #if SYNCLINK_GENERIC_HDLC
4425 mgsl_release_resources(info
);
4427 info
= info
->next_device
;
4432 pci_unregister_driver(&synclink_pci_driver
);
4435 static int __init
synclink_init(void)
4439 if (break_on_load
) {
4440 mgsl_get_text_ptr();
4444 printk("%s %s\n", driver_name
, driver_version
);
4446 mgsl_enum_isa_devices();
4447 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4448 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4450 pci_registered
= true;
4452 if ((rc
= mgsl_init_tty()) < 0)
4462 static void __exit
synclink_exit(void)
4467 module_init(synclink_init
);
4468 module_exit(synclink_exit
);
4473 * Issue a USC Receive/Transmit command to the
4474 * Channel Command/Address Register (CCAR).
4478 * The command is encoded in the most significant 5 bits <15..11>
4479 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4480 * and Bits <6..0> must be written as zeros.
4484 * info pointer to device information structure
4485 * Cmd command mask (use symbolic macros)
4491 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4493 /* output command to CCAR in bits <15..11> */
4494 /* preserve bits <10..7>, bits <6..0> must be zero */
4496 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4498 /* Read to flush write to CCAR */
4499 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4500 inw( info
->io_base
+ CCAR
);
4502 } /* end of usc_RTCmd() */
4507 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4511 * info pointer to device information structure
4512 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4518 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4520 /* write command mask to DCAR */
4521 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4523 /* Read to flush write to DCAR */
4524 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4525 inw( info
->io_base
);
4527 } /* end of usc_DmaCmd() */
4532 * Write a 16-bit value to a USC DMA register
4536 * info pointer to device info structure
4537 * RegAddr register address (number) for write
4538 * RegValue 16-bit value to write to register
4545 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4547 /* Note: The DCAR is located at the adapter base address */
4548 /* Note: must preserve state of BIT8 in DCAR */
4550 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4551 outw( RegValue
, info
->io_base
);
4553 /* Read to flush write to DCAR */
4554 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4555 inw( info
->io_base
);
4557 } /* end of usc_OutDmaReg() */
4562 * Read a 16-bit value from a DMA register
4566 * info pointer to device info structure
4567 * RegAddr register address (number) to read from
4571 * The 16-bit value read from register
4574 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4576 /* Note: The DCAR is located at the adapter base address */
4577 /* Note: must preserve state of BIT8 in DCAR */
4579 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4580 return inw( info
->io_base
);
4582 } /* end of usc_InDmaReg() */
4588 * Write a 16-bit value to a USC serial channel register
4592 * info pointer to device info structure
4593 * RegAddr register address (number) to write to
4594 * RegValue 16-bit value to write to register
4601 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4603 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4604 outw( RegValue
, info
->io_base
+ CCAR
);
4606 /* Read to flush write to CCAR */
4607 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4608 inw( info
->io_base
+ CCAR
);
4610 } /* end of usc_OutReg() */
4615 * Reads a 16-bit value from a USC serial channel register
4619 * info pointer to device extension
4620 * RegAddr register address (number) to read from
4624 * 16-bit value read from register
4626 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4628 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4629 return inw( info
->io_base
+ CCAR
);
4631 } /* end of usc_InReg() */
4633 /* usc_set_sdlc_mode()
4635 * Set up the adapter for SDLC DMA communications.
4637 * Arguments: info pointer to device instance data
4638 * Return Value: NONE
4640 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4646 * determine if the IUSC on the adapter is pre-SL1660. If
4647 * not, take advantage of the UnderWait feature of more
4648 * modern chips. If an underrun occurs and this bit is set,
4649 * the transmitter will idle the programmed idle pattern
4650 * until the driver has time to service the underrun. Otherwise,
4651 * the dma controller may get the cycles previously requested
4652 * and begin transmitting queued tx data.
4654 usc_OutReg(info
,TMCR
,0x1f);
4655 RegValue
=usc_InReg(info
,TMDR
);
4656 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4658 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4661 ** Channel Mode Register (CMR)
4663 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4664 ** <13> 0 0 = Transmit Disabled (initially)
4665 ** <12> 0 1 = Consecutive Idles share common 0
4666 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4667 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4668 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4670 ** 1000 1110 0000 0110 = 0x8e06
4674 /*--------------------------------------------------
4675 * ignore user options for UnderRun Actions and
4677 *--------------------------------------------------*/
4681 /* Channel mode Register (CMR)
4683 * <15..14> 00 Tx Sub modes, Underrun Action
4684 * <13> 0 1 = Send Preamble before opening flag
4685 * <12> 0 1 = Consecutive Idles share common 0
4686 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4687 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4688 * <3..0> 0110 Receiver mode = HDLC/SDLC
4690 * 0000 0110 0000 0110 = 0x0606
4692 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4693 RegValue
= 0x0001; /* Set Receive mode = external sync */
4695 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4696 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4700 * CMR <15> 0 Don't send CRC on Tx Underrun
4701 * CMR <14> x undefined
4702 * CMR <13> 0 Send preamble before openning sync
4703 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4706 * CMR <11-8) 0100 MonoSync
4708 * 0x00 0100 xxxx xxxx 04xx
4716 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4718 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4720 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4721 RegValue
|= BIT15
+ BIT14
;
4724 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4728 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4729 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4732 if ( info
->params
.addr_filter
!= 0xff )
4734 /* set up receive address filtering */
4735 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4739 usc_OutReg( info
, CMR
, RegValue
);
4740 info
->cmr_value
= RegValue
;
4742 /* Receiver mode Register (RMR)
4744 * <15..13> 000 encoding
4745 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4746 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4747 * <9> 0 1 = Include Receive chars in CRC
4748 * <8> 1 1 = Use Abort/PE bit as abort indicator
4749 * <7..6> 00 Even parity
4750 * <5> 0 parity disabled
4751 * <4..2> 000 Receive Char Length = 8 bits
4752 * <1..0> 00 Disable Receiver
4754 * 0000 0101 0000 0000 = 0x0500
4759 switch ( info
->params
.encoding
) {
4760 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4761 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4762 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4763 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4764 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4765 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4769 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4771 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4772 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4774 usc_OutReg( info
, RMR
, RegValue
);
4776 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4777 /* When an opening flag of an SDLC frame is recognized the */
4778 /* Receive Character count (RCC) is loaded with the value in */
4779 /* RCLR. The RCC is decremented for each received byte. The */
4780 /* value of RCC is stored after the closing flag of the frame */
4781 /* allowing the frame size to be computed. */
4783 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4785 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4787 /* Receive Interrupt Control Register (RICR)
4789 * <15..8> ? RxFIFO DMA Request Level
4790 * <7> 0 Exited Hunt IA (Interrupt Arm)
4791 * <6> 0 Idle Received IA
4792 * <5> 0 Break/Abort IA
4794 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4796 * <1> 1 Rx Overrun IA
4797 * <0> 0 Select TC0 value for readback
4799 * 0000 0000 0000 1000 = 0x000a
4802 /* Carry over the Exit Hunt and Idle Received bits */
4803 /* in case they have been armed by usc_ArmEvents. */
4805 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4807 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4808 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4810 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4812 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4814 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4815 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4817 /* Transmit mode Register (TMR)
4819 * <15..13> 000 encoding
4820 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4821 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4822 * <9> 0 1 = Tx CRC Enabled
4823 * <8> 0 1 = Append CRC to end of transmit frame
4824 * <7..6> 00 Transmit parity Even
4825 * <5> 0 Transmit parity Disabled
4826 * <4..2> 000 Tx Char Length = 8 bits
4827 * <1..0> 00 Disable Transmitter
4829 * 0000 0100 0000 0000 = 0x0400
4834 switch ( info
->params
.encoding
) {
4835 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4836 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4837 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4838 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4839 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4840 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4844 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4845 RegValue
|= BIT9
+ BIT8
;
4846 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4847 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4849 usc_OutReg( info
, TMR
, RegValue
);
4851 usc_set_txidle( info
);
4854 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4856 /* Transmit Interrupt Control Register (TICR)
4858 * <15..8> ? Transmit FIFO DMA Level
4859 * <7> 0 Present IA (Interrupt Arm)
4860 * <6> 0 Idle Sent IA
4861 * <5> 1 Abort Sent IA
4862 * <4> 1 EOF/EOM Sent IA
4864 * <2> 1 1 = Wait for SW Trigger to Start Frame
4865 * <1> 1 Tx Underrun IA
4866 * <0> 0 TC0 constant on read back
4868 * 0000 0000 0011 0110 = 0x0036
4871 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4872 usc_OutReg( info
, TICR
, 0x0736 );
4874 usc_OutReg( info
, TICR
, 0x1436 );
4876 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4877 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4880 ** Transmit Command/Status Register (TCSR)
4882 ** <15..12> 0000 TCmd
4883 ** <11> 0/1 UnderWait
4884 ** <10..08> 000 TxIdle
4888 ** <4> x EOF/EOM Sent
4894 ** 0000 0000 0000 0000 = 0x0000
4896 info
->tcsr_value
= 0;
4899 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4901 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4903 /* Clock mode Control Register (CMCR)
4905 * <15..14> 00 counter 1 Source = Disabled
4906 * <13..12> 00 counter 0 Source = Disabled
4907 * <11..10> 11 BRG1 Input is TxC Pin
4908 * <9..8> 11 BRG0 Input is TxC Pin
4909 * <7..6> 01 DPLL Input is BRG1 Output
4910 * <5..3> XXX TxCLK comes from Port 0
4911 * <2..0> XXX RxCLK comes from Port 1
4913 * 0000 1111 0111 0111 = 0x0f77
4918 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4919 RegValue
|= 0x0003; /* RxCLK from DPLL */
4920 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4921 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4922 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4923 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4925 RegValue
|= 0x0007; /* RxCLK from Port1 */
4927 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4928 RegValue
|= 0x0018; /* TxCLK from DPLL */
4929 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4930 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4931 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4932 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4934 RegValue
|= 0x0030; /* TxCLK from Port0 */
4936 usc_OutReg( info
, CMCR
, RegValue
);
4939 /* Hardware Configuration Register (HCR)
4941 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4942 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4943 * <12> 0 CVOK:0=report code violation in biphase
4944 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4945 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4946 * <7..6> 00 reserved
4947 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4949 * <3..2> 00 reserved
4950 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4956 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
4961 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4962 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4964 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4965 XtalSpeed
= 11059200;
4967 XtalSpeed
= 14745600;
4969 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4973 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4980 /* Tc = (Xtal/Speed) - 1 */
4981 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4982 /* then rounding up gives a more precise time constant. Instead */
4983 /* of rounding up and then subtracting 1 we just don't subtract */
4984 /* the one in this case. */
4986 /*--------------------------------------------------
4987 * ejz: for DPLL mode, application should use the
4988 * same clock speed as the partner system, even
4989 * though clocking is derived from the input RxData.
4990 * In case the user uses a 0 for the clock speed,
4991 * default to 0xffffffff and don't try to divide by
4993 *--------------------------------------------------*/
4994 if ( info
->params
.clock_speed
)
4996 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
4997 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
4998 / info
->params
.clock_speed
) )
5005 /* Write 16-bit Time Constant for BRG1 */
5006 usc_OutReg( info
, TC1R
, Tc
);
5008 RegValue
|= BIT4
; /* enable BRG1 */
5010 switch ( info
->params
.encoding
) {
5011 case HDLC_ENCODING_NRZ
:
5012 case HDLC_ENCODING_NRZB
:
5013 case HDLC_ENCODING_NRZI_MARK
:
5014 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5015 case HDLC_ENCODING_BIPHASE_MARK
:
5016 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5017 case HDLC_ENCODING_BIPHASE_LEVEL
:
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5022 usc_OutReg( info
, HCR
, RegValue
);
5025 /* Channel Control/status Register (CCSR)
5027 * <15> X RCC FIFO Overflow status (RO)
5028 * <14> X RCC FIFO Not Empty status (RO)
5029 * <13> 0 1 = Clear RCC FIFO (WO)
5030 * <12> X DPLL Sync (RW)
5031 * <11> X DPLL 2 Missed Clocks status (RO)
5032 * <10> X DPLL 1 Missed Clock status (RO)
5033 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5034 * <7> X SDLC Loop On status (RO)
5035 * <6> X SDLC Loop Send status (RO)
5036 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5037 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5038 * <1..0> 00 reserved
5040 * 0000 0000 0010 0000 = 0x0020
5043 usc_OutReg( info
, CCSR
, 0x1020 );
5046 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5047 usc_OutReg( info
, SICR
,
5048 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5052 /* enable Master Interrupt Enable bit (MIE) */
5053 usc_EnableMasterIrqBit( info
);
5055 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5056 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5058 /* arm RCC underflow interrupt */
5059 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5060 usc_EnableInterrupts(info
, MISC
);
5063 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5064 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5065 info
->mbre_bit
= BIT8
;
5066 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5068 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5069 /* Enable DMAEN (Port 7, Bit 14) */
5070 /* This connects the DMA request signal to the ISA bus */
5071 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5074 /* DMA Control Register (DCR)
5076 * <15..14> 10 Priority mode = Alternating Tx/Rx
5077 * 01 Rx has priority
5078 * 00 Tx has priority
5080 * <13> 1 Enable Priority Preempt per DCR<15..14>
5081 * (WARNING DCR<11..10> must be 00 when this is 1)
5082 * 0 Choose activate channel per DCR<11..10>
5084 * <12> 0 Little Endian for Array/List
5085 * <11..10> 00 Both Channels can use each bus grant
5086 * <9..6> 0000 reserved
5087 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5088 * <4> 0 1 = drive D/C and S/D pins
5089 * <3> 1 1 = Add one wait state to all DMA cycles.
5090 * <2> 0 1 = Strobe /UAS on every transfer.
5091 * <1..0> 11 Addr incrementing only affects LS24 bits
5093 * 0110 0000 0000 1011 = 0x600b
5096 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5097 /* PCI adapter does not need DMA wait state */
5098 usc_OutDmaReg( info
, DCR
, 0xa00b );
5101 usc_OutDmaReg( info
, DCR
, 0x800b );
5104 /* Receive DMA mode Register (RDMR)
5106 * <15..14> 11 DMA mode = Linked List Buffer mode
5107 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5108 * <12> 1 Clear count of List Entry after fetching
5109 * <11..10> 00 Address mode = Increment
5110 * <9> 1 Terminate Buffer on RxBound
5111 * <8> 0 Bus Width = 16bits
5112 * <7..0> ? status Bits (write as 0s)
5114 * 1111 0010 0000 0000 = 0xf200
5117 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5120 /* Transmit DMA mode Register (TDMR)
5122 * <15..14> 11 DMA mode = Linked List Buffer mode
5123 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5124 * <12> 1 Clear count of List Entry after fetching
5125 * <11..10> 00 Address mode = Increment
5126 * <9> 1 Terminate Buffer on end of frame
5127 * <8> 0 Bus Width = 16bits
5128 * <7..0> ? status Bits (Read Only so write as 0)
5130 * 1111 0010 0000 0000 = 0xf200
5133 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5136 /* DMA Interrupt Control Register (DICR)
5138 * <15> 1 DMA Interrupt Enable
5139 * <14> 0 1 = Disable IEO from USC
5140 * <13> 0 1 = Don't provide vector during IntAck
5141 * <12> 1 1 = Include status in Vector
5142 * <10..2> 0 reserved, Must be 0s
5143 * <1> 0 1 = Rx DMA Interrupt Enabled
5144 * <0> 0 1 = Tx DMA Interrupt Enabled
5146 * 1001 0000 0000 0000 = 0x9000
5149 usc_OutDmaReg( info
, DICR
, 0x9000 );
5151 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5152 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5153 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5155 /* Channel Control Register (CCR)
5157 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5158 * <13> 0 Trigger Tx on SW Command Disabled
5159 * <12> 0 Flag Preamble Disabled
5160 * <11..10> 00 Preamble Length
5161 * <9..8> 00 Preamble Pattern
5162 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5163 * <5> 0 Trigger Rx on SW Command Disabled
5166 * 1000 0000 1000 0000 = 0x8080
5171 switch ( info
->params
.preamble_length
) {
5172 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5173 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5174 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5177 switch ( info
->params
.preamble
) {
5178 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5179 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5180 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5181 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5184 usc_OutReg( info
, CCR
, RegValue
);
5188 * Burst/Dwell Control Register
5190 * <15..8> 0x20 Maximum number of transfers per bus grant
5191 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5194 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5195 /* don't limit bus occupancy on PCI adapter */
5196 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5199 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5201 usc_stop_transmitter(info
);
5202 usc_stop_receiver(info
);
5204 } /* end of usc_set_sdlc_mode() */
5206 /* usc_enable_loopback()
5208 * Set the 16C32 for internal loopback mode.
5209 * The TxCLK and RxCLK signals are generated from the BRG0 and
5210 * the TxD is looped back to the RxD internally.
5212 * Arguments: info pointer to device instance data
5213 * enable 1 = enable loopback, 0 = disable
5214 * Return Value: None
5216 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5219 /* blank external TXD output */
5220 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5222 /* Clock mode Control Register (CMCR)
5224 * <15..14> 00 counter 1 Disabled
5225 * <13..12> 00 counter 0 Disabled
5226 * <11..10> 11 BRG1 Input is TxC Pin
5227 * <9..8> 11 BRG0 Input is TxC Pin
5228 * <7..6> 01 DPLL Input is BRG1 Output
5229 * <5..3> 100 TxCLK comes from BRG0
5230 * <2..0> 100 RxCLK comes from BRG0
5232 * 0000 1111 0110 0100 = 0x0f64
5235 usc_OutReg( info
, CMCR
, 0x0f64 );
5237 /* Write 16-bit Time Constant for BRG0 */
5238 /* use clock speed if available, otherwise use 8 for diagnostics */
5239 if (info
->params
.clock_speed
) {
5240 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5241 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5243 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5245 usc_OutReg(info
, TC0R
, (u16
)8);
5247 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5248 mode = Continuous Set Bit 0 to enable BRG0. */
5249 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5251 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5252 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5254 /* set Internal Data loopback mode */
5255 info
->loopback_bits
= 0x300;
5256 outw( 0x0300, info
->io_base
+ CCAR
);
5258 /* enable external TXD output */
5259 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5261 /* clear Internal Data loopback mode */
5262 info
->loopback_bits
= 0;
5263 outw( 0,info
->io_base
+ CCAR
);
5266 } /* end of usc_enable_loopback() */
5268 /* usc_enable_aux_clock()
5270 * Enabled the AUX clock output at the specified frequency.
5274 * info pointer to device extension
5275 * data_rate data rate of clock in bits per second
5276 * A data rate of 0 disables the AUX clock.
5278 * Return Value: None
5280 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5286 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5287 XtalSpeed
= 11059200;
5289 XtalSpeed
= 14745600;
5292 /* Tc = (Xtal/Speed) - 1 */
5293 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5294 /* then rounding up gives a more precise time constant. Instead */
5295 /* of rounding up and then subtracting 1 we just don't subtract */
5296 /* the one in this case. */
5299 Tc
= (u16
)(XtalSpeed
/data_rate
);
5300 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5303 /* Write 16-bit Time Constant for BRG0 */
5304 usc_OutReg( info
, TC0R
, Tc
);
5307 * Hardware Configuration Register (HCR)
5308 * Clear Bit 1, BRG0 mode = Continuous
5309 * Set Bit 0 to enable BRG0.
5312 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5314 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5315 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5317 /* data rate == 0 so turn off BRG0 */
5318 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5321 } /* end of usc_enable_aux_clock() */
5325 * usc_process_rxoverrun_sync()
5327 * This function processes a receive overrun by resetting the
5328 * receive DMA buffers and issuing a Purge Rx FIFO command
5329 * to allow the receiver to continue receiving.
5333 * info pointer to device extension
5335 * Return Value: None
5337 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5341 int frame_start_index
;
5342 bool start_of_frame_found
= false;
5343 bool end_of_frame_found
= false;
5344 bool reprogram_dma
= false;
5346 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5349 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5350 usc_RCmd( info
, RCmd_EnterHuntmode
);
5351 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5353 /* CurrentRxBuffer points to the 1st buffer of the next */
5354 /* possibly available receive frame. */
5356 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5358 /* Search for an unfinished string of buffers. This means */
5359 /* that a receive frame started (at least one buffer with */
5360 /* count set to zero) but there is no terminiting buffer */
5361 /* (status set to non-zero). */
5363 while( !buffer_list
[end_index
].count
)
5365 /* Count field has been reset to zero by 16C32. */
5366 /* This buffer is currently in use. */
5368 if ( !start_of_frame_found
)
5370 start_of_frame_found
= true;
5371 frame_start_index
= end_index
;
5372 end_of_frame_found
= false;
5375 if ( buffer_list
[end_index
].status
)
5377 /* Status field has been set by 16C32. */
5378 /* This is the last buffer of a received frame. */
5380 /* We want to leave the buffers for this frame intact. */
5381 /* Move on to next possible frame. */
5383 start_of_frame_found
= false;
5384 end_of_frame_found
= true;
5387 /* advance to next buffer entry in linked list */
5389 if ( end_index
== info
->rx_buffer_count
)
5392 if ( start_index
== end_index
)
5394 /* The entire list has been searched with all Counts == 0 and */
5395 /* all Status == 0. The receive buffers are */
5396 /* completely screwed, reset all receive buffers! */
5397 mgsl_reset_rx_dma_buffers( info
);
5398 frame_start_index
= 0;
5399 start_of_frame_found
= false;
5400 reprogram_dma
= true;
5405 if ( start_of_frame_found
&& !end_of_frame_found
)
5407 /* There is an unfinished string of receive DMA buffers */
5408 /* as a result of the receiver overrun. */
5410 /* Reset the buffers for the unfinished frame */
5411 /* and reprogram the receive DMA controller to start */
5412 /* at the 1st buffer of unfinished frame. */
5414 start_index
= frame_start_index
;
5418 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5420 /* Adjust index for wrap around. */
5421 if ( start_index
== info
->rx_buffer_count
)
5424 } while( start_index
!= end_index
);
5426 reprogram_dma
= true;
5429 if ( reprogram_dma
)
5431 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5432 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5433 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5435 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5437 /* This empties the receive FIFO and loads the RCC with RCLR */
5438 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5440 /* program 16C32 with physical address of 1st DMA buffer entry */
5441 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5442 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5443 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5445 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5446 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5447 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5449 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5450 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5452 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5453 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5454 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5455 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5456 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5458 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5462 /* This empties the receive FIFO and loads the RCC with RCLR */
5463 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5464 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5467 } /* end of usc_process_rxoverrun_sync() */
5469 /* usc_stop_receiver()
5471 * Disable USC receiver
5473 * Arguments: info pointer to device instance data
5474 * Return Value: None
5476 static void usc_stop_receiver( struct mgsl_struct
*info
)
5478 if (debug_level
>= DEBUG_LEVEL_ISR
)
5479 printk("%s(%d):usc_stop_receiver(%s)\n",
5480 __FILE__
,__LINE__
, info
->device_name
);
5482 /* Disable receive DMA channel. */
5483 /* This also disables receive DMA channel interrupts */
5484 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5486 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5487 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5488 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5490 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5492 /* This empties the receive FIFO and loads the RCC with RCLR */
5493 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5494 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5496 info
->rx_enabled
= false;
5497 info
->rx_overflow
= false;
5498 info
->rx_rcc_underrun
= false;
5500 } /* end of stop_receiver() */
5502 /* usc_start_receiver()
5504 * Enable the USC receiver
5506 * Arguments: info pointer to device instance data
5507 * Return Value: None
5509 static void usc_start_receiver( struct mgsl_struct
*info
)
5513 if (debug_level
>= DEBUG_LEVEL_ISR
)
5514 printk("%s(%d):usc_start_receiver(%s)\n",
5515 __FILE__
,__LINE__
, info
->device_name
);
5517 mgsl_reset_rx_dma_buffers( info
);
5518 usc_stop_receiver( info
);
5520 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5521 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5523 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5524 info
->params
.mode
== MGSL_MODE_RAW
) {
5525 /* DMA mode Transfers */
5526 /* Program the DMA controller. */
5527 /* Enable the DMA controller end of buffer interrupt. */
5529 /* program 16C32 with physical address of 1st DMA buffer entry */
5530 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5531 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5532 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5534 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5535 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5536 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5538 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5539 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5541 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5542 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5543 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5544 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5545 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5547 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5549 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5550 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5551 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5553 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5554 usc_RCmd( info
, RCmd_EnterHuntmode
);
5556 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5559 usc_OutReg( info
, CCSR
, 0x1020 );
5561 info
->rx_enabled
= true;
5563 } /* end of usc_start_receiver() */
5565 /* usc_start_transmitter()
5567 * Enable the USC transmitter and send a transmit frame if
5568 * one is loaded in the DMA buffers.
5570 * Arguments: info pointer to device instance data
5571 * Return Value: None
5573 static void usc_start_transmitter( struct mgsl_struct
*info
)
5576 unsigned int FrameSize
;
5578 if (debug_level
>= DEBUG_LEVEL_ISR
)
5579 printk("%s(%d):usc_start_transmitter(%s)\n",
5580 __FILE__
,__LINE__
, info
->device_name
);
5582 if ( info
->xmit_cnt
) {
5584 /* If auto RTS enabled and RTS is inactive, then assert */
5585 /* RTS and set a flag indicating that the driver should */
5586 /* negate RTS when the transmission completes. */
5588 info
->drop_rts_on_tx_done
= false;
5590 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5591 usc_get_serial_signals( info
);
5592 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5593 info
->serial_signals
|= SerialSignal_RTS
;
5594 usc_set_serial_signals( info
);
5595 info
->drop_rts_on_tx_done
= true;
5600 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5601 if ( !info
->tx_active
) {
5602 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5603 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5604 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5605 usc_load_txfifo(info
);
5608 /* Disable transmit DMA controller while programming. */
5609 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5611 /* Transmit DMA buffer is loaded, so program USC */
5612 /* to send the frame contained in the buffers. */
5614 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5616 /* if operating in Raw sync mode, reset the rcc component
5617 * of the tx dma buffer entry, otherwise, the serial controller
5618 * will send a closing sync char after this count.
5620 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5621 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5623 /* Program the Transmit Character Length Register (TCLR) */
5624 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5625 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5627 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5629 /* Program the address of the 1st DMA Buffer Entry in linked list */
5630 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5631 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5632 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5634 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5635 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5636 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5638 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5639 info
->num_tx_dma_buffers
> 1 ) {
5640 /* When running external sync mode, attempt to 'stream' transmit */
5641 /* by filling tx dma buffers as they become available. To do this */
5642 /* we need to enable Tx DMA EOB Status interrupts : */
5644 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5645 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5647 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5648 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5651 /* Initialize Transmit DMA Channel */
5652 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5654 usc_TCmd( info
, TCmd_SendFrame
);
5656 mod_timer(&info
->tx_timer
, jiffies
+
5657 msecs_to_jiffies(5000));
5659 info
->tx_active
= true;
5662 if ( !info
->tx_enabled
) {
5663 info
->tx_enabled
= true;
5664 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5665 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5667 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5670 } /* end of usc_start_transmitter() */
5672 /* usc_stop_transmitter()
5674 * Stops the transmitter and DMA
5676 * Arguments: info pointer to device isntance data
5677 * Return Value: None
5679 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5681 if (debug_level
>= DEBUG_LEVEL_ISR
)
5682 printk("%s(%d):usc_stop_transmitter(%s)\n",
5683 __FILE__
,__LINE__
, info
->device_name
);
5685 del_timer(&info
->tx_timer
);
5687 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5688 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5689 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5691 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5692 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5693 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5695 info
->tx_enabled
= false;
5696 info
->tx_active
= false;
5698 } /* end of usc_stop_transmitter() */
5700 /* usc_load_txfifo()
5702 * Fill the transmit FIFO until the FIFO is full or
5703 * there is no more data to load.
5705 * Arguments: info pointer to device extension (instance data)
5706 * Return Value: None
5708 static void usc_load_txfifo( struct mgsl_struct
*info
)
5713 if ( !info
->xmit_cnt
&& !info
->x_char
)
5716 /* Select transmit FIFO status readback in TICR */
5717 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5719 /* load the Transmit FIFO until FIFOs full or all data sent */
5721 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5722 /* there is more space in the transmit FIFO and */
5723 /* there is more data in transmit buffer */
5725 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5726 /* write a 16-bit word from transmit buffer to 16C32 */
5728 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5729 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5730 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5731 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5733 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5735 info
->xmit_cnt
-= 2;
5736 info
->icount
.tx
+= 2;
5738 /* only 1 byte left to transmit or 1 FIFO slot left */
5740 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5741 info
->io_base
+ CCAR
);
5744 /* transmit pending high priority char */
5745 outw( info
->x_char
,info
->io_base
+ CCAR
);
5748 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5749 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5756 } /* end of usc_load_txfifo() */
5760 * Reset the adapter to a known state and prepare it for further use.
5762 * Arguments: info pointer to device instance data
5763 * Return Value: None
5765 static void usc_reset( struct mgsl_struct
*info
)
5767 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5771 /* Set BIT30 of Misc Control Register */
5772 /* (Local Control Register 0x50) to force reset of USC. */
5774 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5775 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5777 info
->misc_ctrl_value
|= BIT30
;
5778 *MiscCtrl
= info
->misc_ctrl_value
;
5781 * Force at least 170ns delay before clearing
5782 * reset bit. Each read from LCR takes at least
5783 * 30ns so 10 times for 300ns to be safe.
5786 readval
= *MiscCtrl
;
5788 info
->misc_ctrl_value
&= ~BIT30
;
5789 *MiscCtrl
= info
->misc_ctrl_value
;
5791 *LCR0BRDR
= BUS_DESCRIPTOR(
5792 1, // Write Strobe Hold (0-3)
5793 2, // Write Strobe Delay (0-3)
5794 2, // Read Strobe Delay (0-3)
5795 0, // NWDD (Write data-data) (0-3)
5796 4, // NWAD (Write Addr-data) (0-31)
5797 0, // NXDA (Read/Write Data-Addr) (0-3)
5798 0, // NRDD (Read Data-Data) (0-3)
5799 5 // NRAD (Read Addr-Data) (0-31)
5803 outb( 0,info
->io_base
+ 8 );
5807 info
->loopback_bits
= 0;
5808 info
->usc_idle_mode
= 0;
5811 * Program the Bus Configuration Register (BCR)
5813 * <15> 0 Don't use separate address
5814 * <14..6> 0 reserved
5815 * <5..4> 00 IAckmode = Default, don't care
5816 * <3> 1 Bus Request Totem Pole output
5817 * <2> 1 Use 16 Bit data bus
5818 * <1> 0 IRQ Totem Pole output
5819 * <0> 0 Don't Shift Right Addr
5821 * 0000 0000 0000 1100 = 0x000c
5823 * By writing to io_base + SDPIN the Wait/Ack pin is
5824 * programmed to work as a Wait pin.
5827 outw( 0x000c,info
->io_base
+ SDPIN
);
5830 outw( 0,info
->io_base
);
5831 outw( 0,info
->io_base
+ CCAR
);
5833 /* select little endian byte ordering */
5834 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5837 /* Port Control Register (PCR)
5839 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5840 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5841 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5842 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5843 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5844 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5845 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5846 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5848 * 1111 0000 1111 0101 = 0xf0f5
5851 usc_OutReg( info
, PCR
, 0xf0f5 );
5855 * Input/Output Control Register
5857 * <15..14> 00 CTS is active low input
5858 * <13..12> 00 DCD is active low input
5859 * <11..10> 00 TxREQ pin is input (DSR)
5860 * <9..8> 00 RxREQ pin is input (RI)
5861 * <7..6> 00 TxD is output (Transmit Data)
5862 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5863 * <2..0> 100 RxC is Output (drive with BRG0)
5865 * 0000 0000 0000 0100 = 0x0004
5868 usc_OutReg( info
, IOCR
, 0x0004 );
5870 } /* end of usc_reset() */
5872 /* usc_set_async_mode()
5874 * Program adapter for asynchronous communications.
5876 * Arguments: info pointer to device instance data
5877 * Return Value: None
5879 static void usc_set_async_mode( struct mgsl_struct
*info
)
5883 /* disable interrupts while programming USC */
5884 usc_DisableMasterIrqBit( info
);
5886 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5887 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5889 usc_loopback_frame( info
);
5891 /* Channel mode Register (CMR)
5893 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5894 * <13..12> 00 00 = 16X Clock
5895 * <11..8> 0000 Transmitter mode = Asynchronous
5896 * <7..6> 00 reserved?
5897 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5898 * <3..0> 0000 Receiver mode = Asynchronous
5900 * 0000 0000 0000 0000 = 0x0
5904 if ( info
->params
.stop_bits
!= 1 )
5906 usc_OutReg( info
, CMR
, RegValue
);
5909 /* Receiver mode Register (RMR)
5911 * <15..13> 000 encoding = None
5912 * <12..08> 00000 reserved (Sync Only)
5913 * <7..6> 00 Even parity
5914 * <5> 0 parity disabled
5915 * <4..2> 000 Receive Char Length = 8 bits
5916 * <1..0> 00 Disable Receiver
5918 * 0000 0000 0000 0000 = 0x0
5923 if ( info
->params
.data_bits
!= 8 )
5924 RegValue
|= BIT4
+BIT3
+BIT2
;
5926 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5928 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5932 usc_OutReg( info
, RMR
, RegValue
);
5935 /* Set IRQ trigger level */
5937 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5940 /* Receive Interrupt Control Register (RICR)
5942 * <15..8> ? RxFIFO IRQ Request Level
5944 * Note: For async mode the receive FIFO level must be set
5945 * to 0 to avoid the situation where the FIFO contains fewer bytes
5946 * than the trigger level and no more data is expected.
5948 * <7> 0 Exited Hunt IA (Interrupt Arm)
5949 * <6> 0 Idle Received IA
5950 * <5> 0 Break/Abort IA
5952 * <3> 0 Queued status reflects oldest byte in FIFO
5954 * <1> 0 Rx Overrun IA
5955 * <0> 0 Select TC0 value for readback
5957 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5960 usc_OutReg( info
, RICR
, 0x0000 );
5962 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5963 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5966 /* Transmit mode Register (TMR)
5968 * <15..13> 000 encoding = None
5969 * <12..08> 00000 reserved (Sync Only)
5970 * <7..6> 00 Transmit parity Even
5971 * <5> 0 Transmit parity Disabled
5972 * <4..2> 000 Tx Char Length = 8 bits
5973 * <1..0> 00 Disable Transmitter
5975 * 0000 0000 0000 0000 = 0x0
5980 if ( info
->params
.data_bits
!= 8 )
5981 RegValue
|= BIT4
+BIT3
+BIT2
;
5983 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5985 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5989 usc_OutReg( info
, TMR
, RegValue
);
5991 usc_set_txidle( info
);
5994 /* Set IRQ trigger level */
5996 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
5999 /* Transmit Interrupt Control Register (TICR)
6001 * <15..8> ? Transmit FIFO IRQ Level
6002 * <7> 0 Present IA (Interrupt Arm)
6003 * <6> 1 Idle Sent IA
6004 * <5> 0 Abort Sent IA
6005 * <4> 0 EOF/EOM Sent IA
6007 * <2> 0 1 = Wait for SW Trigger to Start Frame
6008 * <1> 0 Tx Underrun IA
6009 * <0> 0 TC0 constant on read back
6011 * 0000 0000 0100 0000 = 0x0040
6014 usc_OutReg( info
, TICR
, 0x1f40 );
6016 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6017 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6019 usc_enable_async_clock( info
, info
->params
.data_rate
);
6022 /* Channel Control/status Register (CCSR)
6024 * <15> X RCC FIFO Overflow status (RO)
6025 * <14> X RCC FIFO Not Empty status (RO)
6026 * <13> 0 1 = Clear RCC FIFO (WO)
6027 * <12> X DPLL in Sync status (RO)
6028 * <11> X DPLL 2 Missed Clocks status (RO)
6029 * <10> X DPLL 1 Missed Clock status (RO)
6030 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6031 * <7> X SDLC Loop On status (RO)
6032 * <6> X SDLC Loop Send status (RO)
6033 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6034 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6035 * <1..0> 00 reserved
6037 * 0000 0000 0010 0000 = 0x0020
6040 usc_OutReg( info
, CCSR
, 0x0020 );
6042 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6043 RECEIVE_DATA
+ RECEIVE_STATUS
);
6045 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6046 RECEIVE_DATA
+ RECEIVE_STATUS
);
6048 usc_EnableMasterIrqBit( info
);
6050 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6051 /* Enable INTEN (Port 6, Bit12) */
6052 /* This connects the IRQ request signal to the ISA bus */
6053 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6056 if (info
->params
.loopback
) {
6057 info
->loopback_bits
= 0x300;
6058 outw(0x0300, info
->io_base
+ CCAR
);
6061 } /* end of usc_set_async_mode() */
6063 /* usc_loopback_frame()
6065 * Loop back a small (2 byte) dummy SDLC frame.
6066 * Interrupts and DMA are NOT used. The purpose of this is to
6067 * clear any 'stale' status info left over from running in async mode.
6069 * The 16C32 shows the strange behaviour of marking the 1st
6070 * received SDLC frame with a CRC error even when there is no
6071 * CRC error. To get around this a small dummy from of 2 bytes
6072 * is looped back when switching from async to sync mode.
6074 * Arguments: info pointer to device instance data
6075 * Return Value: None
6077 static void usc_loopback_frame( struct mgsl_struct
*info
)
6080 unsigned long oldmode
= info
->params
.mode
;
6082 info
->params
.mode
= MGSL_MODE_HDLC
;
6084 usc_DisableMasterIrqBit( info
);
6086 usc_set_sdlc_mode( info
);
6087 usc_enable_loopback( info
, 1 );
6089 /* Write 16-bit Time Constant for BRG0 */
6090 usc_OutReg( info
, TC0R
, 0 );
6092 /* Channel Control Register (CCR)
6094 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6095 * <13> 0 Trigger Tx on SW Command Disabled
6096 * <12> 0 Flag Preamble Disabled
6097 * <11..10> 00 Preamble Length = 8-Bits
6098 * <9..8> 01 Preamble Pattern = flags
6099 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6100 * <5> 0 Trigger Rx on SW Command Disabled
6103 * 0000 0001 0000 0000 = 0x0100
6106 usc_OutReg( info
, CCR
, 0x0100 );
6108 /* SETUP RECEIVER */
6109 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6110 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6112 /* SETUP TRANSMITTER */
6113 /* Program the Transmit Character Length Register (TCLR) */
6114 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6115 usc_OutReg( info
, TCLR
, 2 );
6116 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6118 /* unlatch Tx status bits, and start transmit channel. */
6119 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6120 outw(0,info
->io_base
+ DATAREG
);
6122 /* ENABLE TRANSMITTER */
6123 usc_TCmd( info
, TCmd_SendFrame
);
6124 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6126 /* WAIT FOR RECEIVE COMPLETE */
6127 for (i
=0 ; i
<1000 ; i
++)
6128 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6131 /* clear Internal Data loopback mode */
6132 usc_enable_loopback(info
, 0);
6134 usc_EnableMasterIrqBit(info
);
6136 info
->params
.mode
= oldmode
;
6138 } /* end of usc_loopback_frame() */
6140 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6142 * Arguments: info pointer to adapter info structure
6143 * Return Value: None
6145 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6147 usc_loopback_frame( info
);
6148 usc_set_sdlc_mode( info
);
6150 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6151 /* Enable INTEN (Port 6, Bit12) */
6152 /* This connects the IRQ request signal to the ISA bus */
6153 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6156 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6158 if (info
->params
.loopback
)
6159 usc_enable_loopback(info
,1);
6161 } /* end of mgsl_set_sync_mode() */
6163 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6165 * Arguments: info pointer to device instance data
6166 * Return Value: None
6168 static void usc_set_txidle( struct mgsl_struct
*info
)
6170 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6172 /* Map API idle mode to USC register bits */
6174 switch( info
->idle_mode
){
6175 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6176 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6177 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6178 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6179 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6180 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6181 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6184 info
->usc_idle_mode
= usc_idle_mode
;
6185 //usc_OutReg(info, TCSR, usc_idle_mode);
6186 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6187 info
->tcsr_value
+= usc_idle_mode
;
6188 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6191 * if SyncLink WAN adapter is running in external sync mode, the
6192 * transmitter has been set to Monosync in order to try to mimic
6193 * a true raw outbound bit stream. Monosync still sends an open/close
6194 * sync char at the start/end of a frame. Try to match those sync
6195 * patterns to the idle mode set here
6197 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6198 unsigned char syncpat
= 0;
6199 switch( info
->idle_mode
) {
6200 case HDLC_TXIDLE_FLAGS
:
6203 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6206 case HDLC_TXIDLE_ZEROS
:
6207 case HDLC_TXIDLE_SPACE
:
6210 case HDLC_TXIDLE_ONES
:
6211 case HDLC_TXIDLE_MARK
:
6214 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6219 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6222 } /* end of usc_set_txidle() */
6224 /* usc_get_serial_signals()
6226 * Query the adapter for the state of the V24 status (input) signals.
6228 * Arguments: info pointer to device instance data
6229 * Return Value: None
6231 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6235 /* clear all serial signals except DTR and RTS */
6236 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6238 /* Read the Misc Interrupt status Register (MISR) to get */
6239 /* the V24 status signals. */
6241 status
= usc_InReg( info
, MISR
);
6243 /* set serial signal bits to reflect MISR */
6245 if ( status
& MISCSTATUS_CTS
)
6246 info
->serial_signals
|= SerialSignal_CTS
;
6248 if ( status
& MISCSTATUS_DCD
)
6249 info
->serial_signals
|= SerialSignal_DCD
;
6251 if ( status
& MISCSTATUS_RI
)
6252 info
->serial_signals
|= SerialSignal_RI
;
6254 if ( status
& MISCSTATUS_DSR
)
6255 info
->serial_signals
|= SerialSignal_DSR
;
6257 } /* end of usc_get_serial_signals() */
6259 /* usc_set_serial_signals()
6261 * Set the state of DTR and RTS based on contents of
6262 * serial_signals member of device extension.
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6267 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6270 unsigned char V24Out
= info
->serial_signals
;
6272 /* get the current value of the Port Control Register (PCR) */
6274 Control
= usc_InReg( info
, PCR
);
6276 if ( V24Out
& SerialSignal_RTS
)
6281 if ( V24Out
& SerialSignal_DTR
)
6286 usc_OutReg( info
, PCR
, Control
);
6288 } /* end of usc_set_serial_signals() */
6290 /* usc_enable_async_clock()
6292 * Enable the async clock at the specified frequency.
6294 * Arguments: info pointer to device instance data
6295 * data_rate data rate of clock in bps
6296 * 0 disables the AUX clock.
6297 * Return Value: None
6299 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6303 * Clock mode Control Register (CMCR)
6305 * <15..14> 00 counter 1 Disabled
6306 * <13..12> 00 counter 0 Disabled
6307 * <11..10> 11 BRG1 Input is TxC Pin
6308 * <9..8> 11 BRG0 Input is TxC Pin
6309 * <7..6> 01 DPLL Input is BRG1 Output
6310 * <5..3> 100 TxCLK comes from BRG0
6311 * <2..0> 100 RxCLK comes from BRG0
6313 * 0000 1111 0110 0100 = 0x0f64
6316 usc_OutReg( info
, CMCR
, 0x0f64 );
6320 * Write 16-bit Time Constant for BRG0
6321 * Time Constant = (ClkSpeed / data_rate) - 1
6322 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6325 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6326 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6328 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6332 * Hardware Configuration Register (HCR)
6333 * Clear Bit 1, BRG0 mode = Continuous
6334 * Set Bit 0 to enable BRG0.
6337 usc_OutReg( info
, HCR
,
6338 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6341 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6343 usc_OutReg( info
, IOCR
,
6344 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6346 /* data rate == 0 so turn off BRG0 */
6347 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6350 } /* end of usc_enable_async_clock() */
6353 * Buffer Structures:
6355 * Normal memory access uses virtual addresses that can make discontiguous
6356 * physical memory pages appear to be contiguous in the virtual address
6357 * space (the processors memory mapping handles the conversions).
6359 * DMA transfers require physically contiguous memory. This is because
6360 * the DMA system controller and DMA bus masters deal with memory using
6361 * only physical addresses.
6363 * This causes a problem under Windows NT when large DMA buffers are
6364 * needed. Fragmentation of the nonpaged pool prevents allocations of
6365 * physically contiguous buffers larger than the PAGE_SIZE.
6367 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6368 * allows DMA transfers to physically discontiguous buffers. Information
6369 * about each data transfer buffer is contained in a memory structure
6370 * called a 'buffer entry'. A list of buffer entries is maintained
6371 * to track and control the use of the data transfer buffers.
6373 * To support this strategy we will allocate sufficient PAGE_SIZE
6374 * contiguous memory buffers to allow for the total required buffer
6377 * The 16C32 accesses the list of buffer entries using Bus Master
6378 * DMA. Control information is read from the buffer entries by the
6379 * 16C32 to control data transfers. status information is written to
6380 * the buffer entries by the 16C32 to indicate the status of completed
6383 * The CPU writes control information to the buffer entries to control
6384 * the 16C32 and reads status information from the buffer entries to
6385 * determine information about received and transmitted frames.
6387 * Because the CPU and 16C32 (adapter) both need simultaneous access
6388 * to the buffer entries, the buffer entry memory is allocated with
6389 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6390 * entry list to PAGE_SIZE.
6392 * The actual data buffers on the other hand will only be accessed
6393 * by the CPU or the adapter but not by both simultaneously. This allows
6394 * Scatter/Gather packet based DMA procedures for using physically
6395 * discontiguous pages.
6399 * mgsl_reset_tx_dma_buffers()
6401 * Set the count for all transmit buffers to 0 to indicate the
6402 * buffer is available for use and set the current buffer to the
6403 * first buffer. This effectively makes all buffers free and
6404 * discards any data in buffers.
6406 * Arguments: info pointer to device instance data
6407 * Return Value: None
6409 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6413 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6414 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6417 info
->current_tx_buffer
= 0;
6418 info
->start_tx_dma_buffer
= 0;
6419 info
->tx_dma_buffers_used
= 0;
6421 info
->get_tx_holding_index
= 0;
6422 info
->put_tx_holding_index
= 0;
6423 info
->tx_holding_count
= 0;
6425 } /* end of mgsl_reset_tx_dma_buffers() */
6428 * num_free_tx_dma_buffers()
6430 * returns the number of free tx dma buffers available
6432 * Arguments: info pointer to device instance data
6433 * Return Value: number of free tx dma buffers
6435 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6437 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6441 * mgsl_reset_rx_dma_buffers()
6443 * Set the count for all receive buffers to DMABUFFERSIZE
6444 * and set the current buffer to the first buffer. This effectively
6445 * makes all buffers free and discards any data in buffers.
6447 * Arguments: info pointer to device instance data
6448 * Return Value: None
6450 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6454 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6455 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6456 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6457 // info->rx_buffer_list[i].status = 0;
6460 info
->current_rx_buffer
= 0;
6462 } /* end of mgsl_reset_rx_dma_buffers() */
6465 * mgsl_free_rx_frame_buffers()
6467 * Free the receive buffers used by a received SDLC
6468 * frame such that the buffers can be reused.
6472 * info pointer to device instance data
6473 * StartIndex index of 1st receive buffer of frame
6474 * EndIndex index of last receive buffer of frame
6476 * Return Value: None
6478 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6481 DMABUFFERENTRY
*pBufEntry
;
6484 /* Starting with 1st buffer entry of the frame clear the status */
6485 /* field and set the count field to DMA Buffer Size. */
6490 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6492 if ( Index
== EndIndex
) {
6493 /* This is the last buffer of the frame! */
6497 /* reset current buffer for reuse */
6498 // pBufEntry->status = 0;
6499 // pBufEntry->count = DMABUFFERSIZE;
6500 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6502 /* advance to next buffer entry in linked list */
6504 if ( Index
== info
->rx_buffer_count
)
6508 /* set current buffer to next buffer after last buffer of frame */
6509 info
->current_rx_buffer
= Index
;
6511 } /* end of free_rx_frame_buffers() */
6513 /* mgsl_get_rx_frame()
6515 * This function attempts to return a received SDLC frame from the
6516 * receive DMA buffers. Only frames received without errors are returned.
6518 * Arguments: info pointer to device extension
6519 * Return Value: true if frame returned, otherwise false
6521 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6523 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6524 unsigned short status
;
6525 DMABUFFERENTRY
*pBufEntry
;
6526 unsigned int framesize
= 0;
6527 bool ReturnCode
= false;
6528 unsigned long flags
;
6529 struct tty_struct
*tty
= info
->port
.tty
;
6530 bool return_frame
= false;
6533 * current_rx_buffer points to the 1st buffer of the next available
6534 * receive frame. To find the last buffer of the frame look for
6535 * a non-zero status field in the buffer entries. (The status
6536 * field is set by the 16C32 after completing a receive frame.
6539 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6541 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6543 * If the count field of the buffer entry is non-zero then
6544 * this buffer has not been used. (The 16C32 clears the count
6545 * field when it starts using the buffer.) If an unused buffer
6546 * is encountered then there are no frames available.
6549 if ( info
->rx_buffer_list
[EndIndex
].count
)
6552 /* advance to next buffer entry in linked list */
6554 if ( EndIndex
== info
->rx_buffer_count
)
6557 /* if entire list searched then no frame available */
6558 if ( EndIndex
== StartIndex
) {
6559 /* If this occurs then something bad happened,
6560 * all buffers have been 'used' but none mark
6561 * the end of a frame. Reset buffers and receiver.
6564 if ( info
->rx_enabled
){
6565 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6566 usc_start_receiver(info
);
6567 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6574 /* check status of receive frame */
6576 status
= info
->rx_buffer_list
[EndIndex
].status
;
6578 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6579 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6580 if ( status
& RXSTATUS_SHORT_FRAME
)
6581 info
->icount
.rxshort
++;
6582 else if ( status
& RXSTATUS_ABORT
)
6583 info
->icount
.rxabort
++;
6584 else if ( status
& RXSTATUS_OVERRUN
)
6585 info
->icount
.rxover
++;
6587 info
->icount
.rxcrc
++;
6588 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6589 return_frame
= true;
6592 #if SYNCLINK_GENERIC_HDLC
6594 info
->netdev
->stats
.rx_errors
++;
6595 info
->netdev
->stats
.rx_frame_errors
++;
6599 return_frame
= true;
6601 if ( return_frame
) {
6602 /* receive frame has no errors, get frame size.
6603 * The frame size is the starting value of the RCC (which was
6604 * set to 0xffff) minus the ending value of the RCC (decremented
6605 * once for each receive character) minus 2 for the 16-bit CRC.
6608 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6610 /* adjust frame size for CRC if any */
6611 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6613 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6617 if ( debug_level
>= DEBUG_LEVEL_BH
)
6618 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6619 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6621 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6622 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6623 min_t(int, framesize
, DMABUFFERSIZE
),0);
6626 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6627 ((framesize
+1) > info
->max_frame_size
) ) ||
6628 (framesize
> info
->max_frame_size
) )
6629 info
->icount
.rxlong
++;
6631 /* copy dma buffer(s) to contiguous intermediate buffer */
6632 int copy_count
= framesize
;
6633 int index
= StartIndex
;
6634 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6636 if ( !(status
& RXSTATUS_CRC_ERROR
))
6637 info
->icount
.rxok
++;
6641 if ( copy_count
> DMABUFFERSIZE
)
6642 partial_count
= DMABUFFERSIZE
;
6644 partial_count
= copy_count
;
6646 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6647 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6648 ptmp
+= partial_count
;
6649 copy_count
-= partial_count
;
6651 if ( ++index
== info
->rx_buffer_count
)
6655 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6657 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6661 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6662 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6663 __FILE__
,__LINE__
,info
->device_name
,
6667 #if SYNCLINK_GENERIC_HDLC
6669 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6672 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6675 /* Free the buffers used by this frame. */
6676 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6682 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6683 /* The receiver needs to restarted because of
6684 * a receive overflow (buffer or FIFO). If the
6685 * receive buffers are now empty, then restart receiver.
6688 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6689 info
->rx_buffer_list
[EndIndex
].count
) {
6690 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6691 usc_start_receiver(info
);
6692 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6698 } /* end of mgsl_get_rx_frame() */
6700 /* mgsl_get_raw_rx_frame()
6702 * This function attempts to return a received frame from the
6703 * receive DMA buffers when running in external loop mode. In this mode,
6704 * we will return at most one DMABUFFERSIZE frame to the application.
6705 * The USC receiver is triggering off of DCD going active to start a new
6706 * frame, and DCD going inactive to terminate the frame (similar to
6707 * processing a closing flag character).
6709 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6710 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6711 * status field and the RCC field will indicate the length of the
6712 * entire received frame. We take this RCC field and get the modulus
6713 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6714 * last Rx DMA buffer and return that last portion of the frame.
6716 * Arguments: info pointer to device extension
6717 * Return Value: true if frame returned, otherwise false
6719 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6721 unsigned int CurrentIndex
, NextIndex
;
6722 unsigned short status
;
6723 DMABUFFERENTRY
*pBufEntry
;
6724 unsigned int framesize
= 0;
6725 bool ReturnCode
= false;
6726 unsigned long flags
;
6727 struct tty_struct
*tty
= info
->port
.tty
;
6730 * current_rx_buffer points to the 1st buffer of the next available
6731 * receive frame. The status field is set by the 16C32 after
6732 * completing a receive frame. If the status field of this buffer
6733 * is zero, either the USC is still filling this buffer or this
6734 * is one of a series of buffers making up a received frame.
6736 * If the count field of this buffer is zero, the USC is either
6737 * using this buffer or has used this buffer. Look at the count
6738 * field of the next buffer. If that next buffer's count is
6739 * non-zero, the USC is still actively using the current buffer.
6740 * Otherwise, if the next buffer's count field is zero, the
6741 * current buffer is complete and the USC is using the next
6744 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6746 if ( NextIndex
== info
->rx_buffer_count
)
6749 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6750 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6751 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6753 * Either the status field of this dma buffer is non-zero
6754 * (indicating the last buffer of a receive frame) or the next
6755 * buffer is marked as in use -- implying this buffer is complete
6756 * and an intermediate buffer for this received frame.
6759 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6761 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6762 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6763 if ( status
& RXSTATUS_SHORT_FRAME
)
6764 info
->icount
.rxshort
++;
6765 else if ( status
& RXSTATUS_ABORT
)
6766 info
->icount
.rxabort
++;
6767 else if ( status
& RXSTATUS_OVERRUN
)
6768 info
->icount
.rxover
++;
6770 info
->icount
.rxcrc
++;
6774 * A receive frame is available, get frame size and status.
6776 * The frame size is the starting value of the RCC (which was
6777 * set to 0xffff) minus the ending value of the RCC (decremented
6778 * once for each receive character) minus 2 or 4 for the 16-bit
6781 * If the status field is zero, this is an intermediate buffer.
6784 * If the DMA Buffer Entry's Status field is non-zero, the
6785 * receive operation completed normally (ie: DCD dropped). The
6786 * RCC field is valid and holds the received frame size.
6787 * It is possible that the RCC field will be zero on a DMA buffer
6788 * entry with a non-zero status. This can occur if the total
6789 * frame size (number of bytes between the time DCD goes active
6790 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6791 * case the 16C32 has underrun on the RCC count and appears to
6792 * stop updating this counter to let us know the actual received
6793 * frame size. If this happens (non-zero status and zero RCC),
6794 * simply return the entire RxDMA Buffer
6798 * In the event that the final RxDMA Buffer is
6799 * terminated with a non-zero status and the RCC
6800 * field is zero, we interpret this as the RCC
6801 * having underflowed (received frame > 65535 bytes).
6803 * Signal the event to the user by passing back
6804 * a status of RxStatus_CrcError returning the full
6805 * buffer and let the app figure out what data is
6808 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6809 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6811 framesize
= DMABUFFERSIZE
;
6814 framesize
= DMABUFFERSIZE
;
6817 if ( framesize
> DMABUFFERSIZE
) {
6819 * if running in raw sync mode, ISR handler for
6820 * End Of Buffer events terminates all buffers at 4K.
6821 * If this frame size is said to be >4K, get the
6822 * actual number of bytes of the frame in this buffer.
6824 framesize
= framesize
% DMABUFFERSIZE
;
6828 if ( debug_level
>= DEBUG_LEVEL_BH
)
6829 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6830 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6832 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6833 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6834 min_t(int, framesize
, DMABUFFERSIZE
),0);
6837 /* copy dma buffer(s) to contiguous intermediate buffer */
6838 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6840 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6841 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6842 info
->icount
.rxok
++;
6844 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6847 /* Free the buffers used by this frame. */
6848 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6854 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6855 /* The receiver needs to restarted because of
6856 * a receive overflow (buffer or FIFO). If the
6857 * receive buffers are now empty, then restart receiver.
6860 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6861 info
->rx_buffer_list
[CurrentIndex
].count
) {
6862 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6863 usc_start_receiver(info
);
6864 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6870 } /* end of mgsl_get_raw_rx_frame() */
6872 /* mgsl_load_tx_dma_buffer()
6874 * Load the transmit DMA buffer with the specified data.
6878 * info pointer to device extension
6879 * Buffer pointer to buffer containing frame to load
6880 * BufferSize size in bytes of frame in Buffer
6882 * Return Value: None
6884 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6885 const char *Buffer
, unsigned int BufferSize
)
6887 unsigned short Copycount
;
6889 DMABUFFERENTRY
*pBufEntry
;
6891 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6892 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6894 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6895 /* set CMR:13 to start transmit when
6896 * next GoAhead (abort) is received
6898 info
->cmr_value
|= BIT13
;
6901 /* begin loading the frame in the next available tx dma
6902 * buffer, remember it's starting location for setting
6903 * up tx dma operation
6905 i
= info
->current_tx_buffer
;
6906 info
->start_tx_dma_buffer
= i
;
6908 /* Setup the status and RCC (Frame Size) fields of the 1st */
6909 /* buffer entry in the transmit DMA buffer list. */
6911 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6912 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6913 info
->tx_buffer_list
[i
].count
= BufferSize
;
6915 /* Copy frame data from 1st source buffer to the DMA buffers. */
6916 /* The frame data may span multiple DMA buffers. */
6918 while( BufferSize
){
6919 /* Get a pointer to next DMA buffer entry. */
6920 pBufEntry
= &info
->tx_buffer_list
[i
++];
6922 if ( i
== info
->tx_buffer_count
)
6925 /* Calculate the number of bytes that can be copied from */
6926 /* the source buffer to this DMA buffer. */
6927 if ( BufferSize
> DMABUFFERSIZE
)
6928 Copycount
= DMABUFFERSIZE
;
6930 Copycount
= BufferSize
;
6932 /* Actually copy data from source buffer to DMA buffer. */
6933 /* Also set the data count for this individual DMA buffer. */
6934 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6935 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6937 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6939 pBufEntry
->count
= Copycount
;
6941 /* Advance source pointer and reduce remaining data count. */
6942 Buffer
+= Copycount
;
6943 BufferSize
-= Copycount
;
6945 ++info
->tx_dma_buffers_used
;
6948 /* remember next available tx dma buffer */
6949 info
->current_tx_buffer
= i
;
6951 } /* end of mgsl_load_tx_dma_buffer() */
6954 * mgsl_register_test()
6956 * Performs a register test of the 16C32.
6958 * Arguments: info pointer to device instance data
6959 * Return Value: true if test passed, otherwise false
6961 static bool mgsl_register_test( struct mgsl_struct
*info
)
6963 static unsigned short BitPatterns
[] =
6964 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6965 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
6968 unsigned long flags
;
6970 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6973 /* Verify the reset state of some registers. */
6975 if ( (usc_InReg( info
, SICR
) != 0) ||
6976 (usc_InReg( info
, IVR
) != 0) ||
6977 (usc_InDmaReg( info
, DIVR
) != 0) ){
6982 /* Write bit patterns to various registers but do it out of */
6983 /* sync, then read back and verify values. */
6985 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6986 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6987 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6988 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6989 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6990 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6991 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6993 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6994 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6995 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
6996 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
6997 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
6998 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7006 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7010 } /* end of mgsl_register_test() */
7012 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7014 * Arguments: info pointer to device instance data
7015 * Return Value: true if test passed, otherwise false
7017 static bool mgsl_irq_test( struct mgsl_struct
*info
)
7019 unsigned long EndTime
;
7020 unsigned long flags
;
7022 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7026 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7027 * The ISR sets irq_occurred to true.
7030 info
->irq_occurred
= false;
7032 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7033 /* Enable INTEN (Port 6, Bit12) */
7034 /* This connects the IRQ request signal to the ISA bus */
7035 /* on the ISA adapter. This has no effect for the PCI adapter */
7036 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7038 usc_EnableMasterIrqBit(info
);
7039 usc_EnableInterrupts(info
, IO_PIN
);
7040 usc_ClearIrqPendingBits(info
, IO_PIN
);
7042 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7043 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7045 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7048 while( EndTime
-- && !info
->irq_occurred
) {
7049 msleep_interruptible(10);
7052 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7054 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7056 return info
->irq_occurred
;
7058 } /* end of mgsl_irq_test() */
7062 * Perform a DMA test of the 16C32. A small frame is
7063 * transmitted via DMA from a transmit buffer to a receive buffer
7064 * using single buffer DMA mode.
7066 * Arguments: info pointer to device instance data
7067 * Return Value: true if test passed, otherwise false
7069 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7071 unsigned short FifoLevel
;
7072 unsigned long phys_addr
;
7073 unsigned int FrameSize
;
7077 unsigned short status
=0;
7078 unsigned long EndTime
;
7079 unsigned long flags
;
7080 MGSL_PARAMS tmp_params
;
7082 /* save current port options */
7083 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7084 /* load default port options */
7085 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7087 #define TESTFRAMESIZE 40
7089 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7091 /* setup 16C32 for SDLC DMA transfer mode */
7094 usc_set_sdlc_mode(info
);
7095 usc_enable_loopback(info
,1);
7097 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7098 * field of the buffer entry after fetching buffer address. This
7099 * way we can detect a DMA failure for a DMA read (which should be
7100 * non-destructive to system memory) before we try and write to
7101 * memory (where a failure could corrupt system memory).
7104 /* Receive DMA mode Register (RDMR)
7106 * <15..14> 11 DMA mode = Linked List Buffer mode
7107 * <13> 1 RSBinA/L = store Rx status Block in List entry
7108 * <12> 0 1 = Clear count of List Entry after fetching
7109 * <11..10> 00 Address mode = Increment
7110 * <9> 1 Terminate Buffer on RxBound
7111 * <8> 0 Bus Width = 16bits
7112 * <7..0> ? status Bits (write as 0s)
7114 * 1110 0010 0000 0000 = 0xe200
7117 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7119 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7122 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7124 FrameSize
= TESTFRAMESIZE
;
7126 /* setup 1st transmit buffer entry: */
7127 /* with frame size and transmit control word */
7129 info
->tx_buffer_list
[0].count
= FrameSize
;
7130 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7131 info
->tx_buffer_list
[0].status
= 0x4000;
7133 /* build a transmit frame in 1st transmit DMA buffer */
7135 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7136 for (i
= 0; i
< FrameSize
; i
++ )
7139 /* setup 1st receive buffer entry: */
7140 /* clear status, set max receive buffer size */
7142 info
->rx_buffer_list
[0].status
= 0;
7143 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7145 /* zero out the 1st receive buffer */
7147 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7149 /* Set count field of next buffer entries to prevent */
7150 /* 16C32 from using buffers after the 1st one. */
7152 info
->tx_buffer_list
[1].count
= 0;
7153 info
->rx_buffer_list
[1].count
= 0;
7156 /***************************/
7157 /* Program 16C32 receiver. */
7158 /***************************/
7160 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7162 /* setup DMA transfers */
7163 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7165 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7166 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7167 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7168 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7170 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7171 usc_InDmaReg( info
, RDMR
);
7172 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7174 /* Enable Receiver (RMR <1..0> = 10) */
7175 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7177 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7180 /*************************************************************/
7181 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7182 /*************************************************************/
7184 /* Wait 100ms for interrupt. */
7185 EndTime
= jiffies
+ msecs_to_jiffies(100);
7188 if (time_after(jiffies
, EndTime
)) {
7193 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7194 status
= usc_InDmaReg( info
, RDMR
);
7195 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7197 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7198 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7199 /* BUSY (BIT 5) is active (channel still active). */
7200 /* This means the buffer entry read has completed. */
7206 /******************************/
7207 /* Program 16C32 transmitter. */
7208 /******************************/
7210 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7212 /* Program the Transmit Character Length Register (TCLR) */
7213 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7215 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7216 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7218 /* Program the address of the 1st DMA Buffer Entry in linked list */
7220 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7221 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7222 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7224 /* unlatch Tx status bits, and start transmit channel. */
7226 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7227 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7229 /* wait for DMA controller to fill transmit FIFO */
7231 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7233 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7236 /**********************************/
7237 /* WAIT FOR TRANSMIT FIFO TO FILL */
7238 /**********************************/
7241 EndTime
= jiffies
+ msecs_to_jiffies(100);
7244 if (time_after(jiffies
, EndTime
)) {
7249 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7250 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7251 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7253 if ( FifoLevel
< 16 )
7256 if ( FrameSize
< 32 ) {
7257 /* This frame is smaller than the entire transmit FIFO */
7258 /* so wait for the entire frame to be loaded. */
7259 if ( FifoLevel
<= (32 - FrameSize
) )
7267 /* Enable 16C32 transmitter. */
7269 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7271 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7272 usc_TCmd( info
, TCmd_SendFrame
);
7273 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7275 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7278 /******************************/
7279 /* WAIT FOR TRANSMIT COMPLETE */
7280 /******************************/
7283 EndTime
= jiffies
+ msecs_to_jiffies(100);
7285 /* While timer not expired wait for transmit complete */
7287 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7288 status
= usc_InReg( info
, TCSR
);
7289 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7291 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7292 if (time_after(jiffies
, EndTime
)) {
7297 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7298 status
= usc_InReg( info
, TCSR
);
7299 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7305 /* CHECK FOR TRANSMIT ERRORS */
7306 if ( status
& (BIT5
+ BIT1
) )
7311 /* WAIT FOR RECEIVE COMPLETE */
7314 EndTime
= jiffies
+ msecs_to_jiffies(100);
7316 /* Wait for 16C32 to write receive status to buffer entry. */
7317 status
=info
->rx_buffer_list
[0].status
;
7318 while ( status
== 0 ) {
7319 if (time_after(jiffies
, EndTime
)) {
7323 status
=info
->rx_buffer_list
[0].status
;
7329 /* CHECK FOR RECEIVE ERRORS */
7330 status
= info
->rx_buffer_list
[0].status
;
7332 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7333 /* receive error has occurred */
7336 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7337 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7343 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7345 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7347 /* restore current port options */
7348 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7352 } /* end of mgsl_dma_test() */
7354 /* mgsl_adapter_test()
7356 * Perform the register, IRQ, and DMA tests for the 16C32.
7358 * Arguments: info pointer to device instance data
7359 * Return Value: 0 if success, otherwise -ENODEV
7361 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7363 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7364 printk( "%s(%d):Testing device %s\n",
7365 __FILE__
,__LINE__
,info
->device_name
);
7367 if ( !mgsl_register_test( info
) ) {
7368 info
->init_error
= DiagStatus_AddressFailure
;
7369 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7370 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7374 if ( !mgsl_irq_test( info
) ) {
7375 info
->init_error
= DiagStatus_IrqFailure
;
7376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7377 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7381 if ( !mgsl_dma_test( info
) ) {
7382 info
->init_error
= DiagStatus_DmaFailure
;
7383 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7384 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7388 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7389 printk( "%s(%d):device %s passed diagnostics\n",
7390 __FILE__
,__LINE__
,info
->device_name
);
7394 } /* end of mgsl_adapter_test() */
7396 /* mgsl_memory_test()
7398 * Test the shared memory on a PCI adapter.
7400 * Arguments: info pointer to device instance data
7401 * Return Value: true if test passed, otherwise false
7403 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7405 static unsigned long BitPatterns
[] =
7406 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7407 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7409 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7410 unsigned long * TestAddr
;
7412 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7415 TestAddr
= (unsigned long *)info
->memory_base
;
7417 /* Test data lines with test pattern at one location. */
7419 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7420 *TestAddr
= BitPatterns
[i
];
7421 if ( *TestAddr
!= BitPatterns
[i
] )
7425 /* Test address lines with incrementing pattern over */
7426 /* entire address range. */
7428 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7433 TestAddr
= (unsigned long *)info
->memory_base
;
7435 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7436 if ( *TestAddr
!= i
* 4 )
7441 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7445 } /* End Of mgsl_memory_test() */
7448 /* mgsl_load_pci_memory()
7450 * Load a large block of data into the PCI shared memory.
7451 * Use this instead of memcpy() or memmove() to move data
7452 * into the PCI shared memory.
7456 * This function prevents the PCI9050 interface chip from hogging
7457 * the adapter local bus, which can starve the 16C32 by preventing
7458 * 16C32 bus master cycles.
7460 * The PCI9050 documentation says that the 9050 will always release
7461 * control of the local bus after completing the current read
7462 * or write operation.
7464 * It appears that as long as the PCI9050 write FIFO is full, the
7465 * PCI9050 treats all of the writes as a single burst transaction
7466 * and will not release the bus. This causes DMA latency problems
7467 * at high speeds when copying large data blocks to the shared
7470 * This function in effect, breaks the a large shared memory write
7471 * into multiple transations by interleaving a shared memory read
7472 * which will flush the write FIFO and 'complete' the write
7473 * transation. This allows any pending DMA request to gain control
7474 * of the local bus in a timely fasion.
7478 * TargetPtr pointer to target address in PCI shared memory
7479 * SourcePtr pointer to source buffer for data
7480 * count count in bytes of data to copy
7482 * Return Value: None
7484 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7485 unsigned short count
)
7487 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7488 #define PCI_LOAD_INTERVAL 64
7490 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7491 unsigned short Index
;
7492 unsigned long Dummy
;
7494 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7496 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7497 Dummy
= *((volatile unsigned long *)TargetPtr
);
7498 TargetPtr
+= PCI_LOAD_INTERVAL
;
7499 SourcePtr
+= PCI_LOAD_INTERVAL
;
7502 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7504 } /* End Of mgsl_load_pci_memory() */
7506 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7511 printk("%s tx data:\n",info
->device_name
);
7513 printk("%s rx data:\n",info
->device_name
);
7521 for(i
=0;i
<linecount
;i
++)
7522 printk("%02X ",(unsigned char)data
[i
]);
7525 for(i
=0;i
<linecount
;i
++) {
7526 if (data
[i
]>=040 && data
[i
]<=0176)
7527 printk("%c",data
[i
]);
7536 } /* end of mgsl_trace_block() */
7538 /* mgsl_tx_timeout()
7540 * called when HDLC frame times out
7541 * update stats and do tx completion processing
7543 * Arguments: context pointer to device instance data
7544 * Return Value: None
7546 static void mgsl_tx_timeout(unsigned long context
)
7548 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7549 unsigned long flags
;
7551 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7552 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7553 __FILE__
,__LINE__
,info
->device_name
);
7554 if(info
->tx_active
&&
7555 (info
->params
.mode
== MGSL_MODE_HDLC
||
7556 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7557 info
->icount
.txtimeout
++;
7559 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7560 info
->tx_active
= false;
7561 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7563 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7564 usc_loopmode_cancel_transmit( info
);
7566 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7568 #if SYNCLINK_GENERIC_HDLC
7570 hdlcdev_tx_done(info
);
7573 mgsl_bh_transmit(info
);
7575 } /* end of mgsl_tx_timeout() */
7577 /* signal that there are no more frames to send, so that
7578 * line is 'released' by echoing RxD to TxD when current
7579 * transmission is complete (or immediately if no tx in progress).
7581 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7583 unsigned long flags
;
7585 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7586 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7587 if (info
->tx_active
)
7588 info
->loopmode_send_done_requested
= true;
7590 usc_loopmode_send_done(info
);
7592 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7597 /* release the line by echoing RxD to TxD
7598 * upon completion of a transmit frame
7600 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7602 info
->loopmode_send_done_requested
= false;
7603 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7604 info
->cmr_value
&= ~BIT13
;
7605 usc_OutReg(info
, CMR
, info
->cmr_value
);
7608 /* abort a transmit in progress while in HDLC LoopMode
7610 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7612 /* reset tx dma channel and purge TxFifo */
7613 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7614 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7615 usc_loopmode_send_done( info
);
7618 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7619 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7620 * we must clear CMR:13 to begin repeating TxData to RxData
7622 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7624 info
->loopmode_insert_requested
= true;
7626 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7627 * begin repeating TxData on RxData (complete insertion)
7629 usc_OutReg( info
, RICR
,
7630 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7632 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7633 info
->cmr_value
|= BIT13
;
7634 usc_OutReg(info
, CMR
, info
->cmr_value
);
7637 /* return 1 if station is inserted into the loop, otherwise 0
7639 static int usc_loopmode_active( struct mgsl_struct
* info
)
7641 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7644 #if SYNCLINK_GENERIC_HDLC
7647 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7648 * set encoding and frame check sequence (FCS) options
7650 * dev pointer to network device structure
7651 * encoding serial encoding setting
7652 * parity FCS setting
7654 * returns 0 if success, otherwise error code
7656 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7657 unsigned short parity
)
7659 struct mgsl_struct
*info
= dev_to_port(dev
);
7660 unsigned char new_encoding
;
7661 unsigned short new_crctype
;
7663 /* return error if TTY interface open */
7664 if (info
->port
.count
)
7669 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7670 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7671 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7672 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7673 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7674 default: return -EINVAL
;
7679 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7680 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7681 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7682 default: return -EINVAL
;
7685 info
->params
.encoding
= new_encoding
;
7686 info
->params
.crc_type
= new_crctype
;
7688 /* if network interface up, reprogram hardware */
7690 mgsl_program_hw(info
);
7696 * called by generic HDLC layer to send frame
7698 * skb socket buffer containing HDLC frame
7699 * dev pointer to network device structure
7701 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
7702 struct net_device
*dev
)
7704 struct mgsl_struct
*info
= dev_to_port(dev
);
7705 unsigned long flags
;
7707 if (debug_level
>= DEBUG_LEVEL_INFO
)
7708 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7710 /* stop sending until this frame completes */
7711 netif_stop_queue(dev
);
7713 /* copy data to device buffers */
7714 info
->xmit_cnt
= skb
->len
;
7715 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7717 /* update network statistics */
7718 dev
->stats
.tx_packets
++;
7719 dev
->stats
.tx_bytes
+= skb
->len
;
7721 /* done with socket buffer, so free it */
7724 /* save start time for transmit timeout detection */
7725 dev
->trans_start
= jiffies
;
7727 /* start hardware transmitter if necessary */
7728 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7729 if (!info
->tx_active
)
7730 usc_start_transmitter(info
);
7731 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7733 return NETDEV_TX_OK
;
7737 * called by network layer when interface enabled
7738 * claim resources and initialize hardware
7740 * dev pointer to network device structure
7742 * returns 0 if success, otherwise error code
7744 static int hdlcdev_open(struct net_device
*dev
)
7746 struct mgsl_struct
*info
= dev_to_port(dev
);
7748 unsigned long flags
;
7750 if (debug_level
>= DEBUG_LEVEL_INFO
)
7751 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7753 /* generic HDLC layer open processing */
7754 if ((rc
= hdlc_open(dev
)))
7757 /* arbitrate between network and tty opens */
7758 spin_lock_irqsave(&info
->netlock
, flags
);
7759 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7760 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7761 spin_unlock_irqrestore(&info
->netlock
, flags
);
7765 spin_unlock_irqrestore(&info
->netlock
, flags
);
7767 /* claim resources and init adapter */
7768 if ((rc
= startup(info
)) != 0) {
7769 spin_lock_irqsave(&info
->netlock
, flags
);
7771 spin_unlock_irqrestore(&info
->netlock
, flags
);
7775 /* assert DTR and RTS, apply hardware settings */
7776 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7777 mgsl_program_hw(info
);
7779 /* enable network layer transmit */
7780 dev
->trans_start
= jiffies
;
7781 netif_start_queue(dev
);
7783 /* inform generic HDLC layer of current DCD status */
7784 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7785 usc_get_serial_signals(info
);
7786 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7787 if (info
->serial_signals
& SerialSignal_DCD
)
7788 netif_carrier_on(dev
);
7790 netif_carrier_off(dev
);
7795 * called by network layer when interface is disabled
7796 * shutdown hardware and release resources
7798 * dev pointer to network device structure
7800 * returns 0 if success, otherwise error code
7802 static int hdlcdev_close(struct net_device
*dev
)
7804 struct mgsl_struct
*info
= dev_to_port(dev
);
7805 unsigned long flags
;
7807 if (debug_level
>= DEBUG_LEVEL_INFO
)
7808 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7810 netif_stop_queue(dev
);
7812 /* shutdown adapter and release resources */
7817 spin_lock_irqsave(&info
->netlock
, flags
);
7819 spin_unlock_irqrestore(&info
->netlock
, flags
);
7825 * called by network layer to process IOCTL call to network device
7827 * dev pointer to network device structure
7828 * ifr pointer to network interface request structure
7829 * cmd IOCTL command code
7831 * returns 0 if success, otherwise error code
7833 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7835 const size_t size
= sizeof(sync_serial_settings
);
7836 sync_serial_settings new_line
;
7837 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7838 struct mgsl_struct
*info
= dev_to_port(dev
);
7841 if (debug_level
>= DEBUG_LEVEL_INFO
)
7842 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7844 /* return error if TTY interface open */
7845 if (info
->port
.count
)
7848 if (cmd
!= SIOCWANDEV
)
7849 return hdlc_ioctl(dev
, ifr
, cmd
);
7851 switch(ifr
->ifr_settings
.type
) {
7852 case IF_GET_IFACE
: /* return current sync_serial_settings */
7854 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7855 if (ifr
->ifr_settings
.size
< size
) {
7856 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7860 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7861 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7862 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7863 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7866 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7867 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7868 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7869 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7870 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7873 new_line
.clock_rate
= info
->params
.clock_speed
;
7874 new_line
.loopback
= info
->params
.loopback
? 1:0;
7876 if (copy_to_user(line
, &new_line
, size
))
7880 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7882 if(!capable(CAP_NET_ADMIN
))
7884 if (copy_from_user(&new_line
, line
, size
))
7887 switch (new_line
.clock_type
)
7889 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7890 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7891 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7892 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7893 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7894 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7895 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7896 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7897 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7898 default: return -EINVAL
;
7901 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7904 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7905 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7906 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7907 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7908 info
->params
.flags
|= flags
;
7910 info
->params
.loopback
= new_line
.loopback
;
7912 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7913 info
->params
.clock_speed
= new_line
.clock_rate
;
7915 info
->params
.clock_speed
= 0;
7917 /* if network interface up, reprogram hardware */
7919 mgsl_program_hw(info
);
7923 return hdlc_ioctl(dev
, ifr
, cmd
);
7928 * called by network layer when transmit timeout is detected
7930 * dev pointer to network device structure
7932 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7934 struct mgsl_struct
*info
= dev_to_port(dev
);
7935 unsigned long flags
;
7937 if (debug_level
>= DEBUG_LEVEL_INFO
)
7938 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7940 dev
->stats
.tx_errors
++;
7941 dev
->stats
.tx_aborted_errors
++;
7943 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7944 usc_stop_transmitter(info
);
7945 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7947 netif_wake_queue(dev
);
7951 * called by device driver when transmit completes
7952 * reenable network layer transmit if stopped
7954 * info pointer to device instance information
7956 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
7958 if (netif_queue_stopped(info
->netdev
))
7959 netif_wake_queue(info
->netdev
);
7963 * called by device driver when frame received
7964 * pass frame to network layer
7966 * info pointer to device instance information
7967 * buf pointer to buffer contianing frame data
7968 * size count of data bytes in buf
7970 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
7972 struct sk_buff
*skb
= dev_alloc_skb(size
);
7973 struct net_device
*dev
= info
->netdev
;
7975 if (debug_level
>= DEBUG_LEVEL_INFO
)
7976 printk("hdlcdev_rx(%s)\n", dev
->name
);
7979 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
7981 dev
->stats
.rx_dropped
++;
7985 memcpy(skb_put(skb
, size
), buf
, size
);
7987 skb
->protocol
= hdlc_type_trans(skb
, dev
);
7989 dev
->stats
.rx_packets
++;
7990 dev
->stats
.rx_bytes
+= size
;
7995 static const struct net_device_ops hdlcdev_ops
= {
7996 .ndo_open
= hdlcdev_open
,
7997 .ndo_stop
= hdlcdev_close
,
7998 .ndo_change_mtu
= hdlc_change_mtu
,
7999 .ndo_start_xmit
= hdlc_start_xmit
,
8000 .ndo_do_ioctl
= hdlcdev_ioctl
,
8001 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
8005 * called by device driver when adding device instance
8006 * do generic HDLC initialization
8008 * info pointer to device instance information
8010 * returns 0 if success, otherwise error code
8012 static int hdlcdev_init(struct mgsl_struct
*info
)
8015 struct net_device
*dev
;
8018 /* allocate and initialize network and HDLC layer objects */
8020 if (!(dev
= alloc_hdlcdev(info
))) {
8021 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8025 /* for network layer reporting purposes only */
8026 dev
->base_addr
= info
->io_base
;
8027 dev
->irq
= info
->irq_level
;
8028 dev
->dma
= info
->dma_level
;
8030 /* network layer callbacks and settings */
8031 dev
->netdev_ops
= &hdlcdev_ops
;
8032 dev
->watchdog_timeo
= 10 * HZ
;
8033 dev
->tx_queue_len
= 50;
8035 /* generic HDLC layer callbacks and settings */
8036 hdlc
= dev_to_hdlc(dev
);
8037 hdlc
->attach
= hdlcdev_attach
;
8038 hdlc
->xmit
= hdlcdev_xmit
;
8040 /* register objects with HDLC layer */
8041 if ((rc
= register_hdlc_device(dev
))) {
8042 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8052 * called by device driver when removing device instance
8053 * do generic HDLC cleanup
8055 * info pointer to device instance information
8057 static void hdlcdev_exit(struct mgsl_struct
*info
)
8059 unregister_hdlc_device(info
->netdev
);
8060 free_netdev(info
->netdev
);
8061 info
->netdev
= NULL
;
8064 #endif /* CONFIG_HDLC */
8067 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8068 const struct pci_device_id
*ent
)
8070 struct mgsl_struct
*info
;
8072 if (pci_enable_device(dev
)) {
8073 printk("error enabling pci device %p\n", dev
);
8077 if (!(info
= mgsl_allocate_device())) {
8078 printk("can't allocate device instance data.\n");
8082 /* Copy user configuration info to device instance data */
8084 info
->io_base
= pci_resource_start(dev
, 2);
8085 info
->irq_level
= dev
->irq
;
8086 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8088 /* Because veremap only works on page boundaries we must map
8089 * a larger area than is actually implemented for the LCR
8090 * memory range. We map a full page starting at the page boundary.
8092 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8093 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8094 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8096 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8097 info
->io_addr_size
= 8;
8098 info
->irq_flags
= IRQF_SHARED
;
8100 if (dev
->device
== 0x0210) {
8101 /* Version 1 PCI9030 based universal PCI adapter */
8102 info
->misc_ctrl_value
= 0x007c4080;
8103 info
->hw_version
= 1;
8105 /* Version 0 PCI9050 based 5V PCI adapter
8106 * A PCI9050 bug prevents reading LCR registers if
8107 * LCR base address bit 7 is set. Maintain shadow
8108 * value so we can write to LCR misc control reg.
8110 info
->misc_ctrl_value
= 0x087e4546;
8111 info
->hw_version
= 0;
8114 mgsl_add_device(info
);
8119 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)