drivers/ata/sata_qstor.c

   1 /*
   2  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Pacific Digital Corporation.
   7  *  (OSL/GPL code release authorized by Jalil Fadavi).
   8  *
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; see the file COPYING.  If not, write to
  22  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  *
  25  *  libata documentation is available via 'make {ps|pdf}docs',
  26  *  as Documentation/DocBook/libata.*
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/gfp.h>
  33 #include <linux/pci.h>
  34 #include <linux/init.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/device.h>
  39 #include <scsi/scsi_host.h>
  40 #include <linux/libata.h>
  41
  42 #define DRV_NAME        "sata_qstor"
  43 #define DRV_VERSION     "0.09"
  44
  45 enum {
  46         QS_MMIO_BAR             = 4,
  47
  48         QS_PORTS                = 4,
  49         QS_MAX_PRD              = LIBATA_MAX_PRD,
  50         QS_CPB_ORDER            = 6,
  51         QS_CPB_BYTES            = (1 << QS_CPB_ORDER),
  52         QS_PRD_BYTES            = QS_MAX_PRD * 16,
  53         QS_PKT_BYTES            = QS_CPB_BYTES + QS_PRD_BYTES,
  54
  55         /* global register offsets */
  56         QS_HCF_CNFG3            = 0x0003, /* host configuration offset */
  57         QS_HID_HPHY             = 0x0004, /* host physical interface info */
  58         QS_HCT_CTRL             = 0x00e4, /* global interrupt mask offset */
  59         QS_HST_SFF              = 0x0100, /* host status fifo offset */
  60         QS_HVS_SERD3            = 0x0393, /* PHY enable offset */
  61
  62         /* global control bits */
  63         QS_HPHY_64BIT           = (1 << 1), /* 64-bit bus detected */
  64         QS_CNFG3_GSRST          = 0x01,     /* global chip reset */
  65         QS_SERD3_PHY_ENA        = 0xf0,     /* PHY detection ENAble*/
  66
  67         /* per-channel register offsets */
  68         QS_CCF_CPBA             = 0x0710, /* chan CPB base address */
  69         QS_CCF_CSEP             = 0x0718, /* chan CPB separation factor */
  70         QS_CFC_HUFT             = 0x0800, /* host upstream fifo threshold */
  71         QS_CFC_HDFT             = 0x0804, /* host downstream fifo threshold */
  72         QS_CFC_DUFT             = 0x0808, /* dev upstream fifo threshold */
  73         QS_CFC_DDFT             = 0x080c, /* dev downstream fifo threshold */
  74         QS_CCT_CTR0             = 0x0900, /* chan control-0 offset */
  75         QS_CCT_CTR1             = 0x0901, /* chan control-1 offset */
  76         QS_CCT_CFF              = 0x0a00, /* chan command fifo offset */
  77
  78         /* channel control bits */
  79         QS_CTR0_REG             = (1 << 1),   /* register mode (vs. pkt mode) */
  80         QS_CTR0_CLER            = (1 << 2),   /* clear channel errors */
  81         QS_CTR1_RDEV            = (1 << 1),   /* sata phy/comms reset */
  82         QS_CTR1_RCHN            = (1 << 4),   /* reset channel logic */
  83         QS_CCF_RUN_PKT          = 0x107,      /* RUN a new dma PKT */
  84
  85         /* pkt sub-field headers */
  86         QS_HCB_HDR              = 0x01,   /* Host Control Block header */
  87         QS_DCB_HDR              = 0x02,   /* Device Control Block header */
  88
  89         /* pkt HCB flag bits */
  90         QS_HF_DIRO              = (1 << 0),   /* data DIRection Out */
  91         QS_HF_DAT               = (1 << 3),   /* DATa pkt */
  92         QS_HF_IEN               = (1 << 4),   /* Interrupt ENable */
  93         QS_HF_VLD               = (1 << 5),   /* VaLiD pkt */
  94
  95         /* pkt DCB flag bits */
  96         QS_DF_PORD              = (1 << 2),   /* Pio OR Dma */
  97         QS_DF_ELBA              = (1 << 3),   /* Extended LBA (lba48) */
  98
  99         /* PCI device IDs */
 100         board_2068_idx          = 0,    /* QStor 4-port SATA/RAID */
 101 };
 102
 103 enum {
 104         QS_DMA_BOUNDARY         = ~0UL
 105 };
 106
 107 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
 108
 109 struct qs_port_priv {
 110         u8                      *pkt;
 111         dma_addr_t              pkt_dma;
 112         qs_state_t              state;
 113 };
 114
 115 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
 116 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
 117 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 118 static int qs_port_start(struct ata_port *ap);
 119 static void qs_host_stop(struct ata_host *host);
 120 static void qs_qc_prep(struct ata_queued_cmd *qc);
 121 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
 122 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
 123 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
 124 static u8 qs_bmdma_status(struct ata_port *ap);
 125 static void qs_freeze(struct ata_port *ap);
 126 static void qs_thaw(struct ata_port *ap);
 127 static int qs_prereset(struct ata_link *link, unsigned long deadline);
 128 static void qs_error_handler(struct ata_port *ap);
 129
 130 static struct scsi_host_template qs_ata_sht = {
 131         ATA_BASE_SHT(DRV_NAME),
 132         .sg_tablesize           = QS_MAX_PRD,
 133         .dma_boundary           = QS_DMA_BOUNDARY,
 134 };
 135
 136 static struct ata_port_operations qs_ata_ops = {
 137         .inherits               = &ata_sff_port_ops,
 138
 139         .check_atapi_dma        = qs_check_atapi_dma,
 140         .bmdma_stop             = qs_bmdma_stop,
 141         .bmdma_status           = qs_bmdma_status,
 142         .qc_prep                = qs_qc_prep,
 143         .qc_issue               = qs_qc_issue,
 144
 145         .freeze                 = qs_freeze,
 146         .thaw                   = qs_thaw,
 147         .prereset               = qs_prereset,
 148         .softreset              = ATA_OP_NULL,
 149         .error_handler          = qs_error_handler,
 150         .lost_interrupt         = ATA_OP_NULL,
 151
 152         .scr_read               = qs_scr_read,
 153         .scr_write              = qs_scr_write,
 154
 155         .port_start             = qs_port_start,
 156         .host_stop              = qs_host_stop,
 157 };
 158
 159 static const struct ata_port_info qs_port_info[] = {
 160         /* board_2068_idx */
 161         {
 162                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 163                                   ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
 164                 .pio_mask       = ATA_PIO4_ONLY,
 165                 .udma_mask      = ATA_UDMA6,
 166                 .port_ops       = &qs_ata_ops,
 167         },
 168 };
 169
 170 static const struct pci_device_id qs_ata_pci_tbl[] = {
 171         { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
 172
 173         { }     /* terminate list */
 174 };
 175
 176 static struct pci_driver qs_ata_pci_driver = {
 177         .name                   = DRV_NAME,
 178         .id_table               = qs_ata_pci_tbl,
 179         .probe                  = qs_ata_init_one,
 180         .remove                 = ata_pci_remove_one,
 181 };
 182
 183 static void __iomem *qs_mmio_base(struct ata_host *host)
 184 {
 185         return host->iomap[QS_MMIO_BAR];
 186 }
 187
 188 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
 189 {
 190         return 1;       /* ATAPI DMA not supported */
 191 }
 192
 193 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
 194 {
 195         /* nothing */
 196 }
 197
 198 static u8 qs_bmdma_status(struct ata_port *ap)
 199 {
 200         return 0;
 201 }
 202
 203 static inline void qs_enter_reg_mode(struct ata_port *ap)
 204 {
 205         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 206         struct qs_port_priv *pp = ap->private_data;
 207
 208         pp->state = qs_state_mmio;
 209         writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 210         readb(chan + QS_CCT_CTR0);        /* flush */
 211 }
 212
 213 static inline void qs_reset_channel_logic(struct ata_port *ap)
 214 {
 215         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 216
 217         writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 218         readb(chan + QS_CCT_CTR0);        /* flush */
 219         qs_enter_reg_mode(ap);
 220 }
 221
 222 static void qs_freeze(struct ata_port *ap)
 223 {
 224         u8 __iomem *mmio_base = qs_mmio_base(ap->host);
 225
 226         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 227         qs_enter_reg_mode(ap);
 228 }
 229
 230 static void qs_thaw(struct ata_port *ap)
 231 {
 232         u8 __iomem *mmio_base = qs_mmio_base(ap->host);
 233
 234         qs_enter_reg_mode(ap);
 235         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 236 }
 237
 238 static int qs_prereset(struct ata_link *link, unsigned long deadline)
 239 {
 240         struct ata_port *ap = link->ap;
 241
 242         qs_reset_channel_logic(ap);
 243         return ata_sff_prereset(link, deadline);
 244 }
 245
 246 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 247 {
 248         if (sc_reg > SCR_CONTROL)
 249                 return -EINVAL;
 250         *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
 251         return 0;
 252 }
 253
 254 static void qs_error_handler(struct ata_port *ap)
 255 {
 256         qs_enter_reg_mode(ap);
 257         ata_sff_error_handler(ap);
 258 }
 259
 260 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
 261 {
 262         if (sc_reg > SCR_CONTROL)
 263                 return -EINVAL;
 264         writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
 265         return 0;
 266 }
 267
 268 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
 269 {
 270         struct scatterlist *sg;
 271         struct ata_port *ap = qc->ap;
 272         struct qs_port_priv *pp = ap->private_data;
 273         u8 *prd = pp->pkt + QS_CPB_BYTES;
 274         unsigned int si;
 275
 276         for_each_sg(qc->sg, sg, qc->n_elem, si) {
 277                 u64 addr;
 278                 u32 len;
 279
 280                 addr = sg_dma_address(sg);
 281                 *(__le64 *)prd = cpu_to_le64(addr);
 282                 prd += sizeof(u64);
 283
 284                 len = sg_dma_len(sg);
 285                 *(__le32 *)prd = cpu_to_le32(len);
 286                 prd += sizeof(u64);
 287
 288                 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
 289                                         (unsigned long long)addr, len);
 290         }
 291
 292         return si;
 293 }
 294
 295 static void qs_qc_prep(struct ata_queued_cmd *qc)
 296 {
 297         struct qs_port_priv *pp = qc->ap->private_data;
 298         u8 dflags = QS_DF_PORD, *buf = pp->pkt;
 299         u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
 300         u64 addr;
 301         unsigned int nelem;
 302
 303         VPRINTK("ENTER\n");
 304
 305         qs_enter_reg_mode(qc->ap);
 306         if (qc->tf.protocol != ATA_PROT_DMA)
 307                 return;
 308
 309         nelem = qs_fill_sg(qc);
 310
 311         if ((qc->tf.flags & ATA_TFLAG_WRITE))
 312                 hflags |= QS_HF_DIRO;
 313         if ((qc->tf.flags & ATA_TFLAG_LBA48))
 314                 dflags |= QS_DF_ELBA;
 315
 316         /* host control block (HCB) */
 317         buf[ 0] = QS_HCB_HDR;
 318         buf[ 1] = hflags;
 319         *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
 320         *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
 321         addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
 322         *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
 323
 324         /* device control block (DCB) */
 325         buf[24] = QS_DCB_HDR;
 326         buf[28] = dflags;
 327
 328         /* frame information structure (FIS) */
 329         ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
 330 }
 331
 332 static inline void qs_packet_start(struct ata_queued_cmd *qc)
 333 {
 334         struct ata_port *ap = qc->ap;
 335         u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 336
 337         VPRINTK("ENTER, ap %p\n", ap);
 338
 339         writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
 340         wmb();                             /* flush PRDs and pkt to memory */
 341         writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
 342         readl(chan + QS_CCT_CFF);          /* flush */
 343 }
 344
 345 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
 346 {
 347         struct qs_port_priv *pp = qc->ap->private_data;
 348
 349         switch (qc->tf.protocol) {
 350         case ATA_PROT_DMA:
 351                 pp->state = qs_state_pkt;
 352                 qs_packet_start(qc);
 353                 return 0;
 354
 355         case ATAPI_PROT_DMA:
 356                 BUG();
 357                 break;
 358
 359         default:
 360                 break;
 361         }
 362
 363         pp->state = qs_state_mmio;
 364         return ata_sff_qc_issue(qc);
 365 }
 366
 367 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
 368 {
 369         qc->err_mask |= ac_err_mask(status);
 370
 371         if (!qc->err_mask) {
 372                 ata_qc_complete(qc);
 373         } else {
 374                 struct ata_port    *ap  = qc->ap;
 375                 struct ata_eh_info *ehi = &ap->link.eh_info;
 376
 377                 ata_ehi_clear_desc(ehi);
 378                 ata_ehi_push_desc(ehi, "status 0x%02X", status);
 379
 380                 if (qc->err_mask == AC_ERR_DEV)
 381                         ata_port_abort(ap);
 382                 else
 383                         ata_port_freeze(ap);
 384         }
 385 }
 386
 387 static inline unsigned int qs_intr_pkt(struct ata_host *host)
 388 {
 389         unsigned int handled = 0;
 390         u8 sFFE;
 391         u8 __iomem *mmio_base = qs_mmio_base(host);
 392
 393         do {
 394                 u32 sff0 = readl(mmio_base + QS_HST_SFF);
 395                 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
 396                 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
 397                 sFFE  = sff1 >> 31;             /* empty flag */
 398
 399                 if (sEVLD) {
 400                         u8 sDST = sff0 >> 16;   /* dev status */
 401                         u8 sHST = sff1 & 0x3f;  /* host status */
 402                         unsigned int port_no = (sff1 >> 8) & 0x03;
 403                         struct ata_port *ap = host->ports[port_no];
 404                         struct qs_port_priv *pp = ap->private_data;
 405                         struct ata_queued_cmd *qc;
 406
 407                         DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
 408                                         sff1, sff0, port_no, sHST, sDST);
 409                         handled = 1;
 410                         if (!pp || pp->state != qs_state_pkt)
 411                                 continue;
 412                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
 413                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 414                                 switch (sHST) {
 415                                 case 0: /* successful CPB */
 416                                 case 3: /* device error */
 417                                         qs_enter_reg_mode(qc->ap);
 418                                         qs_do_or_die(qc, sDST);
 419                                         break;
 420                                 default:
 421                                         break;
 422                                 }
 423                         }
 424                 }
 425         } while (!sFFE);
 426         return handled;
 427 }
 428
 429 static inline unsigned int qs_intr_mmio(struct ata_host *host)
 430 {
 431         unsigned int handled = 0, port_no;
 432
 433         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 434                 struct ata_port *ap = host->ports[port_no];
 435                 struct qs_port_priv *pp = ap->private_data;
 436                 struct ata_queued_cmd *qc;
 437
 438                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 439                 if (!qc) {
 440                         /*
 441                          * The qstor hardware generates spurious
 442                          * interrupts from time to time when switching
 443                          * in and out of packet mode.  There's no
 444                          * obvious way to know if we're here now due
 445                          * to that, so just ack the irq and pretend we
 446                          * knew it was ours.. (ugh).  This does not
 447                          * affect packet mode.
 448                          */
 449                         ata_sff_check_status(ap);
 450                         handled = 1;
 451                         continue;
 452                 }
 453
 454                 if (!pp || pp->state != qs_state_mmio)
 455                         continue;
 456                 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
 457                         handled |= ata_sff_port_intr(ap, qc);
 458         }
 459         return handled;
 460 }
 461
 462 static irqreturn_t qs_intr(int irq, void *dev_instance)
 463 {
 464         struct ata_host *host = dev_instance;
 465         unsigned int handled = 0;
 466         unsigned long flags;
 467
 468         VPRINTK("ENTER\n");
 469
 470         spin_lock_irqsave(&host->lock, flags);
 471         handled  = qs_intr_pkt(host) | qs_intr_mmio(host);
 472         spin_unlock_irqrestore(&host->lock, flags);
 473
 474         VPRINTK("EXIT\n");
 475
 476         return IRQ_RETVAL(handled);
 477 }
 478
 479 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 480 {
 481         port->cmd_addr          =
 482         port->data_addr         = base + 0x400;
 483         port->error_addr        =
 484         port->feature_addr      = base + 0x408; /* hob_feature = 0x409 */
 485         port->nsect_addr        = base + 0x410; /* hob_nsect   = 0x411 */
 486         port->lbal_addr         = base + 0x418; /* hob_lbal    = 0x419 */
 487         port->lbam_addr         = base + 0x420; /* hob_lbam    = 0x421 */
 488         port->lbah_addr         = base + 0x428; /* hob_lbah    = 0x429 */
 489         port->device_addr       = base + 0x430;
 490         port->status_addr       =
 491         port->command_addr      = base + 0x438;
 492         port->altstatus_addr    =
 493         port->ctl_addr          = base + 0x440;
 494         port->scr_addr          = base + 0xc00;
 495 }
 496
 497 static int qs_port_start(struct ata_port *ap)
 498 {
 499         struct device *dev = ap->host->dev;
 500         struct qs_port_priv *pp;
 501         void __iomem *mmio_base = qs_mmio_base(ap->host);
 502         void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
 503         u64 addr;
 504
 505         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 506         if (!pp)
 507                 return -ENOMEM;
 508         pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
 509                                       GFP_KERNEL);
 510         if (!pp->pkt)
 511                 return -ENOMEM;
 512         memset(pp->pkt, 0, QS_PKT_BYTES);
 513         ap->private_data = pp;
 514
 515         qs_enter_reg_mode(ap);
 516         addr = (u64)pp->pkt_dma;
 517         writel((u32) addr,        chan + QS_CCF_CPBA);
 518         writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
 519         return 0;
 520 }
 521
 522 static void qs_host_stop(struct ata_host *host)
 523 {
 524         void __iomem *mmio_base = qs_mmio_base(host);
 525
 526         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 527         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 528 }
 529
 530 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
 531 {
 532         void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
 533         unsigned int port_no;
 534
 535         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 536         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 537
 538         /* reset each channel in turn */
 539         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 540                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 541                 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 542                 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 543                 readb(chan + QS_CCT_CTR0);        /* flush */
 544         }
 545         writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
 546
 547         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 548                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 549                 /* set FIFO depths to same settings as Windows driver */
 550                 writew(32, chan + QS_CFC_HUFT);
 551                 writew(32, chan + QS_CFC_HDFT);
 552                 writew(10, chan + QS_CFC_DUFT);
 553                 writew( 8, chan + QS_CFC_DDFT);
 554                 /* set CPB size in bytes, as a power of two */
 555                 writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
 556         }
 557         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 558 }
 559
 560 /*
 561  * The QStor understands 64-bit buses, and uses 64-bit fields
 562  * for DMA pointers regardless of bus width.  We just have to
 563  * make sure our DMA masks are set appropriately for whatever
 564  * bridge lies between us and the QStor, and then the DMA mapping
 565  * code will ensure we only ever "see" appropriate buffer addresses.
 566  * If we're 32-bit limited somewhere, then our 64-bit fields will
 567  * just end up with zeros in the upper 32-bits, without any special
 568  * logic required outside of this routine (below).
 569  */
 570 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 571 {
 572         u32 bus_info = readl(mmio_base + QS_HID_HPHY);
 573         int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
 574
 575         if (have_64bit_bus &&
 576             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 577                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 578                 if (rc) {
 579                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 580                         if (rc) {
 581                                 dev_printk(KERN_ERR, &pdev->dev,
 582                                            "64-bit DMA enable failed\n");
 583                                 return rc;
 584                         }
 585                 }
 586         } else {
 587                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 588                 if (rc) {
 589                         dev_printk(KERN_ERR, &pdev->dev,
 590                                 "32-bit DMA enable failed\n");
 591                         return rc;
 592                 }
 593                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 594                 if (rc) {
 595                         dev_printk(KERN_ERR, &pdev->dev,
 596                                 "32-bit consistent DMA enable failed\n");
 597                         return rc;
 598                 }
 599         }
 600         return 0;
 601 }
 602
 603 static int qs_ata_init_one(struct pci_dev *pdev,
 604                                 const struct pci_device_id *ent)
 605 {
 606         static int printed_version;
 607         unsigned int board_idx = (unsigned int) ent->driver_data;
 608         const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
 609         struct ata_host *host;
 610         int rc, port_no;
 611
 612         if (!printed_version++)
 613                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 614
 615         /* alloc host */
 616         host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
 617         if (!host)
 618                 return -ENOMEM;
 619
 620         /* acquire resources and fill host */
 621         rc = pcim_enable_device(pdev);
 622         if (rc)
 623                 return rc;
 624
 625         if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
 626                 return -ENODEV;
 627
 628         rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
 629         if (rc)
 630                 return rc;
 631         host->iomap = pcim_iomap_table(pdev);
 632
 633         rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
 634         if (rc)
 635                 return rc;
 636
 637         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 638                 struct ata_port *ap = host->ports[port_no];
 639                 unsigned int offset = port_no * 0x4000;
 640                 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
 641
 642                 qs_ata_setup_port(&ap->ioaddr, chan);
 643
 644                 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
 645                 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
 646         }
 647
 648         /* initialize adapter */
 649         qs_host_init(host, board_idx);
 650
 651         pci_set_master(pdev);
 652         return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
 653                                  &qs_ata_sht);
 654 }
 655
 656 static int __init qs_ata_init(void)
 657 {
 658         return pci_register_driver(&qs_ata_pci_driver);
 659 }
 660
 661 static void __exit qs_ata_exit(void)
 662 {
 663         pci_unregister_driver(&qs_ata_pci_driver);
 664 }
 665
 666 MODULE_AUTHOR("Mark Lord");
 667 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
 668 MODULE_LICENSE("GPL");
 669 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
 670 MODULE_VERSION(DRV_VERSION);
 671
 672 module_init(qs_ata_init);
 673 module_exit(qs_ata_exit);