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Revert "drm/i915: Warn if we run out of FIFO space for a mode"
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob7c9103030036d5ca12d0f534d940ef219e02fe94
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
752
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
757 return true;
758 }
759 }
760 return false;
761 }
762
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 /**
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
767 */
768
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
770 {
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
773
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
792 */
793 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
794 INTELPllInvalid ("dot out of range\n");
795
796 return true;
797 }
798
799 static bool
800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
801 int target, int refclk, intel_clock_t *best_clock)
802
803 {
804 struct drm_device *dev = crtc->dev;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 intel_clock_t clock;
807 int err = target;
808
809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
810 (I915_READ(LVDS)) != 0) {
811 /*
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
815 * even can.
816 */
817 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
818 LVDS_CLKB_POWER_UP)
819 clock.p2 = limit->p2.p2_fast;
820 else
821 clock.p2 = limit->p2.p2_slow;
822 } else {
823 if (target < limit->p2.dot_limit)
824 clock.p2 = limit->p2.p2_slow;
825 else
826 clock.p2 = limit->p2.p2_fast;
827 }
828
829 memset (best_clock, 0, sizeof (*best_clock));
830
831 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
832 clock.m1++) {
833 for (clock.m2 = limit->m2.min;
834 clock.m2 <= limit->m2.max; clock.m2++) {
835 /* m1 is always 0 in Pineview */
836 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
837 break;
838 for (clock.n = limit->n.min;
839 clock.n <= limit->n.max; clock.n++) {
840 for (clock.p1 = limit->p1.min;
841 clock.p1 <= limit->p1.max; clock.p1++) {
842 int this_err;
843
844 intel_clock(dev, refclk, &clock);
845
846 if (!intel_PLL_is_valid(crtc, &clock))
847 continue;
848
849 this_err = abs(clock.dot - target);
850 if (this_err < err) {
851 *best_clock = clock;
852 err = this_err;
853 }
854 }
855 }
856 }
857 }
858
859 return (err != target);
860 }
861
862 static bool
863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc->dev;
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 intel_clock_t clock;
869 int max_n;
870 bool found;
871 /* approximately equals target * 0.00585 */
872 int err_most = (target >> 8) + (target >> 9);
873 found = false;
874
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
876 int lvds_reg;
877
878 if (HAS_PCH_SPLIT(dev))
879 lvds_reg = PCH_LVDS;
880 else
881 lvds_reg = LVDS;
882 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
883 LVDS_CLKB_POWER_UP)
884 clock.p2 = limit->p2.p2_fast;
885 else
886 clock.p2 = limit->p2.p2_slow;
887 } else {
888 if (target < limit->p2.dot_limit)
889 clock.p2 = limit->p2.p2_slow;
890 else
891 clock.p2 = limit->p2.p2_fast;
892 }
893
894 memset(best_clock, 0, sizeof(*best_clock));
895 max_n = limit->n.max;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock.m1 = limit->m1.max;
900 clock.m1 >= limit->m1.min; clock.m1--) {
901 for (clock.m2 = limit->m2.max;
902 clock.m2 >= limit->m2.min; clock.m2--) {
903 for (clock.p1 = limit->p1.max;
904 clock.p1 >= limit->p1.min; clock.p1--) {
905 int this_err;
906
907 intel_clock(dev, refclk, &clock);
908 if (!intel_PLL_is_valid(crtc, &clock))
909 continue;
910 this_err = abs(clock.dot - target) ;
911 if (this_err < err_most) {
912 *best_clock = clock;
913 err_most = this_err;
914 max_n = clock.n;
915 found = true;
916 }
917 }
918 }
919 }
920 }
921 return found;
922 }
923
924 static bool
925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
926 int target, int refclk, intel_clock_t *best_clock)
927 {
928 struct drm_device *dev = crtc->dev;
929 intel_clock_t clock;
930
931 /* return directly when it is eDP */
932 if (HAS_eDP)
933 return true;
934
935 if (target < 200000) {
936 clock.n = 1;
937 clock.p1 = 2;
938 clock.p2 = 10;
939 clock.m1 = 12;
940 clock.m2 = 9;
941 } else {
942 clock.n = 2;
943 clock.p1 = 1;
944 clock.p2 = 10;
945 clock.m1 = 14;
946 clock.m2 = 8;
947 }
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
950 return true;
951 }
952
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 static bool
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
957 {
958 intel_clock_t clock;
959 if (target < 200000) {
960 clock.p1 = 2;
961 clock.p2 = 10;
962 clock.n = 2;
963 clock.m1 = 23;
964 clock.m2 = 8;
965 } else {
966 clock.p1 = 1;
967 clock.p2 = 10;
968 clock.n = 1;
969 clock.m1 = 14;
970 clock.m2 = 2;
971 }
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
975 clock.vco = 0;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
977 return true;
978 }
979
980 /**
981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
989 {
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
992
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for((I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS),
1012 50, 0))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /**
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1027 */
1028 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029 {
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033 u32 last_line;
1034
1035 /* Wait for the display line to settle */
1036 do {
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038 mdelay(5);
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040 time_after(timeout, jiffies));
1041
1042 if (time_after(jiffies, timeout))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
1044 }
1045
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1048 {
1049 struct drm_device *dev = crtc->dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 struct drm_framebuffer *fb = crtc->fb;
1052 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1053 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1055 int plane, i;
1056 u32 fbc_ctl, fbc_ctl2;
1057
1058 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1059
1060 if (fb->pitch < dev_priv->cfb_pitch)
1061 dev_priv->cfb_pitch = fb->pitch;
1062
1063 /* FBC_CTL wants 64B units */
1064 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1065 dev_priv->cfb_fence = obj_priv->fence_reg;
1066 dev_priv->cfb_plane = intel_crtc->plane;
1067 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1068
1069 /* Clear old tags */
1070 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1071 I915_WRITE(FBC_TAG + (i * 4), 0);
1072
1073 /* Set it up... */
1074 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1075 if (obj_priv->tiling_mode != I915_TILING_NONE)
1076 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1077 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1078 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1079
1080 /* enable it... */
1081 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1082 if (IS_I945GM(dev))
1083 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1084 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1085 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1086 if (obj_priv->tiling_mode != I915_TILING_NONE)
1087 fbc_ctl |= dev_priv->cfb_fence;
1088 I915_WRITE(FBC_CONTROL, fbc_ctl);
1089
1090 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1092 }
1093
1094 void i8xx_disable_fbc(struct drm_device *dev)
1095 {
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 fbc_ctl;
1098
1099 if (!I915_HAS_FBC(dev))
1100 return;
1101
1102 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1103 return; /* Already off, just return */
1104
1105 /* Disable compression */
1106 fbc_ctl = I915_READ(FBC_CONTROL);
1107 fbc_ctl &= ~FBC_CTL_EN;
1108 I915_WRITE(FBC_CONTROL, fbc_ctl);
1109
1110 /* Wait for compressing bit to clear */
1111 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1113 return;
1114 }
1115
1116 DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool i8xx_fbc_enabled(struct drm_device *dev)
1120 {
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1124 }
1125
1126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128 struct drm_device *dev = crtc->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 struct drm_framebuffer *fb = crtc->fb;
1131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1132 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1135 DPFC_CTL_PLANEB);
1136 unsigned long stall_watermark = 200;
1137 u32 dpfc_ctl;
1138
1139 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1140 dev_priv->cfb_fence = obj_priv->fence_reg;
1141 dev_priv->cfb_plane = intel_crtc->plane;
1142
1143 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1144 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1145 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1146 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1147 } else {
1148 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1149 }
1150
1151 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1152 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1153 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1154 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1155 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1156
1157 /* enable it... */
1158 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1159
1160 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1161 }
1162
1163 void g4x_disable_fbc(struct drm_device *dev)
1164 {
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 dpfc_ctl;
1167
1168 /* Disable compression */
1169 dpfc_ctl = I915_READ(DPFC_CONTROL);
1170 dpfc_ctl &= ~DPFC_CTL_EN;
1171 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1172
1173 DRM_DEBUG_KMS("disabled FBC\n");
1174 }
1175
1176 static bool g4x_fbc_enabled(struct drm_device *dev)
1177 {
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1181 }
1182
1183 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1184 {
1185 struct drm_device *dev = crtc->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 struct drm_framebuffer *fb = crtc->fb;
1188 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1189 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1192 DPFC_CTL_PLANEB;
1193 unsigned long stall_watermark = 200;
1194 u32 dpfc_ctl;
1195
1196 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1197 dev_priv->cfb_fence = obj_priv->fence_reg;
1198 dev_priv->cfb_plane = intel_crtc->plane;
1199
1200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1201 dpfc_ctl &= DPFC_RESERVED;
1202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1203 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1206 } else {
1207 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1208 }
1209
1210 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1211 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1212 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1213 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1214 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1215 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1216 /* enable it... */
1217 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1218 DPFC_CTL_EN);
1219
1220 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1221 }
1222
1223 void ironlake_disable_fbc(struct drm_device *dev)
1224 {
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 u32 dpfc_ctl;
1227
1228 /* Disable compression */
1229 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1230 dpfc_ctl &= ~DPFC_CTL_EN;
1231 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1232
1233 DRM_DEBUG_KMS("disabled FBC\n");
1234 }
1235
1236 static bool ironlake_fbc_enabled(struct drm_device *dev)
1237 {
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239
1240 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1241 }
1242
1243 bool intel_fbc_enabled(struct drm_device *dev)
1244 {
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247 if (!dev_priv->display.fbc_enabled)
1248 return false;
1249
1250 return dev_priv->display.fbc_enabled(dev);
1251 }
1252
1253 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1254 {
1255 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1256
1257 if (!dev_priv->display.enable_fbc)
1258 return;
1259
1260 dev_priv->display.enable_fbc(crtc, interval);
1261 }
1262
1263 void intel_disable_fbc(struct drm_device *dev)
1264 {
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267 if (!dev_priv->display.disable_fbc)
1268 return;
1269
1270 dev_priv->display.disable_fbc(dev);
1271 }
1272
1273 /**
1274 * intel_update_fbc - enable/disable FBC as needed
1275 * @crtc: CRTC to point the compressor at
1276 * @mode: mode in use
1277 *
1278 * Set up the framebuffer compression hardware at mode set time. We
1279 * enable it if possible:
1280 * - plane A only (on pre-965)
1281 * - no pixel mulitply/line duplication
1282 * - no alpha buffer discard
1283 * - no dual wide
1284 * - framebuffer <= 2048 in width, 1536 in height
1285 *
1286 * We can't assume that any compression will take place (worst case),
1287 * so the compressed buffer has to be the same size as the uncompressed
1288 * one. It also must reside (along with the line length buffer) in
1289 * stolen memory.
1290 *
1291 * We need to enable/disable FBC on a global basis.
1292 */
1293 static void intel_update_fbc(struct drm_crtc *crtc,
1294 struct drm_display_mode *mode)
1295 {
1296 struct drm_device *dev = crtc->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 struct drm_framebuffer *fb = crtc->fb;
1299 struct intel_framebuffer *intel_fb;
1300 struct drm_i915_gem_object *obj_priv;
1301 struct drm_crtc *tmp_crtc;
1302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1303 int plane = intel_crtc->plane;
1304 int crtcs_enabled = 0;
1305
1306 DRM_DEBUG_KMS("\n");
1307
1308 if (!i915_powersave)
1309 return;
1310
1311 if (!I915_HAS_FBC(dev))
1312 return;
1313
1314 if (!crtc->fb)
1315 return;
1316
1317 intel_fb = to_intel_framebuffer(fb);
1318 obj_priv = to_intel_bo(intel_fb->obj);
1319
1320 /*
1321 * If FBC is already on, we just have to verify that we can
1322 * keep it that way...
1323 * Need to disable if:
1324 * - more than one pipe is active
1325 * - changing FBC params (stride, fence, mode)
1326 * - new fb is too large to fit in compressed buffer
1327 * - going to an unsupported config (interlace, pixel multiply, etc.)
1328 */
1329 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1330 if (tmp_crtc->enabled)
1331 crtcs_enabled++;
1332 }
1333 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1334 if (crtcs_enabled > 1) {
1335 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1337 goto out_disable;
1338 }
1339 if (intel_fb->obj->size > dev_priv->cfb_size) {
1340 DRM_DEBUG_KMS("framebuffer too large, disabling "
1341 "compression\n");
1342 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1343 goto out_disable;
1344 }
1345 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1346 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1347 DRM_DEBUG_KMS("mode incompatible with compression, "
1348 "disabling\n");
1349 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1350 goto out_disable;
1351 }
1352 if ((mode->hdisplay > 2048) ||
1353 (mode->vdisplay > 1536)) {
1354 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1356 goto out_disable;
1357 }
1358 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1359 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1361 goto out_disable;
1362 }
1363 if (obj_priv->tiling_mode != I915_TILING_X) {
1364 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1366 goto out_disable;
1367 }
1368
1369 /* If the kernel debugger is active, always disable compression */
1370 if (in_dbg_master())
1371 goto out_disable;
1372
1373 if (intel_fbc_enabled(dev)) {
1374 /* We can re-enable it in this case, but need to update pitch */
1375 if ((fb->pitch > dev_priv->cfb_pitch) ||
1376 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1377 (plane != dev_priv->cfb_plane))
1378 intel_disable_fbc(dev);
1379 }
1380
1381 /* Now try to turn it back on if possible */
1382 if (!intel_fbc_enabled(dev))
1383 intel_enable_fbc(crtc, 500);
1384
1385 return;
1386
1387 out_disable:
1388 /* Multiple disables should be harmless */
1389 if (intel_fbc_enabled(dev)) {
1390 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391 intel_disable_fbc(dev);
1392 }
1393 }
1394
1395 int
1396 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1397 {
1398 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1399 u32 alignment;
1400 int ret;
1401
1402 switch (obj_priv->tiling_mode) {
1403 case I915_TILING_NONE:
1404 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1405 alignment = 128 * 1024;
1406 else if (IS_I965G(dev))
1407 alignment = 4 * 1024;
1408 else
1409 alignment = 64 * 1024;
1410 break;
1411 case I915_TILING_X:
1412 /* pin() will align the object as required by fence */
1413 alignment = 0;
1414 break;
1415 case I915_TILING_Y:
1416 /* FIXME: Is this true? */
1417 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1418 return -EINVAL;
1419 default:
1420 BUG();
1421 }
1422
1423 ret = i915_gem_object_pin(obj, alignment);
1424 if (ret != 0)
1425 return ret;
1426
1427 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428 * fence, whereas 965+ only requires a fence if using
1429 * framebuffer compression. For simplicity, we always install
1430 * a fence as the cost is not that onerous.
1431 */
1432 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1433 obj_priv->tiling_mode != I915_TILING_NONE) {
1434 ret = i915_gem_object_get_fence_reg(obj);
1435 if (ret != 0) {
1436 i915_gem_object_unpin(obj);
1437 return ret;
1438 }
1439 }
1440
1441 return 0;
1442 }
1443
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1445 static int
1446 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1447 int x, int y)
1448 {
1449 struct drm_device *dev = crtc->dev;
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1452 struct intel_framebuffer *intel_fb;
1453 struct drm_i915_gem_object *obj_priv;
1454 struct drm_gem_object *obj;
1455 int plane = intel_crtc->plane;
1456 unsigned long Start, Offset;
1457 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1458 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1459 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1460 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1461 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1462 u32 dspcntr;
1463
1464 switch (plane) {
1465 case 0:
1466 case 1:
1467 break;
1468 default:
1469 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1470 return -EINVAL;
1471 }
1472
1473 intel_fb = to_intel_framebuffer(fb);
1474 obj = intel_fb->obj;
1475 obj_priv = to_intel_bo(obj);
1476
1477 dspcntr = I915_READ(dspcntr_reg);
1478 /* Mask out pixel format bits in case we change it */
1479 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1480 switch (fb->bits_per_pixel) {
1481 case 8:
1482 dspcntr |= DISPPLANE_8BPP;
1483 break;
1484 case 16:
1485 if (fb->depth == 15)
1486 dspcntr |= DISPPLANE_15_16BPP;
1487 else
1488 dspcntr |= DISPPLANE_16BPP;
1489 break;
1490 case 24:
1491 case 32:
1492 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1493 break;
1494 default:
1495 DRM_ERROR("Unknown color depth\n");
1496 return -EINVAL;
1497 }
1498 if (IS_I965G(dev)) {
1499 if (obj_priv->tiling_mode != I915_TILING_NONE)
1500 dspcntr |= DISPPLANE_TILED;
1501 else
1502 dspcntr &= ~DISPPLANE_TILED;
1503 }
1504
1505 if (HAS_PCH_SPLIT(dev))
1506 /* must disable */
1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1508
1509 I915_WRITE(dspcntr_reg, dspcntr);
1510
1511 Start = obj_priv->gtt_offset;
1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1513
1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1516 I915_WRITE(dspstride, fb->pitch);
1517 if (IS_I965G(dev)) {
1518 I915_WRITE(dspsurf, Start);
1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1521 } else {
1522 I915_WRITE(dspbase, Start + Offset);
1523 }
1524 POSTING_READ(dspbase);
1525
1526 if (IS_I965G(dev) || plane == 0)
1527 intel_update_fbc(crtc, &crtc->mode);
1528
1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
1530 intel_increase_pllclock(crtc, true);
1531
1532 return 0;
1533 }
1534
1535 static int
1536 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1537 struct drm_framebuffer *old_fb)
1538 {
1539 struct drm_device *dev = crtc->dev;
1540 struct drm_i915_master_private *master_priv;
1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1542 struct intel_framebuffer *intel_fb;
1543 struct drm_i915_gem_object *obj_priv;
1544 struct drm_gem_object *obj;
1545 int pipe = intel_crtc->pipe;
1546 int plane = intel_crtc->plane;
1547 int ret;
1548
1549 /* no fb bound */
1550 if (!crtc->fb) {
1551 DRM_DEBUG_KMS("No FB bound\n");
1552 return 0;
1553 }
1554
1555 switch (plane) {
1556 case 0:
1557 case 1:
1558 break;
1559 default:
1560 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1561 return -EINVAL;
1562 }
1563
1564 intel_fb = to_intel_framebuffer(crtc->fb);
1565 obj = intel_fb->obj;
1566 obj_priv = to_intel_bo(obj);
1567
1568 mutex_lock(&dev->struct_mutex);
1569 ret = intel_pin_and_fence_fb_obj(dev, obj);
1570 if (ret != 0) {
1571 mutex_unlock(&dev->struct_mutex);
1572 return ret;
1573 }
1574
1575 ret = i915_gem_object_set_to_display_plane(obj);
1576 if (ret != 0) {
1577 i915_gem_object_unpin(obj);
1578 mutex_unlock(&dev->struct_mutex);
1579 return ret;
1580 }
1581
1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1583 if (ret) {
1584 i915_gem_object_unpin(obj);
1585 mutex_unlock(&dev->struct_mutex);
1586 return ret;
1587 }
1588
1589 if (old_fb) {
1590 intel_fb = to_intel_framebuffer(old_fb);
1591 obj_priv = to_intel_bo(intel_fb->obj);
1592 i915_gem_object_unpin(intel_fb->obj);
1593 }
1594
1595 mutex_unlock(&dev->struct_mutex);
1596
1597 if (!dev->primary->master)
1598 return 0;
1599
1600 master_priv = dev->primary->master->driver_priv;
1601 if (!master_priv->sarea_priv)
1602 return 0;
1603
1604 if (pipe) {
1605 master_priv->sarea_priv->pipeB_x = x;
1606 master_priv->sarea_priv->pipeB_y = y;
1607 } else {
1608 master_priv->sarea_priv->pipeA_x = x;
1609 master_priv->sarea_priv->pipeA_y = y;
1610 }
1611
1612 return 0;
1613 }
1614
1615 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1616 {
1617 struct drm_device *dev = crtc->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 u32 dpa_ctl;
1620
1621 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1622 dpa_ctl = I915_READ(DP_A);
1623 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1624
1625 if (clock < 200000) {
1626 u32 temp;
1627 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1628 /* workaround for 160Mhz:
1629 1) program 0x4600c bits 15:0 = 0x8124
1630 2) program 0x46010 bit 0 = 1
1631 3) program 0x46034 bit 24 = 1
1632 4) program 0x64000 bit 14 = 1
1633 */
1634 temp = I915_READ(0x4600c);
1635 temp &= 0xffff0000;
1636 I915_WRITE(0x4600c, temp | 0x8124);
1637
1638 temp = I915_READ(0x46010);
1639 I915_WRITE(0x46010, temp | 1);
1640
1641 temp = I915_READ(0x46034);
1642 I915_WRITE(0x46034, temp | (1 << 24));
1643 } else {
1644 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1645 }
1646 I915_WRITE(DP_A, dpa_ctl);
1647
1648 udelay(500);
1649 }
1650
1651 /* The FDI link training functions for ILK/Ibexpeak. */
1652 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1653 {
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1657 int pipe = intel_crtc->pipe;
1658 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1659 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1660 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1661 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1662 u32 temp, tries = 0;
1663
1664 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1665 for train result */
1666 temp = I915_READ(fdi_rx_imr_reg);
1667 temp &= ~FDI_RX_SYMBOL_LOCK;
1668 temp &= ~FDI_RX_BIT_LOCK;
1669 I915_WRITE(fdi_rx_imr_reg, temp);
1670 I915_READ(fdi_rx_imr_reg);
1671 udelay(150);
1672
1673 /* enable CPU FDI TX and PCH FDI RX */
1674 temp = I915_READ(fdi_tx_reg);
1675 temp |= FDI_TX_ENABLE;
1676 temp &= ~(7 << 19);
1677 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1678 temp &= ~FDI_LINK_TRAIN_NONE;
1679 temp |= FDI_LINK_TRAIN_PATTERN_1;
1680 I915_WRITE(fdi_tx_reg, temp);
1681 I915_READ(fdi_tx_reg);
1682
1683 temp = I915_READ(fdi_rx_reg);
1684 temp &= ~FDI_LINK_TRAIN_NONE;
1685 temp |= FDI_LINK_TRAIN_PATTERN_1;
1686 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1687 I915_READ(fdi_rx_reg);
1688 udelay(150);
1689
1690 for (tries = 0; tries < 5; tries++) {
1691 temp = I915_READ(fdi_rx_iir_reg);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1693
1694 if ((temp & FDI_RX_BIT_LOCK)) {
1695 DRM_DEBUG_KMS("FDI train 1 done.\n");
1696 I915_WRITE(fdi_rx_iir_reg,
1697 temp | FDI_RX_BIT_LOCK);
1698 break;
1699 }
1700 }
1701 if (tries == 5)
1702 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1703
1704 /* Train 2 */
1705 temp = I915_READ(fdi_tx_reg);
1706 temp &= ~FDI_LINK_TRAIN_NONE;
1707 temp |= FDI_LINK_TRAIN_PATTERN_2;
1708 I915_WRITE(fdi_tx_reg, temp);
1709
1710 temp = I915_READ(fdi_rx_reg);
1711 temp &= ~FDI_LINK_TRAIN_NONE;
1712 temp |= FDI_LINK_TRAIN_PATTERN_2;
1713 I915_WRITE(fdi_rx_reg, temp);
1714 udelay(150);
1715
1716 tries = 0;
1717
1718 for (tries = 0; tries < 5; tries++) {
1719 temp = I915_READ(fdi_rx_iir_reg);
1720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1721
1722 if (temp & FDI_RX_SYMBOL_LOCK) {
1723 I915_WRITE(fdi_rx_iir_reg,
1724 temp | FDI_RX_SYMBOL_LOCK);
1725 DRM_DEBUG_KMS("FDI train 2 done.\n");
1726 break;
1727 }
1728 }
1729 if (tries == 5)
1730 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1731
1732 DRM_DEBUG_KMS("FDI train done\n");
1733 }
1734
1735 static int snb_b_fdi_train_param [] = {
1736 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1737 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1738 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1739 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1740 };
1741
1742 /* The FDI link training functions for SNB/Cougarpoint. */
1743 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1744 {
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1748 int pipe = intel_crtc->pipe;
1749 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1750 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1751 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1752 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1753 u32 temp, i;
1754
1755 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1756 for train result */
1757 temp = I915_READ(fdi_rx_imr_reg);
1758 temp &= ~FDI_RX_SYMBOL_LOCK;
1759 temp &= ~FDI_RX_BIT_LOCK;
1760 I915_WRITE(fdi_rx_imr_reg, temp);
1761 I915_READ(fdi_rx_imr_reg);
1762 udelay(150);
1763
1764 /* enable CPU FDI TX and PCH FDI RX */
1765 temp = I915_READ(fdi_tx_reg);
1766 temp |= FDI_TX_ENABLE;
1767 temp &= ~(7 << 19);
1768 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_PATTERN_1;
1771 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1772 /* SNB-B */
1773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1774 I915_WRITE(fdi_tx_reg, temp);
1775 I915_READ(fdi_tx_reg);
1776
1777 temp = I915_READ(fdi_rx_reg);
1778 if (HAS_PCH_CPT(dev)) {
1779 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1781 } else {
1782 temp &= ~FDI_LINK_TRAIN_NONE;
1783 temp |= FDI_LINK_TRAIN_PATTERN_1;
1784 }
1785 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1786 I915_READ(fdi_rx_reg);
1787 udelay(150);
1788
1789 for (i = 0; i < 4; i++ ) {
1790 temp = I915_READ(fdi_tx_reg);
1791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1792 temp |= snb_b_fdi_train_param[i];
1793 I915_WRITE(fdi_tx_reg, temp);
1794 udelay(500);
1795
1796 temp = I915_READ(fdi_rx_iir_reg);
1797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1798
1799 if (temp & FDI_RX_BIT_LOCK) {
1800 I915_WRITE(fdi_rx_iir_reg,
1801 temp | FDI_RX_BIT_LOCK);
1802 DRM_DEBUG_KMS("FDI train 1 done.\n");
1803 break;
1804 }
1805 }
1806 if (i == 4)
1807 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1808
1809 /* Train 2 */
1810 temp = I915_READ(fdi_tx_reg);
1811 temp &= ~FDI_LINK_TRAIN_NONE;
1812 temp |= FDI_LINK_TRAIN_PATTERN_2;
1813 if (IS_GEN6(dev)) {
1814 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1815 /* SNB-B */
1816 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1817 }
1818 I915_WRITE(fdi_tx_reg, temp);
1819
1820 temp = I915_READ(fdi_rx_reg);
1821 if (HAS_PCH_CPT(dev)) {
1822 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1823 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1824 } else {
1825 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_2;
1827 }
1828 I915_WRITE(fdi_rx_reg, temp);
1829 udelay(150);
1830
1831 for (i = 0; i < 4; i++ ) {
1832 temp = I915_READ(fdi_tx_reg);
1833 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1834 temp |= snb_b_fdi_train_param[i];
1835 I915_WRITE(fdi_tx_reg, temp);
1836 udelay(500);
1837
1838 temp = I915_READ(fdi_rx_iir_reg);
1839 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1840
1841 if (temp & FDI_RX_SYMBOL_LOCK) {
1842 I915_WRITE(fdi_rx_iir_reg,
1843 temp | FDI_RX_SYMBOL_LOCK);
1844 DRM_DEBUG_KMS("FDI train 2 done.\n");
1845 break;
1846 }
1847 }
1848 if (i == 4)
1849 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1850
1851 DRM_DEBUG_KMS("FDI train done.\n");
1852 }
1853
1854 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1855 {
1856 struct drm_device *dev = crtc->dev;
1857 struct drm_i915_private *dev_priv = dev->dev_private;
1858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1859 int pipe = intel_crtc->pipe;
1860 int plane = intel_crtc->plane;
1861 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1862 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1863 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1864 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1871 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1872 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1873 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1874 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1875 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1876 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1877 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1878 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1879 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1880 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1881 u32 temp;
1882 u32 pipe_bpc;
1883
1884 temp = I915_READ(pipeconf_reg);
1885 pipe_bpc = temp & PIPE_BPC_MASK;
1886
1887 /* XXX: When our outputs are all unaware of DPMS modes other than off
1888 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1889 */
1890 switch (mode) {
1891 case DRM_MODE_DPMS_ON:
1892 case DRM_MODE_DPMS_STANDBY:
1893 case DRM_MODE_DPMS_SUSPEND:
1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1895
1896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1897 temp = I915_READ(PCH_LVDS);
1898 if ((temp & LVDS_PORT_EN) == 0) {
1899 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1900 POSTING_READ(PCH_LVDS);
1901 }
1902 }
1903
1904 if (!HAS_eDP) {
1905
1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1907 temp = I915_READ(fdi_rx_reg);
1908 /*
1909 * make the BPC in FDI Rx be consistent with that in
1910 * pipeconf reg.
1911 */
1912 temp &= ~(0x7 << 16);
1913 temp |= (pipe_bpc << 11);
1914 temp &= ~(7 << 19);
1915 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1916 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1917 I915_READ(fdi_rx_reg);
1918 udelay(200);
1919
1920 /* Switch from Rawclk to PCDclk */
1921 temp = I915_READ(fdi_rx_reg);
1922 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1923 I915_READ(fdi_rx_reg);
1924 udelay(200);
1925
1926 /* Enable CPU FDI TX PLL, always on for Ironlake */
1927 temp = I915_READ(fdi_tx_reg);
1928 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1929 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1930 I915_READ(fdi_tx_reg);
1931 udelay(100);
1932 }
1933 }
1934
1935 /* Enable panel fitting for LVDS */
1936 if (dev_priv->pch_pf_size &&
1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
1939 /* Force use of hard-coded filter coefficients
1940 * as some pre-programmed values are broken,
1941 * e.g. x201.
1942 */
1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1944 PF_ENABLE | PF_FILTER_MED_3x3);
1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
1949 }
1950
1951 /* Enable CPU pipe */
1952 temp = I915_READ(pipeconf_reg);
1953 if ((temp & PIPEACONF_ENABLE) == 0) {
1954 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1955 I915_READ(pipeconf_reg);
1956 udelay(100);
1957 }
1958
1959 /* configure and enable CPU plane */
1960 temp = I915_READ(dspcntr_reg);
1961 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1962 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1963 /* Flush the plane changes */
1964 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1965 }
1966
1967 if (!HAS_eDP) {
1968 /* For PCH output, training FDI link */
1969 if (IS_GEN6(dev))
1970 gen6_fdi_link_train(crtc);
1971 else
1972 ironlake_fdi_link_train(crtc);
1973
1974 /* enable PCH DPLL */
1975 temp = I915_READ(pch_dpll_reg);
1976 if ((temp & DPLL_VCO_ENABLE) == 0) {
1977 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1978 I915_READ(pch_dpll_reg);
1979 }
1980 udelay(200);
1981
1982 if (HAS_PCH_CPT(dev)) {
1983 /* Be sure PCH DPLL SEL is set */
1984 temp = I915_READ(PCH_DPLL_SEL);
1985 if (trans_dpll_sel == 0 &&
1986 (temp & TRANSA_DPLL_ENABLE) == 0)
1987 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1988 else if (trans_dpll_sel == 1 &&
1989 (temp & TRANSB_DPLL_ENABLE) == 0)
1990 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1991 I915_WRITE(PCH_DPLL_SEL, temp);
1992 I915_READ(PCH_DPLL_SEL);
1993 }
1994
1995 /* set transcoder timing */
1996 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1997 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1998 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1999
2000 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2001 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2002 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2003
2004 /* enable normal train */
2005 temp = I915_READ(fdi_tx_reg);
2006 temp &= ~FDI_LINK_TRAIN_NONE;
2007 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2008 FDI_TX_ENHANCE_FRAME_ENABLE);
2009 I915_READ(fdi_tx_reg);
2010
2011 temp = I915_READ(fdi_rx_reg);
2012 if (HAS_PCH_CPT(dev)) {
2013 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2014 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2015 } else {
2016 temp &= ~FDI_LINK_TRAIN_NONE;
2017 temp |= FDI_LINK_TRAIN_NONE;
2018 }
2019 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2020 I915_READ(fdi_rx_reg);
2021
2022 /* wait one idle pattern time */
2023 udelay(100);
2024
2025 /* For PCH DP, enable TRANS_DP_CTL */
2026 if (HAS_PCH_CPT(dev) &&
2027 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2028 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2029 int reg;
2030
2031 reg = I915_READ(trans_dp_ctl);
2032 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2033 TRANS_DP_SYNC_MASK);
2034 reg |= (TRANS_DP_OUTPUT_ENABLE |
2035 TRANS_DP_ENH_FRAMING);
2036
2037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2038 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2039 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2040 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2041
2042 switch (intel_trans_dp_port_sel(crtc)) {
2043 case PCH_DP_B:
2044 reg |= TRANS_DP_PORT_SEL_B;
2045 break;
2046 case PCH_DP_C:
2047 reg |= TRANS_DP_PORT_SEL_C;
2048 break;
2049 case PCH_DP_D:
2050 reg |= TRANS_DP_PORT_SEL_D;
2051 break;
2052 default:
2053 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2054 reg |= TRANS_DP_PORT_SEL_B;
2055 break;
2056 }
2057
2058 I915_WRITE(trans_dp_ctl, reg);
2059 POSTING_READ(trans_dp_ctl);
2060 }
2061
2062 /* enable PCH transcoder */
2063 temp = I915_READ(transconf_reg);
2064 /*
2065 * make the BPC in transcoder be consistent with
2066 * that in pipeconf reg.
2067 */
2068 temp &= ~PIPE_BPC_MASK;
2069 temp |= pipe_bpc;
2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2071 I915_READ(transconf_reg);
2072
2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2074 DRM_ERROR("failed to enable transcoder\n");
2075 }
2076
2077 intel_crtc_load_lut(crtc);
2078
2079 intel_update_fbc(crtc, &crtc->mode);
2080 break;
2081
2082 case DRM_MODE_DPMS_OFF:
2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2084
2085 drm_vblank_off(dev, pipe);
2086 /* Disable display plane */
2087 temp = I915_READ(dspcntr_reg);
2088 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2089 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2090 /* Flush the plane changes */
2091 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2092 I915_READ(dspbase_reg);
2093 }
2094
2095 if (dev_priv->cfb_plane == plane &&
2096 dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
2098
2099 /* disable cpu pipe, disable after all planes disabled */
2100 temp = I915_READ(pipeconf_reg);
2101 if ((temp & PIPEACONF_ENABLE) != 0) {
2102 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2103
2104 /* wait for cpu pipe off, pipe state */
2105 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2106 DRM_ERROR("failed to turn off cpu pipe\n");
2107 } else
2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2109
2110 udelay(100);
2111
2112 /* Disable PF */
2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2115
2116 /* disable CPU FDI tx and PCH FDI rx */
2117 temp = I915_READ(fdi_tx_reg);
2118 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2119 I915_READ(fdi_tx_reg);
2120
2121 temp = I915_READ(fdi_rx_reg);
2122 /* BPC in FDI rx is consistent with that in pipeconf */
2123 temp &= ~(0x07 << 16);
2124 temp |= (pipe_bpc << 11);
2125 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2126 I915_READ(fdi_rx_reg);
2127
2128 udelay(100);
2129
2130 /* still set train pattern 1 */
2131 temp = I915_READ(fdi_tx_reg);
2132 temp &= ~FDI_LINK_TRAIN_NONE;
2133 temp |= FDI_LINK_TRAIN_PATTERN_1;
2134 I915_WRITE(fdi_tx_reg, temp);
2135 POSTING_READ(fdi_tx_reg);
2136
2137 temp = I915_READ(fdi_rx_reg);
2138 if (HAS_PCH_CPT(dev)) {
2139 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2140 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2141 } else {
2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_PATTERN_1;
2144 }
2145 I915_WRITE(fdi_rx_reg, temp);
2146 POSTING_READ(fdi_rx_reg);
2147
2148 udelay(100);
2149
2150 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2151 temp = I915_READ(PCH_LVDS);
2152 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2153 I915_READ(PCH_LVDS);
2154 udelay(100);
2155 }
2156
2157 /* disable PCH transcoder */
2158 temp = I915_READ(transconf_reg);
2159 if ((temp & TRANS_ENABLE) != 0) {
2160 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2161
2162 /* wait for PCH transcoder off, transcoder state */
2163 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2164 DRM_ERROR("failed to disable transcoder\n");
2165 }
2166
2167 temp = I915_READ(transconf_reg);
2168 /* BPC in transcoder is consistent with that in pipeconf */
2169 temp &= ~PIPE_BPC_MASK;
2170 temp |= pipe_bpc;
2171 I915_WRITE(transconf_reg, temp);
2172 I915_READ(transconf_reg);
2173 udelay(100);
2174
2175 if (HAS_PCH_CPT(dev)) {
2176 /* disable TRANS_DP_CTL */
2177 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2178 int reg;
2179
2180 reg = I915_READ(trans_dp_ctl);
2181 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2182 I915_WRITE(trans_dp_ctl, reg);
2183 POSTING_READ(trans_dp_ctl);
2184
2185 /* disable DPLL_SEL */
2186 temp = I915_READ(PCH_DPLL_SEL);
2187 if (trans_dpll_sel == 0)
2188 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2189 else
2190 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2191 I915_WRITE(PCH_DPLL_SEL, temp);
2192 I915_READ(PCH_DPLL_SEL);
2193
2194 }
2195
2196 /* disable PCH DPLL */
2197 temp = I915_READ(pch_dpll_reg);
2198 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2199 I915_READ(pch_dpll_reg);
2200
2201 /* Switch from PCDclk to Rawclk */
2202 temp = I915_READ(fdi_rx_reg);
2203 temp &= ~FDI_SEL_PCDCLK;
2204 I915_WRITE(fdi_rx_reg, temp);
2205 I915_READ(fdi_rx_reg);
2206
2207 /* Disable CPU FDI TX PLL */
2208 temp = I915_READ(fdi_tx_reg);
2209 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2210 I915_READ(fdi_tx_reg);
2211 udelay(100);
2212
2213 temp = I915_READ(fdi_rx_reg);
2214 temp &= ~FDI_RX_PLL_ENABLE;
2215 I915_WRITE(fdi_rx_reg, temp);
2216 I915_READ(fdi_rx_reg);
2217
2218 /* Wait for the clocks to turn off. */
2219 udelay(100);
2220 break;
2221 }
2222 }
2223
2224 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2225 {
2226 struct intel_overlay *overlay;
2227 int ret;
2228
2229 if (!enable && intel_crtc->overlay) {
2230 overlay = intel_crtc->overlay;
2231 mutex_lock(&overlay->dev->struct_mutex);
2232 for (;;) {
2233 ret = intel_overlay_switch_off(overlay);
2234 if (ret == 0)
2235 break;
2236
2237 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2238 if (ret != 0) {
2239 /* overlay doesn't react anymore. Usually
2240 * results in a black screen and an unkillable
2241 * X server. */
2242 BUG();
2243 overlay->hw_wedged = HW_WEDGED;
2244 break;
2245 }
2246 }
2247 mutex_unlock(&overlay->dev->struct_mutex);
2248 }
2249 /* Let userspace switch the overlay on again. In most cases userspace
2250 * has to recompute where to put it anyway. */
2251
2252 return;
2253 }
2254
2255 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2256 {
2257 struct drm_device *dev = crtc->dev;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260 int pipe = intel_crtc->pipe;
2261 int plane = intel_crtc->plane;
2262 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2263 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2264 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2265 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2266 u32 temp;
2267
2268 /* XXX: When our outputs are all unaware of DPMS modes other than off
2269 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2270 */
2271 switch (mode) {
2272 case DRM_MODE_DPMS_ON:
2273 case DRM_MODE_DPMS_STANDBY:
2274 case DRM_MODE_DPMS_SUSPEND:
2275 /* Enable the DPLL */
2276 temp = I915_READ(dpll_reg);
2277 if ((temp & DPLL_VCO_ENABLE) == 0) {
2278 I915_WRITE(dpll_reg, temp);
2279 I915_READ(dpll_reg);
2280 /* Wait for the clocks to stabilize. */
2281 udelay(150);
2282 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2283 I915_READ(dpll_reg);
2284 /* Wait for the clocks to stabilize. */
2285 udelay(150);
2286 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2287 I915_READ(dpll_reg);
2288 /* Wait for the clocks to stabilize. */
2289 udelay(150);
2290 }
2291
2292 /* Enable the pipe */
2293 temp = I915_READ(pipeconf_reg);
2294 if ((temp & PIPEACONF_ENABLE) == 0)
2295 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2296
2297 /* Enable the plane */
2298 temp = I915_READ(dspcntr_reg);
2299 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2300 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2301 /* Flush the plane changes */
2302 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2303 }
2304
2305 intel_crtc_load_lut(crtc);
2306
2307 if ((IS_I965G(dev) || plane == 0))
2308 intel_update_fbc(crtc, &crtc->mode);
2309
2310 /* Give the overlay scaler a chance to enable if it's on this pipe */
2311 intel_crtc_dpms_overlay(intel_crtc, true);
2312 break;
2313 case DRM_MODE_DPMS_OFF:
2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2315 intel_crtc_dpms_overlay(intel_crtc, false);
2316 drm_vblank_off(dev, pipe);
2317
2318 if (dev_priv->cfb_plane == plane &&
2319 dev_priv->display.disable_fbc)
2320 dev_priv->display.disable_fbc(dev);
2321
2322 /* Disable display plane */
2323 temp = I915_READ(dspcntr_reg);
2324 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2325 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2326 /* Flush the plane changes */
2327 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2328 I915_READ(dspbase_reg);
2329 }
2330
2331 /* Wait for vblank for the disable to take effect */
2332 intel_wait_for_vblank_off(dev, pipe);
2333
2334 /* Don't disable pipe A or pipe A PLLs if needed */
2335 if (pipeconf_reg == PIPEACONF &&
2336 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2337 goto skip_pipe_off;
2338
2339 /* Next, disable display pipes */
2340 temp = I915_READ(pipeconf_reg);
2341 if ((temp & PIPEACONF_ENABLE) != 0) {
2342 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2343 I915_READ(pipeconf_reg);
2344 }
2345
2346 /* Wait for vblank for the disable to take effect. */
2347 intel_wait_for_vblank_off(dev, pipe);
2348
2349 temp = I915_READ(dpll_reg);
2350 if ((temp & DPLL_VCO_ENABLE) != 0) {
2351 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2352 I915_READ(dpll_reg);
2353 }
2354 skip_pipe_off:
2355 /* Wait for the clocks to turn off. */
2356 udelay(150);
2357 break;
2358 }
2359 }
2360
2361 /**
2362 * Sets the power management mode of the pipe and plane.
2363 */
2364 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2365 {
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct drm_i915_master_private *master_priv;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
2371 bool enabled;
2372
2373 if (intel_crtc->dpms_mode == mode)
2374 return;
2375
2376 intel_crtc->dpms_mode = mode;
2377 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2378
2379 /* When switching on the display, ensure that SR is disabled
2380 * with multiple pipes prior to enabling to new pipe.
2381 *
2382 * When switching off the display, make sure the cursor is
2383 * properly hidden prior to disabling the pipe.
2384 */
2385 if (mode == DRM_MODE_DPMS_ON)
2386 intel_update_watermarks(dev);
2387 else
2388 intel_crtc_update_cursor(crtc);
2389
2390 dev_priv->display.dpms(crtc, mode);
2391
2392 if (mode == DRM_MODE_DPMS_ON)
2393 intel_crtc_update_cursor(crtc);
2394 else
2395 intel_update_watermarks(dev);
2396
2397 if (!dev->primary->master)
2398 return;
2399
2400 master_priv = dev->primary->master->driver_priv;
2401 if (!master_priv->sarea_priv)
2402 return;
2403
2404 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2405
2406 switch (pipe) {
2407 case 0:
2408 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2409 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2410 break;
2411 case 1:
2412 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2413 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2414 break;
2415 default:
2416 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2417 break;
2418 }
2419 }
2420
2421 static void intel_crtc_prepare (struct drm_crtc *crtc)
2422 {
2423 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2424 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2425 }
2426
2427 static void intel_crtc_commit (struct drm_crtc *crtc)
2428 {
2429 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2430 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2431 }
2432
2433 void intel_encoder_prepare (struct drm_encoder *encoder)
2434 {
2435 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2436 /* lvds has its own version of prepare see intel_lvds_prepare */
2437 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2438 }
2439
2440 void intel_encoder_commit (struct drm_encoder *encoder)
2441 {
2442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2443 /* lvds has its own version of commit see intel_lvds_commit */
2444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2445 }
2446
2447 void intel_encoder_destroy(struct drm_encoder *encoder)
2448 {
2449 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2450
2451 if (intel_encoder->ddc_bus)
2452 intel_i2c_destroy(intel_encoder->ddc_bus);
2453
2454 if (intel_encoder->i2c_bus)
2455 intel_i2c_destroy(intel_encoder->i2c_bus);
2456
2457 drm_encoder_cleanup(encoder);
2458 kfree(intel_encoder);
2459 }
2460
2461 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2462 struct drm_display_mode *mode,
2463 struct drm_display_mode *adjusted_mode)
2464 {
2465 struct drm_device *dev = crtc->dev;
2466 if (HAS_PCH_SPLIT(dev)) {
2467 /* FDI link clock is fixed at 2.7G */
2468 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2469 return false;
2470 }
2471 return true;
2472 }
2473
2474 static int i945_get_display_clock_speed(struct drm_device *dev)
2475 {
2476 return 400000;
2477 }
2478
2479 static int i915_get_display_clock_speed(struct drm_device *dev)
2480 {
2481 return 333000;
2482 }
2483
2484 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2485 {
2486 return 200000;
2487 }
2488
2489 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2490 {
2491 u16 gcfgc = 0;
2492
2493 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2494
2495 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2496 return 133000;
2497 else {
2498 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2499 case GC_DISPLAY_CLOCK_333_MHZ:
2500 return 333000;
2501 default:
2502 case GC_DISPLAY_CLOCK_190_200_MHZ:
2503 return 190000;
2504 }
2505 }
2506 }
2507
2508 static int i865_get_display_clock_speed(struct drm_device *dev)
2509 {
2510 return 266000;
2511 }
2512
2513 static int i855_get_display_clock_speed(struct drm_device *dev)
2514 {
2515 u16 hpllcc = 0;
2516 /* Assume that the hardware is in the high speed state. This
2517 * should be the default.
2518 */
2519 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2520 case GC_CLOCK_133_200:
2521 case GC_CLOCK_100_200:
2522 return 200000;
2523 case GC_CLOCK_166_250:
2524 return 250000;
2525 case GC_CLOCK_100_133:
2526 return 133000;
2527 }
2528
2529 /* Shouldn't happen */
2530 return 0;
2531 }
2532
2533 static int i830_get_display_clock_speed(struct drm_device *dev)
2534 {
2535 return 133000;
2536 }
2537
2538 /**
2539 * Return the pipe currently connected to the panel fitter,
2540 * or -1 if the panel fitter is not present or not in use
2541 */
2542 int intel_panel_fitter_pipe (struct drm_device *dev)
2543 {
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 u32 pfit_control;
2546
2547 /* i830 doesn't have a panel fitter */
2548 if (IS_I830(dev))
2549 return -1;
2550
2551 pfit_control = I915_READ(PFIT_CONTROL);
2552
2553 /* See if the panel fitter is in use */
2554 if ((pfit_control & PFIT_ENABLE) == 0)
2555 return -1;
2556
2557 /* 965 can place panel fitter on either pipe */
2558 if (IS_I965G(dev))
2559 return (pfit_control >> 29) & 0x3;
2560
2561 /* older chips can only use pipe 1 */
2562 return 1;
2563 }
2564
2565 struct fdi_m_n {
2566 u32 tu;
2567 u32 gmch_m;
2568 u32 gmch_n;
2569 u32 link_m;
2570 u32 link_n;
2571 };
2572
2573 static void
2574 fdi_reduce_ratio(u32 *num, u32 *den)
2575 {
2576 while (*num > 0xffffff || *den > 0xffffff) {
2577 *num >>= 1;
2578 *den >>= 1;
2579 }
2580 }
2581
2582 #define DATA_N 0x800000
2583 #define LINK_N 0x80000
2584
2585 static void
2586 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2587 int link_clock, struct fdi_m_n *m_n)
2588 {
2589 u64 temp;
2590
2591 m_n->tu = 64; /* default size */
2592
2593 temp = (u64) DATA_N * pixel_clock;
2594 temp = div_u64(temp, link_clock);
2595 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2596 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2597 m_n->gmch_n = DATA_N;
2598 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2599
2600 temp = (u64) LINK_N * pixel_clock;
2601 m_n->link_m = div_u64(temp, link_clock);
2602 m_n->link_n = LINK_N;
2603 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2604 }
2605
2606
2607 struct intel_watermark_params {
2608 unsigned long fifo_size;
2609 unsigned long max_wm;
2610 unsigned long default_wm;
2611 unsigned long guard_size;
2612 unsigned long cacheline_size;
2613 };
2614
2615 /* Pineview has different values for various configs */
2616 static struct intel_watermark_params pineview_display_wm = {
2617 PINEVIEW_DISPLAY_FIFO,
2618 PINEVIEW_MAX_WM,
2619 PINEVIEW_DFT_WM,
2620 PINEVIEW_GUARD_WM,
2621 PINEVIEW_FIFO_LINE_SIZE
2622 };
2623 static struct intel_watermark_params pineview_display_hplloff_wm = {
2624 PINEVIEW_DISPLAY_FIFO,
2625 PINEVIEW_MAX_WM,
2626 PINEVIEW_DFT_HPLLOFF_WM,
2627 PINEVIEW_GUARD_WM,
2628 PINEVIEW_FIFO_LINE_SIZE
2629 };
2630 static struct intel_watermark_params pineview_cursor_wm = {
2631 PINEVIEW_CURSOR_FIFO,
2632 PINEVIEW_CURSOR_MAX_WM,
2633 PINEVIEW_CURSOR_DFT_WM,
2634 PINEVIEW_CURSOR_GUARD_WM,
2635 PINEVIEW_FIFO_LINE_SIZE,
2636 };
2637 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2638 PINEVIEW_CURSOR_FIFO,
2639 PINEVIEW_CURSOR_MAX_WM,
2640 PINEVIEW_CURSOR_DFT_WM,
2641 PINEVIEW_CURSOR_GUARD_WM,
2642 PINEVIEW_FIFO_LINE_SIZE
2643 };
2644 static struct intel_watermark_params g4x_wm_info = {
2645 G4X_FIFO_SIZE,
2646 G4X_MAX_WM,
2647 G4X_MAX_WM,
2648 2,
2649 G4X_FIFO_LINE_SIZE,
2650 };
2651 static struct intel_watermark_params g4x_cursor_wm_info = {
2652 I965_CURSOR_FIFO,
2653 I965_CURSOR_MAX_WM,
2654 I965_CURSOR_DFT_WM,
2655 2,
2656 G4X_FIFO_LINE_SIZE,
2657 };
2658 static struct intel_watermark_params i965_cursor_wm_info = {
2659 I965_CURSOR_FIFO,
2660 I965_CURSOR_MAX_WM,
2661 I965_CURSOR_DFT_WM,
2662 2,
2663 I915_FIFO_LINE_SIZE,
2664 };
2665 static struct intel_watermark_params i945_wm_info = {
2666 I945_FIFO_SIZE,
2667 I915_MAX_WM,
2668 1,
2669 2,
2670 I915_FIFO_LINE_SIZE
2671 };
2672 static struct intel_watermark_params i915_wm_info = {
2673 I915_FIFO_SIZE,
2674 I915_MAX_WM,
2675 1,
2676 2,
2677 I915_FIFO_LINE_SIZE
2678 };
2679 static struct intel_watermark_params i855_wm_info = {
2680 I855GM_FIFO_SIZE,
2681 I915_MAX_WM,
2682 1,
2683 2,
2684 I830_FIFO_LINE_SIZE
2685 };
2686 static struct intel_watermark_params i830_wm_info = {
2687 I830_FIFO_SIZE,
2688 I915_MAX_WM,
2689 1,
2690 2,
2691 I830_FIFO_LINE_SIZE
2692 };
2693
2694 static struct intel_watermark_params ironlake_display_wm_info = {
2695 ILK_DISPLAY_FIFO,
2696 ILK_DISPLAY_MAXWM,
2697 ILK_DISPLAY_DFTWM,
2698 2,
2699 ILK_FIFO_LINE_SIZE
2700 };
2701
2702 static struct intel_watermark_params ironlake_cursor_wm_info = {
2703 ILK_CURSOR_FIFO,
2704 ILK_CURSOR_MAXWM,
2705 ILK_CURSOR_DFTWM,
2706 2,
2707 ILK_FIFO_LINE_SIZE
2708 };
2709
2710 static struct intel_watermark_params ironlake_display_srwm_info = {
2711 ILK_DISPLAY_SR_FIFO,
2712 ILK_DISPLAY_MAX_SRWM,
2713 ILK_DISPLAY_DFT_SRWM,
2714 2,
2715 ILK_FIFO_LINE_SIZE
2716 };
2717
2718 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2719 ILK_CURSOR_SR_FIFO,
2720 ILK_CURSOR_MAX_SRWM,
2721 ILK_CURSOR_DFT_SRWM,
2722 2,
2723 ILK_FIFO_LINE_SIZE
2724 };
2725
2726 /**
2727 * intel_calculate_wm - calculate watermark level
2728 * @clock_in_khz: pixel clock
2729 * @wm: chip FIFO params
2730 * @pixel_size: display pixel size
2731 * @latency_ns: memory latency for the platform
2732 *
2733 * Calculate the watermark level (the level at which the display plane will
2734 * start fetching from memory again). Each chip has a different display
2735 * FIFO size and allocation, so the caller needs to figure that out and pass
2736 * in the correct intel_watermark_params structure.
2737 *
2738 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2739 * on the pixel size. When it reaches the watermark level, it'll start
2740 * fetching FIFO line sized based chunks from memory until the FIFO fills
2741 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2742 * will occur, and a display engine hang could result.
2743 */
2744 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2745 struct intel_watermark_params *wm,
2746 int pixel_size,
2747 unsigned long latency_ns)
2748 {
2749 long entries_required, wm_size;
2750
2751 /*
2752 * Note: we need to make sure we don't overflow for various clock &
2753 * latency values.
2754 * clocks go from a few thousand to several hundred thousand.
2755 * latency is usually a few thousand
2756 */
2757 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2758 1000;
2759 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2760
2761 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2762
2763 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2764
2765 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2766
2767 /* Don't promote wm_size to unsigned... */
2768 if (wm_size > (long)wm->max_wm)
2769 wm_size = wm->max_wm;
2770 if (wm_size <= 0)
2771 wm_size = wm->default_wm;
2772 return wm_size;
2773 }
2774
2775 struct cxsr_latency {
2776 int is_desktop;
2777 int is_ddr3;
2778 unsigned long fsb_freq;
2779 unsigned long mem_freq;
2780 unsigned long display_sr;
2781 unsigned long display_hpll_disable;
2782 unsigned long cursor_sr;
2783 unsigned long cursor_hpll_disable;
2784 };
2785
2786 static const struct cxsr_latency cxsr_latency_table[] = {
2787 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2788 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2789 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2790 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2791 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2792
2793 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2794 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2795 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2796 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2797 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2798
2799 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2800 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2801 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2802 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2803 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2804
2805 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2806 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2807 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2808 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2809 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2810
2811 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2812 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2813 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2814 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2815 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2816
2817 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2818 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2819 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2820 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2821 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2822 };
2823
2824 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2825 int is_ddr3,
2826 int fsb,
2827 int mem)
2828 {
2829 const struct cxsr_latency *latency;
2830 int i;
2831
2832 if (fsb == 0 || mem == 0)
2833 return NULL;
2834
2835 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2836 latency = &cxsr_latency_table[i];
2837 if (is_desktop == latency->is_desktop &&
2838 is_ddr3 == latency->is_ddr3 &&
2839 fsb == latency->fsb_freq && mem == latency->mem_freq)
2840 return latency;
2841 }
2842
2843 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2844
2845 return NULL;
2846 }
2847
2848 static void pineview_disable_cxsr(struct drm_device *dev)
2849 {
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851
2852 /* deactivate cxsr */
2853 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2854 }
2855
2856 /*
2857 * Latency for FIFO fetches is dependent on several factors:
2858 * - memory configuration (speed, channels)
2859 * - chipset
2860 * - current MCH state
2861 * It can be fairly high in some situations, so here we assume a fairly
2862 * pessimal value. It's a tradeoff between extra memory fetches (if we
2863 * set this value too high, the FIFO will fetch frequently to stay full)
2864 * and power consumption (set it too low to save power and we might see
2865 * FIFO underruns and display "flicker").
2866 *
2867 * A value of 5us seems to be a good balance; safe for very low end
2868 * platforms but not overly aggressive on lower latency configs.
2869 */
2870 static const int latency_ns = 5000;
2871
2872 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2873 {
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 uint32_t dsparb = I915_READ(DSPARB);
2876 int size;
2877
2878 size = dsparb & 0x7f;
2879 if (plane)
2880 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2881
2882 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2883 plane ? "B" : "A", size);
2884
2885 return size;
2886 }
2887
2888 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2889 {
2890 struct drm_i915_private *dev_priv = dev->dev_private;
2891 uint32_t dsparb = I915_READ(DSPARB);
2892 int size;
2893
2894 size = dsparb & 0x1ff;
2895 if (plane)
2896 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2897 size >>= 1; /* Convert to cachelines */
2898
2899 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2900 plane ? "B" : "A", size);
2901
2902 return size;
2903 }
2904
2905 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2906 {
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 uint32_t dsparb = I915_READ(DSPARB);
2909 int size;
2910
2911 size = dsparb & 0x7f;
2912 size >>= 2; /* Convert to cachelines */
2913
2914 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2915 plane ? "B" : "A",
2916 size);
2917
2918 return size;
2919 }
2920
2921 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2922 {
2923 struct drm_i915_private *dev_priv = dev->dev_private;
2924 uint32_t dsparb = I915_READ(DSPARB);
2925 int size;
2926
2927 size = dsparb & 0x7f;
2928 size >>= 1; /* Convert to cachelines */
2929
2930 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2931 plane ? "B" : "A", size);
2932
2933 return size;
2934 }
2935
2936 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2937 int planeb_clock, int sr_hdisplay, int unused,
2938 int pixel_size)
2939 {
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2941 const struct cxsr_latency *latency;
2942 u32 reg;
2943 unsigned long wm;
2944 int sr_clock;
2945
2946 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2947 dev_priv->fsb_freq, dev_priv->mem_freq);
2948 if (!latency) {
2949 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2950 pineview_disable_cxsr(dev);
2951 return;
2952 }
2953
2954 if (!planea_clock || !planeb_clock) {
2955 sr_clock = planea_clock ? planea_clock : planeb_clock;
2956
2957 /* Display SR */
2958 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2959 pixel_size, latency->display_sr);
2960 reg = I915_READ(DSPFW1);
2961 reg &= ~DSPFW_SR_MASK;
2962 reg |= wm << DSPFW_SR_SHIFT;
2963 I915_WRITE(DSPFW1, reg);
2964 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2965
2966 /* cursor SR */
2967 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2968 pixel_size, latency->cursor_sr);
2969 reg = I915_READ(DSPFW3);
2970 reg &= ~DSPFW_CURSOR_SR_MASK;
2971 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2972 I915_WRITE(DSPFW3, reg);
2973
2974 /* Display HPLL off SR */
2975 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2976 pixel_size, latency->display_hpll_disable);
2977 reg = I915_READ(DSPFW3);
2978 reg &= ~DSPFW_HPLL_SR_MASK;
2979 reg |= wm & DSPFW_HPLL_SR_MASK;
2980 I915_WRITE(DSPFW3, reg);
2981
2982 /* cursor HPLL off SR */
2983 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2984 pixel_size, latency->cursor_hpll_disable);
2985 reg = I915_READ(DSPFW3);
2986 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2987 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2988 I915_WRITE(DSPFW3, reg);
2989 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2990
2991 /* activate cxsr */
2992 I915_WRITE(DSPFW3,
2993 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
2994 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2995 } else {
2996 pineview_disable_cxsr(dev);
2997 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2998 }
2999 }
3000
3001 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3002 int planeb_clock, int sr_hdisplay, int sr_htotal,
3003 int pixel_size)
3004 {
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 int total_size, cacheline_size;
3007 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3008 struct intel_watermark_params planea_params, planeb_params;
3009 unsigned long line_time_us;
3010 int sr_clock, sr_entries = 0, entries_required;
3011
3012 /* Create copies of the base settings for each pipe */
3013 planea_params = planeb_params = g4x_wm_info;
3014
3015 /* Grab a couple of global values before we overwrite them */
3016 total_size = planea_params.fifo_size;
3017 cacheline_size = planea_params.cacheline_size;
3018
3019 /*
3020 * Note: we need to make sure we don't overflow for various clock &
3021 * latency values.
3022 * clocks go from a few thousand to several hundred thousand.
3023 * latency is usually a few thousand
3024 */
3025 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3026 1000;
3027 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3028 planea_wm = entries_required + planea_params.guard_size;
3029
3030 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3031 1000;
3032 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3033 planeb_wm = entries_required + planeb_params.guard_size;
3034
3035 cursora_wm = cursorb_wm = 16;
3036 cursor_sr = 32;
3037
3038 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3039
3040 /* Calc sr entries for one plane configs */
3041 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3042 /* self-refresh has much higher latency */
3043 static const int sr_latency_ns = 12000;
3044
3045 sr_clock = planea_clock ? planea_clock : planeb_clock;
3046 line_time_us = ((sr_htotal * 1000) / sr_clock);
3047
3048 /* Use ns/us then divide to preserve precision */
3049 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3050 pixel_size * sr_hdisplay;
3051 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3052
3053 entries_required = (((sr_latency_ns / line_time_us) +
3054 1000) / 1000) * pixel_size * 64;
3055 entries_required = DIV_ROUND_UP(entries_required,
3056 g4x_cursor_wm_info.cacheline_size);
3057 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3058
3059 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3060 cursor_sr = g4x_cursor_wm_info.max_wm;
3061 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3062 "cursor %d\n", sr_entries, cursor_sr);
3063
3064 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3065 } else {
3066 /* Turn off self refresh if both pipes are enabled */
3067 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3068 & ~FW_BLC_SELF_EN);
3069 }
3070
3071 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3072 planea_wm, planeb_wm, sr_entries);
3073
3074 planea_wm &= 0x3f;
3075 planeb_wm &= 0x3f;
3076
3077 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3078 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3079 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3080 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3081 (cursora_wm << DSPFW_CURSORA_SHIFT));
3082 /* HPLL off in SR has some issues on G4x... disable it */
3083 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3084 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3085 }
3086
3087 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3088 int planeb_clock, int sr_hdisplay, int sr_htotal,
3089 int pixel_size)
3090 {
3091 struct drm_i915_private *dev_priv = dev->dev_private;
3092 unsigned long line_time_us;
3093 int sr_clock, sr_entries, srwm = 1;
3094 int cursor_sr = 16;
3095
3096 /* Calc sr entries for one plane configs */
3097 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3098 /* self-refresh has much higher latency */
3099 static const int sr_latency_ns = 12000;
3100
3101 sr_clock = planea_clock ? planea_clock : planeb_clock;
3102 line_time_us = ((sr_htotal * 1000) / sr_clock);
3103
3104 /* Use ns/us then divide to preserve precision */
3105 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3106 pixel_size * sr_hdisplay;
3107 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3108 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3109 srwm = I965_FIFO_SIZE - sr_entries;
3110 if (srwm < 0)
3111 srwm = 1;
3112 srwm &= 0x1ff;
3113
3114 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3115 pixel_size * 64;
3116 sr_entries = DIV_ROUND_UP(sr_entries,
3117 i965_cursor_wm_info.cacheline_size);
3118 cursor_sr = i965_cursor_wm_info.fifo_size -
3119 (sr_entries + i965_cursor_wm_info.guard_size);
3120
3121 if (cursor_sr > i965_cursor_wm_info.max_wm)
3122 cursor_sr = i965_cursor_wm_info.max_wm;
3123
3124 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3125 "cursor %d\n", srwm, cursor_sr);
3126
3127 if (IS_I965GM(dev))
3128 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3129 } else {
3130 /* Turn off self refresh if both pipes are enabled */
3131 if (IS_I965GM(dev))
3132 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3133 & ~FW_BLC_SELF_EN);
3134 }
3135
3136 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3137 srwm);
3138
3139 /* 965 has limitations... */
3140 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3141 (8 << 0));
3142 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3143 /* update cursor SR watermark */
3144 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3145 }
3146
3147 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3148 int planeb_clock, int sr_hdisplay, int sr_htotal,
3149 int pixel_size)
3150 {
3151 struct drm_i915_private *dev_priv = dev->dev_private;
3152 uint32_t fwater_lo;
3153 uint32_t fwater_hi;
3154 int total_size, cacheline_size, cwm, srwm = 1;
3155 int planea_wm, planeb_wm;
3156 struct intel_watermark_params planea_params, planeb_params;
3157 unsigned long line_time_us;
3158 int sr_clock, sr_entries = 0;
3159
3160 /* Create copies of the base settings for each pipe */
3161 if (IS_I965GM(dev) || IS_I945GM(dev))
3162 planea_params = planeb_params = i945_wm_info;
3163 else if (IS_I9XX(dev))
3164 planea_params = planeb_params = i915_wm_info;
3165 else
3166 planea_params = planeb_params = i855_wm_info;
3167
3168 /* Grab a couple of global values before we overwrite them */
3169 total_size = planea_params.fifo_size;
3170 cacheline_size = planea_params.cacheline_size;
3171
3172 /* Update per-plane FIFO sizes */
3173 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3174 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3175
3176 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3177 pixel_size, latency_ns);
3178 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3179 pixel_size, latency_ns);
3180 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3181
3182 /*
3183 * Overlay gets an aggressive default since video jitter is bad.
3184 */
3185 cwm = 2;
3186
3187 /* Calc sr entries for one plane configs */
3188 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3189 (!planea_clock || !planeb_clock)) {
3190 /* self-refresh has much higher latency */
3191 static const int sr_latency_ns = 6000;
3192
3193 sr_clock = planea_clock ? planea_clock : planeb_clock;
3194 line_time_us = ((sr_htotal * 1000) / sr_clock);
3195
3196 /* Use ns/us then divide to preserve precision */
3197 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3198 pixel_size * sr_hdisplay;
3199 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3200 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3201 srwm = total_size - sr_entries;
3202 if (srwm < 0)
3203 srwm = 1;
3204
3205 if (IS_I945G(dev) || IS_I945GM(dev))
3206 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3207 else if (IS_I915GM(dev)) {
3208 /* 915M has a smaller SRWM field */
3209 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3210 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3211 }
3212 } else {
3213 /* Turn off self refresh if both pipes are enabled */
3214 if (IS_I945G(dev) || IS_I945GM(dev)) {
3215 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3216 & ~FW_BLC_SELF_EN);
3217 } else if (IS_I915GM(dev)) {
3218 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3219 }
3220 }
3221
3222 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3223 planea_wm, planeb_wm, cwm, srwm);
3224
3225 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3226 fwater_hi = (cwm & 0x1f);
3227
3228 /* Set request length to 8 cachelines per fetch */
3229 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3230 fwater_hi = fwater_hi | (1 << 8);
3231
3232 I915_WRITE(FW_BLC, fwater_lo);
3233 I915_WRITE(FW_BLC2, fwater_hi);
3234 }
3235
3236 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3237 int unused2, int unused3, int pixel_size)
3238 {
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3241 int planea_wm;
3242
3243 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3244
3245 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3246 pixel_size, latency_ns);
3247 fwater_lo |= (3<<8) | planea_wm;
3248
3249 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3250
3251 I915_WRITE(FW_BLC, fwater_lo);
3252 }
3253
3254 #define ILK_LP0_PLANE_LATENCY 700
3255 #define ILK_LP0_CURSOR_LATENCY 1300
3256
3257 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3258 int planeb_clock, int sr_hdisplay, int sr_htotal,
3259 int pixel_size)
3260 {
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3263 int sr_wm, cursor_wm;
3264 unsigned long line_time_us;
3265 int sr_clock, entries_required;
3266 u32 reg_value;
3267 int line_count;
3268 int planea_htotal = 0, planeb_htotal = 0;
3269 struct drm_crtc *crtc;
3270
3271 /* Need htotal for all active display plane */
3272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3274 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3275 if (intel_crtc->plane == 0)
3276 planea_htotal = crtc->mode.htotal;
3277 else
3278 planeb_htotal = crtc->mode.htotal;
3279 }
3280 }
3281
3282 /* Calculate and update the watermark for plane A */
3283 if (planea_clock) {
3284 entries_required = ((planea_clock / 1000) * pixel_size *
3285 ILK_LP0_PLANE_LATENCY) / 1000;
3286 entries_required = DIV_ROUND_UP(entries_required,
3287 ironlake_display_wm_info.cacheline_size);
3288 planea_wm = entries_required +
3289 ironlake_display_wm_info.guard_size;
3290
3291 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3292 planea_wm = ironlake_display_wm_info.max_wm;
3293
3294 /* Use the large buffer method to calculate cursor watermark */
3295 line_time_us = (planea_htotal * 1000) / planea_clock;
3296
3297 /* Use ns/us then divide to preserve precision */
3298 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3299
3300 /* calculate the cursor watermark for cursor A */
3301 entries_required = line_count * 64 * pixel_size;
3302 entries_required = DIV_ROUND_UP(entries_required,
3303 ironlake_cursor_wm_info.cacheline_size);
3304 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3305 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3306 cursora_wm = ironlake_cursor_wm_info.max_wm;
3307
3308 reg_value = I915_READ(WM0_PIPEA_ILK);
3309 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3310 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3311 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3312 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3313 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3314 "cursor: %d\n", planea_wm, cursora_wm);
3315 }
3316 /* Calculate and update the watermark for plane B */
3317 if (planeb_clock) {
3318 entries_required = ((planeb_clock / 1000) * pixel_size *
3319 ILK_LP0_PLANE_LATENCY) / 1000;
3320 entries_required = DIV_ROUND_UP(entries_required,
3321 ironlake_display_wm_info.cacheline_size);
3322 planeb_wm = entries_required +
3323 ironlake_display_wm_info.guard_size;
3324
3325 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3326 planeb_wm = ironlake_display_wm_info.max_wm;
3327
3328 /* Use the large buffer method to calculate cursor watermark */
3329 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3330
3331 /* Use ns/us then divide to preserve precision */
3332 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3333
3334 /* calculate the cursor watermark for cursor B */
3335 entries_required = line_count * 64 * pixel_size;
3336 entries_required = DIV_ROUND_UP(entries_required,
3337 ironlake_cursor_wm_info.cacheline_size);
3338 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3339 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3340 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3341
3342 reg_value = I915_READ(WM0_PIPEB_ILK);
3343 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3344 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3345 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3346 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3347 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3348 "cursor: %d\n", planeb_wm, cursorb_wm);
3349 }
3350
3351 /*
3352 * Calculate and update the self-refresh watermark only when one
3353 * display plane is used.
3354 */
3355 if (!planea_clock || !planeb_clock) {
3356
3357 /* Read the self-refresh latency. The unit is 0.5us */
3358 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3359
3360 sr_clock = planea_clock ? planea_clock : planeb_clock;
3361 line_time_us = ((sr_htotal * 1000) / sr_clock);
3362
3363 /* Use ns/us then divide to preserve precision */
3364 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3365 / 1000;
3366
3367 /* calculate the self-refresh watermark for display plane */
3368 entries_required = line_count * sr_hdisplay * pixel_size;
3369 entries_required = DIV_ROUND_UP(entries_required,
3370 ironlake_display_srwm_info.cacheline_size);
3371 sr_wm = entries_required +
3372 ironlake_display_srwm_info.guard_size;
3373
3374 /* calculate the self-refresh watermark for display cursor */
3375 entries_required = line_count * pixel_size * 64;
3376 entries_required = DIV_ROUND_UP(entries_required,
3377 ironlake_cursor_srwm_info.cacheline_size);
3378 cursor_wm = entries_required +
3379 ironlake_cursor_srwm_info.guard_size;
3380
3381 /* configure watermark and enable self-refresh */
3382 reg_value = I915_READ(WM1_LP_ILK);
3383 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3384 WM1_LP_CURSOR_MASK);
3385 reg_value |= WM1_LP_SR_EN |
3386 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3387 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3388
3389 I915_WRITE(WM1_LP_ILK, reg_value);
3390 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3391 "cursor %d\n", sr_wm, cursor_wm);
3392
3393 } else {
3394 /* Turn off self refresh if both pipes are enabled */
3395 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3396 }
3397 }
3398 /**
3399 * intel_update_watermarks - update FIFO watermark values based on current modes
3400 *
3401 * Calculate watermark values for the various WM regs based on current mode
3402 * and plane configuration.
3403 *
3404 * There are several cases to deal with here:
3405 * - normal (i.e. non-self-refresh)
3406 * - self-refresh (SR) mode
3407 * - lines are large relative to FIFO size (buffer can hold up to 2)
3408 * - lines are small relative to FIFO size (buffer can hold more than 2
3409 * lines), so need to account for TLB latency
3410 *
3411 * The normal calculation is:
3412 * watermark = dotclock * bytes per pixel * latency
3413 * where latency is platform & configuration dependent (we assume pessimal
3414 * values here).
3415 *
3416 * The SR calculation is:
3417 * watermark = (trunc(latency/line time)+1) * surface width *
3418 * bytes per pixel
3419 * where
3420 * line time = htotal / dotclock
3421 * surface width = hdisplay for normal plane and 64 for cursor
3422 * and latency is assumed to be high, as above.
3423 *
3424 * The final value programmed to the register should always be rounded up,
3425 * and include an extra 2 entries to account for clock crossings.
3426 *
3427 * We don't use the sprite, so we can ignore that. And on Crestline we have
3428 * to set the non-SR watermarks to 8.
3429 */
3430 static void intel_update_watermarks(struct drm_device *dev)
3431 {
3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433 struct drm_crtc *crtc;
3434 int sr_hdisplay = 0;
3435 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3436 int enabled = 0, pixel_size = 0;
3437 int sr_htotal = 0;
3438
3439 if (!dev_priv->display.update_wm)
3440 return;
3441
3442 /* Get the clock config from both planes */
3443 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3446 enabled++;
3447 if (intel_crtc->plane == 0) {
3448 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3449 intel_crtc->pipe, crtc->mode.clock);
3450 planea_clock = crtc->mode.clock;
3451 } else {
3452 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3453 intel_crtc->pipe, crtc->mode.clock);
3454 planeb_clock = crtc->mode.clock;
3455 }
3456 sr_hdisplay = crtc->mode.hdisplay;
3457 sr_clock = crtc->mode.clock;
3458 sr_htotal = crtc->mode.htotal;
3459 if (crtc->fb)
3460 pixel_size = crtc->fb->bits_per_pixel / 8;
3461 else
3462 pixel_size = 4; /* by default */
3463 }
3464 }
3465
3466 if (enabled <= 0)
3467 return;
3468
3469 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3470 sr_hdisplay, sr_htotal, pixel_size);
3471 }
3472
3473 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3474 struct drm_display_mode *mode,
3475 struct drm_display_mode *adjusted_mode,
3476 int x, int y,
3477 struct drm_framebuffer *old_fb)
3478 {
3479 struct drm_device *dev = crtc->dev;
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482 int pipe = intel_crtc->pipe;
3483 int plane = intel_crtc->plane;
3484 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3485 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3486 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3487 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3488 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3489 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3490 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3491 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3492 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3493 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3494 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3495 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3496 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3497 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3498 int refclk, num_connectors = 0;
3499 intel_clock_t clock, reduced_clock;
3500 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3501 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3502 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3503 struct intel_encoder *has_edp_encoder = NULL;
3504 struct drm_mode_config *mode_config = &dev->mode_config;
3505 struct drm_encoder *encoder;
3506 const intel_limit_t *limit;
3507 int ret;
3508 struct fdi_m_n m_n = {0};
3509 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3510 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3511 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3512 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3513 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3514 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3515 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3516 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3517 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3518 int lvds_reg = LVDS;
3519 u32 temp;
3520 int sdvo_pixel_multiply;
3521 int target_clock;
3522
3523 drm_vblank_pre_modeset(dev, pipe);
3524
3525 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3526 struct intel_encoder *intel_encoder;
3527
3528 if (encoder->crtc != crtc)
3529 continue;
3530
3531 intel_encoder = enc_to_intel_encoder(encoder);
3532 switch (intel_encoder->type) {
3533 case INTEL_OUTPUT_LVDS:
3534 is_lvds = true;
3535 break;
3536 case INTEL_OUTPUT_SDVO:
3537 case INTEL_OUTPUT_HDMI:
3538 is_sdvo = true;
3539 if (intel_encoder->needs_tv_clock)
3540 is_tv = true;
3541 break;
3542 case INTEL_OUTPUT_DVO:
3543 is_dvo = true;
3544 break;
3545 case INTEL_OUTPUT_TVOUT:
3546 is_tv = true;
3547 break;
3548 case INTEL_OUTPUT_ANALOG:
3549 is_crt = true;
3550 break;
3551 case INTEL_OUTPUT_DISPLAYPORT:
3552 is_dp = true;
3553 break;
3554 case INTEL_OUTPUT_EDP:
3555 has_edp_encoder = intel_encoder;
3556 break;
3557 }
3558
3559 num_connectors++;
3560 }
3561
3562 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3563 refclk = dev_priv->lvds_ssc_freq * 1000;
3564 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3565 refclk / 1000);
3566 } else if (IS_I9XX(dev)) {
3567 refclk = 96000;
3568 if (HAS_PCH_SPLIT(dev))
3569 refclk = 120000; /* 120Mhz refclk */
3570 } else {
3571 refclk = 48000;
3572 }
3573
3574
3575 /*
3576 * Returns a set of divisors for the desired target clock with the given
3577 * refclk, or FALSE. The returned values represent the clock equation:
3578 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3579 */
3580 limit = intel_limit(crtc);
3581 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3582 if (!ok) {
3583 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3584 drm_vblank_post_modeset(dev, pipe);
3585 return -EINVAL;
3586 }
3587
3588 /* Ensure that the cursor is valid for the new mode before changing... */
3589 intel_crtc_update_cursor(crtc);
3590
3591 if (is_lvds && dev_priv->lvds_downclock_avail) {
3592 has_reduced_clock = limit->find_pll(limit, crtc,
3593 dev_priv->lvds_downclock,
3594 refclk,
3595 &reduced_clock);
3596 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3597 /*
3598 * If the different P is found, it means that we can't
3599 * switch the display clock by using the FP0/FP1.
3600 * In such case we will disable the LVDS downclock
3601 * feature.
3602 */
3603 DRM_DEBUG_KMS("Different P is found for "
3604 "LVDS clock/downclock\n");
3605 has_reduced_clock = 0;
3606 }
3607 }
3608 /* SDVO TV has fixed PLL values depend on its clock range,
3609 this mirrors vbios setting. */
3610 if (is_sdvo && is_tv) {
3611 if (adjusted_mode->clock >= 100000
3612 && adjusted_mode->clock < 140500) {
3613 clock.p1 = 2;
3614 clock.p2 = 10;
3615 clock.n = 3;
3616 clock.m1 = 16;
3617 clock.m2 = 8;
3618 } else if (adjusted_mode->clock >= 140500
3619 && adjusted_mode->clock <= 200000) {
3620 clock.p1 = 1;
3621 clock.p2 = 10;
3622 clock.n = 6;
3623 clock.m1 = 12;
3624 clock.m2 = 8;
3625 }
3626 }
3627
3628 /* FDI link */
3629 if (HAS_PCH_SPLIT(dev)) {
3630 int lane = 0, link_bw, bpp;
3631 /* eDP doesn't require FDI link, so just set DP M/N
3632 according to current link config */
3633 if (has_edp_encoder) {
3634 target_clock = mode->clock;
3635 intel_edp_link_config(has_edp_encoder,
3636 &lane, &link_bw);
3637 } else {
3638 /* DP over FDI requires target mode clock
3639 instead of link clock */
3640 if (is_dp)
3641 target_clock = mode->clock;
3642 else
3643 target_clock = adjusted_mode->clock;
3644 link_bw = 270000;
3645 }
3646
3647 /* determine panel color depth */
3648 temp = I915_READ(pipeconf_reg);
3649 temp &= ~PIPE_BPC_MASK;
3650 if (is_lvds) {
3651 int lvds_reg = I915_READ(PCH_LVDS);
3652 /* the BPC will be 6 if it is 18-bit LVDS panel */
3653 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3654 temp |= PIPE_8BPC;
3655 else
3656 temp |= PIPE_6BPC;
3657 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3658 switch (dev_priv->edp_bpp/3) {
3659 case 8:
3660 temp |= PIPE_8BPC;
3661 break;
3662 case 10:
3663 temp |= PIPE_10BPC;
3664 break;
3665 case 6:
3666 temp |= PIPE_6BPC;
3667 break;
3668 case 12:
3669 temp |= PIPE_12BPC;
3670 break;
3671 }
3672 } else
3673 temp |= PIPE_8BPC;
3674 I915_WRITE(pipeconf_reg, temp);
3675 I915_READ(pipeconf_reg);
3676
3677 switch (temp & PIPE_BPC_MASK) {
3678 case PIPE_8BPC:
3679 bpp = 24;
3680 break;
3681 case PIPE_10BPC:
3682 bpp = 30;
3683 break;
3684 case PIPE_6BPC:
3685 bpp = 18;
3686 break;
3687 case PIPE_12BPC:
3688 bpp = 36;
3689 break;
3690 default:
3691 DRM_ERROR("unknown pipe bpc value\n");
3692 bpp = 24;
3693 }
3694
3695 if (!lane) {
3696 /*
3697 * Account for spread spectrum to avoid
3698 * oversubscribing the link. Max center spread
3699 * is 2.5%; use 5% for safety's sake.
3700 */
3701 u32 bps = target_clock * bpp * 21 / 20;
3702 lane = bps / (link_bw * 8) + 1;
3703 }
3704
3705 intel_crtc->fdi_lanes = lane;
3706
3707 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3708 }
3709
3710 /* Ironlake: try to setup display ref clock before DPLL
3711 * enabling. This is only under driver's control after
3712 * PCH B stepping, previous chipset stepping should be
3713 * ignoring this setting.
3714 */
3715 if (HAS_PCH_SPLIT(dev)) {
3716 temp = I915_READ(PCH_DREF_CONTROL);
3717 /* Always enable nonspread source */
3718 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3719 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3720 I915_WRITE(PCH_DREF_CONTROL, temp);
3721 POSTING_READ(PCH_DREF_CONTROL);
3722
3723 temp &= ~DREF_SSC_SOURCE_MASK;
3724 temp |= DREF_SSC_SOURCE_ENABLE;
3725 I915_WRITE(PCH_DREF_CONTROL, temp);
3726 POSTING_READ(PCH_DREF_CONTROL);
3727
3728 udelay(200);
3729
3730 if (has_edp_encoder) {
3731 if (dev_priv->lvds_use_ssc) {
3732 temp |= DREF_SSC1_ENABLE;
3733 I915_WRITE(PCH_DREF_CONTROL, temp);
3734 POSTING_READ(PCH_DREF_CONTROL);
3735
3736 udelay(200);
3737
3738 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3739 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3740 I915_WRITE(PCH_DREF_CONTROL, temp);
3741 POSTING_READ(PCH_DREF_CONTROL);
3742 } else {
3743 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3744 I915_WRITE(PCH_DREF_CONTROL, temp);
3745 POSTING_READ(PCH_DREF_CONTROL);
3746 }
3747 }
3748 }
3749
3750 if (IS_PINEVIEW(dev)) {
3751 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3752 if (has_reduced_clock)
3753 fp2 = (1 << reduced_clock.n) << 16 |
3754 reduced_clock.m1 << 8 | reduced_clock.m2;
3755 } else {
3756 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3757 if (has_reduced_clock)
3758 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3759 reduced_clock.m2;
3760 }
3761
3762 if (!HAS_PCH_SPLIT(dev))
3763 dpll = DPLL_VGA_MODE_DIS;
3764
3765 if (IS_I9XX(dev)) {
3766 if (is_lvds)
3767 dpll |= DPLLB_MODE_LVDS;
3768 else
3769 dpll |= DPLLB_MODE_DAC_SERIAL;
3770 if (is_sdvo) {
3771 dpll |= DPLL_DVO_HIGH_SPEED;
3772 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3773 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3774 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3775 else if (HAS_PCH_SPLIT(dev))
3776 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3777 }
3778 if (is_dp)
3779 dpll |= DPLL_DVO_HIGH_SPEED;
3780
3781 /* compute bitmask from p1 value */
3782 if (IS_PINEVIEW(dev))
3783 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3784 else {
3785 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3786 /* also FPA1 */
3787 if (HAS_PCH_SPLIT(dev))
3788 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3789 if (IS_G4X(dev) && has_reduced_clock)
3790 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3791 }
3792 switch (clock.p2) {
3793 case 5:
3794 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3795 break;
3796 case 7:
3797 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3798 break;
3799 case 10:
3800 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3801 break;
3802 case 14:
3803 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3804 break;
3805 }
3806 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3807 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3808 } else {
3809 if (is_lvds) {
3810 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3811 } else {
3812 if (clock.p1 == 2)
3813 dpll |= PLL_P1_DIVIDE_BY_TWO;
3814 else
3815 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3816 if (clock.p2 == 4)
3817 dpll |= PLL_P2_DIVIDE_BY_4;
3818 }
3819 }
3820
3821 if (is_sdvo && is_tv)
3822 dpll |= PLL_REF_INPUT_TVCLKINBC;
3823 else if (is_tv)
3824 /* XXX: just matching BIOS for now */
3825 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3826 dpll |= 3;
3827 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3828 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3829 else
3830 dpll |= PLL_REF_INPUT_DREFCLK;
3831
3832 /* setup pipeconf */
3833 pipeconf = I915_READ(pipeconf_reg);
3834
3835 /* Set up the display plane register */
3836 dspcntr = DISPPLANE_GAMMA_ENABLE;
3837
3838 /* Ironlake's plane is forced to pipe, bit 24 is to
3839 enable color space conversion */
3840 if (!HAS_PCH_SPLIT(dev)) {
3841 if (pipe == 0)
3842 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3843 else
3844 dspcntr |= DISPPLANE_SEL_PIPE_B;
3845 }
3846
3847 if (pipe == 0 && !IS_I965G(dev)) {
3848 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3849 * core speed.
3850 *
3851 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3852 * pipe == 0 check?
3853 */
3854 if (mode->clock >
3855 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3856 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3857 else
3858 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3859 }
3860
3861 dspcntr |= DISPLAY_PLANE_ENABLE;
3862 pipeconf |= PIPEACONF_ENABLE;
3863 dpll |= DPLL_VCO_ENABLE;
3864
3865
3866 /* Disable the panel fitter if it was on our pipe */
3867 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3868 I915_WRITE(PFIT_CONTROL, 0);
3869
3870 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3871 drm_mode_debug_printmodeline(mode);
3872
3873 /* assign to Ironlake registers */
3874 if (HAS_PCH_SPLIT(dev)) {
3875 fp_reg = pch_fp_reg;
3876 dpll_reg = pch_dpll_reg;
3877 }
3878
3879 if (!has_edp_encoder) {
3880 I915_WRITE(fp_reg, fp);
3881 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3882 I915_READ(dpll_reg);
3883 udelay(150);
3884 }
3885
3886 /* enable transcoder DPLL */
3887 if (HAS_PCH_CPT(dev)) {
3888 temp = I915_READ(PCH_DPLL_SEL);
3889 if (trans_dpll_sel == 0)
3890 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3891 else
3892 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3893 I915_WRITE(PCH_DPLL_SEL, temp);
3894 I915_READ(PCH_DPLL_SEL);
3895 udelay(150);
3896 }
3897
3898 if (HAS_PCH_SPLIT(dev)) {
3899 pipeconf &= ~PIPE_ENABLE_DITHER;
3900 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3901 }
3902
3903 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3904 * This is an exception to the general rule that mode_set doesn't turn
3905 * things on.
3906 */
3907 if (is_lvds) {
3908 u32 lvds;
3909
3910 if (HAS_PCH_SPLIT(dev))
3911 lvds_reg = PCH_LVDS;
3912
3913 lvds = I915_READ(lvds_reg);
3914 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3915 if (pipe == 1) {
3916 if (HAS_PCH_CPT(dev))
3917 lvds |= PORT_TRANS_B_SEL_CPT;
3918 else
3919 lvds |= LVDS_PIPEB_SELECT;
3920 } else {
3921 if (HAS_PCH_CPT(dev))
3922 lvds &= ~PORT_TRANS_SEL_MASK;
3923 else
3924 lvds &= ~LVDS_PIPEB_SELECT;
3925 }
3926 /* set the corresponsding LVDS_BORDER bit */
3927 lvds |= dev_priv->lvds_border_bits;
3928 /* Set the B0-B3 data pairs corresponding to whether we're going to
3929 * set the DPLLs for dual-channel mode or not.
3930 */
3931 if (clock.p2 == 7)
3932 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3933 else
3934 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3935
3936 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3937 * appropriately here, but we need to look more thoroughly into how
3938 * panels behave in the two modes.
3939 */
3940 /* set the dithering flag */
3941 if (IS_I965G(dev)) {
3942 if (dev_priv->lvds_dither) {
3943 if (HAS_PCH_SPLIT(dev)) {
3944 pipeconf |= PIPE_ENABLE_DITHER;
3945 pipeconf |= PIPE_DITHER_TYPE_ST01;
3946 } else
3947 lvds |= LVDS_ENABLE_DITHER;
3948 } else {
3949 if (!HAS_PCH_SPLIT(dev)) {
3950 lvds &= ~LVDS_ENABLE_DITHER;
3951 }
3952 }
3953 }
3954 I915_WRITE(lvds_reg, lvds);
3955 I915_READ(lvds_reg);
3956 }
3957 if (is_dp)
3958 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3959 else if (HAS_PCH_SPLIT(dev)) {
3960 /* For non-DP output, clear any trans DP clock recovery setting.*/
3961 if (pipe == 0) {
3962 I915_WRITE(TRANSA_DATA_M1, 0);
3963 I915_WRITE(TRANSA_DATA_N1, 0);
3964 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3965 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3966 } else {
3967 I915_WRITE(TRANSB_DATA_M1, 0);
3968 I915_WRITE(TRANSB_DATA_N1, 0);
3969 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3970 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3971 }
3972 }
3973
3974 if (!has_edp_encoder) {
3975 I915_WRITE(fp_reg, fp);
3976 I915_WRITE(dpll_reg, dpll);
3977 I915_READ(dpll_reg);
3978 /* Wait for the clocks to stabilize. */
3979 udelay(150);
3980
3981 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3982 if (is_sdvo) {
3983 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3984 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3985 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3986 } else
3987 I915_WRITE(dpll_md_reg, 0);
3988 } else {
3989 /* write it again -- the BIOS does, after all */
3990 I915_WRITE(dpll_reg, dpll);
3991 }
3992 I915_READ(dpll_reg);
3993 /* Wait for the clocks to stabilize. */
3994 udelay(150);
3995 }
3996
3997 if (is_lvds && has_reduced_clock && i915_powersave) {
3998 I915_WRITE(fp_reg + 4, fp2);
3999 intel_crtc->lowfreq_avail = true;
4000 if (HAS_PIPE_CXSR(dev)) {
4001 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4002 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4003 }
4004 } else {
4005 I915_WRITE(fp_reg + 4, fp);
4006 intel_crtc->lowfreq_avail = false;
4007 if (HAS_PIPE_CXSR(dev)) {
4008 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4009 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4010 }
4011 }
4012
4013 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4014 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4015 /* the chip adds 2 halflines automatically */
4016 adjusted_mode->crtc_vdisplay -= 1;
4017 adjusted_mode->crtc_vtotal -= 1;
4018 adjusted_mode->crtc_vblank_start -= 1;
4019 adjusted_mode->crtc_vblank_end -= 1;
4020 adjusted_mode->crtc_vsync_end -= 1;
4021 adjusted_mode->crtc_vsync_start -= 1;
4022 } else
4023 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4024
4025 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4026 ((adjusted_mode->crtc_htotal - 1) << 16));
4027 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4028 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4029 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4030 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4031 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4032 ((adjusted_mode->crtc_vtotal - 1) << 16));
4033 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4034 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4035 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4036 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4037 /* pipesrc and dspsize control the size that is scaled from, which should
4038 * always be the user's requested size.
4039 */
4040 if (!HAS_PCH_SPLIT(dev)) {
4041 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4042 (mode->hdisplay - 1));
4043 I915_WRITE(dsppos_reg, 0);
4044 }
4045 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4046
4047 if (HAS_PCH_SPLIT(dev)) {
4048 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4049 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4050 I915_WRITE(link_m1_reg, m_n.link_m);
4051 I915_WRITE(link_n1_reg, m_n.link_n);
4052
4053 if (has_edp_encoder) {
4054 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4055 } else {
4056 /* enable FDI RX PLL too */
4057 temp = I915_READ(fdi_rx_reg);
4058 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4059 I915_READ(fdi_rx_reg);
4060 udelay(200);
4061
4062 /* enable FDI TX PLL too */
4063 temp = I915_READ(fdi_tx_reg);
4064 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4065 I915_READ(fdi_tx_reg);
4066
4067 /* enable FDI RX PCDCLK */
4068 temp = I915_READ(fdi_rx_reg);
4069 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4070 I915_READ(fdi_rx_reg);
4071 udelay(200);
4072 }
4073 }
4074
4075 I915_WRITE(pipeconf_reg, pipeconf);
4076 I915_READ(pipeconf_reg);
4077
4078 intel_wait_for_vblank(dev, pipe);
4079
4080 if (IS_IRONLAKE(dev)) {
4081 /* enable address swizzle for tiling buffer */
4082 temp = I915_READ(DISP_ARB_CTL);
4083 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4084 }
4085
4086 I915_WRITE(dspcntr_reg, dspcntr);
4087
4088 /* Flush the plane changes */
4089 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4090
4091 intel_update_watermarks(dev);
4092
4093 drm_vblank_post_modeset(dev, pipe);
4094
4095 return ret;
4096 }
4097
4098 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4099 void intel_crtc_load_lut(struct drm_crtc *crtc)
4100 {
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4105 int i;
4106
4107 /* The clocks have to be on to load the palette. */
4108 if (!crtc->enabled)
4109 return;
4110
4111 /* use legacy palette for Ironlake */
4112 if (HAS_PCH_SPLIT(dev))
4113 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4114 LGC_PALETTE_B;
4115
4116 for (i = 0; i < 256; i++) {
4117 I915_WRITE(palreg + 4 * i,
4118 (intel_crtc->lut_r[i] << 16) |
4119 (intel_crtc->lut_g[i] << 8) |
4120 intel_crtc->lut_b[i]);
4121 }
4122 }
4123
4124 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4125 {
4126 struct drm_device *dev = crtc->dev;
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 bool visible = base != 0;
4130 u32 cntl;
4131
4132 if (intel_crtc->cursor_visible == visible)
4133 return;
4134
4135 cntl = I915_READ(CURACNTR);
4136 if (visible) {
4137 /* On these chipsets we can only modify the base whilst
4138 * the cursor is disabled.
4139 */
4140 I915_WRITE(CURABASE, base);
4141
4142 cntl &= ~(CURSOR_FORMAT_MASK);
4143 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4144 cntl |= CURSOR_ENABLE |
4145 CURSOR_GAMMA_ENABLE |
4146 CURSOR_FORMAT_ARGB;
4147 } else
4148 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4149 I915_WRITE(CURACNTR, cntl);
4150
4151 intel_crtc->cursor_visible = visible;
4152 }
4153
4154 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4155 {
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159 int pipe = intel_crtc->pipe;
4160 bool visible = base != 0;
4161
4162 if (intel_crtc->cursor_visible != visible) {
4163 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4164 if (base) {
4165 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4166 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4167 cntl |= pipe << 28; /* Connect to correct pipe */
4168 } else {
4169 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4170 cntl |= CURSOR_MODE_DISABLE;
4171 }
4172 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4173
4174 intel_crtc->cursor_visible = visible;
4175 }
4176 /* and commit changes on next vblank */
4177 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4178 }
4179
4180 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4181 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4182 {
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186 int pipe = intel_crtc->pipe;
4187 int x = intel_crtc->cursor_x;
4188 int y = intel_crtc->cursor_y;
4189 u32 base, pos;
4190 bool visible;
4191
4192 pos = 0;
4193
4194 if (intel_crtc->cursor_on && crtc->fb) {
4195 base = intel_crtc->cursor_addr;
4196 if (x > (int) crtc->fb->width)
4197 base = 0;
4198
4199 if (y > (int) crtc->fb->height)
4200 base = 0;
4201 } else
4202 base = 0;
4203
4204 if (x < 0) {
4205 if (x + intel_crtc->cursor_width < 0)
4206 base = 0;
4207
4208 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4209 x = -x;
4210 }
4211 pos |= x << CURSOR_X_SHIFT;
4212
4213 if (y < 0) {
4214 if (y + intel_crtc->cursor_height < 0)
4215 base = 0;
4216
4217 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4218 y = -y;
4219 }
4220 pos |= y << CURSOR_Y_SHIFT;
4221
4222 visible = base != 0;
4223 if (!visible && !intel_crtc->cursor_visible)
4224 return;
4225
4226 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4227 if (IS_845G(dev) || IS_I865G(dev))
4228 i845_update_cursor(crtc, base);
4229 else
4230 i9xx_update_cursor(crtc, base);
4231
4232 if (visible)
4233 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4234 }
4235
4236 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4237 struct drm_file *file_priv,
4238 uint32_t handle,
4239 uint32_t width, uint32_t height)
4240 {
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 struct drm_gem_object *bo;
4245 struct drm_i915_gem_object *obj_priv;
4246 uint32_t addr;
4247 int ret;
4248
4249 DRM_DEBUG_KMS("\n");
4250
4251 /* if we want to turn off the cursor ignore width and height */
4252 if (!handle) {
4253 DRM_DEBUG_KMS("cursor off\n");
4254 addr = 0;
4255 bo = NULL;
4256 mutex_lock(&dev->struct_mutex);
4257 goto finish;
4258 }
4259
4260 /* Currently we only support 64x64 cursors */
4261 if (width != 64 || height != 64) {
4262 DRM_ERROR("we currently only support 64x64 cursors\n");
4263 return -EINVAL;
4264 }
4265
4266 bo = drm_gem_object_lookup(dev, file_priv, handle);
4267 if (!bo)
4268 return -ENOENT;
4269
4270 obj_priv = to_intel_bo(bo);
4271
4272 if (bo->size < width * height * 4) {
4273 DRM_ERROR("buffer is to small\n");
4274 ret = -ENOMEM;
4275 goto fail;
4276 }
4277
4278 /* we only need to pin inside GTT if cursor is non-phy */
4279 mutex_lock(&dev->struct_mutex);
4280 if (!dev_priv->info->cursor_needs_physical) {
4281 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4282 if (ret) {
4283 DRM_ERROR("failed to pin cursor bo\n");
4284 goto fail_locked;
4285 }
4286
4287 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4288 if (ret) {
4289 DRM_ERROR("failed to move cursor bo into the GTT\n");
4290 goto fail_unpin;
4291 }
4292
4293 addr = obj_priv->gtt_offset;
4294 } else {
4295 int align = IS_I830(dev) ? 16 * 1024 : 256;
4296 ret = i915_gem_attach_phys_object(dev, bo,
4297 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4298 align);
4299 if (ret) {
4300 DRM_ERROR("failed to attach phys object\n");
4301 goto fail_locked;
4302 }
4303 addr = obj_priv->phys_obj->handle->busaddr;
4304 }
4305
4306 if (!IS_I9XX(dev))
4307 I915_WRITE(CURSIZE, (height << 12) | width);
4308
4309 finish:
4310 if (intel_crtc->cursor_bo) {
4311 if (dev_priv->info->cursor_needs_physical) {
4312 if (intel_crtc->cursor_bo != bo)
4313 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4314 } else
4315 i915_gem_object_unpin(intel_crtc->cursor_bo);
4316 drm_gem_object_unreference(intel_crtc->cursor_bo);
4317 }
4318
4319 mutex_unlock(&dev->struct_mutex);
4320
4321 intel_crtc->cursor_addr = addr;
4322 intel_crtc->cursor_bo = bo;
4323 intel_crtc->cursor_width = width;
4324 intel_crtc->cursor_height = height;
4325
4326 intel_crtc_update_cursor(crtc);
4327
4328 return 0;
4329 fail_unpin:
4330 i915_gem_object_unpin(bo);
4331 fail_locked:
4332 mutex_unlock(&dev->struct_mutex);
4333 fail:
4334 drm_gem_object_unreference_unlocked(bo);
4335 return ret;
4336 }
4337
4338 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4339 {
4340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4341
4342 intel_crtc->cursor_x = x;
4343 intel_crtc->cursor_y = y;
4344
4345 intel_crtc_update_cursor(crtc);
4346
4347 return 0;
4348 }
4349
4350 /** Sets the color ramps on behalf of RandR */
4351 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4352 u16 blue, int regno)
4353 {
4354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4355
4356 intel_crtc->lut_r[regno] = red >> 8;
4357 intel_crtc->lut_g[regno] = green >> 8;
4358 intel_crtc->lut_b[regno] = blue >> 8;
4359 }
4360
4361 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4362 u16 *blue, int regno)
4363 {
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365
4366 *red = intel_crtc->lut_r[regno] << 8;
4367 *green = intel_crtc->lut_g[regno] << 8;
4368 *blue = intel_crtc->lut_b[regno] << 8;
4369 }
4370
4371 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4372 u16 *blue, uint32_t start, uint32_t size)
4373 {
4374 int end = (start + size > 256) ? 256 : start + size, i;
4375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4376
4377 for (i = start; i < end; i++) {
4378 intel_crtc->lut_r[i] = red[i] >> 8;
4379 intel_crtc->lut_g[i] = green[i] >> 8;
4380 intel_crtc->lut_b[i] = blue[i] >> 8;
4381 }
4382
4383 intel_crtc_load_lut(crtc);
4384 }
4385
4386 /**
4387 * Get a pipe with a simple mode set on it for doing load-based monitor
4388 * detection.
4389 *
4390 * It will be up to the load-detect code to adjust the pipe as appropriate for
4391 * its requirements. The pipe will be connected to no other encoders.
4392 *
4393 * Currently this code will only succeed if there is a pipe with no encoders
4394 * configured for it. In the future, it could choose to temporarily disable
4395 * some outputs to free up a pipe for its use.
4396 *
4397 * \return crtc, or NULL if no pipes are available.
4398 */
4399
4400 /* VESA 640x480x72Hz mode to set on the pipe */
4401 static struct drm_display_mode load_detect_mode = {
4402 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4403 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4404 };
4405
4406 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4407 struct drm_connector *connector,
4408 struct drm_display_mode *mode,
4409 int *dpms_mode)
4410 {
4411 struct intel_crtc *intel_crtc;
4412 struct drm_crtc *possible_crtc;
4413 struct drm_crtc *supported_crtc =NULL;
4414 struct drm_encoder *encoder = &intel_encoder->enc;
4415 struct drm_crtc *crtc = NULL;
4416 struct drm_device *dev = encoder->dev;
4417 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4418 struct drm_crtc_helper_funcs *crtc_funcs;
4419 int i = -1;
4420
4421 /*
4422 * Algorithm gets a little messy:
4423 * - if the connector already has an assigned crtc, use it (but make
4424 * sure it's on first)
4425 * - try to find the first unused crtc that can drive this connector,
4426 * and use that if we find one
4427 * - if there are no unused crtcs available, try to use the first
4428 * one we found that supports the connector
4429 */
4430
4431 /* See if we already have a CRTC for this connector */
4432 if (encoder->crtc) {
4433 crtc = encoder->crtc;
4434 /* Make sure the crtc and connector are running */
4435 intel_crtc = to_intel_crtc(crtc);
4436 *dpms_mode = intel_crtc->dpms_mode;
4437 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4438 crtc_funcs = crtc->helper_private;
4439 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4440 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4441 }
4442 return crtc;
4443 }
4444
4445 /* Find an unused one (if possible) */
4446 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4447 i++;
4448 if (!(encoder->possible_crtcs & (1 << i)))
4449 continue;
4450 if (!possible_crtc->enabled) {
4451 crtc = possible_crtc;
4452 break;
4453 }
4454 if (!supported_crtc)
4455 supported_crtc = possible_crtc;
4456 }
4457
4458 /*
4459 * If we didn't find an unused CRTC, don't use any.
4460 */
4461 if (!crtc) {
4462 return NULL;
4463 }
4464
4465 encoder->crtc = crtc;
4466 connector->encoder = encoder;
4467 intel_encoder->load_detect_temp = true;
4468
4469 intel_crtc = to_intel_crtc(crtc);
4470 *dpms_mode = intel_crtc->dpms_mode;
4471
4472 if (!crtc->enabled) {
4473 if (!mode)
4474 mode = &load_detect_mode;
4475 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4476 } else {
4477 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4478 crtc_funcs = crtc->helper_private;
4479 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4480 }
4481
4482 /* Add this connector to the crtc */
4483 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4484 encoder_funcs->commit(encoder);
4485 }
4486 /* let the connector get through one full cycle before testing */
4487 intel_wait_for_vblank(dev, intel_crtc->pipe);
4488
4489 return crtc;
4490 }
4491
4492 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4493 struct drm_connector *connector, int dpms_mode)
4494 {
4495 struct drm_encoder *encoder = &intel_encoder->enc;
4496 struct drm_device *dev = encoder->dev;
4497 struct drm_crtc *crtc = encoder->crtc;
4498 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4499 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4500
4501 if (intel_encoder->load_detect_temp) {
4502 encoder->crtc = NULL;
4503 connector->encoder = NULL;
4504 intel_encoder->load_detect_temp = false;
4505 crtc->enabled = drm_helper_crtc_in_use(crtc);
4506 drm_helper_disable_unused_functions(dev);
4507 }
4508
4509 /* Switch crtc and encoder back off if necessary */
4510 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4511 if (encoder->crtc == crtc)
4512 encoder_funcs->dpms(encoder, dpms_mode);
4513 crtc_funcs->dpms(crtc, dpms_mode);
4514 }
4515 }
4516
4517 /* Returns the clock of the currently programmed mode of the given pipe. */
4518 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4519 {
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4522 int pipe = intel_crtc->pipe;
4523 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4524 u32 fp;
4525 intel_clock_t clock;
4526
4527 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4528 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4529 else
4530 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4531
4532 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4533 if (IS_PINEVIEW(dev)) {
4534 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4535 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4536 } else {
4537 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4538 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4539 }
4540
4541 if (IS_I9XX(dev)) {
4542 if (IS_PINEVIEW(dev))
4543 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4544 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4545 else
4546 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4547 DPLL_FPA01_P1_POST_DIV_SHIFT);
4548
4549 switch (dpll & DPLL_MODE_MASK) {
4550 case DPLLB_MODE_DAC_SERIAL:
4551 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4552 5 : 10;
4553 break;
4554 case DPLLB_MODE_LVDS:
4555 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4556 7 : 14;
4557 break;
4558 default:
4559 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4560 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4561 return 0;
4562 }
4563
4564 /* XXX: Handle the 100Mhz refclk */
4565 intel_clock(dev, 96000, &clock);
4566 } else {
4567 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4568
4569 if (is_lvds) {
4570 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4571 DPLL_FPA01_P1_POST_DIV_SHIFT);
4572 clock.p2 = 14;
4573
4574 if ((dpll & PLL_REF_INPUT_MASK) ==
4575 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4576 /* XXX: might not be 66MHz */
4577 intel_clock(dev, 66000, &clock);
4578 } else
4579 intel_clock(dev, 48000, &clock);
4580 } else {
4581 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4582 clock.p1 = 2;
4583 else {
4584 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4585 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4586 }
4587 if (dpll & PLL_P2_DIVIDE_BY_4)
4588 clock.p2 = 4;
4589 else
4590 clock.p2 = 2;
4591
4592 intel_clock(dev, 48000, &clock);
4593 }
4594 }
4595
4596 /* XXX: It would be nice to validate the clocks, but we can't reuse
4597 * i830PllIsValid() because it relies on the xf86_config connector
4598 * configuration being accurate, which it isn't necessarily.
4599 */
4600
4601 return clock.dot;
4602 }
4603
4604 /** Returns the currently programmed mode of the given pipe. */
4605 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4606 struct drm_crtc *crtc)
4607 {
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610 int pipe = intel_crtc->pipe;
4611 struct drm_display_mode *mode;
4612 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4613 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4614 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4615 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4616
4617 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4618 if (!mode)
4619 return NULL;
4620
4621 mode->clock = intel_crtc_clock_get(dev, crtc);
4622 mode->hdisplay = (htot & 0xffff) + 1;
4623 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4624 mode->hsync_start = (hsync & 0xffff) + 1;
4625 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4626 mode->vdisplay = (vtot & 0xffff) + 1;
4627 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4628 mode->vsync_start = (vsync & 0xffff) + 1;
4629 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4630
4631 drm_mode_set_name(mode);
4632 drm_mode_set_crtcinfo(mode, 0);
4633
4634 return mode;
4635 }
4636
4637 #define GPU_IDLE_TIMEOUT 500 /* ms */
4638
4639 /* When this timer fires, we've been idle for awhile */
4640 static void intel_gpu_idle_timer(unsigned long arg)
4641 {
4642 struct drm_device *dev = (struct drm_device *)arg;
4643 drm_i915_private_t *dev_priv = dev->dev_private;
4644
4645 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4646
4647 dev_priv->busy = false;
4648
4649 queue_work(dev_priv->wq, &dev_priv->idle_work);
4650 }
4651
4652 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4653
4654 static void intel_crtc_idle_timer(unsigned long arg)
4655 {
4656 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4657 struct drm_crtc *crtc = &intel_crtc->base;
4658 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4659
4660 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4661
4662 intel_crtc->busy = false;
4663
4664 queue_work(dev_priv->wq, &dev_priv->idle_work);
4665 }
4666
4667 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4668 {
4669 struct drm_device *dev = crtc->dev;
4670 drm_i915_private_t *dev_priv = dev->dev_private;
4671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672 int pipe = intel_crtc->pipe;
4673 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4674 int dpll = I915_READ(dpll_reg);
4675
4676 if (HAS_PCH_SPLIT(dev))
4677 return;
4678
4679 if (!dev_priv->lvds_downclock_avail)
4680 return;
4681
4682 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4683 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4684
4685 /* Unlock panel regs */
4686 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4687 PANEL_UNLOCK_REGS);
4688
4689 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4690 I915_WRITE(dpll_reg, dpll);
4691 dpll = I915_READ(dpll_reg);
4692 intel_wait_for_vblank(dev, pipe);
4693 dpll = I915_READ(dpll_reg);
4694 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4695 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4696
4697 /* ...and lock them again */
4698 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4699 }
4700
4701 /* Schedule downclock */
4702 if (schedule)
4703 mod_timer(&intel_crtc->idle_timer, jiffies +
4704 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4705 }
4706
4707 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4708 {
4709 struct drm_device *dev = crtc->dev;
4710 drm_i915_private_t *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
4713 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4714 int dpll = I915_READ(dpll_reg);
4715
4716 if (HAS_PCH_SPLIT(dev))
4717 return;
4718
4719 if (!dev_priv->lvds_downclock_avail)
4720 return;
4721
4722 /*
4723 * Since this is called by a timer, we should never get here in
4724 * the manual case.
4725 */
4726 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4727 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4728
4729 /* Unlock panel regs */
4730 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4731 PANEL_UNLOCK_REGS);
4732
4733 dpll |= DISPLAY_RATE_SELECT_FPA1;
4734 I915_WRITE(dpll_reg, dpll);
4735 dpll = I915_READ(dpll_reg);
4736 intel_wait_for_vblank(dev, pipe);
4737 dpll = I915_READ(dpll_reg);
4738 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4739 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4740
4741 /* ...and lock them again */
4742 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4743 }
4744
4745 }
4746
4747 /**
4748 * intel_idle_update - adjust clocks for idleness
4749 * @work: work struct
4750 *
4751 * Either the GPU or display (or both) went idle. Check the busy status
4752 * here and adjust the CRTC and GPU clocks as necessary.
4753 */
4754 static void intel_idle_update(struct work_struct *work)
4755 {
4756 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4757 idle_work);
4758 struct drm_device *dev = dev_priv->dev;
4759 struct drm_crtc *crtc;
4760 struct intel_crtc *intel_crtc;
4761 int enabled = 0;
4762
4763 if (!i915_powersave)
4764 return;
4765
4766 mutex_lock(&dev->struct_mutex);
4767
4768 i915_update_gfx_val(dev_priv);
4769
4770 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4771 /* Skip inactive CRTCs */
4772 if (!crtc->fb)
4773 continue;
4774
4775 enabled++;
4776 intel_crtc = to_intel_crtc(crtc);
4777 if (!intel_crtc->busy)
4778 intel_decrease_pllclock(crtc);
4779 }
4780
4781 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4782 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4783 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4784 }
4785
4786 mutex_unlock(&dev->struct_mutex);
4787 }
4788
4789 /**
4790 * intel_mark_busy - mark the GPU and possibly the display busy
4791 * @dev: drm device
4792 * @obj: object we're operating on
4793 *
4794 * Callers can use this function to indicate that the GPU is busy processing
4795 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4796 * buffer), we'll also mark the display as busy, so we know to increase its
4797 * clock frequency.
4798 */
4799 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4800 {
4801 drm_i915_private_t *dev_priv = dev->dev_private;
4802 struct drm_crtc *crtc = NULL;
4803 struct intel_framebuffer *intel_fb;
4804 struct intel_crtc *intel_crtc;
4805
4806 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4807 return;
4808
4809 if (!dev_priv->busy) {
4810 if (IS_I945G(dev) || IS_I945GM(dev)) {
4811 u32 fw_blc_self;
4812
4813 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4814 fw_blc_self = I915_READ(FW_BLC_SELF);
4815 fw_blc_self &= ~FW_BLC_SELF_EN;
4816 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4817 }
4818 dev_priv->busy = true;
4819 } else
4820 mod_timer(&dev_priv->idle_timer, jiffies +
4821 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4822
4823 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4824 if (!crtc->fb)
4825 continue;
4826
4827 intel_crtc = to_intel_crtc(crtc);
4828 intel_fb = to_intel_framebuffer(crtc->fb);
4829 if (intel_fb->obj == obj) {
4830 if (!intel_crtc->busy) {
4831 if (IS_I945G(dev) || IS_I945GM(dev)) {
4832 u32 fw_blc_self;
4833
4834 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4835 fw_blc_self = I915_READ(FW_BLC_SELF);
4836 fw_blc_self &= ~FW_BLC_SELF_EN;
4837 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4838 }
4839 /* Non-busy -> busy, upclock */
4840 intel_increase_pllclock(crtc, true);
4841 intel_crtc->busy = true;
4842 } else {
4843 /* Busy -> busy, put off timer */
4844 mod_timer(&intel_crtc->idle_timer, jiffies +
4845 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4846 }
4847 }
4848 }
4849 }
4850
4851 static void intel_crtc_destroy(struct drm_crtc *crtc)
4852 {
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854
4855 drm_crtc_cleanup(crtc);
4856 kfree(intel_crtc);
4857 }
4858
4859 static void intel_unpin_work_fn(struct work_struct *__work)
4860 {
4861 struct intel_unpin_work *work =
4862 container_of(__work, struct intel_unpin_work, work);
4863
4864 mutex_lock(&work->dev->struct_mutex);
4865 i915_gem_object_unpin(work->old_fb_obj);
4866 drm_gem_object_unreference(work->pending_flip_obj);
4867 drm_gem_object_unreference(work->old_fb_obj);
4868 mutex_unlock(&work->dev->struct_mutex);
4869 kfree(work);
4870 }
4871
4872 static void do_intel_finish_page_flip(struct drm_device *dev,
4873 struct drm_crtc *crtc)
4874 {
4875 drm_i915_private_t *dev_priv = dev->dev_private;
4876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4877 struct intel_unpin_work *work;
4878 struct drm_i915_gem_object *obj_priv;
4879 struct drm_pending_vblank_event *e;
4880 struct timeval now;
4881 unsigned long flags;
4882
4883 /* Ignore early vblank irqs */
4884 if (intel_crtc == NULL)
4885 return;
4886
4887 spin_lock_irqsave(&dev->event_lock, flags);
4888 work = intel_crtc->unpin_work;
4889 if (work == NULL || !work->pending) {
4890 spin_unlock_irqrestore(&dev->event_lock, flags);
4891 return;
4892 }
4893
4894 intel_crtc->unpin_work = NULL;
4895 drm_vblank_put(dev, intel_crtc->pipe);
4896
4897 if (work->event) {
4898 e = work->event;
4899 do_gettimeofday(&now);
4900 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4901 e->event.tv_sec = now.tv_sec;
4902 e->event.tv_usec = now.tv_usec;
4903 list_add_tail(&e->base.link,
4904 &e->base.file_priv->event_list);
4905 wake_up_interruptible(&e->base.file_priv->event_wait);
4906 }
4907
4908 spin_unlock_irqrestore(&dev->event_lock, flags);
4909
4910 obj_priv = to_intel_bo(work->pending_flip_obj);
4911
4912 /* Initial scanout buffer will have a 0 pending flip count */
4913 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4914 atomic_dec_and_test(&obj_priv->pending_flip))
4915 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4916 schedule_work(&work->work);
4917
4918 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4919 }
4920
4921 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4922 {
4923 drm_i915_private_t *dev_priv = dev->dev_private;
4924 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4925
4926 do_intel_finish_page_flip(dev, crtc);
4927 }
4928
4929 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4930 {
4931 drm_i915_private_t *dev_priv = dev->dev_private;
4932 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4933
4934 do_intel_finish_page_flip(dev, crtc);
4935 }
4936
4937 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4938 {
4939 drm_i915_private_t *dev_priv = dev->dev_private;
4940 struct intel_crtc *intel_crtc =
4941 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4942 unsigned long flags;
4943
4944 spin_lock_irqsave(&dev->event_lock, flags);
4945 if (intel_crtc->unpin_work) {
4946 if ((++intel_crtc->unpin_work->pending) > 1)
4947 DRM_ERROR("Prepared flip multiple times\n");
4948 } else {
4949 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4950 }
4951 spin_unlock_irqrestore(&dev->event_lock, flags);
4952 }
4953
4954 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4955 struct drm_framebuffer *fb,
4956 struct drm_pending_vblank_event *event)
4957 {
4958 struct drm_device *dev = crtc->dev;
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 struct intel_framebuffer *intel_fb;
4961 struct drm_i915_gem_object *obj_priv;
4962 struct drm_gem_object *obj;
4963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964 struct intel_unpin_work *work;
4965 unsigned long flags, offset;
4966 int pipe = intel_crtc->pipe;
4967 u32 pf, pipesrc;
4968 int ret;
4969
4970 work = kzalloc(sizeof *work, GFP_KERNEL);
4971 if (work == NULL)
4972 return -ENOMEM;
4973
4974 work->event = event;
4975 work->dev = crtc->dev;
4976 intel_fb = to_intel_framebuffer(crtc->fb);
4977 work->old_fb_obj = intel_fb->obj;
4978 INIT_WORK(&work->work, intel_unpin_work_fn);
4979
4980 /* We borrow the event spin lock for protecting unpin_work */
4981 spin_lock_irqsave(&dev->event_lock, flags);
4982 if (intel_crtc->unpin_work) {
4983 spin_unlock_irqrestore(&dev->event_lock, flags);
4984 kfree(work);
4985
4986 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4987 return -EBUSY;
4988 }
4989 intel_crtc->unpin_work = work;
4990 spin_unlock_irqrestore(&dev->event_lock, flags);
4991
4992 intel_fb = to_intel_framebuffer(fb);
4993 obj = intel_fb->obj;
4994
4995 mutex_lock(&dev->struct_mutex);
4996 ret = intel_pin_and_fence_fb_obj(dev, obj);
4997 if (ret)
4998 goto cleanup_work;
4999
5000 /* Reference the objects for the scheduled work. */
5001 drm_gem_object_reference(work->old_fb_obj);
5002 drm_gem_object_reference(obj);
5003
5004 crtc->fb = fb;
5005 ret = i915_gem_object_flush_write_domain(obj);
5006 if (ret)
5007 goto cleanup_objs;
5008
5009 ret = drm_vblank_get(dev, intel_crtc->pipe);
5010 if (ret)
5011 goto cleanup_objs;
5012
5013 obj_priv = to_intel_bo(obj);
5014 atomic_inc(&obj_priv->pending_flip);
5015 work->pending_flip_obj = obj;
5016
5017 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5018 u32 flip_mask;
5019
5020 if (intel_crtc->plane)
5021 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5022 else
5023 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5024
5025 BEGIN_LP_RING(2);
5026 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5027 OUT_RING(0);
5028 ADVANCE_LP_RING();
5029 }
5030
5031 work->enable_stall_check = true;
5032
5033 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5034 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5035
5036 BEGIN_LP_RING(4);
5037 switch(INTEL_INFO(dev)->gen) {
5038 case 2:
5039 OUT_RING(MI_DISPLAY_FLIP |
5040 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5041 OUT_RING(fb->pitch);
5042 OUT_RING(obj_priv->gtt_offset + offset);
5043 OUT_RING(MI_NOOP);
5044 break;
5045
5046 case 3:
5047 OUT_RING(MI_DISPLAY_FLIP_I915 |
5048 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5049 OUT_RING(fb->pitch);
5050 OUT_RING(obj_priv->gtt_offset + offset);
5051 OUT_RING(MI_NOOP);
5052 break;
5053
5054 case 4:
5055 case 5:
5056 /* i965+ uses the linear or tiled offsets from the
5057 * Display Registers (which do not change across a page-flip)
5058 * so we need only reprogram the base address.
5059 */
5060 OUT_RING(MI_DISPLAY_FLIP |
5061 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5062 OUT_RING(fb->pitch);
5063 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5064
5065 /* XXX Enabling the panel-fitter across page-flip is so far
5066 * untested on non-native modes, so ignore it for now.
5067 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5068 */
5069 pf = 0;
5070 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5071 OUT_RING(pf | pipesrc);
5072 break;
5073
5074 case 6:
5075 OUT_RING(MI_DISPLAY_FLIP |
5076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5077 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5078 OUT_RING(obj_priv->gtt_offset);
5079
5080 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5081 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5082 OUT_RING(pf | pipesrc);
5083 break;
5084 }
5085 ADVANCE_LP_RING();
5086
5087 mutex_unlock(&dev->struct_mutex);
5088
5089 trace_i915_flip_request(intel_crtc->plane, obj);
5090
5091 return 0;
5092
5093 cleanup_objs:
5094 drm_gem_object_unreference(work->old_fb_obj);
5095 drm_gem_object_unreference(obj);
5096 cleanup_work:
5097 mutex_unlock(&dev->struct_mutex);
5098
5099 spin_lock_irqsave(&dev->event_lock, flags);
5100 intel_crtc->unpin_work = NULL;
5101 spin_unlock_irqrestore(&dev->event_lock, flags);
5102
5103 kfree(work);
5104
5105 return ret;
5106 }
5107
5108 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5109 .dpms = intel_crtc_dpms,
5110 .mode_fixup = intel_crtc_mode_fixup,
5111 .mode_set = intel_crtc_mode_set,
5112 .mode_set_base = intel_pipe_set_base,
5113 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5114 .prepare = intel_crtc_prepare,
5115 .commit = intel_crtc_commit,
5116 .load_lut = intel_crtc_load_lut,
5117 };
5118
5119 static const struct drm_crtc_funcs intel_crtc_funcs = {
5120 .cursor_set = intel_crtc_cursor_set,
5121 .cursor_move = intel_crtc_cursor_move,
5122 .gamma_set = intel_crtc_gamma_set,
5123 .set_config = drm_crtc_helper_set_config,
5124 .destroy = intel_crtc_destroy,
5125 .page_flip = intel_crtc_page_flip,
5126 };
5127
5128
5129 static void intel_crtc_init(struct drm_device *dev, int pipe)
5130 {
5131 drm_i915_private_t *dev_priv = dev->dev_private;
5132 struct intel_crtc *intel_crtc;
5133 int i;
5134
5135 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5136 if (intel_crtc == NULL)
5137 return;
5138
5139 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5140
5141 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5142 intel_crtc->pipe = pipe;
5143 intel_crtc->plane = pipe;
5144 for (i = 0; i < 256; i++) {
5145 intel_crtc->lut_r[i] = i;
5146 intel_crtc->lut_g[i] = i;
5147 intel_crtc->lut_b[i] = i;
5148 }
5149
5150 /* Swap pipes & planes for FBC on pre-965 */
5151 intel_crtc->pipe = pipe;
5152 intel_crtc->plane = pipe;
5153 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5154 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5155 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5156 }
5157
5158 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5159 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5160 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5161 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5162
5163 intel_crtc->cursor_addr = 0;
5164 intel_crtc->dpms_mode = -1;
5165 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5166
5167 intel_crtc->busy = false;
5168
5169 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5170 (unsigned long)intel_crtc);
5171 }
5172
5173 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5174 struct drm_file *file_priv)
5175 {
5176 drm_i915_private_t *dev_priv = dev->dev_private;
5177 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5178 struct drm_mode_object *drmmode_obj;
5179 struct intel_crtc *crtc;
5180
5181 if (!dev_priv) {
5182 DRM_ERROR("called with no initialization\n");
5183 return -EINVAL;
5184 }
5185
5186 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5187 DRM_MODE_OBJECT_CRTC);
5188
5189 if (!drmmode_obj) {
5190 DRM_ERROR("no such CRTC id\n");
5191 return -EINVAL;
5192 }
5193
5194 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5195 pipe_from_crtc_id->pipe = crtc->pipe;
5196
5197 return 0;
5198 }
5199
5200 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5201 {
5202 struct drm_crtc *crtc = NULL;
5203
5204 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 if (intel_crtc->pipe == pipe)
5207 break;
5208 }
5209 return crtc;
5210 }
5211
5212 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5213 {
5214 int index_mask = 0;
5215 struct drm_encoder *encoder;
5216 int entry = 0;
5217
5218 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5219 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5220 if (type_mask & intel_encoder->clone_mask)
5221 index_mask |= (1 << entry);
5222 entry++;
5223 }
5224 return index_mask;
5225 }
5226
5227
5228 static void intel_setup_outputs(struct drm_device *dev)
5229 {
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 struct drm_encoder *encoder;
5232 bool dpd_is_edp = false;
5233
5234 if (IS_MOBILE(dev) && !IS_I830(dev))
5235 intel_lvds_init(dev);
5236
5237 if (HAS_PCH_SPLIT(dev)) {
5238 dpd_is_edp = intel_dpd_is_edp(dev);
5239
5240 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5241 intel_dp_init(dev, DP_A);
5242
5243 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5244 intel_dp_init(dev, PCH_DP_D);
5245 }
5246
5247 intel_crt_init(dev);
5248
5249 if (HAS_PCH_SPLIT(dev)) {
5250 int found;
5251
5252 if (I915_READ(HDMIB) & PORT_DETECTED) {
5253 /* PCH SDVOB multiplex with HDMIB */
5254 found = intel_sdvo_init(dev, PCH_SDVOB);
5255 if (!found)
5256 intel_hdmi_init(dev, HDMIB);
5257 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5258 intel_dp_init(dev, PCH_DP_B);
5259 }
5260
5261 if (I915_READ(HDMIC) & PORT_DETECTED)
5262 intel_hdmi_init(dev, HDMIC);
5263
5264 if (I915_READ(HDMID) & PORT_DETECTED)
5265 intel_hdmi_init(dev, HDMID);
5266
5267 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5268 intel_dp_init(dev, PCH_DP_C);
5269
5270 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5271 intel_dp_init(dev, PCH_DP_D);
5272
5273 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5274 bool found = false;
5275
5276 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5277 DRM_DEBUG_KMS("probing SDVOB\n");
5278 found = intel_sdvo_init(dev, SDVOB);
5279 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5280 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5281 intel_hdmi_init(dev, SDVOB);
5282 }
5283
5284 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5285 DRM_DEBUG_KMS("probing DP_B\n");
5286 intel_dp_init(dev, DP_B);
5287 }
5288 }
5289
5290 /* Before G4X SDVOC doesn't have its own detect register */
5291
5292 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5293 DRM_DEBUG_KMS("probing SDVOC\n");
5294 found = intel_sdvo_init(dev, SDVOC);
5295 }
5296
5297 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5298
5299 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5300 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5301 intel_hdmi_init(dev, SDVOC);
5302 }
5303 if (SUPPORTS_INTEGRATED_DP(dev)) {
5304 DRM_DEBUG_KMS("probing DP_C\n");
5305 intel_dp_init(dev, DP_C);
5306 }
5307 }
5308
5309 if (SUPPORTS_INTEGRATED_DP(dev) &&
5310 (I915_READ(DP_D) & DP_DETECTED)) {
5311 DRM_DEBUG_KMS("probing DP_D\n");
5312 intel_dp_init(dev, DP_D);
5313 }
5314 } else if (IS_GEN2(dev))
5315 intel_dvo_init(dev);
5316
5317 if (SUPPORTS_TV(dev))
5318 intel_tv_init(dev);
5319
5320 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5321 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5322
5323 encoder->possible_crtcs = intel_encoder->crtc_mask;
5324 encoder->possible_clones = intel_encoder_clones(dev,
5325 intel_encoder->clone_mask);
5326 }
5327 }
5328
5329 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5330 {
5331 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5332
5333 drm_framebuffer_cleanup(fb);
5334 drm_gem_object_unreference_unlocked(intel_fb->obj);
5335
5336 kfree(intel_fb);
5337 }
5338
5339 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5340 struct drm_file *file_priv,
5341 unsigned int *handle)
5342 {
5343 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5344 struct drm_gem_object *object = intel_fb->obj;
5345
5346 return drm_gem_handle_create(file_priv, object, handle);
5347 }
5348
5349 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5350 .destroy = intel_user_framebuffer_destroy,
5351 .create_handle = intel_user_framebuffer_create_handle,
5352 };
5353
5354 int intel_framebuffer_init(struct drm_device *dev,
5355 struct intel_framebuffer *intel_fb,
5356 struct drm_mode_fb_cmd *mode_cmd,
5357 struct drm_gem_object *obj)
5358 {
5359 int ret;
5360
5361 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5362 if (ret) {
5363 DRM_ERROR("framebuffer init failed %d\n", ret);
5364 return ret;
5365 }
5366
5367 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5368 intel_fb->obj = obj;
5369 return 0;
5370 }
5371
5372 static struct drm_framebuffer *
5373 intel_user_framebuffer_create(struct drm_device *dev,
5374 struct drm_file *filp,
5375 struct drm_mode_fb_cmd *mode_cmd)
5376 {
5377 struct drm_gem_object *obj;
5378 struct intel_framebuffer *intel_fb;
5379 int ret;
5380
5381 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5382 if (!obj)
5383 return ERR_PTR(-ENOENT);
5384
5385 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5386 if (!intel_fb)
5387 return ERR_PTR(-ENOMEM);
5388
5389 ret = intel_framebuffer_init(dev, intel_fb,
5390 mode_cmd, obj);
5391 if (ret) {
5392 drm_gem_object_unreference_unlocked(obj);
5393 kfree(intel_fb);
5394 return ERR_PTR(ret);
5395 }
5396
5397 return &intel_fb->base;
5398 }
5399
5400 static const struct drm_mode_config_funcs intel_mode_funcs = {
5401 .fb_create = intel_user_framebuffer_create,
5402 .output_poll_changed = intel_fb_output_poll_changed,
5403 };
5404
5405 static struct drm_gem_object *
5406 intel_alloc_context_page(struct drm_device *dev)
5407 {
5408 struct drm_gem_object *ctx;
5409 int ret;
5410
5411 ctx = i915_gem_alloc_object(dev, 4096);
5412 if (!ctx) {
5413 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5414 return NULL;
5415 }
5416
5417 mutex_lock(&dev->struct_mutex);
5418 ret = i915_gem_object_pin(ctx, 4096);
5419 if (ret) {
5420 DRM_ERROR("failed to pin power context: %d\n", ret);
5421 goto err_unref;
5422 }
5423
5424 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5425 if (ret) {
5426 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5427 goto err_unpin;
5428 }
5429 mutex_unlock(&dev->struct_mutex);
5430
5431 return ctx;
5432
5433 err_unpin:
5434 i915_gem_object_unpin(ctx);
5435 err_unref:
5436 drm_gem_object_unreference(ctx);
5437 mutex_unlock(&dev->struct_mutex);
5438 return NULL;
5439 }
5440
5441 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5442 {
5443 struct drm_i915_private *dev_priv = dev->dev_private;
5444 u16 rgvswctl;
5445
5446 rgvswctl = I915_READ16(MEMSWCTL);
5447 if (rgvswctl & MEMCTL_CMD_STS) {
5448 DRM_DEBUG("gpu busy, RCS change rejected\n");
5449 return false; /* still busy with another command */
5450 }
5451
5452 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5453 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5454 I915_WRITE16(MEMSWCTL, rgvswctl);
5455 POSTING_READ16(MEMSWCTL);
5456
5457 rgvswctl |= MEMCTL_CMD_STS;
5458 I915_WRITE16(MEMSWCTL, rgvswctl);
5459
5460 return true;
5461 }
5462
5463 void ironlake_enable_drps(struct drm_device *dev)
5464 {
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 u32 rgvmodectl = I915_READ(MEMMODECTL);
5467 u8 fmax, fmin, fstart, vstart;
5468
5469 /* 100ms RC evaluation intervals */
5470 I915_WRITE(RCUPEI, 100000);
5471 I915_WRITE(RCDNEI, 100000);
5472
5473 /* Set max/min thresholds to 90ms and 80ms respectively */
5474 I915_WRITE(RCBMAXAVG, 90000);
5475 I915_WRITE(RCBMINAVG, 80000);
5476
5477 I915_WRITE(MEMIHYST, 1);
5478
5479 /* Set up min, max, and cur for interrupt handling */
5480 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5481 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5482 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5483 MEMMODE_FSTART_SHIFT;
5484 fstart = fmax;
5485
5486 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5487 PXVFREQ_PX_SHIFT;
5488
5489 dev_priv->fmax = fstart; /* IPS callback will increase this */
5490 dev_priv->fstart = fstart;
5491
5492 dev_priv->max_delay = fmax;
5493 dev_priv->min_delay = fmin;
5494 dev_priv->cur_delay = fstart;
5495
5496 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5497 fstart);
5498
5499 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5500
5501 /*
5502 * Interrupts will be enabled in ironlake_irq_postinstall
5503 */
5504
5505 I915_WRITE(VIDSTART, vstart);
5506 POSTING_READ(VIDSTART);
5507
5508 rgvmodectl |= MEMMODE_SWMODE_EN;
5509 I915_WRITE(MEMMODECTL, rgvmodectl);
5510
5511 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5512 DRM_ERROR("stuck trying to change perf mode\n");
5513 msleep(1);
5514
5515 ironlake_set_drps(dev, fstart);
5516
5517 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5518 I915_READ(0x112e0);
5519 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5520 dev_priv->last_count2 = I915_READ(0x112f4);
5521 getrawmonotonic(&dev_priv->last_time2);
5522 }
5523
5524 void ironlake_disable_drps(struct drm_device *dev)
5525 {
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 u16 rgvswctl = I915_READ16(MEMSWCTL);
5528
5529 /* Ack interrupts, disable EFC interrupt */
5530 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5531 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5532 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5533 I915_WRITE(DEIIR, DE_PCU_EVENT);
5534 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5535
5536 /* Go back to the starting frequency */
5537 ironlake_set_drps(dev, dev_priv->fstart);
5538 msleep(1);
5539 rgvswctl |= MEMCTL_CMD_STS;
5540 I915_WRITE(MEMSWCTL, rgvswctl);
5541 msleep(1);
5542
5543 }
5544
5545 static unsigned long intel_pxfreq(u32 vidfreq)
5546 {
5547 unsigned long freq;
5548 int div = (vidfreq & 0x3f0000) >> 16;
5549 int post = (vidfreq & 0x3000) >> 12;
5550 int pre = (vidfreq & 0x7);
5551
5552 if (!pre)
5553 return 0;
5554
5555 freq = ((div * 133333) / ((1<<post) * pre));
5556
5557 return freq;
5558 }
5559
5560 void intel_init_emon(struct drm_device *dev)
5561 {
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 u32 lcfuse;
5564 u8 pxw[16];
5565 int i;
5566
5567 /* Disable to program */
5568 I915_WRITE(ECR, 0);
5569 POSTING_READ(ECR);
5570
5571 /* Program energy weights for various events */
5572 I915_WRITE(SDEW, 0x15040d00);
5573 I915_WRITE(CSIEW0, 0x007f0000);
5574 I915_WRITE(CSIEW1, 0x1e220004);
5575 I915_WRITE(CSIEW2, 0x04000004);
5576
5577 for (i = 0; i < 5; i++)
5578 I915_WRITE(PEW + (i * 4), 0);
5579 for (i = 0; i < 3; i++)
5580 I915_WRITE(DEW + (i * 4), 0);
5581
5582 /* Program P-state weights to account for frequency power adjustment */
5583 for (i = 0; i < 16; i++) {
5584 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5585 unsigned long freq = intel_pxfreq(pxvidfreq);
5586 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5587 PXVFREQ_PX_SHIFT;
5588 unsigned long val;
5589
5590 val = vid * vid;
5591 val *= (freq / 1000);
5592 val *= 255;
5593 val /= (127*127*900);
5594 if (val > 0xff)
5595 DRM_ERROR("bad pxval: %ld\n", val);
5596 pxw[i] = val;
5597 }
5598 /* Render standby states get 0 weight */
5599 pxw[14] = 0;
5600 pxw[15] = 0;
5601
5602 for (i = 0; i < 4; i++) {
5603 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5604 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5605 I915_WRITE(PXW + (i * 4), val);
5606 }
5607
5608 /* Adjust magic regs to magic values (more experimental results) */
5609 I915_WRITE(OGW0, 0);
5610 I915_WRITE(OGW1, 0);
5611 I915_WRITE(EG0, 0x00007f00);
5612 I915_WRITE(EG1, 0x0000000e);
5613 I915_WRITE(EG2, 0x000e0000);
5614 I915_WRITE(EG3, 0x68000300);
5615 I915_WRITE(EG4, 0x42000000);
5616 I915_WRITE(EG5, 0x00140031);
5617 I915_WRITE(EG6, 0);
5618 I915_WRITE(EG7, 0);
5619
5620 for (i = 0; i < 8; i++)
5621 I915_WRITE(PXWL + (i * 4), 0);
5622
5623 /* Enable PMON + select events */
5624 I915_WRITE(ECR, 0x80000019);
5625
5626 lcfuse = I915_READ(LCFUSE02);
5627
5628 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5629 }
5630
5631 void intel_init_clock_gating(struct drm_device *dev)
5632 {
5633 struct drm_i915_private *dev_priv = dev->dev_private;
5634
5635 /*
5636 * Disable clock gating reported to work incorrectly according to the
5637 * specs, but enable as much else as we can.
5638 */
5639 if (HAS_PCH_SPLIT(dev)) {
5640 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5641
5642 if (IS_IRONLAKE(dev)) {
5643 /* Required for FBC */
5644 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5645 /* Required for CxSR */
5646 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5647
5648 I915_WRITE(PCH_3DCGDIS0,
5649 MARIUNIT_CLOCK_GATE_DISABLE |
5650 SVSMUNIT_CLOCK_GATE_DISABLE);
5651 }
5652
5653 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5654
5655 /*
5656 * According to the spec the following bits should be set in
5657 * order to enable memory self-refresh
5658 * The bit 22/21 of 0x42004
5659 * The bit 5 of 0x42020
5660 * The bit 15 of 0x45000
5661 */
5662 if (IS_IRONLAKE(dev)) {
5663 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5664 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5665 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5666 I915_WRITE(ILK_DSPCLK_GATE,
5667 (I915_READ(ILK_DSPCLK_GATE) |
5668 ILK_DPARB_CLK_GATE));
5669 I915_WRITE(DISP_ARB_CTL,
5670 (I915_READ(DISP_ARB_CTL) |
5671 DISP_FBC_WM_DIS));
5672 }
5673 /*
5674 * Based on the document from hardware guys the following bits
5675 * should be set unconditionally in order to enable FBC.
5676 * The bit 22 of 0x42000
5677 * The bit 22 of 0x42004
5678 * The bit 7,8,9 of 0x42020.
5679 */
5680 if (IS_IRONLAKE_M(dev)) {
5681 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5682 I915_READ(ILK_DISPLAY_CHICKEN1) |
5683 ILK_FBCQ_DIS);
5684 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5685 I915_READ(ILK_DISPLAY_CHICKEN2) |
5686 ILK_DPARB_GATE);
5687 I915_WRITE(ILK_DSPCLK_GATE,
5688 I915_READ(ILK_DSPCLK_GATE) |
5689 ILK_DPFC_DIS1 |
5690 ILK_DPFC_DIS2 |
5691 ILK_CLK_FBC);
5692 }
5693 return;
5694 } else if (IS_G4X(dev)) {
5695 uint32_t dspclk_gate;
5696 I915_WRITE(RENCLK_GATE_D1, 0);
5697 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5698 GS_UNIT_CLOCK_GATE_DISABLE |
5699 CL_UNIT_CLOCK_GATE_DISABLE);
5700 I915_WRITE(RAMCLK_GATE_D, 0);
5701 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5702 OVRUNIT_CLOCK_GATE_DISABLE |
5703 OVCUNIT_CLOCK_GATE_DISABLE;
5704 if (IS_GM45(dev))
5705 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5706 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5707 } else if (IS_I965GM(dev)) {
5708 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5709 I915_WRITE(RENCLK_GATE_D2, 0);
5710 I915_WRITE(DSPCLK_GATE_D, 0);
5711 I915_WRITE(RAMCLK_GATE_D, 0);
5712 I915_WRITE16(DEUC, 0);
5713 } else if (IS_I965G(dev)) {
5714 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5715 I965_RCC_CLOCK_GATE_DISABLE |
5716 I965_RCPB_CLOCK_GATE_DISABLE |
5717 I965_ISC_CLOCK_GATE_DISABLE |
5718 I965_FBC_CLOCK_GATE_DISABLE);
5719 I915_WRITE(RENCLK_GATE_D2, 0);
5720 } else if (IS_I9XX(dev)) {
5721 u32 dstate = I915_READ(D_STATE);
5722
5723 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5724 DSTATE_DOT_CLOCK_GATING;
5725 I915_WRITE(D_STATE, dstate);
5726 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5727 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5728 } else if (IS_I830(dev)) {
5729 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5730 }
5731
5732 /*
5733 * GPU can automatically power down the render unit if given a page
5734 * to save state.
5735 */
5736 if (IS_IRONLAKE_M(dev)) {
5737 if (dev_priv->renderctx == NULL)
5738 dev_priv->renderctx = intel_alloc_context_page(dev);
5739 if (dev_priv->renderctx) {
5740 struct drm_i915_gem_object *obj_priv;
5741 obj_priv = to_intel_bo(dev_priv->renderctx);
5742 if (obj_priv) {
5743 BEGIN_LP_RING(4);
5744 OUT_RING(MI_SET_CONTEXT);
5745 OUT_RING(obj_priv->gtt_offset |
5746 MI_MM_SPACE_GTT |
5747 MI_SAVE_EXT_STATE_EN |
5748 MI_RESTORE_EXT_STATE_EN |
5749 MI_RESTORE_INHIBIT);
5750 OUT_RING(MI_NOOP);
5751 OUT_RING(MI_FLUSH);
5752 ADVANCE_LP_RING();
5753 }
5754 } else
5755 DRM_DEBUG_KMS("Failed to allocate render context."
5756 "Disable RC6\n");
5757 }
5758
5759 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5760 struct drm_i915_gem_object *obj_priv = NULL;
5761
5762 if (dev_priv->pwrctx) {
5763 obj_priv = to_intel_bo(dev_priv->pwrctx);
5764 } else {
5765 struct drm_gem_object *pwrctx;
5766
5767 pwrctx = intel_alloc_context_page(dev);
5768 if (pwrctx) {
5769 dev_priv->pwrctx = pwrctx;
5770 obj_priv = to_intel_bo(pwrctx);
5771 }
5772 }
5773
5774 if (obj_priv) {
5775 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5776 I915_WRITE(MCHBAR_RENDER_STANDBY,
5777 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5778 }
5779 }
5780 }
5781
5782 /* Set up chip specific display functions */
5783 static void intel_init_display(struct drm_device *dev)
5784 {
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786
5787 /* We always want a DPMS function */
5788 if (HAS_PCH_SPLIT(dev))
5789 dev_priv->display.dpms = ironlake_crtc_dpms;
5790 else
5791 dev_priv->display.dpms = i9xx_crtc_dpms;
5792
5793 if (I915_HAS_FBC(dev)) {
5794 if (IS_IRONLAKE_M(dev)) {
5795 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5796 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5797 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5798 } else if (IS_GM45(dev)) {
5799 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5800 dev_priv->display.enable_fbc = g4x_enable_fbc;
5801 dev_priv->display.disable_fbc = g4x_disable_fbc;
5802 } else if (IS_I965GM(dev)) {
5803 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5804 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5805 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5806 }
5807 /* 855GM needs testing */
5808 }
5809
5810 /* Returns the core display clock speed */
5811 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5812 dev_priv->display.get_display_clock_speed =
5813 i945_get_display_clock_speed;
5814 else if (IS_I915G(dev))
5815 dev_priv->display.get_display_clock_speed =
5816 i915_get_display_clock_speed;
5817 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5818 dev_priv->display.get_display_clock_speed =
5819 i9xx_misc_get_display_clock_speed;
5820 else if (IS_I915GM(dev))
5821 dev_priv->display.get_display_clock_speed =
5822 i915gm_get_display_clock_speed;
5823 else if (IS_I865G(dev))
5824 dev_priv->display.get_display_clock_speed =
5825 i865_get_display_clock_speed;
5826 else if (IS_I85X(dev))
5827 dev_priv->display.get_display_clock_speed =
5828 i855_get_display_clock_speed;
5829 else /* 852, 830 */
5830 dev_priv->display.get_display_clock_speed =
5831 i830_get_display_clock_speed;
5832
5833 /* For FIFO watermark updates */
5834 if (HAS_PCH_SPLIT(dev)) {
5835 if (IS_IRONLAKE(dev)) {
5836 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5837 dev_priv->display.update_wm = ironlake_update_wm;
5838 else {
5839 DRM_DEBUG_KMS("Failed to get proper latency. "
5840 "Disable CxSR\n");
5841 dev_priv->display.update_wm = NULL;
5842 }
5843 } else
5844 dev_priv->display.update_wm = NULL;
5845 } else if (IS_PINEVIEW(dev)) {
5846 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5847 dev_priv->is_ddr3,
5848 dev_priv->fsb_freq,
5849 dev_priv->mem_freq)) {
5850 DRM_INFO("failed to find known CxSR latency "
5851 "(found ddr%s fsb freq %d, mem freq %d), "
5852 "disabling CxSR\n",
5853 (dev_priv->is_ddr3 == 1) ? "3": "2",
5854 dev_priv->fsb_freq, dev_priv->mem_freq);
5855 /* Disable CxSR and never update its watermark again */
5856 pineview_disable_cxsr(dev);
5857 dev_priv->display.update_wm = NULL;
5858 } else
5859 dev_priv->display.update_wm = pineview_update_wm;
5860 } else if (IS_G4X(dev))
5861 dev_priv->display.update_wm = g4x_update_wm;
5862 else if (IS_I965G(dev))
5863 dev_priv->display.update_wm = i965_update_wm;
5864 else if (IS_I9XX(dev)) {
5865 dev_priv->display.update_wm = i9xx_update_wm;
5866 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5867 } else if (IS_I85X(dev)) {
5868 dev_priv->display.update_wm = i9xx_update_wm;
5869 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5870 } else {
5871 dev_priv->display.update_wm = i830_update_wm;
5872 if (IS_845G(dev))
5873 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5874 else
5875 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5876 }
5877 }
5878
5879 /*
5880 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5881 * resume, or other times. This quirk makes sure that's the case for
5882 * affected systems.
5883 */
5884 static void quirk_pipea_force (struct drm_device *dev)
5885 {
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887
5888 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5889 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5890 }
5891
5892 struct intel_quirk {
5893 int device;
5894 int subsystem_vendor;
5895 int subsystem_device;
5896 void (*hook)(struct drm_device *dev);
5897 };
5898
5899 struct intel_quirk intel_quirks[] = {
5900 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5901 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5902 /* HP Mini needs pipe A force quirk (LP: #322104) */
5903 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5904
5905 /* Thinkpad R31 needs pipe A force quirk */
5906 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5907 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5908 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5909
5910 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5911 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5912 /* ThinkPad X40 needs pipe A force quirk */
5913
5914 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5915 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5916
5917 /* 855 & before need to leave pipe A & dpll A up */
5918 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5919 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5920 };
5921
5922 static void intel_init_quirks(struct drm_device *dev)
5923 {
5924 struct pci_dev *d = dev->pdev;
5925 int i;
5926
5927 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5928 struct intel_quirk *q = &intel_quirks[i];
5929
5930 if (d->device == q->device &&
5931 (d->subsystem_vendor == q->subsystem_vendor ||
5932 q->subsystem_vendor == PCI_ANY_ID) &&
5933 (d->subsystem_device == q->subsystem_device ||
5934 q->subsystem_device == PCI_ANY_ID))
5935 q->hook(dev);
5936 }
5937 }
5938
5939 /* Disable the VGA plane that we never use */
5940 static void i915_disable_vga(struct drm_device *dev)
5941 {
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 u8 sr1;
5944 u32 vga_reg;
5945
5946 if (HAS_PCH_SPLIT(dev))
5947 vga_reg = CPU_VGACNTRL;
5948 else
5949 vga_reg = VGACNTRL;
5950
5951 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5952 outb(1, VGA_SR_INDEX);
5953 sr1 = inb(VGA_SR_DATA);
5954 outb(sr1 | 1<<5, VGA_SR_DATA);
5955 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5956 udelay(300);
5957
5958 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5959 POSTING_READ(vga_reg);
5960 }
5961
5962 void intel_modeset_init(struct drm_device *dev)
5963 {
5964 struct drm_i915_private *dev_priv = dev->dev_private;
5965 int i;
5966
5967 drm_mode_config_init(dev);
5968
5969 dev->mode_config.min_width = 0;
5970 dev->mode_config.min_height = 0;
5971
5972 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5973
5974 intel_init_quirks(dev);
5975
5976 intel_init_display(dev);
5977
5978 if (IS_I965G(dev)) {
5979 dev->mode_config.max_width = 8192;
5980 dev->mode_config.max_height = 8192;
5981 } else if (IS_I9XX(dev)) {
5982 dev->mode_config.max_width = 4096;
5983 dev->mode_config.max_height = 4096;
5984 } else {
5985 dev->mode_config.max_width = 2048;
5986 dev->mode_config.max_height = 2048;
5987 }
5988
5989 /* set memory base */
5990 if (IS_I9XX(dev))
5991 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5992 else
5993 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5994
5995 if (IS_MOBILE(dev) || IS_I9XX(dev))
5996 dev_priv->num_pipe = 2;
5997 else
5998 dev_priv->num_pipe = 1;
5999 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6000 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6001
6002 for (i = 0; i < dev_priv->num_pipe; i++) {
6003 intel_crtc_init(dev, i);
6004 }
6005
6006 intel_setup_outputs(dev);
6007
6008 intel_init_clock_gating(dev);
6009
6010 /* Just disable it once at startup */
6011 i915_disable_vga(dev);
6012
6013 if (IS_IRONLAKE_M(dev)) {
6014 ironlake_enable_drps(dev);
6015 intel_init_emon(dev);
6016 }
6017
6018 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6019 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6020 (unsigned long)dev);
6021
6022 intel_setup_overlay(dev);
6023 }
6024
6025 void intel_modeset_cleanup(struct drm_device *dev)
6026 {
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 struct drm_crtc *crtc;
6029 struct intel_crtc *intel_crtc;
6030
6031 mutex_lock(&dev->struct_mutex);
6032
6033 drm_kms_helper_poll_fini(dev);
6034 intel_fbdev_fini(dev);
6035
6036 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6037 /* Skip inactive CRTCs */
6038 if (!crtc->fb)
6039 continue;
6040
6041 intel_crtc = to_intel_crtc(crtc);
6042 intel_increase_pllclock(crtc, false);
6043 del_timer_sync(&intel_crtc->idle_timer);
6044 }
6045
6046 del_timer_sync(&dev_priv->idle_timer);
6047
6048 if (dev_priv->display.disable_fbc)
6049 dev_priv->display.disable_fbc(dev);
6050
6051 if (dev_priv->renderctx) {
6052 struct drm_i915_gem_object *obj_priv;
6053
6054 obj_priv = to_intel_bo(dev_priv->renderctx);
6055 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6056 I915_READ(CCID);
6057 i915_gem_object_unpin(dev_priv->renderctx);
6058 drm_gem_object_unreference(dev_priv->renderctx);
6059 }
6060
6061 if (dev_priv->pwrctx) {
6062 struct drm_i915_gem_object *obj_priv;
6063
6064 obj_priv = to_intel_bo(dev_priv->pwrctx);
6065 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6066 I915_READ(PWRCTXA);
6067 i915_gem_object_unpin(dev_priv->pwrctx);
6068 drm_gem_object_unreference(dev_priv->pwrctx);
6069 }
6070
6071 if (IS_IRONLAKE_M(dev))
6072 ironlake_disable_drps(dev);
6073
6074 mutex_unlock(&dev->struct_mutex);
6075
6076 drm_mode_config_cleanup(dev);
6077 }
6078
6079
6080 /*
6081 * Return which encoder is currently attached for connector.
6082 */
6083 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6084 {
6085 struct drm_mode_object *obj;
6086 struct drm_encoder *encoder;
6087 int i;
6088
6089 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6090 if (connector->encoder_ids[i] == 0)
6091 break;
6092
6093 obj = drm_mode_object_find(connector->dev,
6094 connector->encoder_ids[i],
6095 DRM_MODE_OBJECT_ENCODER);
6096 if (!obj)
6097 continue;
6098
6099 encoder = obj_to_encoder(obj);
6100 return encoder;
6101 }
6102 return NULL;
6103 }
6104
6105 /*
6106 * set vga decode state - true == enable VGA decode
6107 */
6108 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6109 {
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 u16 gmch_ctrl;
6112
6113 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6114 if (state)
6115 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6116 else
6117 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6118 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6119 return 0;
6120 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree