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x86: nmi_watchdog - use NMI_NONE by default
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / io_apic_64.c
blob2b4c40bc12c9199c242f299dcb070ad06e7698de
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 int first_system_vector = 0xfe;
86
87 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
88
89 #define __apicdebuginit __init
90
91 int sis_apic_bug; /* not actually supported, dummy for compile */
92
93 static int no_timer_check;
94
95 static int disable_timer_pin_1 __initdata;
96
97 int timer_through_8259 __initdata;
98
99 /* Where if anywhere is the i8259 connect in external int mode */
100 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
101
102 static DEFINE_SPINLOCK(ioapic_lock);
103 DEFINE_SPINLOCK(vector_lock);
104
105 /*
106 * # of IRQ routing registers
107 */
108 int nr_ioapic_registers[MAX_IO_APICS];
109
110 /* I/O APIC entries */
111 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
112 int nr_ioapics;
113
114 /* MP IRQ source entries */
115 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
116
117 /* # of MP IRQ source entries */
118 int mp_irq_entries;
119
120 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
121
122 /*
123 * Rough estimation of how many shared IRQs there are, can
124 * be changed anytime.
125 */
126 #define MAX_PLUS_SHARED_IRQS NR_IRQS
127 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
128
129 /*
130 * This is performance-critical, we want to do it O(1)
131 *
132 * the indexing order of this array favors 1:1 mappings
133 * between pins and IRQs.
134 */
135
136 static struct irq_pin_list {
137 short apic, pin, next;
138 } irq_2_pin[PIN_MAP_SIZE];
139
140 struct io_apic {
141 unsigned int index;
142 unsigned int unused[3];
143 unsigned int data;
144 };
145
146 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
147 {
148 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
149 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
150 }
151
152 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
153 {
154 struct io_apic __iomem *io_apic = io_apic_base(apic);
155 writel(reg, &io_apic->index);
156 return readl(&io_apic->data);
157 }
158
159 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
160 {
161 struct io_apic __iomem *io_apic = io_apic_base(apic);
162 writel(reg, &io_apic->index);
163 writel(value, &io_apic->data);
164 }
165
166 /*
167 * Re-write a value: to be used for read-modify-write
168 * cycles where the read already set up the index register.
169 */
170 static inline void io_apic_modify(unsigned int apic, unsigned int value)
171 {
172 struct io_apic __iomem *io_apic = io_apic_base(apic);
173 writel(value, &io_apic->data);
174 }
175
176 static bool io_apic_level_ack_pending(unsigned int irq)
177 {
178 struct irq_pin_list *entry;
179 unsigned long flags;
180
181 spin_lock_irqsave(&ioapic_lock, flags);
182 entry = irq_2_pin + irq;
183 for (;;) {
184 unsigned int reg;
185 int pin;
186
187 pin = entry->pin;
188 if (pin == -1)
189 break;
190 reg = io_apic_read(entry->apic, 0x10 + pin*2);
191 /* Is the remote IRR bit set? */
192 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
193 spin_unlock_irqrestore(&ioapic_lock, flags);
194 return true;
195 }
196 if (!entry->next)
197 break;
198 entry = irq_2_pin + entry->next;
199 }
200 spin_unlock_irqrestore(&ioapic_lock, flags);
201
202 return false;
203 }
204
205 /*
206 * Synchronize the IO-APIC and the CPU by doing
207 * a dummy read from the IO-APIC
208 */
209 static inline void io_apic_sync(unsigned int apic)
210 {
211 struct io_apic __iomem *io_apic = io_apic_base(apic);
212 readl(&io_apic->data);
213 }
214
215 #define __DO_ACTION(R, ACTION, FINAL) \
216 \
217 { \
218 int pin; \
219 struct irq_pin_list *entry = irq_2_pin + irq; \
220 \
221 BUG_ON(irq >= NR_IRQS); \
222 for (;;) { \
223 unsigned int reg; \
224 pin = entry->pin; \
225 if (pin == -1) \
226 break; \
227 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
228 reg ACTION; \
229 io_apic_modify(entry->apic, reg); \
230 FINAL; \
231 if (!entry->next) \
232 break; \
233 entry = irq_2_pin + entry->next; \
234 } \
235 }
236
237 union entry_union {
238 struct { u32 w1, w2; };
239 struct IO_APIC_route_entry entry;
240 };
241
242 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
243 {
244 union entry_union eu;
245 unsigned long flags;
246 spin_lock_irqsave(&ioapic_lock, flags);
247 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
248 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
249 spin_unlock_irqrestore(&ioapic_lock, flags);
250 return eu.entry;
251 }
252
253 /*
254 * When we write a new IO APIC routing entry, we need to write the high
255 * word first! If the mask bit in the low word is clear, we will enable
256 * the interrupt, and we need to make sure the entry is fully populated
257 * before that happens.
258 */
259 static void
260 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
261 {
262 union entry_union eu;
263 eu.entry = e;
264 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
265 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
266 }
267
268 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
269 {
270 unsigned long flags;
271 spin_lock_irqsave(&ioapic_lock, flags);
272 __ioapic_write_entry(apic, pin, e);
273 spin_unlock_irqrestore(&ioapic_lock, flags);
274 }
275
276 /*
277 * When we mask an IO APIC routing entry, we need to write the low
278 * word first, in order to set the mask bit before we change the
279 * high bits!
280 */
281 static void ioapic_mask_entry(int apic, int pin)
282 {
283 unsigned long flags;
284 union entry_union eu = { .entry.mask = 1 };
285
286 spin_lock_irqsave(&ioapic_lock, flags);
287 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
288 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
289 spin_unlock_irqrestore(&ioapic_lock, flags);
290 }
291
292 #ifdef CONFIG_SMP
293 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
294 {
295 int apic, pin;
296 struct irq_pin_list *entry = irq_2_pin + irq;
297
298 BUG_ON(irq >= NR_IRQS);
299 for (;;) {
300 unsigned int reg;
301 apic = entry->apic;
302 pin = entry->pin;
303 if (pin == -1)
304 break;
305 io_apic_write(apic, 0x11 + pin*2, dest);
306 reg = io_apic_read(apic, 0x10 + pin*2);
307 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
308 reg |= vector;
309 io_apic_modify(apic, reg);
310 if (!entry->next)
311 break;
312 entry = irq_2_pin + entry->next;
313 }
314 }
315
316 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
317 {
318 struct irq_cfg *cfg = irq_cfg + irq;
319 unsigned long flags;
320 unsigned int dest;
321 cpumask_t tmp;
322
323 cpus_and(tmp, mask, cpu_online_map);
324 if (cpus_empty(tmp))
325 return;
326
327 if (assign_irq_vector(irq, mask))
328 return;
329
330 cpus_and(tmp, cfg->domain, mask);
331 dest = cpu_mask_to_apicid(tmp);
332
333 /*
334 * Only the high 8 bits are valid.
335 */
336 dest = SET_APIC_LOGICAL_ID(dest);
337
338 spin_lock_irqsave(&ioapic_lock, flags);
339 __target_IO_APIC_irq(irq, dest, cfg->vector);
340 irq_desc[irq].affinity = mask;
341 spin_unlock_irqrestore(&ioapic_lock, flags);
342 }
343 #endif
344
345 /*
346 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
347 * shared ISA-space IRQs, so we have to support them. We are super
348 * fast in the common case, and fast for shared ISA-space IRQs.
349 */
350 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
351 {
352 static int first_free_entry = NR_IRQS;
353 struct irq_pin_list *entry = irq_2_pin + irq;
354
355 BUG_ON(irq >= NR_IRQS);
356 while (entry->next)
357 entry = irq_2_pin + entry->next;
358
359 if (entry->pin != -1) {
360 entry->next = first_free_entry;
361 entry = irq_2_pin + entry->next;
362 if (++first_free_entry >= PIN_MAP_SIZE)
363 panic("io_apic.c: ran out of irq_2_pin entries!");
364 }
365 entry->apic = apic;
366 entry->pin = pin;
367 }
368
369 /*
370 * Reroute an IRQ to a different pin.
371 */
372 static void __init replace_pin_at_irq(unsigned int irq,
373 int oldapic, int oldpin,
374 int newapic, int newpin)
375 {
376 struct irq_pin_list *entry = irq_2_pin + irq;
377
378 while (1) {
379 if (entry->apic == oldapic && entry->pin == oldpin) {
380 entry->apic = newapic;
381 entry->pin = newpin;
382 }
383 if (!entry->next)
384 break;
385 entry = irq_2_pin + entry->next;
386 }
387 }
388
389
390 #define DO_ACTION(name,R,ACTION, FINAL) \
391 \
392 static void name##_IO_APIC_irq (unsigned int irq) \
393 __DO_ACTION(R, ACTION, FINAL)
394
395 /* mask = 1 */
396 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
397
398 /* mask = 0 */
399 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
400
401 static void mask_IO_APIC_irq (unsigned int irq)
402 {
403 unsigned long flags;
404
405 spin_lock_irqsave(&ioapic_lock, flags);
406 __mask_IO_APIC_irq(irq);
407 spin_unlock_irqrestore(&ioapic_lock, flags);
408 }
409
410 static void unmask_IO_APIC_irq (unsigned int irq)
411 {
412 unsigned long flags;
413
414 spin_lock_irqsave(&ioapic_lock, flags);
415 __unmask_IO_APIC_irq(irq);
416 spin_unlock_irqrestore(&ioapic_lock, flags);
417 }
418
419 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
420 {
421 struct IO_APIC_route_entry entry;
422
423 /* Check delivery_mode to be sure we're not clearing an SMI pin */
424 entry = ioapic_read_entry(apic, pin);
425 if (entry.delivery_mode == dest_SMI)
426 return;
427 /*
428 * Disable it in the IO-APIC irq-routing table:
429 */
430 ioapic_mask_entry(apic, pin);
431 }
432
433 static void clear_IO_APIC (void)
434 {
435 int apic, pin;
436
437 for (apic = 0; apic < nr_ioapics; apic++)
438 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
439 clear_IO_APIC_pin(apic, pin);
440 }
441
442 int skip_ioapic_setup;
443 int ioapic_force;
444
445 static int __init parse_noapic(char *str)
446 {
447 disable_ioapic_setup();
448 return 0;
449 }
450 early_param("noapic", parse_noapic);
451
452 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
453 static int __init disable_timer_pin_setup(char *arg)
454 {
455 disable_timer_pin_1 = 1;
456 return 1;
457 }
458 __setup("disable_timer_pin_1", disable_timer_pin_setup);
459
460
461 /*
462 * Find the IRQ entry number of a certain pin.
463 */
464 static int find_irq_entry(int apic, int pin, int type)
465 {
466 int i;
467
468 for (i = 0; i < mp_irq_entries; i++)
469 if (mp_irqs[i].mp_irqtype == type &&
470 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
471 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
472 mp_irqs[i].mp_dstirq == pin)
473 return i;
474
475 return -1;
476 }
477
478 /*
479 * Find the pin to which IRQ[irq] (ISA) is connected
480 */
481 static int __init find_isa_irq_pin(int irq, int type)
482 {
483 int i;
484
485 for (i = 0; i < mp_irq_entries; i++) {
486 int lbus = mp_irqs[i].mp_srcbus;
487
488 if (test_bit(lbus, mp_bus_not_pci) &&
489 (mp_irqs[i].mp_irqtype == type) &&
490 (mp_irqs[i].mp_srcbusirq == irq))
491
492 return mp_irqs[i].mp_dstirq;
493 }
494 return -1;
495 }
496
497 static int __init find_isa_irq_apic(int irq, int type)
498 {
499 int i;
500
501 for (i = 0; i < mp_irq_entries; i++) {
502 int lbus = mp_irqs[i].mp_srcbus;
503
504 if (test_bit(lbus, mp_bus_not_pci) &&
505 (mp_irqs[i].mp_irqtype == type) &&
506 (mp_irqs[i].mp_srcbusirq == irq))
507 break;
508 }
509 if (i < mp_irq_entries) {
510 int apic;
511 for(apic = 0; apic < nr_ioapics; apic++) {
512 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
513 return apic;
514 }
515 }
516
517 return -1;
518 }
519
520 /*
521 * Find a specific PCI IRQ entry.
522 * Not an __init, possibly needed by modules
523 */
524 static int pin_2_irq(int idx, int apic, int pin);
525
526 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
527 {
528 int apic, i, best_guess = -1;
529
530 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
531 bus, slot, pin);
532 if (test_bit(bus, mp_bus_not_pci)) {
533 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
534 return -1;
535 }
536 for (i = 0; i < mp_irq_entries; i++) {
537 int lbus = mp_irqs[i].mp_srcbus;
538
539 for (apic = 0; apic < nr_ioapics; apic++)
540 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
541 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
542 break;
543
544 if (!test_bit(lbus, mp_bus_not_pci) &&
545 !mp_irqs[i].mp_irqtype &&
546 (bus == lbus) &&
547 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
548 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
549
550 if (!(apic || IO_APIC_IRQ(irq)))
551 continue;
552
553 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
554 return irq;
555 /*
556 * Use the first all-but-pin matching entry as a
557 * best-guess fuzzy result for broken mptables.
558 */
559 if (best_guess < 0)
560 best_guess = irq;
561 }
562 }
563 BUG_ON(best_guess >= NR_IRQS);
564 return best_guess;
565 }
566
567 /* ISA interrupts are always polarity zero edge triggered,
568 * when listed as conforming in the MP table. */
569
570 #define default_ISA_trigger(idx) (0)
571 #define default_ISA_polarity(idx) (0)
572
573 /* PCI interrupts are always polarity one level triggered,
574 * when listed as conforming in the MP table. */
575
576 #define default_PCI_trigger(idx) (1)
577 #define default_PCI_polarity(idx) (1)
578
579 static int MPBIOS_polarity(int idx)
580 {
581 int bus = mp_irqs[idx].mp_srcbus;
582 int polarity;
583
584 /*
585 * Determine IRQ line polarity (high active or low active):
586 */
587 switch (mp_irqs[idx].mp_irqflag & 3)
588 {
589 case 0: /* conforms, ie. bus-type dependent polarity */
590 if (test_bit(bus, mp_bus_not_pci))
591 polarity = default_ISA_polarity(idx);
592 else
593 polarity = default_PCI_polarity(idx);
594 break;
595 case 1: /* high active */
596 {
597 polarity = 0;
598 break;
599 }
600 case 2: /* reserved */
601 {
602 printk(KERN_WARNING "broken BIOS!!\n");
603 polarity = 1;
604 break;
605 }
606 case 3: /* low active */
607 {
608 polarity = 1;
609 break;
610 }
611 default: /* invalid */
612 {
613 printk(KERN_WARNING "broken BIOS!!\n");
614 polarity = 1;
615 break;
616 }
617 }
618 return polarity;
619 }
620
621 static int MPBIOS_trigger(int idx)
622 {
623 int bus = mp_irqs[idx].mp_srcbus;
624 int trigger;
625
626 /*
627 * Determine IRQ trigger mode (edge or level sensitive):
628 */
629 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
630 {
631 case 0: /* conforms, ie. bus-type dependent */
632 if (test_bit(bus, mp_bus_not_pci))
633 trigger = default_ISA_trigger(idx);
634 else
635 trigger = default_PCI_trigger(idx);
636 break;
637 case 1: /* edge */
638 {
639 trigger = 0;
640 break;
641 }
642 case 2: /* reserved */
643 {
644 printk(KERN_WARNING "broken BIOS!!\n");
645 trigger = 1;
646 break;
647 }
648 case 3: /* level */
649 {
650 trigger = 1;
651 break;
652 }
653 default: /* invalid */
654 {
655 printk(KERN_WARNING "broken BIOS!!\n");
656 trigger = 0;
657 break;
658 }
659 }
660 return trigger;
661 }
662
663 static inline int irq_polarity(int idx)
664 {
665 return MPBIOS_polarity(idx);
666 }
667
668 static inline int irq_trigger(int idx)
669 {
670 return MPBIOS_trigger(idx);
671 }
672
673 static int pin_2_irq(int idx, int apic, int pin)
674 {
675 int irq, i;
676 int bus = mp_irqs[idx].mp_srcbus;
677
678 /*
679 * Debugging check, we are in big trouble if this message pops up!
680 */
681 if (mp_irqs[idx].mp_dstirq != pin)
682 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
683
684 if (test_bit(bus, mp_bus_not_pci)) {
685 irq = mp_irqs[idx].mp_srcbusirq;
686 } else {
687 /*
688 * PCI IRQs are mapped in order
689 */
690 i = irq = 0;
691 while (i < apic)
692 irq += nr_ioapic_registers[i++];
693 irq += pin;
694 }
695 BUG_ON(irq >= NR_IRQS);
696 return irq;
697 }
698
699 static int __assign_irq_vector(int irq, cpumask_t mask)
700 {
701 /*
702 * NOTE! The local APIC isn't very good at handling
703 * multiple interrupts at the same interrupt level.
704 * As the interrupt level is determined by taking the
705 * vector number and shifting that right by 4, we
706 * want to spread these out a bit so that they don't
707 * all fall in the same interrupt level.
708 *
709 * Also, we've got to be careful not to trash gate
710 * 0x80, because int 0x80 is hm, kind of importantish. ;)
711 */
712 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
713 unsigned int old_vector;
714 int cpu;
715 struct irq_cfg *cfg;
716
717 BUG_ON((unsigned)irq >= NR_IRQS);
718 cfg = &irq_cfg[irq];
719
720 /* Only try and allocate irqs on cpus that are present */
721 cpus_and(mask, mask, cpu_online_map);
722
723 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
724 return -EBUSY;
725
726 old_vector = cfg->vector;
727 if (old_vector) {
728 cpumask_t tmp;
729 cpus_and(tmp, cfg->domain, mask);
730 if (!cpus_empty(tmp))
731 return 0;
732 }
733
734 for_each_cpu_mask(cpu, mask) {
735 cpumask_t domain, new_mask;
736 int new_cpu;
737 int vector, offset;
738
739 domain = vector_allocation_domain(cpu);
740 cpus_and(new_mask, domain, cpu_online_map);
741
742 vector = current_vector;
743 offset = current_offset;
744 next:
745 vector += 8;
746 if (vector >= first_system_vector) {
747 /* If we run out of vectors on large boxen, must share them. */
748 offset = (offset + 1) % 8;
749 vector = FIRST_DEVICE_VECTOR + offset;
750 }
751 if (unlikely(current_vector == vector))
752 continue;
753 if (vector == IA32_SYSCALL_VECTOR)
754 goto next;
755 for_each_cpu_mask(new_cpu, new_mask)
756 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
757 goto next;
758 /* Found one! */
759 current_vector = vector;
760 current_offset = offset;
761 if (old_vector) {
762 cfg->move_in_progress = 1;
763 cfg->old_domain = cfg->domain;
764 }
765 for_each_cpu_mask(new_cpu, new_mask)
766 per_cpu(vector_irq, new_cpu)[vector] = irq;
767 cfg->vector = vector;
768 cfg->domain = domain;
769 return 0;
770 }
771 return -ENOSPC;
772 }
773
774 static int assign_irq_vector(int irq, cpumask_t mask)
775 {
776 int err;
777 unsigned long flags;
778
779 spin_lock_irqsave(&vector_lock, flags);
780 err = __assign_irq_vector(irq, mask);
781 spin_unlock_irqrestore(&vector_lock, flags);
782 return err;
783 }
784
785 static void __clear_irq_vector(int irq)
786 {
787 struct irq_cfg *cfg;
788 cpumask_t mask;
789 int cpu, vector;
790
791 BUG_ON((unsigned)irq >= NR_IRQS);
792 cfg = &irq_cfg[irq];
793 BUG_ON(!cfg->vector);
794
795 vector = cfg->vector;
796 cpus_and(mask, cfg->domain, cpu_online_map);
797 for_each_cpu_mask(cpu, mask)
798 per_cpu(vector_irq, cpu)[vector] = -1;
799
800 cfg->vector = 0;
801 cpus_clear(cfg->domain);
802 }
803
804 static void __setup_vector_irq(int cpu)
805 {
806 /* Initialize vector_irq on a new cpu */
807 /* This function must be called with vector_lock held */
808 int irq, vector;
809
810 /* Mark the inuse vectors */
811 for (irq = 0; irq < NR_IRQS; ++irq) {
812 if (!cpu_isset(cpu, irq_cfg[irq].domain))
813 continue;
814 vector = irq_cfg[irq].vector;
815 per_cpu(vector_irq, cpu)[vector] = irq;
816 }
817 /* Mark the free vectors */
818 for (vector = 0; vector < NR_VECTORS; ++vector) {
819 irq = per_cpu(vector_irq, cpu)[vector];
820 if (irq < 0)
821 continue;
822 if (!cpu_isset(cpu, irq_cfg[irq].domain))
823 per_cpu(vector_irq, cpu)[vector] = -1;
824 }
825 }
826
827 void setup_vector_irq(int cpu)
828 {
829 spin_lock(&vector_lock);
830 __setup_vector_irq(smp_processor_id());
831 spin_unlock(&vector_lock);
832 }
833
834
835 static struct irq_chip ioapic_chip;
836
837 static void ioapic_register_intr(int irq, unsigned long trigger)
838 {
839 if (trigger) {
840 irq_desc[irq].status |= IRQ_LEVEL;
841 set_irq_chip_and_handler_name(irq, &ioapic_chip,
842 handle_fasteoi_irq, "fasteoi");
843 } else {
844 irq_desc[irq].status &= ~IRQ_LEVEL;
845 set_irq_chip_and_handler_name(irq, &ioapic_chip,
846 handle_edge_irq, "edge");
847 }
848 }
849
850 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
851 int trigger, int polarity)
852 {
853 struct irq_cfg *cfg = irq_cfg + irq;
854 struct IO_APIC_route_entry entry;
855 cpumask_t mask;
856
857 if (!IO_APIC_IRQ(irq))
858 return;
859
860 mask = TARGET_CPUS;
861 if (assign_irq_vector(irq, mask))
862 return;
863
864 cpus_and(mask, cfg->domain, mask);
865
866 apic_printk(APIC_VERBOSE,KERN_DEBUG
867 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
868 "IRQ %d Mode:%i Active:%i)\n",
869 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
870 irq, trigger, polarity);
871
872 /*
873 * add it to the IO-APIC irq-routing table:
874 */
875 memset(&entry,0,sizeof(entry));
876
877 entry.delivery_mode = INT_DELIVERY_MODE;
878 entry.dest_mode = INT_DEST_MODE;
879 entry.dest = cpu_mask_to_apicid(mask);
880 entry.mask = 0; /* enable IRQ */
881 entry.trigger = trigger;
882 entry.polarity = polarity;
883 entry.vector = cfg->vector;
884
885 /* Mask level triggered irqs.
886 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
887 */
888 if (trigger)
889 entry.mask = 1;
890
891 ioapic_register_intr(irq, trigger);
892 if (irq < 16)
893 disable_8259A_irq(irq);
894
895 ioapic_write_entry(apic, pin, entry);
896 }
897
898 static void __init setup_IO_APIC_irqs(void)
899 {
900 int apic, pin, idx, irq, first_notcon = 1;
901
902 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
903
904 for (apic = 0; apic < nr_ioapics; apic++) {
905 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
906
907 idx = find_irq_entry(apic,pin,mp_INT);
908 if (idx == -1) {
909 if (first_notcon) {
910 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
911 first_notcon = 0;
912 } else
913 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
914 continue;
915 }
916 if (!first_notcon) {
917 apic_printk(APIC_VERBOSE, " not connected.\n");
918 first_notcon = 1;
919 }
920
921 irq = pin_2_irq(idx, apic, pin);
922 add_pin_to_irq(irq, apic, pin);
923
924 setup_IO_APIC_irq(apic, pin, irq,
925 irq_trigger(idx), irq_polarity(idx));
926 }
927 }
928
929 if (!first_notcon)
930 apic_printk(APIC_VERBOSE, " not connected.\n");
931 }
932
933 /*
934 * Set up the timer pin, possibly with the 8259A-master behind.
935 */
936 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
937 int vector)
938 {
939 struct IO_APIC_route_entry entry;
940
941 memset(&entry, 0, sizeof(entry));
942
943 /*
944 * We use logical delivery to get the timer IRQ
945 * to the first CPU.
946 */
947 entry.dest_mode = INT_DEST_MODE;
948 entry.mask = 1; /* mask IRQ now */
949 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
950 entry.delivery_mode = INT_DELIVERY_MODE;
951 entry.polarity = 0;
952 entry.trigger = 0;
953 entry.vector = vector;
954
955 /*
956 * The timer IRQ doesn't have to know that behind the
957 * scene we may have a 8259A-master in AEOI mode ...
958 */
959 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
960
961 /*
962 * Add it to the IO-APIC irq-routing table:
963 */
964 ioapic_write_entry(apic, pin, entry);
965 }
966
967 void __apicdebuginit print_IO_APIC(void)
968 {
969 int apic, i;
970 union IO_APIC_reg_00 reg_00;
971 union IO_APIC_reg_01 reg_01;
972 union IO_APIC_reg_02 reg_02;
973 unsigned long flags;
974
975 if (apic_verbosity == APIC_QUIET)
976 return;
977
978 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
979 for (i = 0; i < nr_ioapics; i++)
980 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
981 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
982
983 /*
984 * We are a bit conservative about what we expect. We have to
985 * know about every hardware change ASAP.
986 */
987 printk(KERN_INFO "testing the IO APIC.......................\n");
988
989 for (apic = 0; apic < nr_ioapics; apic++) {
990
991 spin_lock_irqsave(&ioapic_lock, flags);
992 reg_00.raw = io_apic_read(apic, 0);
993 reg_01.raw = io_apic_read(apic, 1);
994 if (reg_01.bits.version >= 0x10)
995 reg_02.raw = io_apic_read(apic, 2);
996 spin_unlock_irqrestore(&ioapic_lock, flags);
997
998 printk("\n");
999 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1000 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1001 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1002
1003 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1004 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1005
1006 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1007 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1008
1009 if (reg_01.bits.version >= 0x10) {
1010 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1011 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1012 }
1013
1014 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1015
1016 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1017 " Stat Dmod Deli Vect: \n");
1018
1019 for (i = 0; i <= reg_01.bits.entries; i++) {
1020 struct IO_APIC_route_entry entry;
1021
1022 entry = ioapic_read_entry(apic, i);
1023
1024 printk(KERN_DEBUG " %02x %03X ",
1025 i,
1026 entry.dest
1027 );
1028
1029 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1030 entry.mask,
1031 entry.trigger,
1032 entry.irr,
1033 entry.polarity,
1034 entry.delivery_status,
1035 entry.dest_mode,
1036 entry.delivery_mode,
1037 entry.vector
1038 );
1039 }
1040 }
1041 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1042 for (i = 0; i < NR_IRQS; i++) {
1043 struct irq_pin_list *entry = irq_2_pin + i;
1044 if (entry->pin < 0)
1045 continue;
1046 printk(KERN_DEBUG "IRQ%d ", i);
1047 for (;;) {
1048 printk("-> %d:%d", entry->apic, entry->pin);
1049 if (!entry->next)
1050 break;
1051 entry = irq_2_pin + entry->next;
1052 }
1053 printk("\n");
1054 }
1055
1056 printk(KERN_INFO ".................................... done.\n");
1057
1058 return;
1059 }
1060
1061 #if 0
1062
1063 static __apicdebuginit void print_APIC_bitfield (int base)
1064 {
1065 unsigned int v;
1066 int i, j;
1067
1068 if (apic_verbosity == APIC_QUIET)
1069 return;
1070
1071 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1072 for (i = 0; i < 8; i++) {
1073 v = apic_read(base + i*0x10);
1074 for (j = 0; j < 32; j++) {
1075 if (v & (1<<j))
1076 printk("1");
1077 else
1078 printk("0");
1079 }
1080 printk("\n");
1081 }
1082 }
1083
1084 void __apicdebuginit print_local_APIC(void * dummy)
1085 {
1086 unsigned int v, ver, maxlvt;
1087
1088 if (apic_verbosity == APIC_QUIET)
1089 return;
1090
1091 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1092 smp_processor_id(), hard_smp_processor_id());
1093 v = apic_read(APIC_ID);
1094 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1095 v = apic_read(APIC_LVR);
1096 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1097 ver = GET_APIC_VERSION(v);
1098 maxlvt = lapic_get_maxlvt();
1099
1100 v = apic_read(APIC_TASKPRI);
1101 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1102
1103 v = apic_read(APIC_ARBPRI);
1104 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1105 v & APIC_ARBPRI_MASK);
1106 v = apic_read(APIC_PROCPRI);
1107 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1108
1109 v = apic_read(APIC_EOI);
1110 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1111 v = apic_read(APIC_RRR);
1112 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1113 v = apic_read(APIC_LDR);
1114 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1115 v = apic_read(APIC_DFR);
1116 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1117 v = apic_read(APIC_SPIV);
1118 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1119
1120 printk(KERN_DEBUG "... APIC ISR field:\n");
1121 print_APIC_bitfield(APIC_ISR);
1122 printk(KERN_DEBUG "... APIC TMR field:\n");
1123 print_APIC_bitfield(APIC_TMR);
1124 printk(KERN_DEBUG "... APIC IRR field:\n");
1125 print_APIC_bitfield(APIC_IRR);
1126
1127 v = apic_read(APIC_ESR);
1128 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1129
1130 v = apic_read(APIC_ICR);
1131 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1132 v = apic_read(APIC_ICR2);
1133 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1134
1135 v = apic_read(APIC_LVTT);
1136 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1137
1138 if (maxlvt > 3) { /* PC is LVT#4. */
1139 v = apic_read(APIC_LVTPC);
1140 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1141 }
1142 v = apic_read(APIC_LVT0);
1143 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1144 v = apic_read(APIC_LVT1);
1145 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1146
1147 if (maxlvt > 2) { /* ERR is LVT#3. */
1148 v = apic_read(APIC_LVTERR);
1149 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1150 }
1151
1152 v = apic_read(APIC_TMICT);
1153 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1154 v = apic_read(APIC_TMCCT);
1155 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1156 v = apic_read(APIC_TDCR);
1157 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1158 printk("\n");
1159 }
1160
1161 void print_all_local_APICs (void)
1162 {
1163 on_each_cpu(print_local_APIC, NULL, 1, 1);
1164 }
1165
1166 void __apicdebuginit print_PIC(void)
1167 {
1168 unsigned int v;
1169 unsigned long flags;
1170
1171 if (apic_verbosity == APIC_QUIET)
1172 return;
1173
1174 printk(KERN_DEBUG "\nprinting PIC contents\n");
1175
1176 spin_lock_irqsave(&i8259A_lock, flags);
1177
1178 v = inb(0xa1) << 8 | inb(0x21);
1179 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1180
1181 v = inb(0xa0) << 8 | inb(0x20);
1182 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1183
1184 outb(0x0b,0xa0);
1185 outb(0x0b,0x20);
1186 v = inb(0xa0) << 8 | inb(0x20);
1187 outb(0x0a,0xa0);
1188 outb(0x0a,0x20);
1189
1190 spin_unlock_irqrestore(&i8259A_lock, flags);
1191
1192 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1193
1194 v = inb(0x4d1) << 8 | inb(0x4d0);
1195 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1196 }
1197
1198 #endif /* 0 */
1199
1200 void __init enable_IO_APIC(void)
1201 {
1202 union IO_APIC_reg_01 reg_01;
1203 int i8259_apic, i8259_pin;
1204 int i, apic;
1205 unsigned long flags;
1206
1207 for (i = 0; i < PIN_MAP_SIZE; i++) {
1208 irq_2_pin[i].pin = -1;
1209 irq_2_pin[i].next = 0;
1210 }
1211
1212 /*
1213 * The number of IO-APIC IRQ registers (== #pins):
1214 */
1215 for (apic = 0; apic < nr_ioapics; apic++) {
1216 spin_lock_irqsave(&ioapic_lock, flags);
1217 reg_01.raw = io_apic_read(apic, 1);
1218 spin_unlock_irqrestore(&ioapic_lock, flags);
1219 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1220 }
1221 for(apic = 0; apic < nr_ioapics; apic++) {
1222 int pin;
1223 /* See if any of the pins is in ExtINT mode */
1224 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1225 struct IO_APIC_route_entry entry;
1226 entry = ioapic_read_entry(apic, pin);
1227
1228 /* If the interrupt line is enabled and in ExtInt mode
1229 * I have found the pin where the i8259 is connected.
1230 */
1231 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1232 ioapic_i8259.apic = apic;
1233 ioapic_i8259.pin = pin;
1234 goto found_i8259;
1235 }
1236 }
1237 }
1238 found_i8259:
1239 /* Look to see what if the MP table has reported the ExtINT */
1240 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1241 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1242 /* Trust the MP table if nothing is setup in the hardware */
1243 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1244 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1245 ioapic_i8259.pin = i8259_pin;
1246 ioapic_i8259.apic = i8259_apic;
1247 }
1248 /* Complain if the MP table and the hardware disagree */
1249 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1250 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1251 {
1252 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1253 }
1254
1255 /*
1256 * Do not trust the IO-APIC being empty at bootup
1257 */
1258 clear_IO_APIC();
1259 }
1260
1261 /*
1262 * Not an __init, needed by the reboot code
1263 */
1264 void disable_IO_APIC(void)
1265 {
1266 /*
1267 * Clear the IO-APIC before rebooting:
1268 */
1269 clear_IO_APIC();
1270
1271 /*
1272 * If the i8259 is routed through an IOAPIC
1273 * Put that IOAPIC in virtual wire mode
1274 * so legacy interrupts can be delivered.
1275 */
1276 if (ioapic_i8259.pin != -1) {
1277 struct IO_APIC_route_entry entry;
1278
1279 memset(&entry, 0, sizeof(entry));
1280 entry.mask = 0; /* Enabled */
1281 entry.trigger = 0; /* Edge */
1282 entry.irr = 0;
1283 entry.polarity = 0; /* High */
1284 entry.delivery_status = 0;
1285 entry.dest_mode = 0; /* Physical */
1286 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1287 entry.vector = 0;
1288 entry.dest = GET_APIC_ID(read_apic_id());
1289
1290 /*
1291 * Add it to the IO-APIC irq-routing table:
1292 */
1293 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1294 }
1295
1296 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1297 }
1298
1299 /*
1300 * There is a nasty bug in some older SMP boards, their mptable lies
1301 * about the timer IRQ. We do the following to work around the situation:
1302 *
1303 * - timer IRQ defaults to IO-APIC IRQ
1304 * - if this function detects that timer IRQs are defunct, then we fall
1305 * back to ISA timer IRQs
1306 */
1307 static int __init timer_irq_works(void)
1308 {
1309 unsigned long t1 = jiffies;
1310 unsigned long flags;
1311
1312 local_save_flags(flags);
1313 local_irq_enable();
1314 /* Let ten ticks pass... */
1315 mdelay((10 * 1000) / HZ);
1316 local_irq_restore(flags);
1317
1318 /*
1319 * Expect a few ticks at least, to be sure some possible
1320 * glue logic does not lock up after one or two first
1321 * ticks in a non-ExtINT mode. Also the local APIC
1322 * might have cached one ExtINT interrupt. Finally, at
1323 * least one tick may be lost due to delays.
1324 */
1325
1326 /* jiffies wrap? */
1327 if (time_after(jiffies, t1 + 4))
1328 return 1;
1329 return 0;
1330 }
1331
1332 /*
1333 * In the SMP+IOAPIC case it might happen that there are an unspecified
1334 * number of pending IRQ events unhandled. These cases are very rare,
1335 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1336 * better to do it this way as thus we do not have to be aware of
1337 * 'pending' interrupts in the IRQ path, except at this point.
1338 */
1339 /*
1340 * Edge triggered needs to resend any interrupt
1341 * that was delayed but this is now handled in the device
1342 * independent code.
1343 */
1344
1345 /*
1346 * Starting up a edge-triggered IO-APIC interrupt is
1347 * nasty - we need to make sure that we get the edge.
1348 * If it is already asserted for some reason, we need
1349 * return 1 to indicate that is was pending.
1350 *
1351 * This is not complete - we should be able to fake
1352 * an edge even if it isn't on the 8259A...
1353 */
1354
1355 static unsigned int startup_ioapic_irq(unsigned int irq)
1356 {
1357 int was_pending = 0;
1358 unsigned long flags;
1359
1360 spin_lock_irqsave(&ioapic_lock, flags);
1361 if (irq < 16) {
1362 disable_8259A_irq(irq);
1363 if (i8259A_irq_pending(irq))
1364 was_pending = 1;
1365 }
1366 __unmask_IO_APIC_irq(irq);
1367 spin_unlock_irqrestore(&ioapic_lock, flags);
1368
1369 return was_pending;
1370 }
1371
1372 static int ioapic_retrigger_irq(unsigned int irq)
1373 {
1374 struct irq_cfg *cfg = &irq_cfg[irq];
1375 cpumask_t mask;
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&vector_lock, flags);
1379 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1380 send_IPI_mask(mask, cfg->vector);
1381 spin_unlock_irqrestore(&vector_lock, flags);
1382
1383 return 1;
1384 }
1385
1386 /*
1387 * Level and edge triggered IO-APIC interrupts need different handling,
1388 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1389 * handled with the level-triggered descriptor, but that one has slightly
1390 * more overhead. Level-triggered interrupts cannot be handled with the
1391 * edge-triggered handler, without risking IRQ storms and other ugly
1392 * races.
1393 */
1394
1395 #ifdef CONFIG_SMP
1396 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1397 {
1398 unsigned vector, me;
1399 ack_APIC_irq();
1400 exit_idle();
1401 irq_enter();
1402
1403 me = smp_processor_id();
1404 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1405 unsigned int irq;
1406 struct irq_desc *desc;
1407 struct irq_cfg *cfg;
1408 irq = __get_cpu_var(vector_irq)[vector];
1409 if (irq >= NR_IRQS)
1410 continue;
1411
1412 desc = irq_desc + irq;
1413 cfg = irq_cfg + irq;
1414 spin_lock(&desc->lock);
1415 if (!cfg->move_cleanup_count)
1416 goto unlock;
1417
1418 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1419 goto unlock;
1420
1421 __get_cpu_var(vector_irq)[vector] = -1;
1422 cfg->move_cleanup_count--;
1423 unlock:
1424 spin_unlock(&desc->lock);
1425 }
1426
1427 irq_exit();
1428 }
1429
1430 static void irq_complete_move(unsigned int irq)
1431 {
1432 struct irq_cfg *cfg = irq_cfg + irq;
1433 unsigned vector, me;
1434
1435 if (likely(!cfg->move_in_progress))
1436 return;
1437
1438 vector = ~get_irq_regs()->orig_ax;
1439 me = smp_processor_id();
1440 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1441 cpumask_t cleanup_mask;
1442
1443 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1444 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1445 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1446 cfg->move_in_progress = 0;
1447 }
1448 }
1449 #else
1450 static inline void irq_complete_move(unsigned int irq) {}
1451 #endif
1452
1453 static void ack_apic_edge(unsigned int irq)
1454 {
1455 irq_complete_move(irq);
1456 move_native_irq(irq);
1457 ack_APIC_irq();
1458 }
1459
1460 static void ack_apic_level(unsigned int irq)
1461 {
1462 int do_unmask_irq = 0;
1463
1464 irq_complete_move(irq);
1465 #ifdef CONFIG_GENERIC_PENDING_IRQ
1466 /* If we are moving the irq we need to mask it */
1467 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1468 do_unmask_irq = 1;
1469 mask_IO_APIC_irq(irq);
1470 }
1471 #endif
1472
1473 /*
1474 * We must acknowledge the irq before we move it or the acknowledge will
1475 * not propagate properly.
1476 */
1477 ack_APIC_irq();
1478
1479 /* Now we can move and renable the irq */
1480 if (unlikely(do_unmask_irq)) {
1481 /* Only migrate the irq if the ack has been received.
1482 *
1483 * On rare occasions the broadcast level triggered ack gets
1484 * delayed going to ioapics, and if we reprogram the
1485 * vector while Remote IRR is still set the irq will never
1486 * fire again.
1487 *
1488 * To prevent this scenario we read the Remote IRR bit
1489 * of the ioapic. This has two effects.
1490 * - On any sane system the read of the ioapic will
1491 * flush writes (and acks) going to the ioapic from
1492 * this cpu.
1493 * - We get to see if the ACK has actually been delivered.
1494 *
1495 * Based on failed experiments of reprogramming the
1496 * ioapic entry from outside of irq context starting
1497 * with masking the ioapic entry and then polling until
1498 * Remote IRR was clear before reprogramming the
1499 * ioapic I don't trust the Remote IRR bit to be
1500 * completey accurate.
1501 *
1502 * However there appears to be no other way to plug
1503 * this race, so if the Remote IRR bit is not
1504 * accurate and is causing problems then it is a hardware bug
1505 * and you can go talk to the chipset vendor about it.
1506 */
1507 if (!io_apic_level_ack_pending(irq))
1508 move_masked_irq(irq);
1509 unmask_IO_APIC_irq(irq);
1510 }
1511 }
1512
1513 static struct irq_chip ioapic_chip __read_mostly = {
1514 .name = "IO-APIC",
1515 .startup = startup_ioapic_irq,
1516 .mask = mask_IO_APIC_irq,
1517 .unmask = unmask_IO_APIC_irq,
1518 .ack = ack_apic_edge,
1519 .eoi = ack_apic_level,
1520 #ifdef CONFIG_SMP
1521 .set_affinity = set_ioapic_affinity_irq,
1522 #endif
1523 .retrigger = ioapic_retrigger_irq,
1524 };
1525
1526 static inline void init_IO_APIC_traps(void)
1527 {
1528 int irq;
1529
1530 /*
1531 * NOTE! The local APIC isn't very good at handling
1532 * multiple interrupts at the same interrupt level.
1533 * As the interrupt level is determined by taking the
1534 * vector number and shifting that right by 4, we
1535 * want to spread these out a bit so that they don't
1536 * all fall in the same interrupt level.
1537 *
1538 * Also, we've got to be careful not to trash gate
1539 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1540 */
1541 for (irq = 0; irq < NR_IRQS ; irq++) {
1542 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1543 /*
1544 * Hmm.. We don't have an entry for this,
1545 * so default to an old-fashioned 8259
1546 * interrupt if we can..
1547 */
1548 if (irq < 16)
1549 make_8259A_irq(irq);
1550 else
1551 /* Strange. Oh, well.. */
1552 irq_desc[irq].chip = &no_irq_chip;
1553 }
1554 }
1555 }
1556
1557 static void enable_lapic_irq (unsigned int irq)
1558 {
1559 unsigned long v;
1560
1561 v = apic_read(APIC_LVT0);
1562 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1563 }
1564
1565 static void disable_lapic_irq (unsigned int irq)
1566 {
1567 unsigned long v;
1568
1569 v = apic_read(APIC_LVT0);
1570 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1571 }
1572
1573 static void ack_lapic_irq (unsigned int irq)
1574 {
1575 ack_APIC_irq();
1576 }
1577
1578 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1579
1580 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1581 .name = "local-APIC",
1582 .typename = "local-APIC-edge",
1583 .startup = NULL, /* startup_irq() not used for IRQ0 */
1584 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1585 .enable = enable_lapic_irq,
1586 .disable = disable_lapic_irq,
1587 .ack = ack_lapic_irq,
1588 .end = end_lapic_irq,
1589 };
1590
1591 static void __init setup_nmi(void)
1592 {
1593 /*
1594 * Dirty trick to enable the NMI watchdog ...
1595 * We put the 8259A master into AEOI mode and
1596 * unmask on all local APICs LVT0 as NMI.
1597 *
1598 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1599 * is from Maciej W. Rozycki - so we do not have to EOI from
1600 * the NMI handler or the timer interrupt.
1601 */
1602 printk(KERN_INFO "activating NMI Watchdog ...");
1603
1604 enable_NMI_through_LVT0();
1605
1606 printk(" done.\n");
1607 }
1608
1609 /*
1610 * This looks a bit hackish but it's about the only one way of sending
1611 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1612 * not support the ExtINT mode, unfortunately. We need to send these
1613 * cycles as some i82489DX-based boards have glue logic that keeps the
1614 * 8259A interrupt line asserted until INTA. --macro
1615 */
1616 static inline void __init unlock_ExtINT_logic(void)
1617 {
1618 int apic, pin, i;
1619 struct IO_APIC_route_entry entry0, entry1;
1620 unsigned char save_control, save_freq_select;
1621
1622 pin = find_isa_irq_pin(8, mp_INT);
1623 apic = find_isa_irq_apic(8, mp_INT);
1624 if (pin == -1)
1625 return;
1626
1627 entry0 = ioapic_read_entry(apic, pin);
1628
1629 clear_IO_APIC_pin(apic, pin);
1630
1631 memset(&entry1, 0, sizeof(entry1));
1632
1633 entry1.dest_mode = 0; /* physical delivery */
1634 entry1.mask = 0; /* unmask IRQ now */
1635 entry1.dest = hard_smp_processor_id();
1636 entry1.delivery_mode = dest_ExtINT;
1637 entry1.polarity = entry0.polarity;
1638 entry1.trigger = 0;
1639 entry1.vector = 0;
1640
1641 ioapic_write_entry(apic, pin, entry1);
1642
1643 save_control = CMOS_READ(RTC_CONTROL);
1644 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1645 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1646 RTC_FREQ_SELECT);
1647 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1648
1649 i = 100;
1650 while (i-- > 0) {
1651 mdelay(10);
1652 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1653 i -= 10;
1654 }
1655
1656 CMOS_WRITE(save_control, RTC_CONTROL);
1657 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1658 clear_IO_APIC_pin(apic, pin);
1659
1660 ioapic_write_entry(apic, pin, entry0);
1661 }
1662
1663 /*
1664 * This code may look a bit paranoid, but it's supposed to cooperate with
1665 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1666 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1667 * fanatically on his truly buggy board.
1668 *
1669 * FIXME: really need to revamp this for modern platforms only.
1670 */
1671 static inline void __init check_timer(void)
1672 {
1673 struct irq_cfg *cfg = irq_cfg + 0;
1674 int apic1, pin1, apic2, pin2;
1675 unsigned long flags;
1676 int no_pin1 = 0;
1677
1678 local_irq_save(flags);
1679
1680 /*
1681 * get/set the timer IRQ vector:
1682 */
1683 disable_8259A_irq(0);
1684 assign_irq_vector(0, TARGET_CPUS);
1685
1686 /*
1687 * As IRQ0 is to be enabled in the 8259A, the virtual
1688 * wire has to be disabled in the local APIC.
1689 */
1690 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1691 init_8259A(1);
1692
1693 pin1 = find_isa_irq_pin(0, mp_INT);
1694 apic1 = find_isa_irq_apic(0, mp_INT);
1695 pin2 = ioapic_i8259.pin;
1696 apic2 = ioapic_i8259.apic;
1697
1698 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1699 cfg->vector, apic1, pin1, apic2, pin2);
1700
1701 /*
1702 * Some BIOS writers are clueless and report the ExtINTA
1703 * I/O APIC input from the cascaded 8259A as the timer
1704 * interrupt input. So just in case, if only one pin
1705 * was found above, try it both directly and through the
1706 * 8259A.
1707 */
1708 if (pin1 == -1) {
1709 pin1 = pin2;
1710 apic1 = apic2;
1711 no_pin1 = 1;
1712 } else if (pin2 == -1) {
1713 pin2 = pin1;
1714 apic2 = apic1;
1715 }
1716
1717 replace_pin_at_irq(0, 0, 0, apic1, pin1);
1718 apic1 = 0;
1719 pin1 = 0;
1720 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1721
1722 if (pin1 != -1) {
1723 /*
1724 * Ok, does IRQ0 through the IOAPIC work?
1725 */
1726 if (no_pin1) {
1727 add_pin_to_irq(0, apic1, pin1);
1728 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1729 }
1730 unmask_IO_APIC_irq(0);
1731 if (!no_timer_check && timer_irq_works()) {
1732 if (nmi_watchdog == NMI_IO_APIC) {
1733 setup_nmi();
1734 enable_8259A_irq(0);
1735 }
1736 if (disable_timer_pin_1 > 0)
1737 clear_IO_APIC_pin(0, pin1);
1738 goto out;
1739 }
1740 clear_IO_APIC_pin(apic1, pin1);
1741 if (!no_pin1)
1742 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1743 "8254 timer not connected to IO-APIC\n");
1744
1745 apic_printk(APIC_VERBOSE,KERN_INFO
1746 "...trying to set up timer (IRQ0) "
1747 "through the 8259A ... ");
1748 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1749 apic2, pin2);
1750 /*
1751 * legacy devices should be connected to IO APIC #0
1752 */
1753 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1754 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1755 unmask_IO_APIC_irq(0);
1756 enable_8259A_irq(0);
1757 if (timer_irq_works()) {
1758 apic_printk(APIC_VERBOSE," works.\n");
1759 timer_through_8259 = 1;
1760 if (nmi_watchdog == NMI_IO_APIC) {
1761 disable_8259A_irq(0);
1762 setup_nmi();
1763 enable_8259A_irq(0);
1764 }
1765 goto out;
1766 }
1767 /*
1768 * Cleanup, just in case ...
1769 */
1770 disable_8259A_irq(0);
1771 clear_IO_APIC_pin(apic2, pin2);
1772 apic_printk(APIC_VERBOSE," failed.\n");
1773 }
1774
1775 if (nmi_watchdog == NMI_IO_APIC) {
1776 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1777 nmi_watchdog = NMI_NONE;
1778 }
1779
1780 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1781
1782 irq_desc[0].chip = &lapic_irq_type;
1783 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1784 enable_8259A_irq(0);
1785
1786 if (timer_irq_works()) {
1787 apic_printk(APIC_VERBOSE," works.\n");
1788 goto out;
1789 }
1790 disable_8259A_irq(0);
1791 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1792 apic_printk(APIC_VERBOSE," failed.\n");
1793
1794 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1795
1796 init_8259A(0);
1797 make_8259A_irq(0);
1798 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1799
1800 unlock_ExtINT_logic();
1801
1802 if (timer_irq_works()) {
1803 apic_printk(APIC_VERBOSE," works.\n");
1804 goto out;
1805 }
1806 apic_printk(APIC_VERBOSE," failed :(.\n");
1807 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1808 out:
1809 local_irq_restore(flags);
1810 }
1811
1812 static int __init notimercheck(char *s)
1813 {
1814 no_timer_check = 1;
1815 return 1;
1816 }
1817 __setup("no_timer_check", notimercheck);
1818
1819 /*
1820 *
1821 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1822 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1823 * Linux doesn't really care, as it's not actually used
1824 * for any interrupt handling anyway.
1825 */
1826 #define PIC_IRQS (1<<2)
1827
1828 void __init setup_IO_APIC(void)
1829 {
1830
1831 /*
1832 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1833 */
1834
1835 if (acpi_ioapic)
1836 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1837 else
1838 io_apic_irqs = ~PIC_IRQS;
1839
1840 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1841
1842 sync_Arb_IDs();
1843 setup_IO_APIC_irqs();
1844 init_IO_APIC_traps();
1845 check_timer();
1846 if (!acpi_ioapic)
1847 print_IO_APIC();
1848 }
1849
1850 struct sysfs_ioapic_data {
1851 struct sys_device dev;
1852 struct IO_APIC_route_entry entry[0];
1853 };
1854 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1855
1856 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1857 {
1858 struct IO_APIC_route_entry *entry;
1859 struct sysfs_ioapic_data *data;
1860 int i;
1861
1862 data = container_of(dev, struct sysfs_ioapic_data, dev);
1863 entry = data->entry;
1864 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1865 *entry = ioapic_read_entry(dev->id, i);
1866
1867 return 0;
1868 }
1869
1870 static int ioapic_resume(struct sys_device *dev)
1871 {
1872 struct IO_APIC_route_entry *entry;
1873 struct sysfs_ioapic_data *data;
1874 unsigned long flags;
1875 union IO_APIC_reg_00 reg_00;
1876 int i;
1877
1878 data = container_of(dev, struct sysfs_ioapic_data, dev);
1879 entry = data->entry;
1880
1881 spin_lock_irqsave(&ioapic_lock, flags);
1882 reg_00.raw = io_apic_read(dev->id, 0);
1883 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
1884 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1885 io_apic_write(dev->id, 0, reg_00.raw);
1886 }
1887 spin_unlock_irqrestore(&ioapic_lock, flags);
1888 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1889 ioapic_write_entry(dev->id, i, entry[i]);
1890
1891 return 0;
1892 }
1893
1894 static struct sysdev_class ioapic_sysdev_class = {
1895 .name = "ioapic",
1896 .suspend = ioapic_suspend,
1897 .resume = ioapic_resume,
1898 };
1899
1900 static int __init ioapic_init_sysfs(void)
1901 {
1902 struct sys_device * dev;
1903 int i, size, error;
1904
1905 error = sysdev_class_register(&ioapic_sysdev_class);
1906 if (error)
1907 return error;
1908
1909 for (i = 0; i < nr_ioapics; i++ ) {
1910 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1911 * sizeof(struct IO_APIC_route_entry);
1912 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1913 if (!mp_ioapic_data[i]) {
1914 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1915 continue;
1916 }
1917 dev = &mp_ioapic_data[i]->dev;
1918 dev->id = i;
1919 dev->cls = &ioapic_sysdev_class;
1920 error = sysdev_register(dev);
1921 if (error) {
1922 kfree(mp_ioapic_data[i]);
1923 mp_ioapic_data[i] = NULL;
1924 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1925 continue;
1926 }
1927 }
1928
1929 return 0;
1930 }
1931
1932 device_initcall(ioapic_init_sysfs);
1933
1934 /*
1935 * Dynamic irq allocate and deallocation
1936 */
1937 int create_irq(void)
1938 {
1939 /* Allocate an unused irq */
1940 int irq;
1941 int new;
1942 unsigned long flags;
1943
1944 irq = -ENOSPC;
1945 spin_lock_irqsave(&vector_lock, flags);
1946 for (new = (NR_IRQS - 1); new >= 0; new--) {
1947 if (platform_legacy_irq(new))
1948 continue;
1949 if (irq_cfg[new].vector != 0)
1950 continue;
1951 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1952 irq = new;
1953 break;
1954 }
1955 spin_unlock_irqrestore(&vector_lock, flags);
1956
1957 if (irq >= 0) {
1958 dynamic_irq_init(irq);
1959 }
1960 return irq;
1961 }
1962
1963 void destroy_irq(unsigned int irq)
1964 {
1965 unsigned long flags;
1966
1967 dynamic_irq_cleanup(irq);
1968
1969 spin_lock_irqsave(&vector_lock, flags);
1970 __clear_irq_vector(irq);
1971 spin_unlock_irqrestore(&vector_lock, flags);
1972 }
1973
1974 /*
1975 * MSI message composition
1976 */
1977 #ifdef CONFIG_PCI_MSI
1978 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1979 {
1980 struct irq_cfg *cfg = irq_cfg + irq;
1981 int err;
1982 unsigned dest;
1983 cpumask_t tmp;
1984
1985 tmp = TARGET_CPUS;
1986 err = assign_irq_vector(irq, tmp);
1987 if (!err) {
1988 cpus_and(tmp, cfg->domain, tmp);
1989 dest = cpu_mask_to_apicid(tmp);
1990
1991 msg->address_hi = MSI_ADDR_BASE_HI;
1992 msg->address_lo =
1993 MSI_ADDR_BASE_LO |
1994 ((INT_DEST_MODE == 0) ?
1995 MSI_ADDR_DEST_MODE_PHYSICAL:
1996 MSI_ADDR_DEST_MODE_LOGICAL) |
1997 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1998 MSI_ADDR_REDIRECTION_CPU:
1999 MSI_ADDR_REDIRECTION_LOWPRI) |
2000 MSI_ADDR_DEST_ID(dest);
2001
2002 msg->data =
2003 MSI_DATA_TRIGGER_EDGE |
2004 MSI_DATA_LEVEL_ASSERT |
2005 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2006 MSI_DATA_DELIVERY_FIXED:
2007 MSI_DATA_DELIVERY_LOWPRI) |
2008 MSI_DATA_VECTOR(cfg->vector);
2009 }
2010 return err;
2011 }
2012
2013 #ifdef CONFIG_SMP
2014 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2015 {
2016 struct irq_cfg *cfg = irq_cfg + irq;
2017 struct msi_msg msg;
2018 unsigned int dest;
2019 cpumask_t tmp;
2020
2021 cpus_and(tmp, mask, cpu_online_map);
2022 if (cpus_empty(tmp))
2023 return;
2024
2025 if (assign_irq_vector(irq, mask))
2026 return;
2027
2028 cpus_and(tmp, cfg->domain, mask);
2029 dest = cpu_mask_to_apicid(tmp);
2030
2031 read_msi_msg(irq, &msg);
2032
2033 msg.data &= ~MSI_DATA_VECTOR_MASK;
2034 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2035 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2036 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2037
2038 write_msi_msg(irq, &msg);
2039 irq_desc[irq].affinity = mask;
2040 }
2041 #endif /* CONFIG_SMP */
2042
2043 /*
2044 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2045 * which implement the MSI or MSI-X Capability Structure.
2046 */
2047 static struct irq_chip msi_chip = {
2048 .name = "PCI-MSI",
2049 .unmask = unmask_msi_irq,
2050 .mask = mask_msi_irq,
2051 .ack = ack_apic_edge,
2052 #ifdef CONFIG_SMP
2053 .set_affinity = set_msi_irq_affinity,
2054 #endif
2055 .retrigger = ioapic_retrigger_irq,
2056 };
2057
2058 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2059 {
2060 struct msi_msg msg;
2061 int irq, ret;
2062 irq = create_irq();
2063 if (irq < 0)
2064 return irq;
2065
2066 ret = msi_compose_msg(dev, irq, &msg);
2067 if (ret < 0) {
2068 destroy_irq(irq);
2069 return ret;
2070 }
2071
2072 set_irq_msi(irq, desc);
2073 write_msi_msg(irq, &msg);
2074
2075 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2076
2077 return 0;
2078 }
2079
2080 void arch_teardown_msi_irq(unsigned int irq)
2081 {
2082 destroy_irq(irq);
2083 }
2084
2085 #ifdef CONFIG_DMAR
2086 #ifdef CONFIG_SMP
2087 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2088 {
2089 struct irq_cfg *cfg = irq_cfg + irq;
2090 struct msi_msg msg;
2091 unsigned int dest;
2092 cpumask_t tmp;
2093
2094 cpus_and(tmp, mask, cpu_online_map);
2095 if (cpus_empty(tmp))
2096 return;
2097
2098 if (assign_irq_vector(irq, mask))
2099 return;
2100
2101 cpus_and(tmp, cfg->domain, mask);
2102 dest = cpu_mask_to_apicid(tmp);
2103
2104 dmar_msi_read(irq, &msg);
2105
2106 msg.data &= ~MSI_DATA_VECTOR_MASK;
2107 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2108 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2109 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2110
2111 dmar_msi_write(irq, &msg);
2112 irq_desc[irq].affinity = mask;
2113 }
2114 #endif /* CONFIG_SMP */
2115
2116 struct irq_chip dmar_msi_type = {
2117 .name = "DMAR_MSI",
2118 .unmask = dmar_msi_unmask,
2119 .mask = dmar_msi_mask,
2120 .ack = ack_apic_edge,
2121 #ifdef CONFIG_SMP
2122 .set_affinity = dmar_msi_set_affinity,
2123 #endif
2124 .retrigger = ioapic_retrigger_irq,
2125 };
2126
2127 int arch_setup_dmar_msi(unsigned int irq)
2128 {
2129 int ret;
2130 struct msi_msg msg;
2131
2132 ret = msi_compose_msg(NULL, irq, &msg);
2133 if (ret < 0)
2134 return ret;
2135 dmar_msi_write(irq, &msg);
2136 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2137 "edge");
2138 return 0;
2139 }
2140 #endif
2141
2142 #endif /* CONFIG_PCI_MSI */
2143 /*
2144 * Hypertransport interrupt support
2145 */
2146 #ifdef CONFIG_HT_IRQ
2147
2148 #ifdef CONFIG_SMP
2149
2150 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2151 {
2152 struct ht_irq_msg msg;
2153 fetch_ht_irq_msg(irq, &msg);
2154
2155 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2156 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2157
2158 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2159 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2160
2161 write_ht_irq_msg(irq, &msg);
2162 }
2163
2164 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2165 {
2166 struct irq_cfg *cfg = irq_cfg + irq;
2167 unsigned int dest;
2168 cpumask_t tmp;
2169
2170 cpus_and(tmp, mask, cpu_online_map);
2171 if (cpus_empty(tmp))
2172 return;
2173
2174 if (assign_irq_vector(irq, mask))
2175 return;
2176
2177 cpus_and(tmp, cfg->domain, mask);
2178 dest = cpu_mask_to_apicid(tmp);
2179
2180 target_ht_irq(irq, dest, cfg->vector);
2181 irq_desc[irq].affinity = mask;
2182 }
2183 #endif
2184
2185 static struct irq_chip ht_irq_chip = {
2186 .name = "PCI-HT",
2187 .mask = mask_ht_irq,
2188 .unmask = unmask_ht_irq,
2189 .ack = ack_apic_edge,
2190 #ifdef CONFIG_SMP
2191 .set_affinity = set_ht_irq_affinity,
2192 #endif
2193 .retrigger = ioapic_retrigger_irq,
2194 };
2195
2196 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2197 {
2198 struct irq_cfg *cfg = irq_cfg + irq;
2199 int err;
2200 cpumask_t tmp;
2201
2202 tmp = TARGET_CPUS;
2203 err = assign_irq_vector(irq, tmp);
2204 if (!err) {
2205 struct ht_irq_msg msg;
2206 unsigned dest;
2207
2208 cpus_and(tmp, cfg->domain, tmp);
2209 dest = cpu_mask_to_apicid(tmp);
2210
2211 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2212
2213 msg.address_lo =
2214 HT_IRQ_LOW_BASE |
2215 HT_IRQ_LOW_DEST_ID(dest) |
2216 HT_IRQ_LOW_VECTOR(cfg->vector) |
2217 ((INT_DEST_MODE == 0) ?
2218 HT_IRQ_LOW_DM_PHYSICAL :
2219 HT_IRQ_LOW_DM_LOGICAL) |
2220 HT_IRQ_LOW_RQEOI_EDGE |
2221 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2222 HT_IRQ_LOW_MT_FIXED :
2223 HT_IRQ_LOW_MT_ARBITRATED) |
2224 HT_IRQ_LOW_IRQ_MASKED;
2225
2226 write_ht_irq_msg(irq, &msg);
2227
2228 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2229 handle_edge_irq, "edge");
2230 }
2231 return err;
2232 }
2233 #endif /* CONFIG_HT_IRQ */
2234
2235 /* --------------------------------------------------------------------------
2236 ACPI-based IOAPIC Configuration
2237 -------------------------------------------------------------------------- */
2238
2239 #ifdef CONFIG_ACPI
2240
2241 #define IO_APIC_MAX_ID 0xFE
2242
2243 int __init io_apic_get_redir_entries (int ioapic)
2244 {
2245 union IO_APIC_reg_01 reg_01;
2246 unsigned long flags;
2247
2248 spin_lock_irqsave(&ioapic_lock, flags);
2249 reg_01.raw = io_apic_read(ioapic, 1);
2250 spin_unlock_irqrestore(&ioapic_lock, flags);
2251
2252 return reg_01.bits.entries;
2253 }
2254
2255
2256 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2257 {
2258 if (!IO_APIC_IRQ(irq)) {
2259 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2260 ioapic);
2261 return -EINVAL;
2262 }
2263
2264 /*
2265 * IRQs < 16 are already in the irq_2_pin[] map
2266 */
2267 if (irq >= 16)
2268 add_pin_to_irq(irq, ioapic, pin);
2269
2270 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2271
2272 return 0;
2273 }
2274
2275
2276 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2277 {
2278 int i;
2279
2280 if (skip_ioapic_setup)
2281 return -1;
2282
2283 for (i = 0; i < mp_irq_entries; i++)
2284 if (mp_irqs[i].mp_irqtype == mp_INT &&
2285 mp_irqs[i].mp_srcbusirq == bus_irq)
2286 break;
2287 if (i >= mp_irq_entries)
2288 return -1;
2289
2290 *trigger = irq_trigger(i);
2291 *polarity = irq_polarity(i);
2292 return 0;
2293 }
2294
2295 #endif /* CONFIG_ACPI */
2296
2297 /*
2298 * This function currently is only a helper for the i386 smp boot process where
2299 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2300 * so mask in all cases should simply be TARGET_CPUS
2301 */
2302 #ifdef CONFIG_SMP
2303 void __init setup_ioapic_dest(void)
2304 {
2305 int pin, ioapic, irq, irq_entry;
2306
2307 if (skip_ioapic_setup == 1)
2308 return;
2309
2310 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2311 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2312 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2313 if (irq_entry == -1)
2314 continue;
2315 irq = pin_2_irq(irq_entry, ioapic, pin);
2316
2317 /* setup_IO_APIC_irqs could fail to get vector for some device
2318 * when you have too many devices, because at that time only boot
2319 * cpu is online.
2320 */
2321 if (!irq_cfg[irq].vector)
2322 setup_IO_APIC_irq(ioapic, pin, irq,
2323 irq_trigger(irq_entry),
2324 irq_polarity(irq_entry));
2325 else
2326 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2327 }
2328
2329 }
2330 }
2331 #endif
2332
2333 #define IOAPIC_RESOURCE_NAME_SIZE 11
2334
2335 static struct resource *ioapic_resources;
2336
2337 static struct resource * __init ioapic_setup_resources(void)
2338 {
2339 unsigned long n;
2340 struct resource *res;
2341 char *mem;
2342 int i;
2343
2344 if (nr_ioapics <= 0)
2345 return NULL;
2346
2347 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2348 n *= nr_ioapics;
2349
2350 mem = alloc_bootmem(n);
2351 res = (void *)mem;
2352
2353 if (mem != NULL) {
2354 mem += sizeof(struct resource) * nr_ioapics;
2355
2356 for (i = 0; i < nr_ioapics; i++) {
2357 res[i].name = mem;
2358 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2359 sprintf(mem, "IOAPIC %u", i);
2360 mem += IOAPIC_RESOURCE_NAME_SIZE;
2361 }
2362 }
2363
2364 ioapic_resources = res;
2365
2366 return res;
2367 }
2368
2369 void __init ioapic_init_mappings(void)
2370 {
2371 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2372 struct resource *ioapic_res;
2373 int i;
2374
2375 ioapic_res = ioapic_setup_resources();
2376 for (i = 0; i < nr_ioapics; i++) {
2377 if (smp_found_config) {
2378 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2379 } else {
2380 ioapic_phys = (unsigned long)
2381 alloc_bootmem_pages(PAGE_SIZE);
2382 ioapic_phys = __pa(ioapic_phys);
2383 }
2384 set_fixmap_nocache(idx, ioapic_phys);
2385 apic_printk(APIC_VERBOSE,
2386 "mapped IOAPIC to %016lx (%016lx)\n",
2387 __fix_to_virt(idx), ioapic_phys);
2388 idx++;
2389
2390 if (ioapic_res != NULL) {
2391 ioapic_res->start = ioapic_phys;
2392 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2393 ioapic_res++;
2394 }
2395 }
2396 }
2397
2398 static int __init ioapic_insert_resources(void)
2399 {
2400 int i;
2401 struct resource *r = ioapic_resources;
2402
2403 if (!r) {
2404 printk(KERN_ERR
2405 "IO APIC resources could be not be allocated.\n");
2406 return -1;
2407 }
2408
2409 for (i = 0; i < nr_ioapics; i++) {
2410 insert_resource(&iomem_resource, r);
2411 r++;
2412 }
2413
2414 return 0;
2415 }
2416
2417 /* Insert the IO APIC resources after PCI initialization has occured to handle
2418 * IO APICS that are mapped in on a BAR in PCI space. */
2419 late_initcall(ioapic_insert_resources);
2420
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