drivers/spi/spi_sh_msiof.c

   1 /*
   2  * SuperH MSIOF SPI Master Interface
   3  *
   4  * Copyright (c) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/completion.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/gpio.h>
  20 #include <linux/bitmap.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <linux/spi/spi.h>
  25 #include <linux/spi/spi_bitbang.h>
  26 #include <linux/spi/sh_msiof.h>
  27
  28 #include <asm/spi.h>
  29 #include <asm/unaligned.h>
  30
  31 struct sh_msiof_spi_priv {
  32         struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
  33         void __iomem *mapbase;
  34         struct clk *clk;
  35         struct platform_device *pdev;
  36         struct sh_msiof_spi_info *info;
  37         struct completion done;
  38         unsigned long flags;
  39         int tx_fifo_size;
  40         int rx_fifo_size;
  41 };
  42
  43 #define TMDR1   0x00
  44 #define TMDR2   0x04
  45 #define TMDR3   0x08
  46 #define RMDR1   0x10
  47 #define RMDR2   0x14
  48 #define RMDR3   0x18
  49 #define TSCR    0x20
  50 #define RSCR    0x22
  51 #define CTR     0x28
  52 #define FCTR    0x30
  53 #define STR     0x40
  54 #define IER     0x44
  55 #define TDR1    0x48
  56 #define TDR2    0x4c
  57 #define TFDR    0x50
  58 #define RDR1    0x58
  59 #define RDR2    0x5c
  60 #define RFDR    0x60
  61
  62 #define CTR_TSCKE (1 << 15)
  63 #define CTR_TFSE  (1 << 14)
  64 #define CTR_TXE   (1 << 9)
  65 #define CTR_RXE   (1 << 8)
  66
  67 #define STR_TEOF  (1 << 23)
  68 #define STR_REOF  (1 << 7)
  69
  70 static unsigned long sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
  71 {
  72         switch (reg_offs) {
  73         case TSCR:
  74         case RSCR:
  75                 return ioread16(p->mapbase + reg_offs);
  76         default:
  77                 return ioread32(p->mapbase + reg_offs);
  78         }
  79 }
  80
  81 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
  82                            unsigned long value)
  83 {
  84         switch (reg_offs) {
  85         case TSCR:
  86         case RSCR:
  87                 iowrite16(value, p->mapbase + reg_offs);
  88                 break;
  89         default:
  90                 iowrite32(value, p->mapbase + reg_offs);
  91                 break;
  92         }
  93 }
  94
  95 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
  96                                     unsigned long clr, unsigned long set)
  97 {
  98         unsigned long mask = clr | set;
  99         unsigned long data;
 100         int k;
 101
 102         data = sh_msiof_read(p, CTR);
 103         data &= ~clr;
 104         data |= set;
 105         sh_msiof_write(p, CTR, data);
 106
 107         for (k = 100; k > 0; k--) {
 108                 if ((sh_msiof_read(p, CTR) & mask) == set)
 109                         break;
 110
 111                 udelay(10);
 112         }
 113
 114         return k > 0 ? 0 : -ETIMEDOUT;
 115 }
 116
 117 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
 118 {
 119         struct sh_msiof_spi_priv *p = data;
 120
 121         /* just disable the interrupt and wake up */
 122         sh_msiof_write(p, IER, 0);
 123         complete(&p->done);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static struct {
 129         unsigned short div;
 130         unsigned short scr;
 131 } const sh_msiof_spi_clk_table[] = {
 132         { 1, 0x0007 },
 133         { 2, 0x0000 },
 134         { 4, 0x0001 },
 135         { 8, 0x0002 },
 136         { 16, 0x0003 },
 137         { 32, 0x0004 },
 138         { 64, 0x1f00 },
 139         { 128, 0x1f01 },
 140         { 256, 0x1f02 },
 141         { 512, 0x1f03 },
 142         { 1024, 0x1f04 },
 143 };
 144
 145 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
 146                                       unsigned long parent_rate,
 147                                       unsigned long spi_hz)
 148 {
 149         unsigned long div = 1024;
 150         size_t k;
 151
 152         if (!WARN_ON(!spi_hz || !parent_rate))
 153                 div = parent_rate / spi_hz;
 154
 155         /* TODO: make more fine grained */
 156
 157         for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
 158                 if (sh_msiof_spi_clk_table[k].div >= div)
 159                         break;
 160         }
 161
 162         k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
 163
 164         sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
 165         sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
 166 }
 167
 168 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
 169                                       int cpol, int cpha,
 170                                       int tx_hi_z, int lsb_first)
 171 {
 172         unsigned long tmp;
 173         int edge;
 174
 175         /*
 176          * CPOL CPHA     TSCKIZ RSCKIZ TEDG REDG
 177          *    0    0         10     10    1    1
 178          *    0    1         10     10    0    0
 179          *    1    0         11     11    0    0
 180          *    1    1         11     11    1    1
 181          */
 182         sh_msiof_write(p, FCTR, 0);
 183         sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
 184         sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
 185
 186         tmp = 0xa0000000;
 187         tmp |= cpol << 30; /* TSCKIZ */
 188         tmp |= cpol << 28; /* RSCKIZ */
 189
 190         edge = cpol ? cpha : !cpha;
 191
 192         tmp |= edge << 27; /* TEDG */
 193         tmp |= edge << 26; /* REDG */
 194         tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
 195         sh_msiof_write(p, CTR, tmp);
 196 }
 197
 198 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
 199                                        const void *tx_buf, void *rx_buf,
 200                                        int bits, int words)
 201 {
 202         unsigned long dr2;
 203
 204         dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
 205
 206         if (tx_buf)
 207                 sh_msiof_write(p, TMDR2, dr2);
 208         else
 209                 sh_msiof_write(p, TMDR2, dr2 | 1);
 210
 211         if (rx_buf)
 212                 sh_msiof_write(p, RMDR2, dr2);
 213
 214         sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
 215 }
 216
 217 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
 218 {
 219         sh_msiof_write(p, STR, sh_msiof_read(p, STR));
 220 }
 221
 222 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
 223                                       const void *tx_buf, int words, int fs)
 224 {
 225         const unsigned char *buf_8 = tx_buf;
 226         int k;
 227
 228         for (k = 0; k < words; k++)
 229                 sh_msiof_write(p, TFDR, buf_8[k] << fs);
 230 }
 231
 232 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
 233                                        const void *tx_buf, int words, int fs)
 234 {
 235         const unsigned short *buf_16 = tx_buf;
 236         int k;
 237
 238         for (k = 0; k < words; k++)
 239                 sh_msiof_write(p, TFDR, buf_16[k] << fs);
 240 }
 241
 242 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
 243                                         const void *tx_buf, int words, int fs)
 244 {
 245         const unsigned short *buf_16 = tx_buf;
 246         int k;
 247
 248         for (k = 0; k < words; k++)
 249                 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
 250 }
 251
 252 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
 253                                        const void *tx_buf, int words, int fs)
 254 {
 255         const unsigned int *buf_32 = tx_buf;
 256         int k;
 257
 258         for (k = 0; k < words; k++)
 259                 sh_msiof_write(p, TFDR, buf_32[k] << fs);
 260 }
 261
 262 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
 263                                         const void *tx_buf, int words, int fs)
 264 {
 265         const unsigned int *buf_32 = tx_buf;
 266         int k;
 267
 268         for (k = 0; k < words; k++)
 269                 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
 270 }
 271
 272 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
 273                                      void *rx_buf, int words, int fs)
 274 {
 275         unsigned char *buf_8 = rx_buf;
 276         int k;
 277
 278         for (k = 0; k < words; k++)
 279                 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
 280 }
 281
 282 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
 283                                       void *rx_buf, int words, int fs)
 284 {
 285         unsigned short *buf_16 = rx_buf;
 286         int k;
 287
 288         for (k = 0; k < words; k++)
 289                 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
 290 }
 291
 292 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
 293                                        void *rx_buf, int words, int fs)
 294 {
 295         unsigned short *buf_16 = rx_buf;
 296         int k;
 297
 298         for (k = 0; k < words; k++)
 299                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
 300 }
 301
 302 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
 303                                       void *rx_buf, int words, int fs)
 304 {
 305         unsigned int *buf_32 = rx_buf;
 306         int k;
 307
 308         for (k = 0; k < words; k++)
 309                 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
 310 }
 311
 312 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
 313                                        void *rx_buf, int words, int fs)
 314 {
 315         unsigned int *buf_32 = rx_buf;
 316         int k;
 317
 318         for (k = 0; k < words; k++)
 319                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
 320 }
 321
 322 static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
 323 {
 324         int bits;
 325
 326         bits = t ? t->bits_per_word : 0;
 327         bits = bits ? bits : spi->bits_per_word;
 328         return bits;
 329 }
 330
 331 static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
 332                                      struct spi_transfer *t)
 333 {
 334         unsigned long hz;
 335
 336         hz = t ? t->speed_hz : 0;
 337         hz = hz ? hz : spi->max_speed_hz;
 338         return hz;
 339 }
 340
 341 static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
 342                                        struct spi_transfer *t)
 343 {
 344         int bits;
 345
 346         /* noting to check hz values against since parent clock is disabled */
 347
 348         bits = sh_msiof_spi_bits(spi, t);
 349         if (bits < 8)
 350                 return -EINVAL;
 351         if (bits > 32)
 352                 return -EINVAL;
 353
 354         return spi_bitbang_setup_transfer(spi, t);
 355 }
 356
 357 static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
 358 {
 359         struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
 360         int value;
 361
 362         /* chip select is active low unless SPI_CS_HIGH is set */
 363         if (spi->mode & SPI_CS_HIGH)
 364                 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
 365         else
 366                 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
 367
 368         if (is_on == BITBANG_CS_ACTIVE) {
 369                 if (!test_and_set_bit(0, &p->flags)) {
 370                         pm_runtime_get_sync(&p->pdev->dev);
 371                         clk_enable(p->clk);
 372                 }
 373
 374                 /* Configure pins before asserting CS */
 375                 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
 376                                           !!(spi->mode & SPI_CPHA),
 377                                           !!(spi->mode & SPI_3WIRE),
 378                                           !!(spi->mode & SPI_LSB_FIRST));
 379         }
 380
 381         /* use spi->controller data for CS (same strategy as spi_gpio) */
 382         gpio_set_value((unsigned)spi->controller_data, value);
 383
 384         if (is_on == BITBANG_CS_INACTIVE) {
 385                 if (test_and_clear_bit(0, &p->flags)) {
 386                         clk_disable(p->clk);
 387                         pm_runtime_put(&p->pdev->dev);
 388                 }
 389         }
 390 }
 391
 392 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
 393                                   void (*tx_fifo)(struct sh_msiof_spi_priv *,
 394                                                   const void *, int, int),
 395                                   void (*rx_fifo)(struct sh_msiof_spi_priv *,
 396                                                   void *, int, int),
 397                                   const void *tx_buf, void *rx_buf,
 398                                   int words, int bits)
 399 {
 400         int fifo_shift;
 401         int ret;
 402
 403         /* limit maximum word transfer to rx/tx fifo size */
 404         if (tx_buf)
 405                 words = min_t(int, words, p->tx_fifo_size);
 406         if (rx_buf)
 407                 words = min_t(int, words, p->rx_fifo_size);
 408
 409         /* the fifo contents need shifting */
 410         fifo_shift = 32 - bits;
 411
 412         /* setup msiof transfer mode registers */
 413         sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
 414
 415         /* write tx fifo */
 416         if (tx_buf)
 417                 tx_fifo(p, tx_buf, words, fifo_shift);
 418
 419         /* setup clock and rx/tx signals */
 420         ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
 421         if (rx_buf)
 422                 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
 423         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
 424
 425         /* start by setting frame bit */
 426         INIT_COMPLETION(p->done);
 427         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
 428         if (ret) {
 429                 dev_err(&p->pdev->dev, "failed to start hardware\n");
 430                 goto err;
 431         }
 432
 433         /* wait for tx fifo to be emptied / rx fifo to be filled */
 434         wait_for_completion(&p->done);
 435
 436         /* read rx fifo */
 437         if (rx_buf)
 438                 rx_fifo(p, rx_buf, words, fifo_shift);
 439
 440         /* clear status bits */
 441         sh_msiof_reset_str(p);
 442
 443         /* shut down frame, tx/tx and clock signals */
 444         ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
 445         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
 446         if (rx_buf)
 447                 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
 448         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
 449         if (ret) {
 450                 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
 451                 goto err;
 452         }
 453
 454         return words;
 455
 456  err:
 457         sh_msiof_write(p, IER, 0);
 458         return ret;
 459 }
 460
 461 static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 462 {
 463         struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
 464         void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
 465         void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
 466         int bits;
 467         int bytes_per_word;
 468         int bytes_done;
 469         int words;
 470         int n;
 471
 472         bits = sh_msiof_spi_bits(spi, t);
 473
 474         /* setup bytes per word and fifo read/write functions */
 475         if (bits <= 8) {
 476                 bytes_per_word = 1;
 477                 tx_fifo = sh_msiof_spi_write_fifo_8;
 478                 rx_fifo = sh_msiof_spi_read_fifo_8;
 479         } else if (bits <= 16) {
 480                 bytes_per_word = 2;
 481                 if ((unsigned long)t->tx_buf & 0x01)
 482                         tx_fifo = sh_msiof_spi_write_fifo_16u;
 483                 else
 484                         tx_fifo = sh_msiof_spi_write_fifo_16;
 485
 486                 if ((unsigned long)t->rx_buf & 0x01)
 487                         rx_fifo = sh_msiof_spi_read_fifo_16u;
 488                 else
 489                         rx_fifo = sh_msiof_spi_read_fifo_16;
 490         } else {
 491                 bytes_per_word = 4;
 492                 if ((unsigned long)t->tx_buf & 0x03)
 493                         tx_fifo = sh_msiof_spi_write_fifo_32u;
 494                 else
 495                         tx_fifo = sh_msiof_spi_write_fifo_32;
 496
 497                 if ((unsigned long)t->rx_buf & 0x03)
 498                         rx_fifo = sh_msiof_spi_read_fifo_32u;
 499                 else
 500                         rx_fifo = sh_msiof_spi_read_fifo_32;
 501         }
 502
 503         /* setup clocks (clock already enabled in chipselect()) */
 504         sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
 505                                   sh_msiof_spi_hz(spi, t));
 506
 507         /* transfer in fifo sized chunks */
 508         words = t->len / bytes_per_word;
 509         bytes_done = 0;
 510
 511         while (bytes_done < t->len) {
 512                 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
 513                                            t->tx_buf + bytes_done,
 514                                            t->rx_buf + bytes_done,
 515                                            words, bits);
 516                 if (n < 0)
 517                         break;
 518
 519                 bytes_done += n * bytes_per_word;
 520                 words -= n;
 521         }
 522
 523         return bytes_done;
 524 }
 525
 526 static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
 527                                   u32 word, u8 bits)
 528 {
 529         BUG(); /* unused but needed by bitbang code */
 530         return 0;
 531 }
 532
 533 static int sh_msiof_spi_probe(struct platform_device *pdev)
 534 {
 535         struct resource *r;
 536         struct spi_master *master;
 537         struct sh_msiof_spi_priv *p;
 538         char clk_name[16];
 539         int i;
 540         int ret;
 541
 542         master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
 543         if (master == NULL) {
 544                 dev_err(&pdev->dev, "failed to allocate spi master\n");
 545                 ret = -ENOMEM;
 546                 goto err0;
 547         }
 548
 549         p = spi_master_get_devdata(master);
 550
 551         platform_set_drvdata(pdev, p);
 552         p->info = pdev->dev.platform_data;
 553         init_completion(&p->done);
 554
 555         snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id);
 556         p->clk = clk_get(&pdev->dev, clk_name);
 557         if (IS_ERR(p->clk)) {
 558                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 559                 ret = PTR_ERR(p->clk);
 560                 goto err1;
 561         }
 562
 563         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 564         i = platform_get_irq(pdev, 0);
 565         if (!r || i < 0) {
 566                 dev_err(&pdev->dev, "cannot get platform resources\n");
 567                 ret = -ENOENT;
 568                 goto err2;
 569         }
 570         p->mapbase = ioremap_nocache(r->start, resource_size(r));
 571         if (!p->mapbase) {
 572                 dev_err(&pdev->dev, "unable to ioremap\n");
 573                 ret = -ENXIO;
 574                 goto err2;
 575         }
 576
 577         ret = request_irq(i, sh_msiof_spi_irq, IRQF_DISABLED,
 578                           dev_name(&pdev->dev), p);
 579         if (ret) {
 580                 dev_err(&pdev->dev, "unable to request irq\n");
 581                 goto err3;
 582         }
 583
 584         p->pdev = pdev;
 585         pm_runtime_enable(&pdev->dev);
 586
 587         /* The standard version of MSIOF use 64 word FIFOs */
 588         p->tx_fifo_size = 64;
 589         p->rx_fifo_size = 64;
 590
 591         /* Platform data may override FIFO sizes */
 592         if (p->info->tx_fifo_override)
 593                 p->tx_fifo_size = p->info->tx_fifo_override;
 594         if (p->info->rx_fifo_override)
 595                 p->rx_fifo_size = p->info->rx_fifo_override;
 596
 597         /* init master and bitbang code */
 598         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 599         master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
 600         master->flags = 0;
 601         master->bus_num = pdev->id;
 602         master->num_chipselect = p->info->num_chipselect;
 603         master->setup = spi_bitbang_setup;
 604         master->cleanup = spi_bitbang_cleanup;
 605
 606         p->bitbang.master = master;
 607         p->bitbang.chipselect = sh_msiof_spi_chipselect;
 608         p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
 609         p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
 610         p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
 611         p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
 612         p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
 613         p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
 614
 615         ret = spi_bitbang_start(&p->bitbang);
 616         if (ret == 0)
 617                 return 0;
 618
 619         pm_runtime_disable(&pdev->dev);
 620  err3:
 621         iounmap(p->mapbase);
 622  err2:
 623         clk_put(p->clk);
 624  err1:
 625         spi_master_put(master);
 626  err0:
 627         return ret;
 628 }
 629
 630 static int sh_msiof_spi_remove(struct platform_device *pdev)
 631 {
 632         struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
 633         int ret;
 634
 635         ret = spi_bitbang_stop(&p->bitbang);
 636         if (!ret) {
 637                 pm_runtime_disable(&pdev->dev);
 638                 free_irq(platform_get_irq(pdev, 0), sh_msiof_spi_irq);
 639                 iounmap(p->mapbase);
 640                 clk_put(p->clk);
 641                 spi_master_put(p->bitbang.master);
 642         }
 643         return ret;
 644 }
 645
 646 static int sh_msiof_spi_runtime_nop(struct device *dev)
 647 {
 648         /* Runtime PM callback shared between ->runtime_suspend()
 649          * and ->runtime_resume(). Simply returns success.
 650          *
 651          * This driver re-initializes all registers after
 652          * pm_runtime_get_sync() anyway so there is no need
 653          * to save and restore registers here.
 654          */
 655         return 0;
 656 }
 657
 658 static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = {
 659         .runtime_suspend = sh_msiof_spi_runtime_nop,
 660         .runtime_resume = sh_msiof_spi_runtime_nop,
 661 };
 662
 663 static struct platform_driver sh_msiof_spi_drv = {
 664         .probe          = sh_msiof_spi_probe,
 665         .remove         = sh_msiof_spi_remove,
 666         .driver         = {
 667                 .name           = "spi_sh_msiof",
 668                 .owner          = THIS_MODULE,
 669                 .pm             = &sh_msiof_spi_dev_pm_ops,
 670         },
 671 };
 672
 673 static int __init sh_msiof_spi_init(void)
 674 {
 675         return platform_driver_register(&sh_msiof_spi_drv);
 676 }
 677 module_init(sh_msiof_spi_init);
 678
 679 static void __exit sh_msiof_spi_exit(void)
 680 {
 681         platform_driver_unregister(&sh_msiof_spi_drv);
 682 }
 683 module_exit(sh_msiof_spi_exit);
 684
 685 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
 686 MODULE_AUTHOR("Magnus Damm");
 687 MODULE_LICENSE("GPL v2");
 688 MODULE_ALIAS("platform:spi_sh_msiof");