drivers/staging/agnx/pci.c

   1 /**
   2  * Airgo MIMO wireless driver
   3  *
   4  * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
   5
   6  * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
   7  * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18
  19 #include "agnx.h"
  20 #include "debug.h"
  21 #include "xmit.h"
  22 #include "phy.h"
  23
  24 MODULE_AUTHOR("Li YanBo <dreamfly281@gmail.com>");
  25 MODULE_DESCRIPTION("Airgo MIMO PCI wireless driver");
  26 MODULE_LICENSE("GPL");
  27
  28 static struct pci_device_id agnx_pci_id_tbl[] __devinitdata = {
  29         { PCI_DEVICE(0x17cb, 0x0001) }, /* Beklin F5d8010, Netgear WGM511 etc */
  30         { PCI_DEVICE(0x17cb, 0x0002) }, /* Netgear Wpnt511 */
  31         { 0 }
  32 };
  33
  34 MODULE_DEVICE_TABLE(pci, agnx_pci_id_tbl);
  35
  36
  37 static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
  38 {
  39         void __iomem *ctl = priv->ctl;
  40         u32 reg;
  41
  42         if (*reason & AGNX_STAT_RX) {
  43                 /* Mark complete RX */
  44                 reg = ioread32(ctl + AGNX_CIR_RXCTL);
  45                 reg |= 0x4;
  46                 iowrite32(reg, ctl + AGNX_CIR_RXCTL);
  47                 /* disable Rx interrupt */
  48         }
  49         if (*reason & AGNX_STAT_TX) {
  50                 reg = ioread32(ctl + AGNX_CIR_TXDCTL);
  51                 if (reg & 0x4) {
  52                         iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
  53                         *reason |= AGNX_STAT_TXD;
  54                 }
  55                 reg = ioread32(ctl + AGNX_CIR_TXMCTL);
  56                 if (reg & 0x4) {
  57                         iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
  58                         *reason |= AGNX_STAT_TXM;
  59                 }
  60         }
  61 /*      if (*reason & AGNX_STAT_X) {
  62                 reg = ioread32(ctl + AGNX_INT_STAT);
  63                 iowrite32(reg, ctl + AGNX_INT_STAT);
  64                 /* FIXME reinit interrupt mask *\/
  65                 reg = 0xc390bf9 & ~IRQ_TX_BEACON;
  66                 reg &= ~IRQ_TX_DISABLE;
  67                 iowrite32(reg, ctl + AGNX_INT_MASK);
  68                 iowrite32(0x800, ctl + AGNX_CIR_BLKCTL);
  69         } */
  70 } /* agnx_interrupt_ack */
  71
  72 static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
  73 {
  74         struct ieee80211_hw *dev = dev_id;
  75         struct agnx_priv *priv = dev->priv;
  76         void __iomem *ctl = priv->ctl;
  77         irqreturn_t ret = IRQ_NONE;
  78         u32 irq_reason;
  79
  80         spin_lock(&priv->lock);
  81
  82 /*      printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); */
  83
  84         if (priv->init_status != AGNX_START)
  85                 goto out;
  86
  87         /* FiXME  Here has no lock, Is this will lead to race? */
  88         irq_reason = ioread32(ctl + AGNX_CIR_BLKCTL);
  89         if (!(irq_reason & 0x7))
  90                 goto out;
  91
  92         ret = IRQ_HANDLED;
  93         priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
  94
  95 /*      printk(PFX "Interrupt reason is 0x%x\n", irq_reason); */
  96         /* Make sure the txm and txd flags don't conflict with other unknown
  97            interrupt flag, maybe is not necessary */
  98         irq_reason &= 0xF;
  99
 100         disable_rx_interrupt(priv);
 101         /* TODO Make sure the card finished initialized */
 102         agnx_interrupt_ack(priv, &irq_reason);
 103
 104         if (irq_reason & AGNX_STAT_RX)
 105                 handle_rx_irq(priv);
 106         if (irq_reason & AGNX_STAT_TXD)
 107                 handle_txd_irq(priv);
 108         if (irq_reason & AGNX_STAT_TXM)
 109                 handle_txm_irq(priv);
 110         if (irq_reason & AGNX_STAT_X)
 111                 handle_other_irq(priv);
 112
 113         enable_rx_interrupt(priv);
 114 out:
 115         spin_unlock(&priv->lock);
 116         return ret;
 117 } /* agnx_interrupt_handler */
 118
 119
 120 /* FIXME */
 121 static int agnx_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 122 {
 123         AGNX_TRACE;
 124         return _agnx_tx(dev->priv, skb);
 125 } /* agnx_tx */
 126
 127
 128 static int agnx_get_mac_address(struct agnx_priv *priv)
 129 {
 130         void __iomem *ctl = priv->ctl;
 131         u32 reg;
 132         AGNX_TRACE;
 133
 134         /* Attention! directly read the MAC or other date from EEPROM will
 135          lead to cardbus(WGM511) lock up when write to PM PLL register */
 136         reg = agnx_read32(ctl, 0x3544);
 137         udelay(40);
 138         reg = agnx_read32(ctl, 0x354c);
 139         udelay(50);
 140         /* Get the mac address */
 141         reg = agnx_read32(ctl, 0x3544);
 142         udelay(40);
 143
 144         /* HACK */
 145         reg = cpu_to_le32(reg);
 146         priv->mac_addr[0] = ((u8 *)&reg)[2];
 147         priv->mac_addr[1] = ((u8 *)&reg)[3];
 148         reg = agnx_read32(ctl, 0x3548);
 149         udelay(50);
 150         *((u32 *)(priv->mac_addr + 2)) = cpu_to_le32(reg);
 151
 152         if (!is_valid_ether_addr(priv->mac_addr)) {
 153                 printk(KERN_WARNING PFX "read mac %pM\n", priv->mac_addr);
 154                 printk(KERN_WARNING PFX "Invalid hwaddr! Using random hwaddr\n");
 155                 random_ether_addr(priv->mac_addr);
 156         }
 157
 158         return 0;
 159 } /* agnx_get_mac_address */
 160
 161 static int agnx_alloc_rings(struct agnx_priv *priv)
 162 {
 163         unsigned int len;
 164         AGNX_TRACE;
 165
 166         /* Allocate RX/TXM/TXD rings info */
 167         priv->rx.size = AGNX_RX_RING_SIZE;
 168         priv->txm.size = AGNX_TXM_RING_SIZE;
 169         priv->txd.size = AGNX_TXD_RING_SIZE;
 170
 171         len = priv->rx.size + priv->txm.size + priv->txd.size;
 172
 173 /*      priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); */
 174         priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
 175         if (!priv->rx.info)
 176                 return -ENOMEM;
 177         priv->txm.info = priv->rx.info + priv->rx.size;
 178         priv->txd.info = priv->txm.info + priv->txm.size;
 179
 180         /* Allocate RX/TXM/TXD descriptors */
 181         priv->rx.desc = pci_alloc_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
 182                                              &priv->rx.dma);
 183         if (!priv->rx.desc) {
 184                 kfree(priv->rx.info);
 185                 return -ENOMEM;
 186         }
 187
 188         priv->txm.desc = priv->rx.desc + priv->rx.size;
 189         priv->txm.dma = priv->rx.dma + sizeof(struct agnx_desc) * priv->rx.size;
 190         priv->txd.desc = priv->txm.desc + priv->txm.size;
 191         priv->txd.dma = priv->txm.dma + sizeof(struct agnx_desc) * priv->txm.size;
 192
 193         return 0;
 194 } /* agnx_alloc_rings */
 195
 196 static void rings_free(struct agnx_priv *priv)
 197 {
 198         unsigned int len = priv->rx.size + priv->txm.size + priv->txd.size;
 199         unsigned long flags;
 200         AGNX_TRACE;
 201
 202         spin_lock_irqsave(&priv->lock, flags);
 203         kfree(priv->rx.info);
 204         pci_free_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
 205                             priv->rx.desc, priv->rx.dma);
 206         spin_unlock_irqrestore(&priv->lock, flags);
 207 }
 208
 209 #if 0
 210 static void agnx_periodic_work_handler(struct work_struct *work)
 211 {
 212         struct agnx_priv *priv = container_of(work, struct agnx_priv, periodic_work.work);
 213 /*      unsigned long flags; */
 214         unsigned long delay;
 215
 216         /* fixme: using mutex?? */
 217 /*      spin_lock_irqsave(&priv->lock, flags); */
 218
 219         /* TODO Recalibrate*/
 220 /*      calibrate_oscillator(priv); */
 221 /*      antenna_calibrate(priv); */
 222 /*      agnx_send_packet(priv, 997); /
 223         /* FIXME */
 224 /*      if (debug == 3) */
 225 /*                 delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
 226 /*      else */
 227         delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
 228 /*      delay = round_jiffies(HZ * 15); */
 229
 230         queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
 231
 232 /*      spin_unlock_irqrestore(&priv->lock, flags); */
 233 }
 234 #endif
 235
 236 static int agnx_start(struct ieee80211_hw *dev)
 237 {
 238         struct agnx_priv *priv = dev->priv;
 239         /* unsigned long delay; */
 240         int err = 0;
 241         AGNX_TRACE;
 242
 243         err = agnx_alloc_rings(priv);
 244         if (err) {
 245                 printk(KERN_ERR PFX "Can't alloc RX/TXM/TXD rings\n");
 246                 goto out;
 247         }
 248         err = request_irq(priv->pdev->irq, &agnx_interrupt_handler,
 249                           IRQF_SHARED, "agnx_pci", dev);
 250         if (err) {
 251                 printk(KERN_ERR PFX "Failed to register IRQ handler\n");
 252                 rings_free(priv);
 253                 goto out;
 254         }
 255
 256 /*      mdelay(500); */
 257
 258         might_sleep();
 259         agnx_hw_init(priv);
 260
 261 /*      mdelay(500); */
 262         might_sleep();
 263
 264         priv->init_status = AGNX_START;
 265 /*         INIT_DELAYED_WORK(&priv->periodic_work, agnx_periodic_work_handler); */
 266 /*      delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
 267 /*         queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay); */
 268 out:
 269         return err;
 270 } /* agnx_start */
 271
 272 static void agnx_stop(struct ieee80211_hw *dev)
 273 {
 274         struct agnx_priv *priv = dev->priv;
 275         AGNX_TRACE;
 276
 277         priv->init_status = AGNX_STOP;
 278         /* make sure hardware will not generate irq */
 279         agnx_hw_reset(priv);
 280         free_irq(priv->pdev->irq, dev);
 281         flush_workqueue(priv->hw->workqueue);
 282 /*      cancel_delayed_work_sync(&priv->periodic_work); */
 283         unfill_rings(priv);
 284         rings_free(priv);
 285 }
 286
 287 static int agnx_config(struct ieee80211_hw *dev, u32 changed)
 288 {
 289         struct agnx_priv *priv = dev->priv;
 290         struct ieee80211_conf *conf = &dev->conf;
 291         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
 292         AGNX_TRACE;
 293
 294         spin_lock(&priv->lock);
 295         /* FIXME need priv lock? */
 296         if (channel != priv->channel) {
 297                 priv->channel = channel;
 298                 agnx_set_channel(priv, priv->channel);
 299         }
 300
 301         spin_unlock(&priv->lock);
 302         return 0;
 303 }
 304
 305 static void agnx_bss_info_changed(struct ieee80211_hw *dev,
 306                                   struct ieee80211_vif *vif,
 307                                   struct ieee80211_bss_conf *conf,
 308                                   u32 changed)
 309 {
 310         struct agnx_priv *priv = dev->priv;
 311         void __iomem *ctl = priv->ctl;
 312         AGNX_TRACE;
 313
 314         if (!(changed & BSS_CHANGED_BSSID))
 315                 return;
 316
 317         spin_lock(&priv->lock);
 318
 319         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
 320                 agnx_set_bssid(priv, conf->bssid);
 321                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
 322                 hash_write(priv, conf->bssid, BSSID_STAID);
 323                 sta_init(priv, BSSID_STAID);
 324                 /* FIXME needed? */
 325                 sta_power_init(priv, BSSID_STAID);
 326                 agnx_write32(ctl, AGNX_BM_MTSM, 0xff & ~0x1);
 327         }
 328         spin_unlock(&priv->lock);
 329 } /* agnx_bss_info_changed */
 330
 331
 332 static void agnx_configure_filter(struct ieee80211_hw *dev,
 333                                   unsigned int changed_flags,
 334                                   unsigned int *total_flags,
 335                                   int mc_count, struct dev_mc_list *mclist)
 336 {
 337         unsigned int new_flags = 0;
 338
 339         *total_flags = new_flags;
 340         /* TODO */
 341 }
 342
 343 static int agnx_add_interface(struct ieee80211_hw *dev,
 344                               struct ieee80211_if_init_conf *conf)
 345 {
 346         struct agnx_priv *priv = dev->priv;
 347         AGNX_TRACE;
 348
 349         spin_lock(&priv->lock);
 350         /* FIXME */
 351         if (priv->mode != NL80211_IFTYPE_MONITOR)
 352                 return -EOPNOTSUPP;
 353
 354         switch (conf->type) {
 355         case NL80211_IFTYPE_STATION:
 356                 priv->mode = conf->type;
 357                 break;
 358         default:
 359                 return -EOPNOTSUPP;
 360         }
 361
 362         spin_unlock(&priv->lock);
 363
 364         return 0;
 365 }
 366
 367 static void agnx_remove_interface(struct ieee80211_hw *dev,
 368                                   struct ieee80211_if_init_conf *conf)
 369 {
 370         struct agnx_priv *priv = dev->priv;
 371         AGNX_TRACE;
 372
 373         /* TODO */
 374         priv->mode = NL80211_IFTYPE_MONITOR;
 375 }
 376
 377 static int agnx_get_stats(struct ieee80211_hw *dev,
 378                           struct ieee80211_low_level_stats *stats)
 379 {
 380         struct agnx_priv *priv = dev->priv;
 381         AGNX_TRACE;
 382         spin_lock(&priv->lock);
 383         /* TODO !! */
 384         memcpy(stats, &priv->stats, sizeof(*stats));
 385         spin_unlock(&priv->lock);
 386
 387         return 0;
 388 }
 389
 390 static u64 agnx_get_tsft(struct ieee80211_hw *dev)
 391 {
 392         void __iomem *ctl = ((struct agnx_priv *)dev->priv)->ctl;
 393         u32 tsftl;
 394         u64 tsft;
 395         AGNX_TRACE;
 396
 397         /* FIXME */
 398         tsftl = ioread32(ctl + AGNX_TXM_TIMESTAMPLO);
 399         tsft = ioread32(ctl + AGNX_TXM_TIMESTAMPHI);
 400         tsft <<= 32;
 401         tsft |= tsftl;
 402
 403         return tsft;
 404 }
 405
 406 static int agnx_get_tx_stats(struct ieee80211_hw *dev,
 407                              struct ieee80211_tx_queue_stats *stats)
 408 {
 409         struct agnx_priv *priv = dev->priv;
 410         AGNX_TRACE;
 411
 412         /* FIXME now we just using txd queue, but should using txm queue too */
 413         stats[0].len = (priv->txd.idx - priv->txd.idx_sent) / 2;
 414         stats[0].limit = priv->txd.size - 2;
 415         stats[0].count = priv->txd.idx / 2;
 416
 417         return 0;
 418 }
 419
 420 static struct ieee80211_ops agnx_ops = {
 421         .tx                     = agnx_tx,
 422         .start                  = agnx_start,
 423         .stop                   = agnx_stop,
 424         .add_interface          = agnx_add_interface,
 425         .remove_interface       = agnx_remove_interface,
 426         .config                 = agnx_config,
 427         .bss_info_changed       = agnx_bss_info_changed,
 428         .configure_filter       = agnx_configure_filter,
 429         .get_stats              = agnx_get_stats,
 430         .get_tx_stats           = agnx_get_tx_stats,
 431         .get_tsf                = agnx_get_tsft
 432 };
 433
 434 static void __devexit agnx_pci_remove(struct pci_dev *pdev)
 435 {
 436         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 437         struct agnx_priv *priv;
 438         AGNX_TRACE;
 439
 440         if (!dev)
 441                 return;
 442         priv = dev->priv;
 443         ieee80211_unregister_hw(dev);
 444         pci_iounmap(pdev, priv->ctl);
 445         pci_iounmap(pdev, priv->data);
 446         pci_release_regions(pdev);
 447         pci_disable_device(pdev);
 448
 449         ieee80211_free_hw(dev);
 450 }
 451
 452 static int __devinit agnx_pci_probe(struct pci_dev *pdev,
 453                                     const struct pci_device_id *id)
 454 {
 455         struct ieee80211_hw *dev;
 456         struct agnx_priv *priv;
 457         int err;
 458
 459         err = pci_enable_device(pdev);
 460         if (err) {
 461                 dev_err(&pdev->dev, "can't enable pci device\n");
 462                 return err;
 463         }
 464
 465         err = pci_request_regions(pdev, "agnx-pci");
 466         if (err) {
 467                 dev_err(&pdev->dev, "can't reserve PCI resources\n");
 468                 return err;
 469         }
 470
 471         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
 472             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
 473                 dev_err(&pdev->dev, "no suitable DMA available\n");
 474                 err = -EIO;
 475                 goto err_free_reg;
 476         }
 477
 478         pci_set_master(pdev);
 479
 480         dev = ieee80211_alloc_hw(sizeof(*priv), &agnx_ops);
 481         if (!dev) {
 482                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 483                 err = -ENOMEM;
 484                 goto err_free_reg;
 485         }
 486         priv = dev->priv;
 487         memset(priv, 0, sizeof(*priv));
 488         priv->mode = NL80211_IFTYPE_MONITOR;
 489         priv->pdev = pdev;
 490         priv->hw = dev;
 491         spin_lock_init(&priv->lock);
 492         priv->init_status = AGNX_UNINIT;
 493
 494         priv->ctl = pci_iomap(pdev, 0, 0);
 495 /*      dev_dbg(&pdev->dev, "MEM1 mapped address is 0x%p\n", priv->ctl); */
 496         if (!priv->ctl) {
 497                 dev_err(&pdev->dev, "can't map device memory\n");
 498                 err = -ENOMEM;
 499                 goto err_free_dev;
 500         }
 501         priv->data = pci_iomap(pdev, 1, 0);
 502         if (!priv->data) {
 503                 dev_err(&pdev->dev, "can't map device memory\n");
 504                 err = -ENOMEM;
 505                 goto err_iounmap2;
 506         }
 507
 508         pci_read_config_byte(pdev, PCI_REVISION_ID, &priv->revid);
 509
 510         priv->band.channels   = (struct ieee80211_channel *)agnx_channels;
 511         priv->band.n_channels = ARRAY_SIZE(agnx_channels);
 512         priv->band.bitrates   = (struct ieee80211_rate *)agnx_rates_80211g;
 513         priv->band.n_bitrates = ARRAY_SIZE(agnx_rates_80211g);
 514
 515         /* Init ieee802.11 dev  */
 516         SET_IEEE80211_DEV(dev, &pdev->dev);
 517         pci_set_drvdata(pdev, dev);
 518         dev->extra_tx_headroom = sizeof(struct agnx_hdr);
 519
 520         /* FIXME It only include FCS in promious mode but not manage mode */
 521 /*      dev->flags =  IEEE80211_HW_RX_INCLUDES_FCS; */
 522         dev->channel_change_time = 5000;
 523         dev->max_signal = 100;
 524         /* FIXME */
 525         dev->queues = 1;
 526
 527         agnx_get_mac_address(priv);
 528
 529         SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
 530
 531 /*      /\* FIXME *\/ */
 532 /*      for (i = 1; i < NUM_DRIVE_MODES; i++) { */
 533 /*              err = ieee80211_register_hwmode(dev, &priv->modes[i]); */
 534 /*              if (err) { */
 535 /*                      printk(KERN_ERR PFX "Can't register hwmode\n"); */
 536 /*                      goto  err_iounmap; */
 537 /*              } */
 538 /*      } */
 539
 540         priv->channel = 1;
 541         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
 542
 543         err = ieee80211_register_hw(dev);
 544         if (err) {
 545                 dev_err(&pdev->dev, "can't register hardware\n");
 546                 goto err_iounmap;
 547         }
 548
 549         agnx_hw_reset(priv);
 550
 551         dev_info(&pdev->dev, "%s: hwaddr %pM, Rev 0x%02x\n",
 552                 wiphy_name(dev->wiphy),
 553                 dev->wiphy->perm_addr, priv->revid);
 554         return 0;
 555
 556  err_iounmap:
 557         pci_iounmap(pdev, priv->data);
 558
 559  err_iounmap2:
 560         pci_iounmap(pdev, priv->ctl);
 561
 562  err_free_dev:
 563         pci_set_drvdata(pdev, NULL);
 564         ieee80211_free_hw(dev);
 565
 566  err_free_reg:
 567         pci_release_regions(pdev);
 568
 569         pci_disable_device(pdev);
 570         return err;
 571 } /* agnx_pci_probe*/
 572
 573 #ifdef CONFIG_PM
 574
 575 static int agnx_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 576 {
 577         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 578         AGNX_TRACE;
 579
 580         ieee80211_stop_queues(dev);
 581         agnx_stop(dev);
 582
 583         pci_save_state(pdev);
 584         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 585         return 0;
 586 }
 587
 588 static int agnx_pci_resume(struct pci_dev *pdev)
 589 {
 590         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 591         AGNX_TRACE;
 592
 593         pci_set_power_state(pdev, PCI_D0);
 594         pci_restore_state(pdev);
 595
 596         agnx_start(dev);
 597         ieee80211_wake_queues(dev);
 598
 599         return 0;
 600 }
 601
 602 #else
 603
 604 #define agnx_pci_suspend NULL
 605 #define agnx_pci_resume NULL
 606
 607 #endif /* CONFIG_PM */
 608
 609
 610 static struct pci_driver agnx_pci_driver = {
 611         .name           = "agnx-pci",
 612         .id_table       = agnx_pci_id_tbl,
 613         .probe          = agnx_pci_probe,
 614         .remove         = __devexit_p(agnx_pci_remove),
 615         .suspend        = agnx_pci_suspend,
 616         .resume         = agnx_pci_resume,
 617 };
 618
 619 static int __init agnx_pci_init(void)
 620 {
 621         AGNX_TRACE;
 622         return pci_register_driver(&agnx_pci_driver);
 623 }
 624
 625 static void __exit agnx_pci_exit(void)
 626 {
 627         AGNX_TRACE;
 628         pci_unregister_driver(&agnx_pci_driver);
 629 }
 630
 631
 632 module_init(agnx_pci_init);
 633 module_exit(agnx_pci_exit);