arch/arm/mach-davinci/clock.c

   1 /*
   2  * Clock and PLL control for DaVinci devices
   3  *
   4  * Copyright (C) 2006-2007 Texas Instruments.
   5  * Copyright (C) 2008-2009 Deep Root Systems, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/mutex.h>
  20 #include <linux/io.h>
  21 #include <linux/delay.h>
  22
  23 #include <mach/hardware.h>
  24
  25 #include <mach/psc.h>
  26 #include <mach/cputype.h>
  27 #include "clock.h"
  28
  29 static LIST_HEAD(clocks);
  30 static DEFINE_MUTEX(clocks_mutex);
  31 static DEFINE_SPINLOCK(clockfw_lock);
  32
  33 static unsigned psc_domain(struct clk *clk)
  34 {
  35         return (clk->flags & PSC_DSP)
  36                 ? DAVINCI_GPSC_DSPDOMAIN
  37                 : DAVINCI_GPSC_ARMDOMAIN;
  38 }
  39
  40 static void __clk_enable(struct clk *clk)
  41 {
  42         if (clk->parent)
  43                 __clk_enable(clk->parent);
  44         if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
  45                 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
  46 }
  47
  48 static void __clk_disable(struct clk *clk)
  49 {
  50         if (WARN_ON(clk->usecount == 0))
  51                 return;
  52         if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
  53                 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
  54         if (clk->parent)
  55                 __clk_disable(clk->parent);
  56 }
  57
  58 int clk_enable(struct clk *clk)
  59 {
  60         unsigned long flags;
  61
  62         if (clk == NULL || IS_ERR(clk))
  63                 return -EINVAL;
  64
  65         spin_lock_irqsave(&clockfw_lock, flags);
  66         __clk_enable(clk);
  67         spin_unlock_irqrestore(&clockfw_lock, flags);
  68
  69         return 0;
  70 }
  71 EXPORT_SYMBOL(clk_enable);
  72
  73 void clk_disable(struct clk *clk)
  74 {
  75         unsigned long flags;
  76
  77         if (clk == NULL || IS_ERR(clk))
  78                 return;
  79
  80         spin_lock_irqsave(&clockfw_lock, flags);
  81         __clk_disable(clk);
  82         spin_unlock_irqrestore(&clockfw_lock, flags);
  83 }
  84 EXPORT_SYMBOL(clk_disable);
  85
  86 unsigned long clk_get_rate(struct clk *clk)
  87 {
  88         if (clk == NULL || IS_ERR(clk))
  89                 return -EINVAL;
  90
  91         return clk->rate;
  92 }
  93 EXPORT_SYMBOL(clk_get_rate);
  94
  95 long clk_round_rate(struct clk *clk, unsigned long rate)
  96 {
  97         if (clk == NULL || IS_ERR(clk))
  98                 return -EINVAL;
  99
 100         if (clk->round_rate)
 101                 return clk->round_rate(clk, rate);
 102
 103         return clk->rate;
 104 }
 105 EXPORT_SYMBOL(clk_round_rate);
 106
 107 /* Propagate rate to children */
 108 static void propagate_rate(struct clk *root)
 109 {
 110         struct clk *clk;
 111
 112         list_for_each_entry(clk, &root->children, childnode) {
 113                 if (clk->recalc)
 114                         clk->rate = clk->recalc(clk);
 115                 propagate_rate(clk);
 116         }
 117 }
 118
 119 int clk_set_rate(struct clk *clk, unsigned long rate)
 120 {
 121         unsigned long flags;
 122         int ret = -EINVAL;
 123
 124         if (clk == NULL || IS_ERR(clk))
 125                 return ret;
 126
 127         spin_lock_irqsave(&clockfw_lock, flags);
 128         if (clk->set_rate)
 129                 ret = clk->set_rate(clk, rate);
 130         if (ret == 0) {
 131                 if (clk->recalc)
 132                         clk->rate = clk->recalc(clk);
 133                 propagate_rate(clk);
 134         }
 135         spin_unlock_irqrestore(&clockfw_lock, flags);
 136
 137         return ret;
 138 }
 139 EXPORT_SYMBOL(clk_set_rate);
 140
 141 int clk_set_parent(struct clk *clk, struct clk *parent)
 142 {
 143         unsigned long flags;
 144
 145         if (clk == NULL || IS_ERR(clk))
 146                 return -EINVAL;
 147
 148         /* Cannot change parent on enabled clock */
 149         if (WARN_ON(clk->usecount))
 150                 return -EINVAL;
 151
 152         mutex_lock(&clocks_mutex);
 153         clk->parent = parent;
 154         list_del_init(&clk->childnode);
 155         list_add(&clk->childnode, &clk->parent->children);
 156         mutex_unlock(&clocks_mutex);
 157
 158         spin_lock_irqsave(&clockfw_lock, flags);
 159         if (clk->recalc)
 160                 clk->rate = clk->recalc(clk);
 161         propagate_rate(clk);
 162         spin_unlock_irqrestore(&clockfw_lock, flags);
 163
 164         return 0;
 165 }
 166 EXPORT_SYMBOL(clk_set_parent);
 167
 168 int clk_register(struct clk *clk)
 169 {
 170         if (clk == NULL || IS_ERR(clk))
 171                 return -EINVAL;
 172
 173         if (WARN(clk->parent && !clk->parent->rate,
 174                         "CLK: %s parent %s has no rate!\n",
 175                         clk->name, clk->parent->name))
 176                 return -EINVAL;
 177
 178         INIT_LIST_HEAD(&clk->children);
 179
 180         mutex_lock(&clocks_mutex);
 181         list_add_tail(&clk->node, &clocks);
 182         if (clk->parent)
 183                 list_add_tail(&clk->childnode, &clk->parent->children);
 184         mutex_unlock(&clocks_mutex);
 185
 186         /* If rate is already set, use it */
 187         if (clk->rate)
 188                 return 0;
 189
 190         /* Else, see if there is a way to calculate it */
 191         if (clk->recalc)
 192                 clk->rate = clk->recalc(clk);
 193
 194         /* Otherwise, default to parent rate */
 195         else if (clk->parent)
 196                 clk->rate = clk->parent->rate;
 197
 198         return 0;
 199 }
 200 EXPORT_SYMBOL(clk_register);
 201
 202 void clk_unregister(struct clk *clk)
 203 {
 204         if (clk == NULL || IS_ERR(clk))
 205                 return;
 206
 207         mutex_lock(&clocks_mutex);
 208         list_del(&clk->node);
 209         list_del(&clk->childnode);
 210         mutex_unlock(&clocks_mutex);
 211 }
 212 EXPORT_SYMBOL(clk_unregister);
 213
 214 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
 215 /*
 216  * Disable any unused clocks left on by the bootloader
 217  */
 218 static int __init clk_disable_unused(void)
 219 {
 220         struct clk *ck;
 221
 222         spin_lock_irq(&clockfw_lock);
 223         list_for_each_entry(ck, &clocks, node) {
 224                 if (ck->usecount > 0)
 225                         continue;
 226                 if (!(ck->flags & CLK_PSC))
 227                         continue;
 228
 229                 /* ignore if in Disabled or SwRstDisable states */
 230                 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
 231                         continue;
 232
 233                 pr_info("Clocks: disable unused %s\n", ck->name);
 234                 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
 235         }
 236         spin_unlock_irq(&clockfw_lock);
 237
 238         return 0;
 239 }
 240 late_initcall(clk_disable_unused);
 241 #endif
 242
 243 static unsigned long clk_sysclk_recalc(struct clk *clk)
 244 {
 245         u32 v, plldiv;
 246         struct pll_data *pll;
 247         unsigned long rate = clk->rate;
 248
 249         /* If this is the PLL base clock, no more calculations needed */
 250         if (clk->pll_data)
 251                 return rate;
 252
 253         if (WARN_ON(!clk->parent))
 254                 return rate;
 255
 256         rate = clk->parent->rate;
 257
 258         /* Otherwise, the parent must be a PLL */
 259         if (WARN_ON(!clk->parent->pll_data))
 260                 return rate;
 261
 262         pll = clk->parent->pll_data;
 263
 264         /* If pre-PLL, source clock is before the multiplier and divider(s) */
 265         if (clk->flags & PRE_PLL)
 266                 rate = pll->input_rate;
 267
 268         if (!clk->div_reg)
 269                 return rate;
 270
 271         v = __raw_readl(pll->base + clk->div_reg);
 272         if (v & PLLDIV_EN) {
 273                 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
 274                 if (plldiv)
 275                         rate /= plldiv;
 276         }
 277
 278         return rate;
 279 }
 280
 281 static unsigned long clk_leafclk_recalc(struct clk *clk)
 282 {
 283         if (WARN_ON(!clk->parent))
 284                 return clk->rate;
 285
 286         return clk->parent->rate;
 287 }
 288
 289 static unsigned long clk_pllclk_recalc(struct clk *clk)
 290 {
 291         u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
 292         u8 bypass;
 293         struct pll_data *pll = clk->pll_data;
 294         unsigned long rate = clk->rate;
 295
 296         pll->base = IO_ADDRESS(pll->phys_base);
 297         ctrl = __raw_readl(pll->base + PLLCTL);
 298         rate = pll->input_rate = clk->parent->rate;
 299
 300         if (ctrl & PLLCTL_PLLEN) {
 301                 bypass = 0;
 302                 mult = __raw_readl(pll->base + PLLM);
 303                 if (cpu_is_davinci_dm365())
 304                         mult = 2 * (mult & PLLM_PLLM_MASK);
 305                 else
 306                         mult = (mult & PLLM_PLLM_MASK) + 1;
 307         } else
 308                 bypass = 1;
 309
 310         if (pll->flags & PLL_HAS_PREDIV) {
 311                 prediv = __raw_readl(pll->base + PREDIV);
 312                 if (prediv & PLLDIV_EN)
 313                         prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
 314                 else
 315                         prediv = 1;
 316         }
 317
 318         /* pre-divider is fixed, but (some?) chips won't report that */
 319         if (cpu_is_davinci_dm355() && pll->num == 1)
 320                 prediv = 8;
 321
 322         if (pll->flags & PLL_HAS_POSTDIV) {
 323                 postdiv = __raw_readl(pll->base + POSTDIV);
 324                 if (postdiv & PLLDIV_EN)
 325                         postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
 326                 else
 327                         postdiv = 1;
 328         }
 329
 330         if (!bypass) {
 331                 rate /= prediv;
 332                 rate *= mult;
 333                 rate /= postdiv;
 334         }
 335
 336         pr_debug("PLL%d: input = %lu MHz [ ",
 337                  pll->num, clk->parent->rate / 1000000);
 338         if (bypass)
 339                 pr_debug("bypass ");
 340         if (prediv > 1)
 341                 pr_debug("/ %d ", prediv);
 342         if (mult > 1)
 343                 pr_debug("* %d ", mult);
 344         if (postdiv > 1)
 345                 pr_debug("/ %d ", postdiv);
 346         pr_debug("] --> %lu MHz output.\n", rate / 1000000);
 347
 348         return rate;
 349 }
 350
 351 /**
 352  * davinci_set_pllrate - set the output rate of a given PLL.
 353  *
 354  * Note: Currently tested to work with OMAP-L138 only.
 355  *
 356  * @pll: pll whose rate needs to be changed.
 357  * @prediv: The pre divider value. Passing 0 disables the pre-divider.
 358  * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
 359  * @postdiv: The post divider value. Passing 0 disables the post-divider.
 360  */
 361 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 362                                         unsigned int mult, unsigned int postdiv)
 363 {
 364         u32 ctrl;
 365         unsigned int locktime;
 366
 367         if (pll->base == NULL)
 368                 return -EINVAL;
 369
 370         /*
 371          *  PLL lock time required per OMAP-L138 datasheet is
 372          * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
 373          * as 4 and OSCIN cycle as 25 MHz.
 374          */
 375         if (prediv) {
 376                 locktime = ((2000 * prediv) / 100);
 377                 prediv = (prediv - 1) | PLLDIV_EN;
 378         } else {
 379                 locktime = PLL_LOCK_TIME;
 380         }
 381         if (postdiv)
 382                 postdiv = (postdiv - 1) | PLLDIV_EN;
 383         if (mult)
 384                 mult = mult - 1;
 385
 386         ctrl = __raw_readl(pll->base + PLLCTL);
 387
 388         /* Switch the PLL to bypass mode */
 389         ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
 390         __raw_writel(ctrl, pll->base + PLLCTL);
 391
 392         udelay(PLL_BYPASS_TIME);
 393
 394         /* Reset and enable PLL */
 395         ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
 396         __raw_writel(ctrl, pll->base + PLLCTL);
 397
 398         if (pll->flags & PLL_HAS_PREDIV)
 399                 __raw_writel(prediv, pll->base + PREDIV);
 400
 401         __raw_writel(mult, pll->base + PLLM);
 402
 403         if (pll->flags & PLL_HAS_POSTDIV)
 404                 __raw_writel(postdiv, pll->base + POSTDIV);
 405
 406         udelay(PLL_RESET_TIME);
 407
 408         /* Bring PLL out of reset */
 409         ctrl |= PLLCTL_PLLRST;
 410         __raw_writel(ctrl, pll->base + PLLCTL);
 411
 412         udelay(locktime);
 413
 414         /* Remove PLL from bypass mode */
 415         ctrl |= PLLCTL_PLLEN;
 416         __raw_writel(ctrl, pll->base + PLLCTL);
 417
 418         return 0;
 419 }
 420 EXPORT_SYMBOL(davinci_set_pllrate);
 421
 422 int __init davinci_clk_init(struct davinci_clk *clocks)
 423   {
 424         struct davinci_clk *c;
 425         struct clk *clk;
 426
 427         for (c = clocks; c->lk.clk; c++) {
 428                 clk = c->lk.clk;
 429
 430                 if (!clk->recalc) {
 431
 432                         /* Check if clock is a PLL */
 433                         if (clk->pll_data)
 434                                 clk->recalc = clk_pllclk_recalc;
 435
 436                         /* Else, if it is a PLL-derived clock */
 437                         else if (clk->flags & CLK_PLL)
 438                                 clk->recalc = clk_sysclk_recalc;
 439
 440                         /* Otherwise, it is a leaf clock (PSC clock) */
 441                         else if (clk->parent)
 442                                 clk->recalc = clk_leafclk_recalc;
 443                 }
 444
 445                 if (clk->recalc)
 446                         clk->rate = clk->recalc(clk);
 447
 448                 if (clk->lpsc)
 449                         clk->flags |= CLK_PSC;
 450
 451                 clkdev_add(&c->lk);
 452                 clk_register(clk);
 453
 454                 /* Turn on clocks that Linux doesn't otherwise manage */
 455                 if (clk->flags & ALWAYS_ENABLED)
 456                         clk_enable(clk);
 457         }
 458
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_PROC_FS
 463 #include <linux/proc_fs.h>
 464 #include <linux/seq_file.h>
 465
 466 static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
 467 {
 468         return *pos < 1 ? (void *)1 : NULL;
 469 }
 470
 471 static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
 472 {
 473         ++*pos;
 474         return NULL;
 475 }
 476
 477 static void davinci_ck_stop(struct seq_file *m, void *v)
 478 {
 479 }
 480
 481 #define CLKNAME_MAX     10              /* longest clock name */
 482 #define NEST_DELTA      2
 483 #define NEST_MAX        4
 484
 485 static void
 486 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 487 {
 488         char            *state;
 489         char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
 490         struct clk      *clk;
 491         unsigned        i;
 492
 493         if (parent->flags & CLK_PLL)
 494                 state = "pll";
 495         else if (parent->flags & CLK_PSC)
 496                 state = "psc";
 497         else
 498                 state = "";
 499
 500         /* <nest spaces> name <pad to end> */
 501         memset(buf, ' ', sizeof(buf) - 1);
 502         buf[sizeof(buf) - 1] = 0;
 503         i = strlen(parent->name);
 504         memcpy(buf + nest, parent->name,
 505                         min(i, (unsigned)(sizeof(buf) - 1 - nest)));
 506
 507         seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
 508                    buf, parent->usecount, state, clk_get_rate(parent));
 509         /* REVISIT show device associations too */
 510
 511         /* cost is now small, but not linear... */
 512         list_for_each_entry(clk, &parent->children, childnode) {
 513                 dump_clock(s, nest + NEST_DELTA, clk);
 514         }
 515 }
 516
 517 static int davinci_ck_show(struct seq_file *m, void *v)
 518 {
 519         /* Show clock tree; we know the main oscillator is first.
 520          * We trust nonzero usecounts equate to PSC enables...
 521          */
 522         mutex_lock(&clocks_mutex);
 523         if (!list_empty(&clocks))
 524                 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
 525         mutex_unlock(&clocks_mutex);
 526
 527         return 0;
 528 }
 529
 530 static const struct seq_operations davinci_ck_op = {
 531         .start  = davinci_ck_start,
 532         .next   = davinci_ck_next,
 533         .stop   = davinci_ck_stop,
 534         .show   = davinci_ck_show
 535 };
 536
 537 static int davinci_ck_open(struct inode *inode, struct file *file)
 538 {
 539         return seq_open(file, &davinci_ck_op);
 540 }
 541
 542 static const struct file_operations proc_davinci_ck_operations = {
 543         .open           = davinci_ck_open,
 544         .read           = seq_read,
 545         .llseek         = seq_lseek,
 546         .release        = seq_release,
 547 };
 548
 549 static int __init davinci_ck_proc_init(void)
 550 {
 551         proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
 552         return 0;
 553
 554 }
 555 __initcall(davinci_ck_proc_init);
 556 #endif /* CONFIG_DEBUG_PROC_FS */