arch/arm/common/gic.c

   1 /*
   2  *  linux/arch/arm/common/gic.c
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Interrupt architecture for the GIC:
  11  *
  12  * o There is one Interrupt Distributor, which receives interrupts
  13  *   from system devices and sends them to the Interrupt Controllers.
  14  *
  15  * o There is one CPU Interface per CPU, which sends interrupts sent
  16  *   by the Distributor, and interrupts generated locally, to the
  17  *   associated CPU. The base address of the CPU interface is usually
  18  *   aliased so that the same address points to different chips depending
  19  *   on the CPU it is accessed from.
  20  *
  21  * Note that IRQs 0-31 are special - they are local to each CPU.
  22  * As such, the enable set/clear, pending set/clear and active bit
  23  * registers are banked per-cpu for these sources.
  24  */
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/smp.h>
  29 #include <linux/cpumask.h>
  30 #include <linux/io.h>
  31
  32 #include <asm/irq.h>
  33 #include <asm/mach/irq.h>
  34 #include <asm/hardware/gic.h>
  35
  36 static DEFINE_SPINLOCK(irq_controller_lock);
  37
  38 /* Address of GIC 0 CPU interface */
  39 void __iomem *gic_cpu_base_addr __read_mostly;
  40
  41 struct gic_chip_data {
  42         unsigned int irq_offset;
  43         void __iomem *dist_base;
  44         void __iomem *cpu_base;
  45 };
  46
  47 #ifndef MAX_GIC_NR
  48 #define MAX_GIC_NR      1
  49 #endif
  50
  51 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
  52
  53 static inline void __iomem *gic_dist_base(struct irq_data *d)
  54 {
  55         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
  56         return gic_data->dist_base;
  57 }
  58
  59 static inline void __iomem *gic_cpu_base(struct irq_data *d)
  60 {
  61         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
  62         return gic_data->cpu_base;
  63 }
  64
  65 static inline unsigned int gic_irq(struct irq_data *d)
  66 {
  67         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
  68         return d->irq - gic_data->irq_offset;
  69 }
  70
  71 /*
  72  * Routines to acknowledge, disable and enable interrupts
  73  */
  74 static void gic_ack_irq(struct irq_data *d)
  75 {
  76         spin_lock(&irq_controller_lock);
  77         writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
  78         spin_unlock(&irq_controller_lock);
  79 }
  80
  81 static void gic_mask_irq(struct irq_data *d)
  82 {
  83         u32 mask = 1 << (d->irq % 32);
  84
  85         spin_lock(&irq_controller_lock);
  86         writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
  87         spin_unlock(&irq_controller_lock);
  88 }
  89
  90 static void gic_unmask_irq(struct irq_data *d)
  91 {
  92         u32 mask = 1 << (d->irq % 32);
  93
  94         spin_lock(&irq_controller_lock);
  95         writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
  96         spin_unlock(&irq_controller_lock);
  97 }
  98
  99 static int gic_set_type(struct irq_data *d, unsigned int type)
 100 {
 101         void __iomem *base = gic_dist_base(d);
 102         unsigned int gicirq = gic_irq(d);
 103         u32 enablemask = 1 << (gicirq % 32);
 104         u32 enableoff = (gicirq / 32) * 4;
 105         u32 confmask = 0x2 << ((gicirq % 16) * 2);
 106         u32 confoff = (gicirq / 16) * 4;
 107         bool enabled = false;
 108         u32 val;
 109
 110         /* Interrupt configuration for SGIs can't be changed */
 111         if (gicirq < 16)
 112                 return -EINVAL;
 113
 114         if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 115                 return -EINVAL;
 116
 117         spin_lock(&irq_controller_lock);
 118
 119         val = readl(base + GIC_DIST_CONFIG + confoff);
 120         if (type == IRQ_TYPE_LEVEL_HIGH)
 121                 val &= ~confmask;
 122         else if (type == IRQ_TYPE_EDGE_RISING)
 123                 val |= confmask;
 124
 125         /*
 126          * As recommended by the spec, disable the interrupt before changing
 127          * the configuration
 128          */
 129         if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
 130                 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
 131                 enabled = true;
 132         }
 133
 134         writel(val, base + GIC_DIST_CONFIG + confoff);
 135
 136         if (enabled)
 137                 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 138
 139         spin_unlock(&irq_controller_lock);
 140
 141         return 0;
 142 }
 143
 144 #ifdef CONFIG_SMP
 145 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 146                             bool force)
 147 {
 148         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
 149         unsigned int shift = (d->irq % 4) * 8;
 150         unsigned int cpu = cpumask_first(mask_val);
 151         u32 val, mask, bit;
 152
 153         if (cpu >= 8)
 154                 return -EINVAL;
 155
 156         mask = 0xff << shift;
 157         bit = 1 << (cpu + shift);
 158
 159         spin_lock(&irq_controller_lock);
 160         d->node = cpu;
 161         val = readl(reg) & ~mask;
 162         writel(val | bit, reg);
 163         spin_unlock(&irq_controller_lock);
 164
 165         return 0;
 166 }
 167 #endif
 168
 169 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 170 {
 171         struct gic_chip_data *chip_data = get_irq_data(irq);
 172         struct irq_chip *chip = get_irq_chip(irq);
 173         unsigned int cascade_irq, gic_irq;
 174         unsigned long status;
 175
 176         /* primary controller ack'ing */
 177         chip->irq_ack(&desc->irq_data);
 178
 179         spin_lock(&irq_controller_lock);
 180         status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
 181         spin_unlock(&irq_controller_lock);
 182
 183         gic_irq = (status & 0x3ff);
 184         if (gic_irq == 1023)
 185                 goto out;
 186
 187         cascade_irq = gic_irq + chip_data->irq_offset;
 188         if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
 189                 do_bad_IRQ(cascade_irq, desc);
 190         else
 191                 generic_handle_irq(cascade_irq);
 192
 193  out:
 194         /* primary controller unmasking */
 195         chip->irq_unmask(&desc->irq_data);
 196 }
 197
 198 static struct irq_chip gic_chip = {
 199         .name                   = "GIC",
 200         .irq_ack                = gic_ack_irq,
 201         .irq_mask               = gic_mask_irq,
 202         .irq_unmask             = gic_unmask_irq,
 203         .irq_set_type           = gic_set_type,
 204 #ifdef CONFIG_SMP
 205         .irq_set_affinity       = gic_set_affinity,
 206 #endif
 207 };
 208
 209 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 210 {
 211         if (gic_nr >= MAX_GIC_NR)
 212                 BUG();
 213         if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
 214                 BUG();
 215         set_irq_chained_handler(irq, gic_handle_cascade_irq);
 216 }
 217
 218 static void __init gic_dist_init(struct gic_chip_data *gic,
 219         unsigned int irq_start)
 220 {
 221         unsigned int gic_irqs, irq_limit, i;
 222         void __iomem *base = gic->dist_base;
 223         u32 cpumask = 1 << smp_processor_id();
 224
 225         cpumask |= cpumask << 8;
 226         cpumask |= cpumask << 16;
 227
 228         writel(0, base + GIC_DIST_CTRL);
 229
 230         /*
 231          * Find out how many interrupts are supported.
 232          * The GIC only supports up to 1020 interrupt sources.
 233          */
 234         gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
 235         gic_irqs = (gic_irqs + 1) * 32;
 236         if (gic_irqs > 1020)
 237                 gic_irqs = 1020;
 238
 239         /*
 240          * Set all global interrupts to be level triggered, active low.
 241          */
 242         for (i = 32; i < gic_irqs; i += 16)
 243                 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 244
 245         /*
 246          * Set all global interrupts to this CPU only.
 247          */
 248         for (i = 32; i < gic_irqs; i += 4)
 249                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 250
 251         /*
 252          * Set priority on all global interrupts.
 253          */
 254         for (i = 32; i < gic_irqs; i += 4)
 255                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 256
 257         /*
 258          * Disable all interrupts.  Leave the PPI and SGIs alone
 259          * as these enables are banked registers.
 260          */
 261         for (i = 32; i < gic_irqs; i += 32)
 262                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 263
 264         /*
 265          * Limit number of interrupts registered to the platform maximum
 266          */
 267         irq_limit = gic->irq_offset + gic_irqs;
 268         if (WARN_ON(irq_limit > NR_IRQS))
 269                 irq_limit = NR_IRQS;
 270
 271         /*
 272          * Setup the Linux IRQ subsystem.
 273          */
 274         for (i = irq_start; i < irq_limit; i++) {
 275                 set_irq_chip(i, &gic_chip);
 276                 set_irq_chip_data(i, gic);
 277                 set_irq_handler(i, handle_level_irq);
 278                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 279         }
 280
 281         writel(1, base + GIC_DIST_CTRL);
 282 }
 283
 284 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 285 {
 286         void __iomem *dist_base = gic->dist_base;
 287         void __iomem *base = gic->cpu_base;
 288         int i;
 289
 290         /*
 291          * Deal with the banked PPI and SGI interrupts - disable all
 292          * PPI interrupts, ensure all SGI interrupts are enabled.
 293          */
 294         writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
 295         writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
 296
 297         /*
 298          * Set priority on PPI and SGI interrupts
 299          */
 300         for (i = 0; i < 32; i += 4)
 301                 writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
 302
 303         writel(0xf0, base + GIC_CPU_PRIMASK);
 304         writel(1, base + GIC_CPU_CTRL);
 305 }
 306
 307 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
 308         void __iomem *dist_base, void __iomem *cpu_base)
 309 {
 310         struct gic_chip_data *gic;
 311
 312         BUG_ON(gic_nr >= MAX_GIC_NR);
 313
 314         gic = &gic_data[gic_nr];
 315         gic->dist_base = dist_base;
 316         gic->cpu_base = cpu_base;
 317         gic->irq_offset = (irq_start - 1) & ~31;
 318
 319         if (gic_nr == 0)
 320                 gic_cpu_base_addr = cpu_base;
 321
 322         gic_dist_init(gic, irq_start);
 323         gic_cpu_init(gic);
 324 }
 325
 326 void __cpuinit gic_secondary_init(unsigned int gic_nr)
 327 {
 328         BUG_ON(gic_nr >= MAX_GIC_NR);
 329
 330         gic_cpu_init(&gic_data[gic_nr]);
 331 }
 332
 333 void __cpuinit gic_enable_ppi(unsigned int irq)
 334 {
 335         unsigned long flags;
 336
 337         local_irq_save(flags);
 338         irq_to_desc(irq)->status |= IRQ_NOPROBE;
 339         gic_unmask_irq(irq_get_irq_data(irq));
 340         local_irq_restore(flags);
 341 }
 342
 343 #ifdef CONFIG_SMP
 344 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 345 {
 346         unsigned long map = *cpus_addr(*mask);
 347
 348         /* this always happens on GIC0 */
 349         writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 350 }
 351 #endif