block: share request flush fields with elevator_private
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / edac / amd64_edac_inj.c
blob29f1f7a612d92671976b356b48efd10594f09d6f
1 #include "amd64_edac.h"
3 static ssize_t amd64_inject_section_show(struct mem_ctl_info *mci, char *buf)
5 struct amd64_pvt *pvt = mci->pvt_info;
6 return sprintf(buf, "0x%x\n", pvt->injection.section);
9 /*
10 * store error injection section value which refers to one of 4 16-byte sections
11 * within a 64-byte cacheline
13 * range: 0..3
15 static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
16 const char *data, size_t count)
18 struct amd64_pvt *pvt = mci->pvt_info;
19 unsigned long value;
20 int ret = 0;
22 ret = strict_strtoul(data, 10, &value);
23 if (ret != -EINVAL) {
25 if (value > 3) {
26 amd64_printk(KERN_WARNING,
27 "%s: invalid section 0x%lx\n",
28 __func__, value);
29 return -EINVAL;
32 pvt->injection.section = (u32) value;
33 return count;
35 return ret;
38 static ssize_t amd64_inject_word_show(struct mem_ctl_info *mci, char *buf)
40 struct amd64_pvt *pvt = mci->pvt_info;
41 return sprintf(buf, "0x%x\n", pvt->injection.word);
45 * store error injection word value which refers to one of 9 16-bit word of the
46 * 16-byte (128-bit + ECC bits) section
48 * range: 0..8
50 static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
51 const char *data, size_t count)
53 struct amd64_pvt *pvt = mci->pvt_info;
54 unsigned long value;
55 int ret = 0;
57 ret = strict_strtoul(data, 10, &value);
58 if (ret != -EINVAL) {
60 if (value > 8) {
61 amd64_printk(KERN_WARNING,
62 "%s: invalid word 0x%lx\n",
63 __func__, value);
64 return -EINVAL;
67 pvt->injection.word = (u32) value;
68 return count;
70 return ret;
73 static ssize_t amd64_inject_ecc_vector_show(struct mem_ctl_info *mci, char *buf)
75 struct amd64_pvt *pvt = mci->pvt_info;
76 return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
80 * store 16 bit error injection vector which enables injecting errors to the
81 * corresponding bit within the error injection word above. When used during a
82 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
84 static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
85 const char *data, size_t count)
87 struct amd64_pvt *pvt = mci->pvt_info;
88 unsigned long value;
89 int ret = 0;
91 ret = strict_strtoul(data, 16, &value);
92 if (ret != -EINVAL) {
94 if (value & 0xFFFF0000) {
95 amd64_printk(KERN_WARNING,
96 "%s: invalid EccVector: 0x%lx\n",
97 __func__, value);
98 return -EINVAL;
101 pvt->injection.bit_map = (u32) value;
102 return count;
104 return ret;
108 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
109 * fields needed by the injection registers and read the NB Array Data Port.
111 static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
112 const char *data, size_t count)
114 struct amd64_pvt *pvt = mci->pvt_info;
115 unsigned long value;
116 u32 section, word_bits;
117 int ret = 0;
119 ret = strict_strtoul(data, 10, &value);
120 if (ret != -EINVAL) {
122 /* Form value to choose 16-byte section of cacheline */
123 section = F10_NB_ARRAY_DRAM_ECC |
124 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
125 pci_write_config_dword(pvt->misc_f3_ctl,
126 F10_NB_ARRAY_ADDR, section);
128 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
129 pvt->injection.bit_map);
131 /* Issue 'word' and 'bit' along with the READ request */
132 pci_write_config_dword(pvt->misc_f3_ctl,
133 F10_NB_ARRAY_DATA, word_bits);
135 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
137 return count;
139 return ret;
143 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
144 * fields needed by the injection registers.
146 static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
147 const char *data, size_t count)
149 struct amd64_pvt *pvt = mci->pvt_info;
150 unsigned long value;
151 u32 section, word_bits;
152 int ret = 0;
154 ret = strict_strtoul(data, 10, &value);
155 if (ret != -EINVAL) {
157 /* Form value to choose 16-byte section of cacheline */
158 section = F10_NB_ARRAY_DRAM_ECC |
159 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
160 pci_write_config_dword(pvt->misc_f3_ctl,
161 F10_NB_ARRAY_ADDR, section);
163 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
164 pvt->injection.bit_map);
166 /* Issue 'word' and 'bit' along with the READ request */
167 pci_write_config_dword(pvt->misc_f3_ctl,
168 F10_NB_ARRAY_DATA, word_bits);
170 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
172 return count;
174 return ret;
178 * update NUM_INJ_ATTRS in case you add new members
180 struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
183 .attr = {
184 .name = "inject_section",
185 .mode = (S_IRUGO | S_IWUSR)
187 .show = amd64_inject_section_show,
188 .store = amd64_inject_section_store,
191 .attr = {
192 .name = "inject_word",
193 .mode = (S_IRUGO | S_IWUSR)
195 .show = amd64_inject_word_show,
196 .store = amd64_inject_word_store,
199 .attr = {
200 .name = "inject_ecc_vector",
201 .mode = (S_IRUGO | S_IWUSR)
203 .show = amd64_inject_ecc_vector_show,
204 .store = amd64_inject_ecc_vector_store,
207 .attr = {
208 .name = "inject_write",
209 .mode = (S_IRUGO | S_IWUSR)
211 .show = NULL,
212 .store = amd64_inject_write_store,
215 .attr = {
216 .name = "inject_read",
217 .mode = (S_IRUGO | S_IWUSR)
219 .show = NULL,
220 .store = amd64_inject_read_store,