drivers/staging/silicom/bp_mod.h

   1 /******************************************************************************/
   2 /*                                                                            */
   3 /* Bypass Control utility, Copyright (c) 2005 Silicom                         */
   4 /*                                                                            */
   5 /* This program is free software; you can redistribute it and/or modify       */
   6 /* it under the terms of the GNU General Public License as published by       */
   7 /* the Free Software Foundation, located in the file LICENSE.                 */
   8 /*                                                                            */
   9 /*                                                                            */
  10 /* bp_mod.h                                                                   */
  11 /*                                                                            */
  12 /******************************************************************************/
  13
  14 #ifndef BP_MOD_H
  15 #define BP_MOD_H
  16 #include "bits.h"
  17
  18 #define EXPORT_SYMBOL_NOVERS EXPORT_SYMBOL
  19
  20 #define usec_delay(x) udelay(x)
  21 #ifndef msec_delay_bp
  22 #define msec_delay_bp(x)                        \
  23 do {                                            \
  24         int  i;                                 \
  25         if (1) {                                \
  26                 for (i = 0; i < 1000; i++) {    \
  27                         udelay(x) ;             \
  28                 }                               \
  29         } else {                                \
  30                 msleep(x);                      \
  31         }                                       \
  32 } while (0)
  33
  34 #endif
  35
  36 #include <linux/param.h>
  37
  38 #ifndef jiffies_to_msecs
  39 #define jiffies_to_msecs(x) _kc_jiffies_to_msecs(x)
  40 static inline unsigned int jiffies_to_msecs(const unsigned long j)
  41 {
  42 #if HZ <= 1000 && !(1000 % HZ)
  43         return (1000 / HZ) * j;
  44 #elif HZ > 1000 && !(HZ % 1000)
  45         return (j + (HZ / 1000) - 1) / (HZ / 1000);
  46 #else
  47         return (j * 1000) / HZ;
  48 #endif
  49 }
  50 #endif
  51
  52 #define SILICOM_VID              0x1374
  53 #define SILICOM_SVID             0x1374
  54
  55 #define SILICOM_PXG2BPFI_SSID    0x0026
  56 #define SILICOM_PXG2BPFILX_SSID  0x0027
  57 #define SILICOM_PXGBPI_SSID      0x0028
  58 #define SILICOM_PXGBPIG_SSID     0x0029
  59 #define SILICOM_PXG2TBFI_SSID    0x002a
  60 #define SILICOM_PXG4BPI_SSID     0x002c
  61 #define SILICOM_PXG4BPFI_SSID    0x002d
  62 #define SILICOM_PXG4BPFILX_SSID  0x002e
  63 #define SILICOM_PXG2BPFIL_SSID   0x002F
  64 #define SILICOM_PXG2BPFILLX_SSID 0x0030
  65 #define SILICOM_PEG4BPI_SSID     0x0031
  66 #define SILICOM_PEG2BPI_SSID     0x0037
  67 #define SILICOM_PEG4BPIN_SSID    0x0038
  68 #define SILICOM_PEG2BPFI_SSID    0x0039
  69 #define SILICOM_PEG2BPFILX_SSID  0x003A
  70 #define SILICOM_PMCXG2BPFI_SSID  0x003B
  71 #define NOKIA_PMCXG2BPFIN_SSID   0x0510
  72 #define NOKIA_PMCXG2BPIN_SSID    0x0513
  73 #define NOKIA_PMCXG4BPIN_SSID    0x0514
  74 #define NOKIA_PMCXG2BPFIN_SVID   0x13B8
  75 #define NOKIA_PMCXG2BPIN2_SSID    0x0515
  76 #define NOKIA_PMCXG4BPIN2_SSID    0x0516
  77 #define SILICOM_PMCX2BPI_SSID       0x041
  78 #define SILICOM_PMCX4BPI_SSID       0x042
  79 #define SILICOM_PXG2BISC1_SSID   0x003d
  80 #define SILICOM_PEG2TBFI_SSID    0x003E
  81 #define SILICOM_PXG2TBI_SSID     0x003f
  82 #define SILICOM_PXG4BPFID_SSID   0x0043
  83 #define SILICOM_PEG4BPFI_SSID    0x0040
  84 #define SILICOM_PEG4BPIPT_SSID   0x0044
  85 #define SILICOM_PXG6BPI_SSID     0x0045
  86 #define SILICOM_PEG4BPIL_SSID    0x0046
  87 #define SILICOM_PEG2BPI5_SSID    0x0052
  88 #define SILICOM_PEG6BPI_SSID    0x0053
  89 #define SILICOM_PEG4BPFI5_SSID   0x0050
  90 #define SILICOM_PEG4BPFI5LX_SSID   0x0051
  91 #define SILICOM_PEG2BISC6_SSID 0x54
  92
  93 #define SILICOM_PEG6BPIFC_SSID 0x55
  94
  95 #define SILICOM_PEG2BPFI5_SSID   0x0056
  96 #define SILICOM_PEG2BPFI5LX_SSID   0x0057
  97
  98 #define SILICOM_PXEG4BPFI_SSID    0x0058
  99
 100 #define SILICOM_PEG2BPFID_SSID   0x0047
 101 #define SILICOM_PEG2BPFIDLX_SSID  0x004C
 102 #define SILICOM_MEG2BPFILN_SSID  0x0048
 103 #define SILICOM_MEG2BPFINX_SSID  0x0049
 104 #define SILICOM_PEG4BPFILX_SSID  0x004A
 105 #define SILICOM_MHIO8AD_SSID    0x004F
 106
 107 #define SILICOM_MEG2BPFILXLN_SSID 0x004b
 108 #define SILICOM_PEG2BPIX1_SSID    0x004d
 109 #define SILICOM_MEG2BPFILXNX_SSID 0x004e
 110
 111 #define SILICOM_PE10G2BPISR_SSID  0x0102
 112 #define SILICOM_PE10G2BPILR_SSID  0x0103
 113 #define SILICOM_PE10G2BPICX4_SSID  0x0101
 114
 115 #define SILICOM_XE10G2BPILR_SSID 0x0163
 116 #define SILICOM_XE10G2BPISR_SSID 0x0162
 117 #define SILICOM_XE10G2BPICX4_SSID 0x0161
 118 #define SILICOM_XE10G2BPIT_SSID   0x0160
 119
 120 #define SILICOM_PE10GDBISR_SSID   0x0181
 121 #define SILICOM_PE10GDBILR_SSID   0x0182
 122
 123 #define SILICOM_PE210G2DBi9SR_SSID          0x0188
 124 #define SILICOM_PE210G2DBi9SRRB_SSID    0x0188
 125 #define SILICOM_PE210G2DBi9LR_SSID          0x0189
 126 #define SILICOM_PE210G2DBi9LRRB_SSID    0x0189
 127 #define SILICOM_PE310G4DBi940SR_SSID    0x018C
 128
 129 #define SILICOM_PE310G4BPi9T_SSID       0x130
 130 #define SILICOM_PE310G4BPi9SR_SSID        0x132
 131 #define SILICOM_PE310G4BPi9LR_SSID        0x133
 132
 133 #define NOKIA_XE10G2BPIXR_SVID   0x13B8
 134 #define NOKIA_XE10G2BPIXR_SSID   0x051C
 135
 136 #define INTEL_PEG4BPII_PID   0x10A0
 137 #define INTEL_PEG4BPFII_PID   0x10A1
 138 #define INTEL_PEG4BPII_SSID   0x11A0
 139 #define INTEL_PEG4BPFII_SSID   0x11A1
 140
 141 #define INTEL_PEG4BPIIO_SSID   0x10A0
 142 #define INTEL_PEG4BPIIO_PID   0x105e
 143
 144 #define BROADCOM_VID         0x14e4
 145 #define BROADCOM_PE10G2_PID  0x164e
 146
 147 #define SILICOM_PE10G2BPTCX4_SSID 0x0141
 148 #define SILICOM_PE10G2BPTSR_SSID  0x0142
 149 #define SILICOM_PE10G2BPTLR_SSID  0x0143
 150 #define SILICOM_PE10G2BPTT_SSID   0x0140
 151
 152 #define SILICOM_PEG4BPI6_SSID     0x0320
 153 #define SILICOM_PEG4BPFI6_SSID    0x0321
 154 #define SILICOM_PEG4BPFI6LX_SSID    0x0322
 155 #define SILICOM_PEG4BPFI6ZX_SSID    0x0323
 156
 157 #define SILICOM_PEG2BPI6_SSID    0x0300
 158 #define SILICOM_PEG2BPFI6_SSID    0x0301
 159 #define SILICOM_PEG2BPFI6LX_SSID    0x0302
 160 #define SILICOM_PEG2BPFI6ZX_SSID    0x0303
 161 #define SILICOM_PEG2BPFI6FLXM_SSID  0x0304
 162
 163 #define SILICOM_PEG2DBI6_SSID    0x0308
 164 #define SILICOM_PEG2DBFI6_SSID    0x0309
 165 #define SILICOM_PEG2DBFI6LX_SSID    0x030A
 166 #define SILICOM_PEG2DBFI6ZX_SSID    0x030B
 167
 168 #define SILICOM_MEG2BPI6_SSID     0x0310
 169 #define SILICOM_XEG2BPI6_SSID    0x0318
 170 #define SILICOM_PEG4BPI6FC_SSID     0x0328
 171 #define SILICOM_PEG4BPFI6FC_SSID    0x0329
 172 #define SILICOM_PEG4BPFI6FCLX_SSID    0x032A
 173 #define SILICOM_PEG4BPFI6FCZX_SSID    0x032B
 174
 175 #define SILICOM_PEG6BPI6_SSID     0x0340
 176
 177 #define SILICOM_PEG2BPI6SC6_SSID     0x0360
 178
 179 #define SILICOM_MEG2BPI6_SSID     0x0310
 180 #define SILICOM_XEG2BPI6_SSID     0x0318
 181 #define SILICOM_MEG4BPI6_SSID     0x0330
 182
 183 #define SILICOM_PE2G4BPi80L_SSID    0x0380
 184
 185 #define SILICOM_M6E2G8BPi80A_SSID    0x0474
 186
 187 #define SILICOM_PE2G4BPi35_SSID    0x03d8
 188
 189 #define SILICOM_PE2G4BPFi80_SSID    0x0381
 190 #define SILICOM_PE2G4BPFi80LX_SSID    0x0382
 191 #define SILICOM_PE2G4BPFi80ZX_SSID    0x0383
 192
 193 #define SILICOM_PE2G4BPi80_SSID    0x0388
 194
 195 #define SILICOM_PE2G2BPi80_SSID    0x0390
 196 #define SILICOM_PE2G2BPFi80_SSID    0x0391
 197 #define SILICOM_PE2G2BPFi80LX_SSID    0x0392
 198 #define SILICOM_PE2G2BPFi80ZX_SSID    0x0393
 199
 200 #define SILICOM_PE2G4BPi35L_SSID    0x03D0
 201 #define SILICOM_PE2G4BPFi35_SSID    0x03D1
 202 #define SILICOM_PE2G4BPFi35LX_SSID    0x03D2
 203 #define SILICOM_PE2G4BPFi35ZX_SSID    0x03D3
 204
 205 #define SILICOM_PE2G2BPi35_SSID    0x03c0
 206 #define SILICOM_PAC1200BPi35_SSID    0x03cc
 207 #define SILICOM_PE2G2BPFi35_SSID    0x03C1
 208 #define SILICOM_PE2G2BPFi35LX_SSID    0x03C2
 209 #define SILICOM_PE2G2BPFi35ZX_SSID    0x03C3
 210
 211 #define SILICOM_PE2G6BPi35_SSID    0x03E0
 212 #define SILICOM_PE2G6BPi35CX_SSID  0x0AA0
 213
 214 #define INTEL_PE210G2SPI9_SSID     0x00C
 215
 216 #define SILICOM_M1EG2BPI6_SSID     0x400
 217
 218 #define SILICOM_M1EG2BPFI6_SSID     0x0401
 219 #define SILICOM_M1EG2BPFI6LX_SSID     0x0402
 220 #define SILICOM_M1EG2BPFI6ZX_SSID     0x0403
 221
 222 #define SILICOM_M1EG4BPI6_SSID     0x0420
 223
 224 #define SILICOM_M1EG4BPFI6_SSID       0x0421
 225 #define SILICOM_M1EG4BPFI6LX_SSID     0x0422
 226 #define SILICOM_M1EG4BPFI6ZX_SSID     0x0423
 227
 228 #define SILICOM_M1EG6BPI6_SSID     0x0440
 229
 230 #define SILICOM_M1E2G4BPi80_SSID     0x0460
 231 #define SILICOM_M1E2G4BPFi80_SSID       0x0461
 232 #define SILICOM_M1E2G4BPFi80LX_SSID     0x0462
 233 #define SILICOM_M1E2G4BPFi80ZX_SSID     0x0463
 234
 235 #define SILICOM_M6E2G8BPi80_SSID        0x0470
 236 #define SILICOM_PE210G2BPi40_SSID       0x01a0
 237
 238 #define PEG540_IF_SERIES(pid) \
 239         ((pid == SILICOM_PE210G2BPi40_SSID))
 240
 241 #define OLD_IF_SERIES(pid)\
 242         ((pid == SILICOM_PXG2BPFI_SSID) || \
 243          (pid == SILICOM_PXG2BPFILX_SSID))
 244
 245 #define P2BPFI_IF_SERIES(pid) \
 246         ((pid == SILICOM_PXG2BPFI_SSID) || \
 247          (pid == SILICOM_PXG2BPFILX_SSID) || \
 248          (pid == SILICOM_PEG2BPFI_SSID) || \
 249          (pid == SILICOM_PEG2BPFID_SSID) || \
 250          (pid == SILICOM_PEG2BPFIDLX_SSID) || \
 251          (pid == SILICOM_MEG2BPFILN_SSID) || \
 252          (pid == SILICOM_MEG2BPFINX_SSID) || \
 253          (pid == SILICOM_PEG4BPFILX_SSID) || \
 254          (pid == SILICOM_PEG4BPFI_SSID) || \
 255          (pid == SILICOM_PXEG4BPFI_SSID) || \
 256          (pid == SILICOM_PXG4BPFID_SSID) || \
 257          (pid == SILICOM_PEG2TBFI_SSID) || \
 258          (pid == SILICOM_PE10G2BPISR_SSID) || \
 259          (pid == SILICOM_PE10G2BPILR_SSID) || \
 260          (pid == SILICOM_PEG2BPFILX_SSID) || \
 261          (pid == SILICOM_PMCXG2BPFI_SSID) || \
 262          (pid == SILICOM_MHIO8AD_SSID) || \
 263          (pid == SILICOM_PEG4BPFI5LX_SSID) || \
 264          (pid == SILICOM_PEG4BPFI5_SSID) || \
 265          (pid == SILICOM_PEG4BPFI6FC_SSID) || \
 266          (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
 267          (pid == SILICOM_PEG4BPFI6FCZX_SSID) || \
 268          (pid == NOKIA_PMCXG2BPFIN_SSID) || \
 269          (pid == SILICOM_MEG2BPFILXLN_SSID) || \
 270          (pid == SILICOM_MEG2BPFILXNX_SSID) || \
 271          (pid == SILICOM_XE10G2BPIT_SSID) || \
 272          (pid == SILICOM_XE10G2BPICX4_SSID) || \
 273          (pid == SILICOM_XE10G2BPISR_SSID) || \
 274          (pid == NOKIA_XE10G2BPIXR_SSID) || \
 275          (pid == SILICOM_PE10GDBISR_SSID) || \
 276          (pid == SILICOM_PE10GDBILR_SSID) || \
 277          (pid == SILICOM_XE10G2BPILR_SSID))
 278
 279 #define INTEL_IF_SERIES(pid) \
 280         ((pid == INTEL_PEG4BPII_SSID) || \
 281          (pid == INTEL_PEG4BPIIO_SSID) || \
 282          (pid == INTEL_PEG4BPFII_SSID))
 283
 284 #define NOKIA_SERIES(pid) \
 285         ((pid == NOKIA_PMCXG2BPIN_SSID) || \
 286          (pid == NOKIA_PMCXG4BPIN_SSID) || \
 287          (pid == SILICOM_PMCX4BPI_SSID) || \
 288          (pid == NOKIA_PMCXG2BPFIN_SSID) || \
 289          (pid == SILICOM_PMCXG2BPFI_SSID) || \
 290          (pid == NOKIA_PMCXG2BPIN2_SSID) || \
 291          (pid == NOKIA_PMCXG4BPIN2_SSID) || \
 292          (pid == SILICOM_PMCX2BPI_SSID))
 293
 294 #define DISCF_IF_SERIES(pid) \
 295         (pid == SILICOM_PEG2TBFI_SSID)
 296
 297 #define PEGF_IF_SERIES(pid) \
 298         ((pid == SILICOM_PEG2BPFI_SSID) || \
 299          (pid == SILICOM_PEG2BPFID_SSID) || \
 300          (pid == SILICOM_PEG2BPFIDLX_SSID) || \
 301          (pid == SILICOM_PEG2BPFILX_SSID) || \
 302          (pid == SILICOM_PEG4BPFI_SSID) || \
 303          (pid == SILICOM_PXEG4BPFI_SSID) || \
 304          (pid == SILICOM_MEG2BPFILN_SSID) || \
 305          (pid == SILICOM_MEG2BPFINX_SSID) || \
 306          (pid == SILICOM_PEG4BPFILX_SSID) || \
 307          (pid == SILICOM_PEG2TBFI_SSID) || \
 308          (pid == SILICOM_MEG2BPFILXLN_SSID) || \
 309          (pid == SILICOM_MEG2BPFILXNX_SSID))
 310
 311 #define TPL_IF_SERIES(pid) \
 312         ((pid == SILICOM_PXG2BPFIL_SSID) || \
 313          (pid == SILICOM_PXG2BPFILLX_SSID) || \
 314          (pid == SILICOM_PXG2TBFI_SSID) || \
 315          (pid == SILICOM_PXG4BPFID_SSID) || \
 316          (pid == SILICOM_PXG4BPFI_SSID))
 317
 318 #define BP10G_IF_SERIES(pid) \
 319         ((pid == SILICOM_PE10G2BPISR_SSID) || \
 320          (pid == SILICOM_PE10G2BPICX4_SSID) || \
 321          (pid == SILICOM_PE10G2BPILR_SSID) || \
 322          (pid == SILICOM_XE10G2BPIT_SSID) || \
 323          (pid == SILICOM_XE10G2BPICX4_SSID) || \
 324          (pid == SILICOM_XE10G2BPISR_SSID) || \
 325          (pid == NOKIA_XE10G2BPIXR_SSID) || \
 326          (pid == SILICOM_PE10GDBISR_SSID) || \
 327          (pid == SILICOM_PE10GDBILR_SSID) || \
 328          (pid == SILICOM_XE10G2BPILR_SSID))
 329
 330 #define BP10GB_IF_SERIES(pid) \
 331         ((pid == SILICOM_PE10G2BPTCX4_SSID) || \
 332          (pid == SILICOM_PE10G2BPTSR_SSID) || \
 333          (pid == SILICOM_PE10G2BPTLR_SSID) || \
 334          (pid == SILICOM_PE10G2BPTT_SSID))
 335
 336 #define BP10G_CX4_SERIES(pid) \
 337         (pid == SILICOM_PE10G2BPICX4_SSID)
 338
 339 #define BP10GB_CX4_SERIES(pid) \
 340         (pid == SILICOM_PE10G2BPTCX4_SSID)
 341
 342 #define SILICOM_M2EG2BPFI6_SSID       0x0501
 343 #define SILICOM_M2EG2BPFI6LX_SSID     0x0502
 344 #define SILICOM_M2EG2BPFI6ZX_SSID     0x0503
 345 #define SILICOM_M2EG4BPI6_SSID        0x0520
 346
 347 #define SILICOM_M2EG4BPFI6_SSID       0x0521
 348 #define SILICOM_M2EG4BPFI6LX_SSID     0x0522
 349 #define SILICOM_M2EG4BPFI6ZX_SSID     0x0523
 350
 351 #define SILICOM_M2EG6BPI6_SSID     0x0540
 352
 353 #define SILICOM_M1E10G2BPI9CX4_SSID  0x481
 354 #define SILICOM_M1E10G2BPI9SR_SSID   0x482
 355 #define SILICOM_M1E10G2BPI9LR_SSID   0x483
 356 #define SILICOM_M1E10G2BPI9T_SSID    0x480
 357
 358 #define SILICOM_M2E10G2BPI9CX4_SSID  0x581
 359 #define SILICOM_M2E10G2BPI9SR_SSID   0x582
 360 #define SILICOM_M2E10G2BPI9LR_SSID   0x583
 361 #define SILICOM_M2E10G2BPI9T_SSID    0x580
 362
 363 #define SILICOM_PE210G2BPI9CX4_SSID  0x121
 364 #define SILICOM_PE210G2BPI9SR_SSID   0x122
 365 #define SILICOM_PE210G2BPI9LR_SSID   0x123
 366 #define SILICOM_PE210G2BPI9T_SSID    0x120
 367
 368 #define DBI_IF_SERIES(pid) \
 369         ((pid == SILICOM_PE10GDBISR_SSID) || \
 370          (pid == SILICOM_PE10GDBILR_SSID) || \
 371          (pid == SILICOM_XE10G2BPILR_SSID) || \
 372          (pid == SILICOM_PE210G2DBi9LR_SSID))
 373
 374 #define PEGF5_IF_SERIES(pid) \
 375         ((pid == SILICOM_PEG2BPFI5_SSID) || \
 376          (pid == SILICOM_PEG2BPFI5LX_SSID) || \
 377          (pid == SILICOM_PEG4BPFI6_SSID) || \
 378          (pid == SILICOM_PEG4BPFI6LX_SSID) || \
 379          (pid == SILICOM_PEG4BPFI6ZX_SSID) || \
 380          (pid == SILICOM_PEG2BPFI6_SSID) || \
 381          (pid == SILICOM_PEG2BPFI6LX_SSID) || \
 382          (pid == SILICOM_PEG2BPFI6ZX_SSID) || \
 383          (pid == SILICOM_PEG2BPFI6FLXM_SSID) || \
 384          (pid == SILICOM_PEG2DBFI6_SSID) || \
 385          (pid == SILICOM_PEG2DBFI6LX_SSID) || \
 386          (pid == SILICOM_PEG2DBFI6ZX_SSID) || \
 387          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 388          (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
 389          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 390          (pid == SILICOM_M1EG2BPFI6_SSID) || \
 391          (pid == SILICOM_M1EG2BPFI6LX_SSID) || \
 392          (pid == SILICOM_M1EG2BPFI6ZX_SSID) || \
 393          (pid == SILICOM_M1EG4BPFI6_SSID) || \
 394          (pid == SILICOM_M1EG4BPFI6LX_SSID) || \
 395          (pid == SILICOM_M1EG4BPFI6ZX_SSID) || \
 396          (pid == SILICOM_M2EG2BPFI6_SSID) || \
 397          (pid == SILICOM_M2EG2BPFI6LX_SSID) || \
 398          (pid == SILICOM_M2EG2BPFI6ZX_SSID) || \
 399          (pid == SILICOM_M2EG4BPFI6_SSID) || \
 400          (pid == SILICOM_M2EG4BPFI6LX_SSID) || \
 401          (pid == SILICOM_M2EG4BPFI6ZX_SSID) || \
 402          (pid == SILICOM_PEG4BPFI6FCZX_SSID))
 403
 404 #define PEG5_IF_SERIES(pid) \
 405         ((pid == SILICOM_PEG4BPI6_SSID) || \
 406          (pid == SILICOM_PEG2BPI6_SSID) || \
 407          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 408          (pid == SILICOM_PEG6BPI6_SSID) || \
 409          (pid == SILICOM_PEG2BPI6SC6_SSID) || \
 410          (pid == SILICOM_MEG2BPI6_SSID) || \
 411          (pid == SILICOM_XEG2BPI6_SSID) || \
 412          (pid == SILICOM_MEG4BPI6_SSID) || \
 413          (pid == SILICOM_M1EG2BPI6_SSID) || \
 414          (pid == SILICOM_M1EG4BPI6_SSID) || \
 415          (pid == SILICOM_M1EG6BPI6_SSID) || \
 416          (pid == SILICOM_PEG6BPI_SSID) || \
 417          (pid == SILICOM_PEG4BPIL_SSID) || \
 418          (pid == SILICOM_PEG2BISC6_SSID) || \
 419          (pid == SILICOM_PEG2BPI5_SSID))
 420
 421 #define PEG80_IF_SERIES(pid) \
 422         ((pid == SILICOM_M1E2G4BPi80_SSID) || \
 423          (pid == SILICOM_M6E2G8BPi80_SSID) || \
 424          (pid == SILICOM_PE2G4BPi80L_SSID) || \
 425          (pid == SILICOM_M6E2G8BPi80A_SSID) || \
 426          (pid == SILICOM_PE2G2BPi35_SSID) || \
 427          (pid == SILICOM_PAC1200BPi35_SSID) || \
 428          (pid == SILICOM_PE2G4BPi35_SSID) || \
 429          (pid == SILICOM_PE2G4BPi35L_SSID) || \
 430          (pid == SILICOM_PE2G6BPi35_SSID) || \
 431          (pid == SILICOM_PE2G2BPi80_SSID) || \
 432          (pid == SILICOM_PE2G4BPi80_SSID) || \
 433          (pid == SILICOM_PE2G4BPFi80_SSID) || \
 434          (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
 435          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 436          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 437          (pid == SILICOM_PE2G2BPFi80_SSID) || \
 438          (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
 439          (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
 440          (pid == SILICOM_PE2G2BPFi35_SSID) || \
 441          (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
 442          (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
 443          (pid == SILICOM_PE2G4BPFi35_SSID) || \
 444          (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
 445          (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 446
 447 #define PEGF80_IF_SERIES(pid) \
 448         ((pid == SILICOM_PE2G4BPFi80_SSID) || \
 449          (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
 450          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 451          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 452          (pid == SILICOM_M1E2G4BPFi80_SSID) || \
 453          (pid == SILICOM_M1E2G4BPFi80LX_SSID) || \
 454          (pid == SILICOM_M1E2G4BPFi80ZX_SSID) || \
 455          (pid == SILICOM_PE2G2BPFi80_SSID) || \
 456          (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
 457          (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
 458          (pid == SILICOM_PE2G2BPFi35_SSID) || \
 459          (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
 460          (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
 461          (pid == SILICOM_PE2G4BPFi35_SSID) || \
 462          (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
 463          (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 464
 465 #define BP10G9_IF_SERIES(pid) \
 466         ((pid == INTEL_PE210G2SPI9_SSID) || \
 467          (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \
 468          (pid == SILICOM_M1E10G2BPI9SR_SSID) || \
 469          (pid == SILICOM_M1E10G2BPI9LR_SSID) || \
 470          (pid == SILICOM_M1E10G2BPI9T_SSID) || \
 471          (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \
 472          (pid == SILICOM_M2E10G2BPI9SR_SSID) || \
 473          (pid == SILICOM_M2E10G2BPI9LR_SSID) || \
 474          (pid == SILICOM_M2E10G2BPI9T_SSID) || \
 475          (pid == SILICOM_PE210G2BPI9CX4_SSID) || \
 476          (pid == SILICOM_PE210G2BPI9SR_SSID) || \
 477          (pid == SILICOM_PE210G2BPI9LR_SSID) || \
 478          (pid == SILICOM_PE210G2DBi9SR_SSID) || \
 479          (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \
 480          (pid == SILICOM_PE210G2DBi9LR_SSID) || \
 481          (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \
 482          (pid == SILICOM_PE310G4DBi940SR_SSID) || \
 483          (pid == SILICOM_PEG2BISC6_SSID) || \
 484          (pid == SILICOM_PE310G4BPi9T_SSID) || \
 485          (pid == SILICOM_PE310G4BPi9SR_SSID) || \
 486          (pid == SILICOM_PE310G4BPi9LR_SSID) || \
 487          (pid == SILICOM_PE210G2BPI9T_SSID))
 488
 489 /*******************************************************/
 490 /* 1G INTERFACE ****************************************/
 491 /*******************************************************/
 492
 493 /* Intel Registers */
 494 #define BPCTLI_CTRL          0x00000
 495 #define BPCTLI_CTRL_SWDPIO0  0x00400000
 496 #define BPCTLI_CTRL_SWDPIN0  0x00040000
 497
 498 #define BPCTLI_CTRL_EXT 0x00018 /* Extended Device Control - RW */
 499 #define BPCTLI_STATUS   0x00008 /* Device Status - RO */
 500
 501 /* HW related */
 502 #define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040    /* Value of SW Defineable Pin 6 */
 503 #define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080    /* Value of SW Defineable Pin 7 */
 504 #define BPCTLI_CTRL_SDP0_DATA     0x00040000    /* SWDPIN 0 value */
 505 #define BPCTLI_CTRL_EXT_SDP6_DIR  0x00000400    /* Direction of SDP6 0=in 1=out */
 506 #define BPCTLI_CTRL_EXT_SDP7_DIR  0x00000800    /* Direction of SDP7 0=in 1=out */
 507 #define BPCTLI_CTRL_SDP0_DIR      0x00400000    /* SDP0 Input or output */
 508 #define BPCTLI_CTRL_SWDPIN1       0x00080000
 509 #define BPCTLI_CTRL_SDP1_DIR      0x00800000
 510
 511 #define BPCTLI_STATUS_LU          0x00000002    /* Link up.0=no,1=link */
 512
 513 #define BPCTLI_CTRL_SDP0_SHIFT     18
 514 #define BPCTLI_CTRL_EXT_SDP6_SHIFT 6
 515
 516 #define BPCTLI_STATUS_TBIMODE     0x00000020
 517 #define BPCTLI_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
 518 #define BPCTLI_CTRL_EXT_LINK_MODE_MASK         0x00C00000
 519
 520 #define BPCTLI_CTRL_EXT_MCLK_DIR  BPCTLI_CTRL_EXT_SDP7_DIR
 521 #define BPCTLI_CTRL_EXT_MCLK_DATA BPCTLI_CTRL_EXT_SDP7_DATA
 522 #define BPCTLI_CTRL_EXT_MDIO_DIR  BPCTLI_CTRL_EXT_SDP6_DIR
 523 #define BPCTLI_CTRL_EXT_MDIO_DATA BPCTLI_CTRL_EXT_SDP6_DATA
 524
 525 #define BPCTLI_CTRL_EXT_MCLK_DIR5  BPCTLI_CTRL_SDP1_DIR
 526 #define BPCTLI_CTRL_EXT_MCLK_DATA5 BPCTLI_CTRL_SWDPIN1
 527 #define BPCTLI_CTRL_EXT_MCLK_DIR80  BPCTLI_CTRL_EXT_SDP6_DIR
 528 #define BPCTLI_CTRL_EXT_MCLK_DATA80 BPCTLI_CTRL_EXT_SDP6_DATA
 529 #define BPCTLI_CTRL_EXT_MDIO_DIR5  BPCTLI_CTRL_SWDPIO0
 530 #define BPCTLI_CTRL_EXT_MDIO_DATA5 BPCTLI_CTRL_SWDPIN0
 531 #define BPCTLI_CTRL_EXT_MDIO_DIR80  BPCTLI_CTRL_SWDPIO0
 532 #define BPCTLI_CTRL_EXT_MDIO_DATA80 BPCTLI_CTRL_SWDPIN0
 533
 534 #define BPCTL_WRITE_REG(a, reg, value) \
 535         (writel((value), (void *)(((a)->mem_map) + BPCTLI_##reg)))
 536
 537 #define BPCTL_READ_REG(a, reg) ( \
 538         readl((void *)((a)->mem_map) + BPCTLI_##reg))
 539
 540 #define BPCTL_WRITE_FLUSH(a) BPCTL_READ_REG(a, STATUS)
 541
 542 #define BPCTL_BP_WRITE_REG(a, reg, value) ({ \
 543         BPCTL_WRITE_REG(a, reg, value); \
 544         BPCTL_WRITE_FLUSH(a); })
 545
 546 /**************************************************************/
 547 /************** 82575 Interface********************************/
 548 /**************************************************************/
 549
 550 #define BPCTLI_MII_CR_POWER_DOWN       0x0800
 551 #define BPCTLI_PHY_CONTROL      0x00    /* Control Register */
 552 #define BPCTLI_MDIC     0x00020 /* MDI Control - RW */
 553 #define BPCTLI_IGP01E1000_PHY_PAGE_SELECT        0x1F   /* Page Select */
 554 #define BPCTLI_MAX_PHY_REG_ADDRESS    0x1F      /* 5 bit address bus (0-0x1F) */
 555
 556 #define BPCTLI_MDIC_DATA_MASK 0x0000FFFF
 557 #define BPCTLI_MDIC_REG_MASK  0x001F0000
 558 #define BPCTLI_MDIC_REG_SHIFT 16
 559 #define BPCTLI_MDIC_PHY_MASK  0x03E00000
 560 #define BPCTLI_MDIC_PHY_SHIFT 21
 561 #define BPCTLI_MDIC_OP_WRITE  0x04000000
 562 #define BPCTLI_MDIC_OP_READ   0x08000000
 563 #define BPCTLI_MDIC_READY     0x10000000
 564 #define BPCTLI_MDIC_INT_EN    0x20000000
 565 #define BPCTLI_MDIC_ERROR     0x40000000
 566
 567 #define BPCTLI_SWFW_PHY0_SM  0x02
 568 #define BPCTLI_SWFW_PHY1_SM  0x04
 569
 570 #define BPCTLI_SW_FW_SYNC  0x05B5C      /* Software-Firmware Synchronization - RW */
 571
 572 #define BPCTLI_SWSM      0x05B50        /* SW Semaphore */
 573 #define BPCTLI_FWSM      0x05B54        /* FW Semaphore */
 574
 575 #define BPCTLI_SWSM_SMBI         0x00000001     /* Driver Semaphore bit */
 576 #define BPCTLI_SWSM_SWESMBI      0x00000002     /* FW Semaphore bit */
 577 #define BPCTLI_MAX_PHY_MULTI_PAGE_REG 0xF
 578 #define BPCTLI_GEN_POLL_TIMEOUT          640
 579
 580 /********************************************************/
 581
 582 /********************************************************/
 583 /* 10G INTERFACE ****************************************/
 584 /********************************************************/
 585
 586 #define BP10G_I2CCTL              0x28
 587
 588 /* I2CCTL Bit Masks */
 589 #define BP10G_I2C_CLK_IN    0x00000001
 590 #define BP10G_I2C_CLK_OUT   0x00000002
 591 #define BP10G_I2C_DATA_IN   0x00000004
 592 #define BP10G_I2C_DATA_OUT  0x00000008
 593
 594 #define BP10G_ESDP                0x20
 595
 596 #define BP10G_SDP0_DIR            0x100
 597 #define BP10G_SDP1_DIR            0x200
 598 #define BP10G_SDP3_DIR            0x800
 599 #define BP10G_SDP4_DIR            BIT_12
 600 #define BP10G_SDP5_DIR            0x2000
 601 #define BP10G_SDP0_DATA           0x001
 602 #define BP10G_SDP1_DATA           0x002
 603 #define BP10G_SDP3_DATA           0x008
 604 #define BP10G_SDP4_DATA           0x010
 605 #define BP10G_SDP5_DATA           0x020
 606
 607 #define BP10G_SDP2_DIR            0x400
 608 #define BP10G_SDP2_DATA            0x4
 609
 610 #define BP10G_EODSDP              0x28
 611
 612 #define BP10G_SDP6_DATA_IN        0x001
 613 #define BP10G_SDP6_DATA_OUT       0x002
 614
 615 #define BP10G_SDP7_DATA_IN        0x004
 616 #define BP10G_SDP7_DATA_OUT       0x008
 617
 618 #define BP10G_MCLK_DATA_OUT       BP10G_SDP7_DATA_OUT
 619 #define BP10G_MDIO_DATA_OUT       BP10G_SDP6_DATA_OUT
 620 #define BP10G_MDIO_DATA_IN        BP10G_SDP6_DATA_IN
 621
 622 #define BP10G_MDIO_DATA           /*BP10G_SDP5_DATA*/ BP10G_SDP3_DATA
 623 #define BP10G_MDIO_DIR            /*BP10G_SDP5_DIR*/  BP10G_SDP3_DATA
 624
 625 /*#define BP10G_MCLK_DATA_OUT9       BP10G_I2C_CLK_OUT
 626 #define BP10G_MDIO_DATA_OUT9       BP10G_I2C_DATA_OUT*/
 627
 628                                        /*#define BP10G_MCLK_DATA_OUT9*//*BP10G_I2C_DATA_OUT */
 629 #define BP10G_MDIO_DATA_OUT9           BP10G_I2C_DATA_OUT       /*BP10G_I2C_CLK_OUT */
 630
 631 /* VIA EOSDP ! */
 632 #define BP10G_MCLK_DATA_OUT9           BP10G_SDP4_DATA
 633 #define BP10G_MCLK_DIR_OUT9            BP10G_SDP4_DIR
 634
 635 /*#define BP10G_MDIO_DATA_IN9        BP10G_I2C_DATA_IN*/
 636
 637 #define BP10G_MDIO_DATA_IN9           BP10G_I2C_DATA_IN /*BP10G_I2C_CLK_IN */
 638
 639 #define BP540_MDIO_DATA           /*BP10G_SDP5_DATA*/ BP10G_SDP0_DATA
 640 #define BP540_MDIO_DIR            /*BP10G_SDP5_DIR*/  BP10G_SDP0_DIR
 641 #define BP540_MCLK_DATA       BP10G_SDP2_DATA
 642 #define BP540_MCLK_DIR       BP10G_SDP2_DIR
 643
 644 #define BP10G_WRITE_REG(a, reg, value) \
 645         (writel((value), (void *)(((a)->mem_map) + BP10G_##reg)))
 646
 647 #define BP10G_READ_REG(a, reg) ( \
 648         readl((void *)((a)->mem_map) + BP10G_##reg))
 649
 650 /*****BROADCOM*******************************************/
 651
 652 #define BP10GB_MISC_REG_GPIO                                             0xa490
 653 #define BP10GB_GPIO3_P0                              BIT_3
 654 #define BP10GB_GPIO3_P1                              BIT_7
 655
 656 #define BP10GB_GPIO3_SET_P0                          BIT_11
 657 #define BP10GB_GPIO3_CLR_P0                          BIT_19
 658 #define BP10GB_GPIO3_OE_P0                           BIT_27
 659
 660 #define BP10GB_GPIO3_SET_P1                          BIT_15
 661 #define BP10GB_GPIO3_CLR_P1                          BIT_23
 662 #define BP10GB_GPIO3_OE_P1                           BIT_31
 663
 664 #define BP10GB_GPIO0_P1                              0x10
 665 #define BP10GB_GPIO0_P0                              0x1
 666 #define BP10GB_GPIO0_CLR_P0                          0x10000
 667 #define BP10GB_GPIO0_CLR_P1                          0x100000
 668 #define BP10GB_GPIO0_SET_P0                          0x100
 669 #define BP10GB_GPIO0_SET_P1                          0x1000
 670
 671 #define BP10GB_GPIO0_OE_P1                           0x10000000
 672 #define BP10GB_GPIO0_OE_P0                           0x1000000
 673
 674 #define BP10GB_MISC_REG_SPIO                                             0xa4fc
 675 #define BP10GB_GPIO4_OE                              BIT_28
 676 #define BP10GB_GPIO5_OE                              BIT_29
 677 #define BP10GB_GPIO4_CLR                             BIT_20
 678 #define BP10GB_GPIO5_CLR                             BIT_21
 679 #define BP10GB_GPIO4_SET                             BIT_12
 680 #define BP10GB_GPIO5_SET                             BIT_13
 681 #define BP10GB_GPIO4                                 BIT_4
 682 #define BP10GB_GPIO5                                 BIT_5
 683
 684 #define BP10GB_MCLK_DIR  BP10GB_GPIO5_OE
 685 #define BP10GB_MDIO_DIR  BP10GB_GPIO4_OE
 686
 687 #define BP10GB_MCLK_DATA BP10GB_GPIO5
 688 #define BP10GB_MDIO_DATA BP10GB_GPIO4
 689
 690 #define BP10GB_MCLK_SET BP10GB_GPIO5_SET
 691 #define BP10GB_MDIO_SET BP10GB_GPIO4_SET
 692
 693 #define BP10GB_MCLK_CLR BP10GB_GPIO5_CLR
 694 #define BP10GB_MDIO_CLR BP10GB_GPIO4_CLR
 695
 696 #define BP10GB_WRITE_REG(a, reg, value) \
 697         (writel((value), (void *)(((a)->mem_map) + BP10GB_##reg)))
 698
 699 #define BP10GB_READ_REG(a, reg) ( \
 700         readl((void *)((a)->mem_map) + BP10GB_##reg))
 701
 702 #endif
 703
 704 int bp_proc_create(void);