2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define NVME_IO_TIMEOUT (5 * HZ)
50 #define ADMIN_TIMEOUT (60 * HZ)
52 static int nvme_major
;
53 module_param(nvme_major
, int, 0);
55 static int use_threaded_interrupts
;
56 module_param(use_threaded_interrupts
, int, 0);
58 static DEFINE_SPINLOCK(dev_list_lock
);
59 static LIST_HEAD(dev_list
);
60 static struct task_struct
*nvme_thread
;
63 * Represents an NVM Express device. Each nvme_dev is a PCI function.
66 struct list_head node
;
67 struct nvme_queue
**queues
;
69 struct pci_dev
*pci_dev
;
70 struct dma_pool
*prp_page_pool
;
71 struct dma_pool
*prp_small_pool
;
76 struct msix_entry
*entry
;
77 struct nvme_bar __iomem
*bar
;
78 struct list_head namespaces
;
86 * An NVM Express namespace is equivalent to a SCSI LUN
89 struct list_head list
;
92 struct request_queue
*queue
;
100 * An NVM Express queue. Each device has at least two (one for admin
101 * commands and one for I/O commands).
104 struct device
*q_dmadev
;
105 struct nvme_dev
*dev
;
107 struct nvme_command
*sq_cmds
;
108 volatile struct nvme_completion
*cqes
;
109 dma_addr_t sq_dma_addr
;
110 dma_addr_t cq_dma_addr
;
111 wait_queue_head_t sq_full
;
112 wait_queue_t sq_cong_wait
;
113 struct bio_list sq_cong
;
121 unsigned long cmdid_data
[];
125 * Check we didin't inadvertently grow the command struct
127 static inline void _nvme_check_size(void)
129 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
140 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
141 struct nvme_completion
*);
143 struct nvme_cmd_info
{
144 nvme_completion_fn fn
;
146 unsigned long timeout
;
149 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
151 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
155 * alloc_cmdid() - Allocate a Command ID
156 * @nvmeq: The queue that will be used for this command
157 * @ctx: A pointer that will be passed to the handler
158 * @handler: The function to call on completion
160 * Allocate a Command ID for a queue. The data passed in will
161 * be passed to the completion handler. This is implemented by using
162 * the bottom two bits of the ctx pointer to store the handler ID.
163 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
164 * We can change this if it becomes a problem.
166 * May be called with local interrupts disabled and the q_lock held,
167 * or with interrupts enabled and no locks held.
169 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
170 nvme_completion_fn handler
, unsigned timeout
)
172 int depth
= nvmeq
->q_depth
- 1;
173 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
177 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
180 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
182 info
[cmdid
].fn
= handler
;
183 info
[cmdid
].ctx
= ctx
;
184 info
[cmdid
].timeout
= jiffies
+ timeout
;
188 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
189 nvme_completion_fn handler
, unsigned timeout
)
192 wait_event_killable(nvmeq
->sq_full
,
193 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
194 return (cmdid
< 0) ? -EINTR
: cmdid
;
197 /* Special values must be less than 0x1000 */
198 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
199 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
200 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
201 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
202 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
204 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
205 struct nvme_completion
*cqe
)
207 if (ctx
== CMD_CTX_CANCELLED
)
209 if (ctx
== CMD_CTX_FLUSH
)
211 if (ctx
== CMD_CTX_COMPLETED
) {
212 dev_warn(&dev
->pci_dev
->dev
,
213 "completed id %d twice on queue %d\n",
214 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
217 if (ctx
== CMD_CTX_INVALID
) {
218 dev_warn(&dev
->pci_dev
->dev
,
219 "invalid id %d completed on queue %d\n",
220 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
224 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
228 * Called with local interrupts disabled and the q_lock held. May not sleep.
230 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
231 nvme_completion_fn
*fn
)
234 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
236 if (cmdid
>= nvmeq
->q_depth
) {
237 *fn
= special_completion
;
238 return CMD_CTX_INVALID
;
240 *fn
= info
[cmdid
].fn
;
241 ctx
= info
[cmdid
].ctx
;
242 info
[cmdid
].fn
= special_completion
;
243 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
244 clear_bit(cmdid
, nvmeq
->cmdid_data
);
245 wake_up(&nvmeq
->sq_full
);
249 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
250 nvme_completion_fn
*fn
)
253 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
255 *fn
= info
[cmdid
].fn
;
256 ctx
= info
[cmdid
].ctx
;
257 info
[cmdid
].fn
= special_completion
;
258 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
262 static struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
264 return dev
->queues
[get_cpu() + 1];
267 static void put_nvmeq(struct nvme_queue
*nvmeq
)
273 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
274 * @nvmeq: The queue to use
275 * @cmd: The command to send
277 * Safe to use from interrupt context
279 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
283 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
284 tail
= nvmeq
->sq_tail
;
285 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
286 if (++tail
== nvmeq
->q_depth
)
288 writel(tail
, nvmeq
->q_db
);
289 nvmeq
->sq_tail
= tail
;
290 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
296 * The nvme_iod describes the data in an I/O, including the list of PRP
297 * entries. You can't see it in this data structure because C doesn't let
298 * me express that. Use nvme_alloc_iod to ensure there's enough space
299 * allocated to store the PRP list.
302 void *private; /* For the use of the submitter of the I/O */
303 int npages
; /* In the PRP list. 0 means small pool in use */
304 int offset
; /* Of PRP list */
305 int nents
; /* Used in scatterlist */
306 int length
; /* Of data, in bytes */
307 dma_addr_t first_dma
;
308 struct scatterlist sg
[0];
311 static __le64
**iod_list(struct nvme_iod
*iod
)
313 return ((void *)iod
) + iod
->offset
;
317 * Will slightly overestimate the number of pages needed. This is OK
318 * as it only leads to a small amount of wasted memory for the lifetime of
321 static int nvme_npages(unsigned size
)
323 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
324 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
327 static struct nvme_iod
*
328 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
330 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
331 sizeof(__le64
*) * nvme_npages(nbytes
) +
332 sizeof(struct scatterlist
) * nseg
, gfp
);
335 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
337 iod
->length
= nbytes
;
343 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
345 const int last_prp
= PAGE_SIZE
/ 8 - 1;
347 __le64
**list
= iod_list(iod
);
348 dma_addr_t prp_dma
= iod
->first_dma
;
350 if (iod
->npages
== 0)
351 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
352 for (i
= 0; i
< iod
->npages
; i
++) {
353 __le64
*prp_list
= list
[i
];
354 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
355 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
356 prp_dma
= next_prp_dma
;
361 static void requeue_bio(struct nvme_dev
*dev
, struct bio
*bio
)
363 struct nvme_queue
*nvmeq
= get_nvmeq(dev
);
364 if (bio_list_empty(&nvmeq
->sq_cong
))
365 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
366 bio_list_add(&nvmeq
->sq_cong
, bio
);
368 wake_up_process(nvme_thread
);
371 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
372 struct nvme_completion
*cqe
)
374 struct nvme_iod
*iod
= ctx
;
375 struct bio
*bio
= iod
->private;
376 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
378 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
379 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
380 nvme_free_iod(dev
, iod
);
382 bio_endio(bio
, -EIO
);
383 } else if (bio
->bi_vcnt
> bio
->bi_idx
) {
384 requeue_bio(dev
, bio
);
390 /* length is in bytes. gfp flags indicates whether we may sleep. */
391 static int nvme_setup_prps(struct nvme_dev
*dev
,
392 struct nvme_common_command
*cmd
, struct nvme_iod
*iod
,
393 int total_len
, gfp_t gfp
)
395 struct dma_pool
*pool
;
396 int length
= total_len
;
397 struct scatterlist
*sg
= iod
->sg
;
398 int dma_len
= sg_dma_len(sg
);
399 u64 dma_addr
= sg_dma_address(sg
);
400 int offset
= offset_in_page(dma_addr
);
402 __le64
**list
= iod_list(iod
);
406 cmd
->prp1
= cpu_to_le64(dma_addr
);
407 length
-= (PAGE_SIZE
- offset
);
411 dma_len
-= (PAGE_SIZE
- offset
);
413 dma_addr
+= (PAGE_SIZE
- offset
);
416 dma_addr
= sg_dma_address(sg
);
417 dma_len
= sg_dma_len(sg
);
420 if (length
<= PAGE_SIZE
) {
421 cmd
->prp2
= cpu_to_le64(dma_addr
);
425 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
426 if (nprps
<= (256 / 8)) {
427 pool
= dev
->prp_small_pool
;
430 pool
= dev
->prp_page_pool
;
434 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
436 cmd
->prp2
= cpu_to_le64(dma_addr
);
438 return (total_len
- length
) + PAGE_SIZE
;
441 iod
->first_dma
= prp_dma
;
442 cmd
->prp2
= cpu_to_le64(prp_dma
);
445 if (i
== PAGE_SIZE
/ 8) {
446 __le64
*old_prp_list
= prp_list
;
447 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
449 return total_len
- length
;
450 list
[iod
->npages
++] = prp_list
;
451 prp_list
[0] = old_prp_list
[i
- 1];
452 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
455 prp_list
[i
++] = cpu_to_le64(dma_addr
);
456 dma_len
-= PAGE_SIZE
;
457 dma_addr
+= PAGE_SIZE
;
465 dma_addr
= sg_dma_address(sg
);
466 dma_len
= sg_dma_len(sg
);
472 /* NVMe scatterlists require no holes in the virtual address */
473 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
474 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
476 static int nvme_map_bio(struct device
*dev
, struct nvme_iod
*iod
,
477 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
479 struct bio_vec
*bvec
, *bvprv
= NULL
;
480 struct scatterlist
*sg
= NULL
;
481 int i
, old_idx
, length
= 0, nsegs
= 0;
483 sg_init_table(iod
->sg
, psegs
);
484 old_idx
= bio
->bi_idx
;
485 bio_for_each_segment(bvec
, bio
, i
) {
486 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
487 sg
->length
+= bvec
->bv_len
;
489 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
491 sg
= sg
? sg
+ 1 : iod
->sg
;
492 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
496 length
+= bvec
->bv_len
;
502 if (dma_map_sg(dev
, iod
->sg
, iod
->nents
, dma_dir
) == 0) {
503 bio
->bi_idx
= old_idx
;
509 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
512 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
514 memset(cmnd
, 0, sizeof(*cmnd
));
515 cmnd
->common
.opcode
= nvme_cmd_flush
;
516 cmnd
->common
.command_id
= cmdid
;
517 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
519 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
521 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
526 static int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
528 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
529 special_completion
, NVME_IO_TIMEOUT
);
530 if (unlikely(cmdid
< 0))
533 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
537 * Called with local interrupts disabled and the q_lock held. May not sleep.
539 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
542 struct nvme_command
*cmnd
;
543 struct nvme_iod
*iod
;
544 enum dma_data_direction dma_dir
;
545 int cmdid
, length
, result
= -ENOMEM
;
548 int psegs
= bio_phys_segments(ns
->queue
, bio
);
550 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
551 result
= nvme_submit_flush_data(nvmeq
, ns
);
556 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
562 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
563 if (unlikely(cmdid
< 0))
566 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
567 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
570 if (bio
->bi_rw
& REQ_FUA
)
571 control
|= NVME_RW_FUA
;
572 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
573 control
|= NVME_RW_LR
;
576 if (bio
->bi_rw
& REQ_RAHEAD
)
577 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
579 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
581 memset(cmnd
, 0, sizeof(*cmnd
));
582 if (bio_data_dir(bio
)) {
583 cmnd
->rw
.opcode
= nvme_cmd_write
;
584 dma_dir
= DMA_TO_DEVICE
;
586 cmnd
->rw
.opcode
= nvme_cmd_read
;
587 dma_dir
= DMA_FROM_DEVICE
;
590 result
= nvme_map_bio(nvmeq
->q_dmadev
, iod
, bio
, dma_dir
, psegs
);
595 cmnd
->rw
.command_id
= cmdid
;
596 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
597 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
599 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
600 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
601 cmnd
->rw
.control
= cpu_to_le16(control
);
602 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
604 bio
->bi_sector
+= length
>> 9;
606 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
608 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
613 nvme_free_iod(nvmeq
->dev
, iod
);
618 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
620 struct nvme_ns
*ns
= q
->queuedata
;
621 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
624 spin_lock_irq(&nvmeq
->q_lock
);
625 if (bio_list_empty(&nvmeq
->sq_cong
))
626 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
627 if (unlikely(result
)) {
628 if (bio_list_empty(&nvmeq
->sq_cong
))
629 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
630 bio_list_add(&nvmeq
->sq_cong
, bio
);
633 spin_unlock_irq(&nvmeq
->q_lock
);
637 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
641 head
= nvmeq
->cq_head
;
642 phase
= nvmeq
->cq_phase
;
646 nvme_completion_fn fn
;
647 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
648 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
650 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
651 if (++head
== nvmeq
->q_depth
) {
656 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
657 fn(nvmeq
->dev
, ctx
, &cqe
);
660 /* If the controller ignores the cq head doorbell and continuously
661 * writes to the queue, it is theoretically possible to wrap around
662 * the queue twice and mistakenly return IRQ_NONE. Linux only
663 * requires that 0.1% of your interrupts are handled, so this isn't
666 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
669 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
670 nvmeq
->cq_head
= head
;
671 nvmeq
->cq_phase
= phase
;
676 static irqreturn_t
nvme_irq(int irq
, void *data
)
679 struct nvme_queue
*nvmeq
= data
;
680 spin_lock(&nvmeq
->q_lock
);
681 result
= nvme_process_cq(nvmeq
);
682 spin_unlock(&nvmeq
->q_lock
);
686 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
688 struct nvme_queue
*nvmeq
= data
;
689 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
690 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
692 return IRQ_WAKE_THREAD
;
695 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
697 spin_lock_irq(&nvmeq
->q_lock
);
698 cancel_cmdid(nvmeq
, cmdid
, NULL
);
699 spin_unlock_irq(&nvmeq
->q_lock
);
702 struct sync_cmd_info
{
703 struct task_struct
*task
;
708 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
709 struct nvme_completion
*cqe
)
711 struct sync_cmd_info
*cmdinfo
= ctx
;
712 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
713 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
714 wake_up_process(cmdinfo
->task
);
718 * Returns 0 on success. If the result is negative, it's a Linux error code;
719 * if the result is positive, it's an NVM Express status code
721 static int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
,
722 struct nvme_command
*cmd
, u32
*result
, unsigned timeout
)
725 struct sync_cmd_info cmdinfo
;
727 cmdinfo
.task
= current
;
728 cmdinfo
.status
= -EINTR
;
730 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
734 cmd
->common
.command_id
= cmdid
;
736 set_current_state(TASK_KILLABLE
);
737 nvme_submit_cmd(nvmeq
, cmd
);
740 if (cmdinfo
.status
== -EINTR
) {
741 nvme_abort_command(nvmeq
, cmdid
);
746 *result
= cmdinfo
.result
;
748 return cmdinfo
.status
;
751 static int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
754 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
757 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
760 struct nvme_command c
;
762 memset(&c
, 0, sizeof(c
));
763 c
.delete_queue
.opcode
= opcode
;
764 c
.delete_queue
.qid
= cpu_to_le16(id
);
766 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
772 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
773 struct nvme_queue
*nvmeq
)
776 struct nvme_command c
;
777 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
779 memset(&c
, 0, sizeof(c
));
780 c
.create_cq
.opcode
= nvme_admin_create_cq
;
781 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
782 c
.create_cq
.cqid
= cpu_to_le16(qid
);
783 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
784 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
785 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
787 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
793 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
794 struct nvme_queue
*nvmeq
)
797 struct nvme_command c
;
798 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
800 memset(&c
, 0, sizeof(c
));
801 c
.create_sq
.opcode
= nvme_admin_create_sq
;
802 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
803 c
.create_sq
.sqid
= cpu_to_le16(qid
);
804 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
805 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
806 c
.create_sq
.cqid
= cpu_to_le16(qid
);
808 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
814 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
816 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
819 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
821 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
824 static int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
827 struct nvme_command c
;
829 memset(&c
, 0, sizeof(c
));
830 c
.identify
.opcode
= nvme_admin_identify
;
831 c
.identify
.nsid
= cpu_to_le32(nsid
);
832 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
833 c
.identify
.cns
= cpu_to_le32(cns
);
835 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
838 static int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
,
839 unsigned nsid
, dma_addr_t dma_addr
)
841 struct nvme_command c
;
843 memset(&c
, 0, sizeof(c
));
844 c
.features
.opcode
= nvme_admin_get_features
;
845 c
.features
.nsid
= cpu_to_le32(nsid
);
846 c
.features
.prp1
= cpu_to_le64(dma_addr
);
847 c
.features
.fid
= cpu_to_le32(fid
);
849 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
852 static int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
,
853 unsigned dword11
, dma_addr_t dma_addr
, u32
*result
)
855 struct nvme_command c
;
857 memset(&c
, 0, sizeof(c
));
858 c
.features
.opcode
= nvme_admin_set_features
;
859 c
.features
.prp1
= cpu_to_le64(dma_addr
);
860 c
.features
.fid
= cpu_to_le32(fid
);
861 c
.features
.dword11
= cpu_to_le32(dword11
);
863 return nvme_submit_admin_cmd(dev
, &c
, result
);
867 * nvme_cancel_ios - Cancel outstanding I/Os
868 * @queue: The queue to cancel I/Os on
869 * @timeout: True to only cancel I/Os which have timed out
871 static void nvme_cancel_ios(struct nvme_queue
*nvmeq
, bool timeout
)
873 int depth
= nvmeq
->q_depth
- 1;
874 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
875 unsigned long now
= jiffies
;
878 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
880 nvme_completion_fn fn
;
881 static struct nvme_completion cqe
= {
882 .status
= cpu_to_le16(NVME_SC_ABORT_REQ
) << 1,
885 if (timeout
&& !time_after(now
, info
[cmdid
].timeout
))
887 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d\n", cmdid
);
888 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
889 fn(nvmeq
->dev
, ctx
, &cqe
);
893 static void nvme_free_queue_mem(struct nvme_queue
*nvmeq
)
895 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
896 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
897 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
898 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
902 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
904 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
905 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
907 spin_lock_irq(&nvmeq
->q_lock
);
908 nvme_cancel_ios(nvmeq
, false);
909 spin_unlock_irq(&nvmeq
->q_lock
);
911 irq_set_affinity_hint(vector
, NULL
);
912 free_irq(vector
, nvmeq
);
914 /* Don't tell the adapter to delete the admin queue */
916 adapter_delete_sq(dev
, qid
);
917 adapter_delete_cq(dev
, qid
);
920 nvme_free_queue_mem(nvmeq
);
923 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
924 int depth
, int vector
)
926 struct device
*dmadev
= &dev
->pci_dev
->dev
;
927 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
928 sizeof(struct nvme_cmd_info
));
929 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
933 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
934 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
937 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
939 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
940 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
944 nvmeq
->q_dmadev
= dmadev
;
946 spin_lock_init(&nvmeq
->q_lock
);
949 init_waitqueue_head(&nvmeq
->sq_full
);
950 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
951 bio_list_init(&nvmeq
->sq_cong
);
952 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
953 nvmeq
->q_depth
= depth
;
954 nvmeq
->cq_vector
= vector
;
959 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
966 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
969 if (use_threaded_interrupts
)
970 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
971 nvme_irq_check
, nvme_irq
,
972 IRQF_DISABLED
| IRQF_SHARED
,
974 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
975 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
978 static struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
, int qid
,
979 int cq_size
, int vector
)
982 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
985 return ERR_PTR(-ENOMEM
);
987 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
991 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
995 result
= queue_request_irq(dev
, nvmeq
, "nvme");
1002 adapter_delete_sq(dev
, qid
);
1004 adapter_delete_cq(dev
, qid
);
1006 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1007 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1008 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1009 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1011 return ERR_PTR(result
);
1014 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1019 unsigned long timeout
;
1020 struct nvme_queue
*nvmeq
;
1022 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1024 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
1028 aqa
= nvmeq
->q_depth
- 1;
1031 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1032 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1033 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1034 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1036 writel(0, &dev
->bar
->cc
);
1037 writel(aqa
, &dev
->bar
->aqa
);
1038 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1039 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1040 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1042 cap
= readq(&dev
->bar
->cap
);
1043 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1044 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1046 while (!result
&& !(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1048 if (fatal_signal_pending(current
))
1050 if (time_after(jiffies
, timeout
)) {
1051 dev_err(&dev
->pci_dev
->dev
,
1052 "Device not ready; aborting initialisation\n");
1058 nvme_free_queue_mem(nvmeq
);
1062 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1063 dev
->queues
[0] = nvmeq
;
1067 static struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1068 unsigned long addr
, unsigned length
)
1070 int i
, err
, count
, nents
, offset
;
1071 struct scatterlist
*sg
;
1072 struct page
**pages
;
1073 struct nvme_iod
*iod
;
1076 return ERR_PTR(-EINVAL
);
1078 return ERR_PTR(-EINVAL
);
1080 offset
= offset_in_page(addr
);
1081 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1082 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1084 return ERR_PTR(-ENOMEM
);
1086 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1093 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1095 sg_init_table(sg
, count
);
1096 for (i
= 0; i
< count
; i
++) {
1097 sg_set_page(&sg
[i
], pages
[i
],
1098 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1099 length
-= (PAGE_SIZE
- offset
);
1102 sg_mark_end(&sg
[i
- 1]);
1106 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1107 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1117 for (i
= 0; i
< count
; i
++)
1120 return ERR_PTR(err
);
1123 static void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1124 struct nvme_iod
*iod
)
1128 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1129 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1131 for (i
= 0; i
< iod
->nents
; i
++)
1132 put_page(sg_page(&iod
->sg
[i
]));
1135 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1137 struct nvme_dev
*dev
= ns
->dev
;
1138 struct nvme_queue
*nvmeq
;
1139 struct nvme_user_io io
;
1140 struct nvme_command c
;
1143 struct nvme_iod
*iod
;
1145 if (copy_from_user(&io
, uio
, sizeof(io
)))
1147 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1149 switch (io
.opcode
) {
1150 case nvme_cmd_write
:
1152 case nvme_cmd_compare
:
1153 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1160 return PTR_ERR(iod
);
1162 memset(&c
, 0, sizeof(c
));
1163 c
.rw
.opcode
= io
.opcode
;
1164 c
.rw
.flags
= io
.flags
;
1165 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1166 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1167 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1168 c
.rw
.control
= cpu_to_le16(io
.control
);
1169 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
1170 c
.rw
.reftag
= io
.reftag
;
1171 c
.rw
.apptag
= io
.apptag
;
1172 c
.rw
.appmask
= io
.appmask
;
1174 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1176 nvmeq
= get_nvmeq(dev
);
1178 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1179 * disabled. We may be preempted at any point, and be rescheduled
1180 * to a different CPU. That will cause cacheline bouncing, but no
1181 * additional races since q_lock already protects against other CPUs.
1184 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1187 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1189 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1190 nvme_free_iod(dev
, iod
);
1194 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1195 struct nvme_admin_cmd __user
*ucmd
)
1197 struct nvme_admin_cmd cmd
;
1198 struct nvme_command c
;
1200 struct nvme_iod
*uninitialized_var(iod
);
1202 if (!capable(CAP_SYS_ADMIN
))
1204 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1207 memset(&c
, 0, sizeof(c
));
1208 c
.common
.opcode
= cmd
.opcode
;
1209 c
.common
.flags
= cmd
.flags
;
1210 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1211 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1212 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1213 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1214 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1215 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1216 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1217 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1218 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1220 length
= cmd
.data_len
;
1222 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1225 return PTR_ERR(iod
);
1226 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1230 if (length
!= cmd
.data_len
)
1233 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
1236 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1237 nvme_free_iod(dev
, iod
);
1242 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1245 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1250 case NVME_IOCTL_ADMIN_CMD
:
1251 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1252 case NVME_IOCTL_SUBMIT_IO
:
1253 return nvme_submit_io(ns
, (void __user
*)arg
);
1259 static const struct block_device_operations nvme_fops
= {
1260 .owner
= THIS_MODULE
,
1261 .ioctl
= nvme_ioctl
,
1262 .compat_ioctl
= nvme_ioctl
,
1265 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1267 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1268 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1269 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1270 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1271 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1274 if (bio_list_empty(&nvmeq
->sq_cong
))
1275 remove_wait_queue(&nvmeq
->sq_full
,
1276 &nvmeq
->sq_cong_wait
);
1280 static int nvme_kthread(void *data
)
1282 struct nvme_dev
*dev
;
1284 while (!kthread_should_stop()) {
1285 __set_current_state(TASK_RUNNING
);
1286 spin_lock(&dev_list_lock
);
1287 list_for_each_entry(dev
, &dev_list
, node
) {
1289 for (i
= 0; i
< dev
->queue_count
; i
++) {
1290 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1293 spin_lock_irq(&nvmeq
->q_lock
);
1294 if (nvme_process_cq(nvmeq
))
1295 printk("process_cq did something\n");
1296 nvme_cancel_ios(nvmeq
, true);
1297 nvme_resubmit_bios(nvmeq
);
1298 spin_unlock_irq(&nvmeq
->q_lock
);
1301 spin_unlock(&dev_list_lock
);
1302 set_current_state(TASK_INTERRUPTIBLE
);
1303 schedule_timeout(HZ
);
1308 static DEFINE_IDA(nvme_index_ida
);
1310 static int nvme_get_ns_idx(void)
1315 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1318 spin_lock(&dev_list_lock
);
1319 error
= ida_get_new(&nvme_index_ida
, &index
);
1320 spin_unlock(&dev_list_lock
);
1321 } while (error
== -EAGAIN
);
1328 static void nvme_put_ns_idx(int index
)
1330 spin_lock(&dev_list_lock
);
1331 ida_remove(&nvme_index_ida
, index
);
1332 spin_unlock(&dev_list_lock
);
1335 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1336 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1339 struct gendisk
*disk
;
1342 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1345 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1348 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1351 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1352 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1353 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1354 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1355 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1357 ns
->queue
->queuedata
= ns
;
1359 disk
= alloc_disk(NVME_MINORS
);
1361 goto out_free_queue
;
1364 lbaf
= id
->flbas
& 0xf;
1365 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1366 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1367 if (dev
->max_hw_sectors
)
1368 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1370 disk
->major
= nvme_major
;
1371 disk
->minors
= NVME_MINORS
;
1372 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1373 disk
->fops
= &nvme_fops
;
1374 disk
->private_data
= ns
;
1375 disk
->queue
= ns
->queue
;
1376 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1377 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1378 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1383 blk_cleanup_queue(ns
->queue
);
1389 static void nvme_ns_free(struct nvme_ns
*ns
)
1391 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1393 nvme_put_ns_idx(index
);
1394 blk_cleanup_queue(ns
->queue
);
1398 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1402 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1404 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1408 return min(result
& 0xffff, result
>> 16) + 1;
1411 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1413 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1415 nr_io_queues
= num_online_cpus();
1416 result
= set_queue_count(dev
, nr_io_queues
);
1419 if (result
< nr_io_queues
)
1420 nr_io_queues
= result
;
1422 /* Deregister the admin queue's interrupt */
1423 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1425 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1426 if (db_bar_size
> 8192) {
1428 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1430 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1431 dev
->queues
[0]->q_db
= dev
->dbs
;
1434 for (i
= 0; i
< nr_io_queues
; i
++)
1435 dev
->entry
[i
].entry
= i
;
1437 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1441 } else if (result
> 0) {
1442 nr_io_queues
= result
;
1450 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1451 /* XXX: handle failure here */
1453 cpu
= cpumask_first(cpu_online_mask
);
1454 for (i
= 0; i
< nr_io_queues
; i
++) {
1455 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1456 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1459 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1461 for (i
= 0; i
< nr_io_queues
; i
++) {
1462 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1463 if (IS_ERR(dev
->queues
[i
+ 1]))
1464 return PTR_ERR(dev
->queues
[i
+ 1]);
1468 for (; i
< num_possible_cpus(); i
++) {
1469 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1470 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1476 static void nvme_free_queues(struct nvme_dev
*dev
)
1480 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1481 nvme_free_queue(dev
, i
);
1484 static int nvme_dev_add(struct nvme_dev
*dev
)
1487 struct nvme_ns
*ns
, *next
;
1488 struct nvme_id_ctrl
*ctrl
;
1489 struct nvme_id_ns
*id_ns
;
1491 dma_addr_t dma_addr
;
1493 res
= nvme_setup_io_queues(dev
);
1497 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1500 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1507 nn
= le32_to_cpup(&ctrl
->nn
);
1508 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1509 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1510 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1512 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1513 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1517 for (i
= 1; i
<= nn
; i
++) {
1518 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1522 if (id_ns
->ncap
== 0)
1525 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1530 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1532 list_add_tail(&ns
->list
, &dev
->namespaces
);
1534 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1540 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1541 list_del(&ns
->list
);
1546 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1550 static int nvme_dev_remove(struct nvme_dev
*dev
)
1552 struct nvme_ns
*ns
, *next
;
1554 spin_lock(&dev_list_lock
);
1555 list_del(&dev
->node
);
1556 spin_unlock(&dev_list_lock
);
1558 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1559 list_del(&ns
->list
);
1560 del_gendisk(ns
->disk
);
1564 nvme_free_queues(dev
);
1569 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1571 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1572 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1573 PAGE_SIZE
, PAGE_SIZE
, 0);
1574 if (!dev
->prp_page_pool
)
1577 /* Optimisation for I/Os between 4k and 128k */
1578 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1580 if (!dev
->prp_small_pool
) {
1581 dma_pool_destroy(dev
->prp_page_pool
);
1587 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1589 dma_pool_destroy(dev
->prp_page_pool
);
1590 dma_pool_destroy(dev
->prp_small_pool
);
1593 static DEFINE_IDA(nvme_instance_ida
);
1595 static int nvme_set_instance(struct nvme_dev
*dev
)
1597 int instance
, error
;
1600 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
1603 spin_lock(&dev_list_lock
);
1604 error
= ida_get_new(&nvme_instance_ida
, &instance
);
1605 spin_unlock(&dev_list_lock
);
1606 } while (error
== -EAGAIN
);
1611 dev
->instance
= instance
;
1615 static void nvme_release_instance(struct nvme_dev
*dev
)
1617 spin_lock(&dev_list_lock
);
1618 ida_remove(&nvme_instance_ida
, dev
->instance
);
1619 spin_unlock(&dev_list_lock
);
1622 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1624 int bars
, result
= -ENOMEM
;
1625 struct nvme_dev
*dev
;
1627 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1630 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1634 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1639 if (pci_enable_device_mem(pdev
))
1641 pci_set_master(pdev
);
1642 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1643 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1646 INIT_LIST_HEAD(&dev
->namespaces
);
1647 dev
->pci_dev
= pdev
;
1648 pci_set_drvdata(pdev
, dev
);
1649 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1650 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1651 result
= nvme_set_instance(dev
);
1655 dev
->entry
[0].vector
= pdev
->irq
;
1657 result
= nvme_setup_prp_pools(dev
);
1661 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1667 result
= nvme_configure_admin_queue(dev
);
1672 spin_lock(&dev_list_lock
);
1673 list_add(&dev
->node
, &dev_list
);
1674 spin_unlock(&dev_list_lock
);
1676 result
= nvme_dev_add(dev
);
1683 spin_lock(&dev_list_lock
);
1684 list_del(&dev
->node
);
1685 spin_unlock(&dev_list_lock
);
1687 nvme_free_queues(dev
);
1691 pci_disable_msix(pdev
);
1692 nvme_release_instance(dev
);
1693 nvme_release_prp_pools(dev
);
1695 pci_disable_device(pdev
);
1696 pci_release_regions(pdev
);
1704 static void nvme_remove(struct pci_dev
*pdev
)
1706 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1707 nvme_dev_remove(dev
);
1708 pci_disable_msix(pdev
);
1710 nvme_release_instance(dev
);
1711 nvme_release_prp_pools(dev
);
1712 pci_disable_device(pdev
);
1713 pci_release_regions(pdev
);
1719 /* These functions are yet to be implemented */
1720 #define nvme_error_detected NULL
1721 #define nvme_dump_registers NULL
1722 #define nvme_link_reset NULL
1723 #define nvme_slot_reset NULL
1724 #define nvme_error_resume NULL
1725 #define nvme_suspend NULL
1726 #define nvme_resume NULL
1728 static const struct pci_error_handlers nvme_err_handler
= {
1729 .error_detected
= nvme_error_detected
,
1730 .mmio_enabled
= nvme_dump_registers
,
1731 .link_reset
= nvme_link_reset
,
1732 .slot_reset
= nvme_slot_reset
,
1733 .resume
= nvme_error_resume
,
1736 /* Move to pci_ids.h later */
1737 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1739 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1740 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1743 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1745 static struct pci_driver nvme_driver
= {
1747 .id_table
= nvme_id_table
,
1748 .probe
= nvme_probe
,
1749 .remove
= nvme_remove
,
1750 .suspend
= nvme_suspend
,
1751 .resume
= nvme_resume
,
1752 .err_handler
= &nvme_err_handler
,
1755 static int __init
nvme_init(void)
1759 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1760 if (IS_ERR(nvme_thread
))
1761 return PTR_ERR(nvme_thread
);
1763 result
= register_blkdev(nvme_major
, "nvme");
1766 else if (result
> 0)
1767 nvme_major
= result
;
1769 result
= pci_register_driver(&nvme_driver
);
1771 goto unregister_blkdev
;
1775 unregister_blkdev(nvme_major
, "nvme");
1777 kthread_stop(nvme_thread
);
1781 static void __exit
nvme_exit(void)
1783 pci_unregister_driver(&nvme_driver
);
1784 unregister_blkdev(nvme_major
, "nvme");
1785 kthread_stop(nvme_thread
);
1788 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1789 MODULE_LICENSE("GPL");
1790 MODULE_VERSION("0.8");
1791 module_init(nvme_init
);
1792 module_exit(nvme_exit
);