3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
55 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
56 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
57 static char *model
[SNDRV_CARDS
];
58 static int position_fix
[SNDRV_CARDS
];
59 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
60 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
61 static int probe_only
[SNDRV_CARDS
];
62 static int single_cmd
;
63 static int enable_msi
;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch
[SNDRV_CARDS
];
68 module_param_array(index
, int, NULL
, 0444);
69 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
70 module_param_array(id
, charp
, NULL
, 0444);
71 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
72 module_param_array(enable
, bool, NULL
, 0444);
73 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
74 module_param_array(model
, charp
, NULL
, 0444);
75 MODULE_PARM_DESC(model
, "Use the given board model.");
76 module_param_array(position_fix
, int, NULL
, 0444);
77 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer "
78 "(0 = auto, 1 = none, 2 = POSBUF).");
79 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
80 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
81 module_param_array(probe_mask
, int, NULL
, 0444);
82 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
83 module_param_array(probe_only
, bool, NULL
, 0444);
84 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
85 module_param(single_cmd
, bool, 0444);
86 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
87 "(for debugging only).");
88 module_param(enable_msi
, int, 0444);
89 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
90 #ifdef CONFIG_SND_HDA_PATCH_LOADER
91 module_param_array(patch
, charp
, NULL
, 0444);
92 MODULE_PARM_DESC(patch
, "Patch file for Intel HD audio interface.");
95 #ifdef CONFIG_SND_HDA_POWER_SAVE
96 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
97 module_param(power_save
, int, 0644);
98 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
99 "(in second, 0 = disable).");
101 /* reset the HD-audio controller in power save mode.
102 * this may give more power-saving, but will take longer time to
105 static int power_save_controller
= 1;
106 module_param(power_save_controller
, bool, 0644);
107 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
110 MODULE_LICENSE("GPL");
111 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
137 MODULE_DESCRIPTION("Intel HDA driver");
139 #ifdef CONFIG_SND_VERBOSE_PRINTK
140 #define SFX /* nop */
142 #define SFX "hda-intel: "
148 #define ICH6_REG_GCAP 0x00
149 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
150 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
151 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
152 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
153 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
154 #define ICH6_REG_VMIN 0x02
155 #define ICH6_REG_VMAJ 0x03
156 #define ICH6_REG_OUTPAY 0x04
157 #define ICH6_REG_INPAY 0x06
158 #define ICH6_REG_GCTL 0x08
159 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
160 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
161 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
162 #define ICH6_REG_WAKEEN 0x0c
163 #define ICH6_REG_STATESTS 0x0e
164 #define ICH6_REG_GSTS 0x10
165 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
166 #define ICH6_REG_INTCTL 0x20
167 #define ICH6_REG_INTSTS 0x24
168 #define ICH6_REG_WALCLK 0x30
169 #define ICH6_REG_SYNC 0x34
170 #define ICH6_REG_CORBLBASE 0x40
171 #define ICH6_REG_CORBUBASE 0x44
172 #define ICH6_REG_CORBWP 0x48
173 #define ICH6_REG_CORBRP 0x4a
174 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
175 #define ICH6_REG_CORBCTL 0x4c
176 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
177 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
178 #define ICH6_REG_CORBSTS 0x4d
179 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
180 #define ICH6_REG_CORBSIZE 0x4e
182 #define ICH6_REG_RIRBLBASE 0x50
183 #define ICH6_REG_RIRBUBASE 0x54
184 #define ICH6_REG_RIRBWP 0x58
185 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
186 #define ICH6_REG_RINTCNT 0x5a
187 #define ICH6_REG_RIRBCTL 0x5c
188 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
189 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
190 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
191 #define ICH6_REG_RIRBSTS 0x5d
192 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
193 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
194 #define ICH6_REG_RIRBSIZE 0x5e
196 #define ICH6_REG_IC 0x60
197 #define ICH6_REG_IR 0x64
198 #define ICH6_REG_IRS 0x68
199 #define ICH6_IRS_VALID (1<<1)
200 #define ICH6_IRS_BUSY (1<<0)
202 #define ICH6_REG_DPLBASE 0x70
203 #define ICH6_REG_DPUBASE 0x74
204 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
206 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
207 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
209 /* stream register offsets from stream base */
210 #define ICH6_REG_SD_CTL 0x00
211 #define ICH6_REG_SD_STS 0x03
212 #define ICH6_REG_SD_LPIB 0x04
213 #define ICH6_REG_SD_CBL 0x08
214 #define ICH6_REG_SD_LVI 0x0c
215 #define ICH6_REG_SD_FIFOW 0x0e
216 #define ICH6_REG_SD_FIFOSIZE 0x10
217 #define ICH6_REG_SD_FORMAT 0x12
218 #define ICH6_REG_SD_BDLPL 0x18
219 #define ICH6_REG_SD_BDLPU 0x1c
222 #define ICH6_PCIREG_TCSEL 0x44
228 /* max number of SDs */
229 /* ICH, ATI and VIA have 4 playback and 4 capture */
230 #define ICH6_NUM_CAPTURE 4
231 #define ICH6_NUM_PLAYBACK 4
233 /* ULI has 6 playback and 5 capture */
234 #define ULI_NUM_CAPTURE 5
235 #define ULI_NUM_PLAYBACK 6
237 /* ATI HDMI has 1 playback and 0 capture */
238 #define ATIHDMI_NUM_CAPTURE 0
239 #define ATIHDMI_NUM_PLAYBACK 1
241 /* TERA has 4 playback and 3 capture */
242 #define TERA_NUM_CAPTURE 3
243 #define TERA_NUM_PLAYBACK 4
245 /* this number is statically defined for simplicity */
246 #define MAX_AZX_DEV 16
248 /* max number of fragments - we may use more if allocating more pages for BDL */
249 #define BDL_SIZE 4096
250 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
251 #define AZX_MAX_FRAG 32
252 /* max buffer size - no h/w limit, you can increase as you like */
253 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
254 /* max number of PCM devics per card */
255 #define AZX_MAX_PCMS 8
257 /* RIRB int mask: overrun[2], response[0] */
258 #define RIRB_INT_RESPONSE 0x01
259 #define RIRB_INT_OVERRUN 0x04
260 #define RIRB_INT_MASK 0x05
262 /* STATESTS int mask: S3,SD2,SD1,SD0 */
263 #define AZX_MAX_CODECS 4
264 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
267 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
268 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
269 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
270 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
271 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
272 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
273 #define SD_CTL_STREAM_TAG_SHIFT 20
275 /* SD_CTL and SD_STS */
276 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
277 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
278 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
279 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
283 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
285 /* INTCTL and INTSTS */
286 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
287 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
288 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
290 /* below are so far hardcoded - should read registers in future */
291 #define ICH6_MAX_CORB_ENTRIES 256
292 #define ICH6_MAX_RIRB_ENTRIES 256
294 /* position fix mode */
301 /* Defines for ATI HD Audio support in SB450 south bridge */
302 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
303 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
305 /* Defines for Nvidia HDA support */
306 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
307 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
308 #define NVIDIA_HDA_ISTRM_COH 0x4d
309 #define NVIDIA_HDA_OSTRM_COH 0x4c
310 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
312 /* Defines for Intel SCH HDA snoop control */
313 #define INTEL_SCH_HDA_DEVC 0x78
314 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
316 /* Define IN stream 0 FIFO size offset in VIA controller */
317 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
318 /* Define VIA HD Audio Device ID*/
319 #define VIA_HDAC_DEVICE_ID 0x3288
321 /* HD Audio class code */
322 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
328 struct snd_dma_buffer bdl
; /* BDL buffer */
329 u32
*posbuf
; /* position buffer pointer */
331 unsigned int bufsize
; /* size of the play buffer in bytes */
332 unsigned int period_bytes
; /* size of the period in bytes */
333 unsigned int frags
; /* number for period in the play buffer */
334 unsigned int fifo_size
; /* FIFO size */
335 unsigned long start_jiffies
; /* start + minimum jiffies */
336 unsigned long min_jiffies
; /* minimum jiffies before position is valid */
338 void __iomem
*sd_addr
; /* stream descriptor pointer */
340 u32 sd_int_sta_mask
; /* stream int status mask */
343 struct snd_pcm_substream
*substream
; /* assigned substream,
346 unsigned int format_val
; /* format value to be set in the
347 * controller and the codec
349 unsigned char stream_tag
; /* assigned stream */
350 unsigned char index
; /* stream index */
352 unsigned int opened
:1;
353 unsigned int running
:1;
354 unsigned int irq_pending
:1;
355 unsigned int start_flag
: 1; /* stream full start flag */
358 * A flag to ensure DMA position is 0
359 * when link position is not greater than FIFO size
361 unsigned int insufficient
:1;
366 u32
*buf
; /* CORB/RIRB buffer
367 * Each CORB entry is 4byte, RIRB is 8byte
369 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
371 unsigned short rp
, wp
; /* read/write pointers */
372 int cmds
[AZX_MAX_CODECS
]; /* number of pending requests */
373 u32 res
[AZX_MAX_CODECS
]; /* last read value */
377 struct snd_card
*card
;
381 /* chip type specific */
383 int playback_streams
;
384 int playback_index_offset
;
386 int capture_index_offset
;
391 void __iomem
*remap_addr
;
396 struct mutex open_mutex
;
398 /* streams (x num_streams) */
399 struct azx_dev
*azx_dev
;
402 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
405 unsigned short codec_mask
;
406 int codec_probe_mask
; /* copied from probe_mask option */
413 /* CORB/RIRB and position buffers */
414 struct snd_dma_buffer rb
;
415 struct snd_dma_buffer posbuf
;
419 unsigned int running
:1;
420 unsigned int initialized
:1;
421 unsigned int single_cmd
:1;
422 unsigned int polling_mode
:1;
424 unsigned int irq_pending_warned
:1;
425 unsigned int via_dmapos_patch
:1; /* enable DMA-position fix for VIA */
426 unsigned int probing
:1; /* codec probing phase */
429 unsigned int last_cmd
[AZX_MAX_CODECS
];
431 /* for pending irqs */
432 struct work_struct irq_pending_work
;
434 /* reboot notifier (for mysterious hangup problem at power-down) */
435 struct notifier_block reboot_notifier
;
451 AZX_NUM_DRIVERS
, /* keep this as last entry */
454 static char *driver_short_names
[] __devinitdata
= {
455 [AZX_DRIVER_ICH
] = "HDA Intel",
456 [AZX_DRIVER_PCH
] = "HDA Intel PCH",
457 [AZX_DRIVER_SCH
] = "HDA Intel MID",
458 [AZX_DRIVER_ATI
] = "HDA ATI SB",
459 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
460 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
461 [AZX_DRIVER_SIS
] = "HDA SIS966",
462 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
463 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
464 [AZX_DRIVER_TERA
] = "HDA Teradici",
465 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
469 * macros for easy use
471 #define azx_writel(chip,reg,value) \
472 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
473 #define azx_readl(chip,reg) \
474 readl((chip)->remap_addr + ICH6_REG_##reg)
475 #define azx_writew(chip,reg,value) \
476 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
477 #define azx_readw(chip,reg) \
478 readw((chip)->remap_addr + ICH6_REG_##reg)
479 #define azx_writeb(chip,reg,value) \
480 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
481 #define azx_readb(chip,reg) \
482 readb((chip)->remap_addr + ICH6_REG_##reg)
484 #define azx_sd_writel(dev,reg,value) \
485 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
486 #define azx_sd_readl(dev,reg) \
487 readl((dev)->sd_addr + ICH6_REG_##reg)
488 #define azx_sd_writew(dev,reg,value) \
489 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
490 #define azx_sd_readw(dev,reg) \
491 readw((dev)->sd_addr + ICH6_REG_##reg)
492 #define azx_sd_writeb(dev,reg,value) \
493 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
494 #define azx_sd_readb(dev,reg) \
495 readb((dev)->sd_addr + ICH6_REG_##reg)
497 /* for pcm support */
498 #define get_azx_dev(substream) (substream->runtime->private_data)
500 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
503 * Interface for HD codec
507 * CORB / RIRB interface
509 static int azx_alloc_cmd_io(struct azx
*chip
)
513 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
514 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
515 snd_dma_pci_data(chip
->pci
),
516 PAGE_SIZE
, &chip
->rb
);
518 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
524 static void azx_init_cmd_io(struct azx
*chip
)
526 spin_lock_irq(&chip
->reg_lock
);
528 chip
->corb
.addr
= chip
->rb
.addr
;
529 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
530 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
531 azx_writel(chip
, CORBUBASE
, upper_32_bits(chip
->corb
.addr
));
533 /* set the corb size to 256 entries (ULI requires explicitly) */
534 azx_writeb(chip
, CORBSIZE
, 0x02);
535 /* set the corb write pointer to 0 */
536 azx_writew(chip
, CORBWP
, 0);
537 /* reset the corb hw read pointer */
538 azx_writew(chip
, CORBRP
, ICH6_CORBRP_RST
);
539 /* enable corb dma */
540 azx_writeb(chip
, CORBCTL
, ICH6_CORBCTL_RUN
);
543 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
544 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
545 chip
->rirb
.wp
= chip
->rirb
.rp
= 0;
546 memset(chip
->rirb
.cmds
, 0, sizeof(chip
->rirb
.cmds
));
547 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
548 azx_writel(chip
, RIRBUBASE
, upper_32_bits(chip
->rirb
.addr
));
550 /* set the rirb size to 256 entries (ULI requires explicitly) */
551 azx_writeb(chip
, RIRBSIZE
, 0x02);
552 /* reset the rirb hw write pointer */
553 azx_writew(chip
, RIRBWP
, ICH6_RIRBWP_RST
);
554 /* set N=1, get RIRB response interrupt for new entry */
555 azx_writew(chip
, RINTCNT
, 1);
556 /* enable rirb dma and response irq */
557 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
558 spin_unlock_irq(&chip
->reg_lock
);
561 static void azx_free_cmd_io(struct azx
*chip
)
563 spin_lock_irq(&chip
->reg_lock
);
564 /* disable ringbuffer DMAs */
565 azx_writeb(chip
, RIRBCTL
, 0);
566 azx_writeb(chip
, CORBCTL
, 0);
567 spin_unlock_irq(&chip
->reg_lock
);
570 static unsigned int azx_command_addr(u32 cmd
)
572 unsigned int addr
= cmd
>> 28;
574 if (addr
>= AZX_MAX_CODECS
) {
582 static unsigned int azx_response_addr(u32 res
)
584 unsigned int addr
= res
& 0xf;
586 if (addr
>= AZX_MAX_CODECS
) {
595 static int azx_corb_send_cmd(struct hda_bus
*bus
, u32 val
)
597 struct azx
*chip
= bus
->private_data
;
598 unsigned int addr
= azx_command_addr(val
);
601 spin_lock_irq(&chip
->reg_lock
);
603 /* add command to corb */
604 wp
= azx_readb(chip
, CORBWP
);
606 wp
%= ICH6_MAX_CORB_ENTRIES
;
608 chip
->rirb
.cmds
[addr
]++;
609 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
610 azx_writel(chip
, CORBWP
, wp
);
612 spin_unlock_irq(&chip
->reg_lock
);
617 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
619 /* retrieve RIRB entry - called from interrupt handler */
620 static void azx_update_rirb(struct azx
*chip
)
626 wp
= azx_readb(chip
, RIRBWP
);
627 if (wp
== chip
->rirb
.wp
)
631 while (chip
->rirb
.rp
!= wp
) {
633 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
635 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
636 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
637 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
638 addr
= azx_response_addr(res_ex
);
639 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
640 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
641 else if (chip
->rirb
.cmds
[addr
]) {
642 chip
->rirb
.res
[addr
] = res
;
644 chip
->rirb
.cmds
[addr
]--;
646 snd_printk(KERN_ERR SFX
"spurious response %#x:%#x, "
649 chip
->last_cmd
[addr
]);
653 /* receive a response */
654 static unsigned int azx_rirb_get_response(struct hda_bus
*bus
,
657 struct azx
*chip
= bus
->private_data
;
658 unsigned long timeout
;
661 timeout
= jiffies
+ msecs_to_jiffies(1000);
663 if (chip
->polling_mode
) {
664 spin_lock_irq(&chip
->reg_lock
);
665 azx_update_rirb(chip
);
666 spin_unlock_irq(&chip
->reg_lock
);
668 if (!chip
->rirb
.cmds
[addr
]) {
671 return chip
->rirb
.res
[addr
]; /* the last value */
673 if (time_after(jiffies
, timeout
))
675 if (bus
->needs_damn_long_delay
)
676 msleep(2); /* temporary workaround */
684 snd_printk(KERN_WARNING SFX
"No response from codec, "
685 "disabling MSI: last cmd=0x%08x\n",
686 chip
->last_cmd
[addr
]);
687 free_irq(chip
->irq
, chip
);
689 pci_disable_msi(chip
->pci
);
691 if (azx_acquire_irq(chip
, 1) < 0) {
698 if (!chip
->polling_mode
) {
699 snd_printk(KERN_WARNING SFX
"azx_get_response timeout, "
700 "switching to polling mode: last cmd=0x%08x\n",
701 chip
->last_cmd
[addr
]);
702 chip
->polling_mode
= 1;
707 /* If this critical timeout happens during the codec probing
708 * phase, this is likely an access to a non-existing codec
709 * slot. Better to return an error and reset the system.
714 /* a fatal communication error; need either to reset or to fallback
715 * to the single_cmd mode
718 if (bus
->allow_bus_reset
&& !bus
->response_reset
&& !bus
->in_reset
) {
719 bus
->response_reset
= 1;
720 return -1; /* give a chance to retry */
723 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
724 "switching to single_cmd mode: last cmd=0x%08x\n",
725 chip
->last_cmd
[addr
]);
726 chip
->single_cmd
= 1;
727 bus
->response_reset
= 0;
728 /* release CORB/RIRB */
729 azx_free_cmd_io(chip
);
730 /* disable unsolicited responses */
731 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_UNSOL
);
736 * Use the single immediate command instead of CORB/RIRB for simplicity
738 * Note: according to Intel, this is not preferred use. The command was
739 * intended for the BIOS only, and may get confused with unsolicited
740 * responses. So, we shouldn't use it for normal operation from the
742 * I left the codes, however, for debugging/testing purposes.
745 /* receive a response */
746 static int azx_single_wait_for_response(struct azx
*chip
, unsigned int addr
)
751 /* check IRV busy bit */
752 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
) {
753 /* reuse rirb.res as the response return value */
754 chip
->rirb
.res
[addr
] = azx_readl(chip
, IR
);
759 if (printk_ratelimit())
760 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
761 azx_readw(chip
, IRS
));
762 chip
->rirb
.res
[addr
] = -1;
767 static int azx_single_send_cmd(struct hda_bus
*bus
, u32 val
)
769 struct azx
*chip
= bus
->private_data
;
770 unsigned int addr
= azx_command_addr(val
);
775 /* check ICB busy bit */
776 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
777 /* Clear IRV valid bit */
778 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
780 azx_writel(chip
, IC
, val
);
781 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
783 return azx_single_wait_for_response(chip
, addr
);
787 if (printk_ratelimit())
788 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
789 azx_readw(chip
, IRS
), val
);
793 /* receive a response */
794 static unsigned int azx_single_get_response(struct hda_bus
*bus
,
797 struct azx
*chip
= bus
->private_data
;
798 return chip
->rirb
.res
[addr
];
802 * The below are the main callbacks from hda_codec.
804 * They are just the skeleton to call sub-callbacks according to the
805 * current setting of chip->single_cmd.
809 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
)
811 struct azx
*chip
= bus
->private_data
;
813 chip
->last_cmd
[azx_command_addr(val
)] = val
;
814 if (chip
->single_cmd
)
815 return azx_single_send_cmd(bus
, val
);
817 return azx_corb_send_cmd(bus
, val
);
821 static unsigned int azx_get_response(struct hda_bus
*bus
,
824 struct azx
*chip
= bus
->private_data
;
825 if (chip
->single_cmd
)
826 return azx_single_get_response(bus
, addr
);
828 return azx_rirb_get_response(bus
, addr
);
831 #ifdef CONFIG_SND_HDA_POWER_SAVE
832 static void azx_power_notify(struct hda_bus
*bus
);
835 /* reset codec link */
836 static int azx_reset(struct azx
*chip
)
841 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
843 /* reset controller */
844 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
847 while (azx_readb(chip
, GCTL
) && --count
)
850 /* delay for >= 100us for codec PLL to settle per spec
851 * Rev 0.9 section 5.5.1
855 /* Bring controller out of reset */
856 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
859 while (!azx_readb(chip
, GCTL
) && --count
)
862 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
865 /* check to see if controller is ready */
866 if (!azx_readb(chip
, GCTL
)) {
867 snd_printd(SFX
"azx_reset: controller not ready!\n");
871 /* Accept unsolicited responses */
872 if (!chip
->single_cmd
)
873 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) |
877 if (!chip
->codec_mask
) {
878 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
879 snd_printdd(SFX
"codec_mask = 0x%x\n", chip
->codec_mask
);
890 /* enable interrupts */
891 static void azx_int_enable(struct azx
*chip
)
893 /* enable controller CIE and GIE */
894 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
895 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
898 /* disable interrupts */
899 static void azx_int_disable(struct azx
*chip
)
903 /* disable interrupts in stream descriptor */
904 for (i
= 0; i
< chip
->num_streams
; i
++) {
905 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
906 azx_sd_writeb(azx_dev
, SD_CTL
,
907 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
910 /* disable SIE for all streams */
911 azx_writeb(chip
, INTCTL
, 0);
913 /* disable controller CIE and GIE */
914 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
915 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
918 /* clear interrupts */
919 static void azx_int_clear(struct azx
*chip
)
923 /* clear stream status */
924 for (i
= 0; i
< chip
->num_streams
; i
++) {
925 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
926 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
930 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
932 /* clear rirb status */
933 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
935 /* clear int status */
936 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
940 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
943 * Before stream start, initialize parameter
945 azx_dev
->insufficient
= 1;
948 azx_writeb(chip
, INTCTL
,
949 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
950 /* set DMA start and interrupt mask */
951 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
952 SD_CTL_DMA_START
| SD_INT_MASK
);
956 static void azx_stream_clear(struct azx
*chip
, struct azx_dev
*azx_dev
)
958 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
959 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
960 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
964 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
966 azx_stream_clear(chip
, azx_dev
);
968 azx_writeb(chip
, INTCTL
,
969 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
974 * reset and start the controller registers
976 static void azx_init_chip(struct azx
*chip
)
978 if (chip
->initialized
)
981 /* reset controller */
984 /* initialize interrupts */
986 azx_int_enable(chip
);
988 /* initialize the codec command I/O */
989 if (!chip
->single_cmd
)
990 azx_init_cmd_io(chip
);
992 /* program the position buffer */
993 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
994 azx_writel(chip
, DPUBASE
, upper_32_bits(chip
->posbuf
.addr
));
996 chip
->initialized
= 1;
1000 * initialize the PCI registers
1002 /* update bits in a PCI register byte */
1003 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
1004 unsigned char mask
, unsigned char val
)
1008 pci_read_config_byte(pci
, reg
, &data
);
1010 data
|= (val
& mask
);
1011 pci_write_config_byte(pci
, reg
, data
);
1014 static void azx_init_pci(struct azx
*chip
)
1016 unsigned short snoop
;
1018 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1019 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1020 * Ensuring these bits are 0 clears playback static on some HD Audio
1023 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
1025 switch (chip
->driver_type
) {
1026 case AZX_DRIVER_ATI
:
1027 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1028 update_pci_byte(chip
->pci
,
1029 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
1030 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
1032 case AZX_DRIVER_NVIDIA
:
1033 /* For NVIDIA HDA, enable snoop */
1034 update_pci_byte(chip
->pci
,
1035 NVIDIA_HDA_TRANSREG_ADDR
,
1036 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
1037 update_pci_byte(chip
->pci
,
1038 NVIDIA_HDA_ISTRM_COH
,
1039 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1040 update_pci_byte(chip
->pci
,
1041 NVIDIA_HDA_OSTRM_COH
,
1042 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1044 case AZX_DRIVER_SCH
:
1045 case AZX_DRIVER_PCH
:
1046 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
1047 if (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) {
1048 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
,
1049 snoop
& (~INTEL_SCH_HDA_DEVC_NOSNOOP
));
1050 pci_read_config_word(chip
->pci
,
1051 INTEL_SCH_HDA_DEVC
, &snoop
);
1052 snd_printdd(SFX
"HDA snoop disabled, enabling ... %s\n",
1053 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)
1062 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
1067 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
1069 struct azx
*chip
= dev_id
;
1070 struct azx_dev
*azx_dev
;
1074 spin_lock(&chip
->reg_lock
);
1076 status
= azx_readl(chip
, INTSTS
);
1078 spin_unlock(&chip
->reg_lock
);
1082 for (i
= 0; i
< chip
->num_streams
; i
++) {
1083 azx_dev
= &chip
->azx_dev
[i
];
1084 if (status
& azx_dev
->sd_int_sta_mask
) {
1085 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
1086 if (!azx_dev
->substream
|| !azx_dev
->running
)
1088 /* check whether this IRQ is really acceptable */
1089 ok
= azx_position_ok(chip
, azx_dev
);
1091 azx_dev
->irq_pending
= 0;
1092 spin_unlock(&chip
->reg_lock
);
1093 snd_pcm_period_elapsed(azx_dev
->substream
);
1094 spin_lock(&chip
->reg_lock
);
1095 } else if (ok
== 0 && chip
->bus
&& chip
->bus
->workq
) {
1096 /* bogus IRQ, process it later */
1097 azx_dev
->irq_pending
= 1;
1098 queue_work(chip
->bus
->workq
,
1099 &chip
->irq_pending_work
);
1104 /* clear rirb int */
1105 status
= azx_readb(chip
, RIRBSTS
);
1106 if (status
& RIRB_INT_MASK
) {
1107 if (status
& RIRB_INT_RESPONSE
)
1108 azx_update_rirb(chip
);
1109 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1113 /* clear state status int */
1114 if (azx_readb(chip
, STATESTS
) & 0x04)
1115 azx_writeb(chip
, STATESTS
, 0x04);
1117 spin_unlock(&chip
->reg_lock
);
1124 * set up a BDL entry
1126 static int setup_bdle(struct snd_pcm_substream
*substream
,
1127 struct azx_dev
*azx_dev
, u32
**bdlp
,
1128 int ofs
, int size
, int with_ioc
)
1136 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
1139 addr
= snd_pcm_sgbuf_get_addr(substream
, ofs
);
1140 /* program the address field of the BDL entry */
1141 bdl
[0] = cpu_to_le32((u32
)addr
);
1142 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
1143 /* program the size field of the BDL entry */
1144 chunk
= snd_pcm_sgbuf_get_chunk_size(substream
, ofs
, size
);
1145 bdl
[2] = cpu_to_le32(chunk
);
1146 /* program the IOC to enable interrupt
1147 * only when the whole fragment is processed
1150 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
1160 * set up BDL entries
1162 static int azx_setup_periods(struct azx
*chip
,
1163 struct snd_pcm_substream
*substream
,
1164 struct azx_dev
*azx_dev
)
1167 int i
, ofs
, periods
, period_bytes
;
1170 /* reset BDL address */
1171 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1172 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1174 period_bytes
= azx_dev
->period_bytes
;
1175 periods
= azx_dev
->bufsize
/ period_bytes
;
1177 /* program the initial BDL entries */
1178 bdl
= (u32
*)azx_dev
->bdl
.area
;
1181 pos_adj
= bdl_pos_adj
[chip
->dev_index
];
1183 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1184 int pos_align
= pos_adj
;
1185 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
1187 pos_adj
= pos_align
;
1189 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
1191 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
1192 if (pos_adj
>= period_bytes
) {
1193 snd_printk(KERN_WARNING SFX
"Too big adjustment %d\n",
1194 bdl_pos_adj
[chip
->dev_index
]);
1197 ofs
= setup_bdle(substream
, azx_dev
,
1198 &bdl
, ofs
, pos_adj
, 1);
1204 for (i
= 0; i
< periods
; i
++) {
1205 if (i
== periods
- 1 && pos_adj
)
1206 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1207 period_bytes
- pos_adj
, 0);
1209 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1217 snd_printk(KERN_ERR SFX
"Too many BDL entries: buffer=%d, period=%d\n",
1218 azx_dev
->bufsize
, period_bytes
);
1223 static void azx_stream_reset(struct azx
*chip
, struct azx_dev
*azx_dev
)
1228 azx_stream_clear(chip
, azx_dev
);
1230 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1231 SD_CTL_STREAM_RESET
);
1234 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1237 val
&= ~SD_CTL_STREAM_RESET
;
1238 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
1242 /* waiting for hardware to report that the stream is out of reset */
1243 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1247 /* reset first position - may not be synced with hw at this time */
1248 *azx_dev
->posbuf
= 0;
1252 * set up the SD for streaming
1254 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
1256 /* make sure the run bit is zero for SD */
1257 azx_stream_clear(chip
, azx_dev
);
1258 /* program the stream_tag */
1259 azx_sd_writel(azx_dev
, SD_CTL
,
1260 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
)|
1261 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
1263 /* program the length of samples in cyclic buffer */
1264 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
1266 /* program the stream format */
1267 /* this value needs to be the same as the one programmed */
1268 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1270 /* program the stream LVI (last valid index) of the BDL */
1271 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1273 /* program the BDL address */
1274 /* lower BDL address */
1275 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
1276 /* upper BDL address */
1277 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32_bits(azx_dev
->bdl
.addr
));
1279 /* enable the position buffer */
1280 if (chip
->position_fix
== POS_FIX_POSBUF
||
1281 chip
->position_fix
== POS_FIX_AUTO
||
1282 chip
->via_dmapos_patch
) {
1283 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1284 azx_writel(chip
, DPLBASE
,
1285 (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
1288 /* set the interrupt enable bits in the descriptor control register */
1289 azx_sd_writel(azx_dev
, SD_CTL
,
1290 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1296 * Probe the given codec address
1298 static int probe_codec(struct azx
*chip
, int addr
)
1300 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1301 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1304 mutex_lock(&chip
->bus
->cmd_mutex
);
1306 azx_send_cmd(chip
->bus
, cmd
);
1307 res
= azx_get_response(chip
->bus
, addr
);
1309 mutex_unlock(&chip
->bus
->cmd_mutex
);
1312 snd_printdd(SFX
"codec #%d probed OK\n", addr
);
1316 static int azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1317 struct hda_pcm
*cpcm
);
1318 static void azx_stop_chip(struct azx
*chip
);
1320 static void azx_bus_reset(struct hda_bus
*bus
)
1322 struct azx
*chip
= bus
->private_data
;
1325 azx_stop_chip(chip
);
1326 azx_init_chip(chip
);
1328 if (chip
->initialized
) {
1331 for (i
= 0; i
< AZX_MAX_PCMS
; i
++)
1332 snd_pcm_suspend_all(chip
->pcm
[i
]);
1333 snd_hda_suspend(chip
->bus
);
1334 snd_hda_resume(chip
->bus
);
1341 * Codec initialization
1344 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1345 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] __devinitdata
= {
1346 [AZX_DRIVER_TERA
] = 1,
1349 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
1351 struct hda_bus_template bus_temp
;
1355 memset(&bus_temp
, 0, sizeof(bus_temp
));
1356 bus_temp
.private_data
= chip
;
1357 bus_temp
.modelname
= model
;
1358 bus_temp
.pci
= chip
->pci
;
1359 bus_temp
.ops
.command
= azx_send_cmd
;
1360 bus_temp
.ops
.get_response
= azx_get_response
;
1361 bus_temp
.ops
.attach_pcm
= azx_attach_pcm_stream
;
1362 bus_temp
.ops
.bus_reset
= azx_bus_reset
;
1363 #ifdef CONFIG_SND_HDA_POWER_SAVE
1364 bus_temp
.power_save
= &power_save
;
1365 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1368 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1372 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
)
1373 chip
->bus
->needs_damn_long_delay
= 1;
1376 max_slots
= azx_max_codecs
[chip
->driver_type
];
1378 max_slots
= AZX_MAX_CODECS
;
1380 /* First try to probe all given codec slots */
1381 for (c
= 0; c
< max_slots
; c
++) {
1382 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1383 if (probe_codec(chip
, c
) < 0) {
1384 /* Some BIOSen give you wrong codec addresses
1387 snd_printk(KERN_WARNING SFX
1388 "Codec #%d probe error; "
1389 "disabling it...\n", c
);
1390 chip
->codec_mask
&= ~(1 << c
);
1391 /* More badly, accessing to a non-existing
1392 * codec often screws up the controller chip,
1393 * and distrubs the further communications.
1394 * Thus if an error occurs during probing,
1395 * better to reset the controller chip to
1396 * get back to the sanity state.
1398 azx_stop_chip(chip
);
1399 azx_init_chip(chip
);
1404 /* Then create codec instances */
1405 for (c
= 0; c
< max_slots
; c
++) {
1406 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1407 struct hda_codec
*codec
;
1408 err
= snd_hda_codec_new(chip
->bus
, c
, &codec
);
1415 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1421 /* configure each codec instance */
1422 static int __devinit
azx_codec_configure(struct azx
*chip
)
1424 struct hda_codec
*codec
;
1425 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1426 snd_hda_codec_configure(codec
);
1436 /* assign a stream for the PCM */
1437 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
1440 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1441 dev
= chip
->playback_index_offset
;
1442 nums
= chip
->playback_streams
;
1444 dev
= chip
->capture_index_offset
;
1445 nums
= chip
->capture_streams
;
1447 for (i
= 0; i
< nums
; i
++, dev
++)
1448 if (!chip
->azx_dev
[dev
].opened
) {
1449 chip
->azx_dev
[dev
].opened
= 1;
1450 return &chip
->azx_dev
[dev
];
1455 /* release the assigned stream */
1456 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1458 azx_dev
->opened
= 0;
1461 static struct snd_pcm_hardware azx_pcm_hw
= {
1462 .info
= (SNDRV_PCM_INFO_MMAP
|
1463 SNDRV_PCM_INFO_INTERLEAVED
|
1464 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1465 SNDRV_PCM_INFO_MMAP_VALID
|
1466 /* No full-resume yet implemented */
1467 /* SNDRV_PCM_INFO_RESUME |*/
1468 SNDRV_PCM_INFO_PAUSE
|
1469 SNDRV_PCM_INFO_SYNC_START
),
1470 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1471 .rates
= SNDRV_PCM_RATE_48000
,
1476 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1477 .period_bytes_min
= 128,
1478 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1480 .periods_max
= AZX_MAX_FRAG
,
1486 struct hda_codec
*codec
;
1487 struct hda_pcm_stream
*hinfo
[2];
1490 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1492 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1493 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1494 struct azx
*chip
= apcm
->chip
;
1495 struct azx_dev
*azx_dev
;
1496 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1497 unsigned long flags
;
1500 mutex_lock(&chip
->open_mutex
);
1501 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1502 if (azx_dev
== NULL
) {
1503 mutex_unlock(&chip
->open_mutex
);
1506 runtime
->hw
= azx_pcm_hw
;
1507 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1508 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1509 runtime
->hw
.formats
= hinfo
->formats
;
1510 runtime
->hw
.rates
= hinfo
->rates
;
1511 snd_pcm_limit_hw_rates(runtime
);
1512 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1513 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1515 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1517 snd_hda_power_up(apcm
->codec
);
1518 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1520 azx_release_device(azx_dev
);
1521 snd_hda_power_down(apcm
->codec
);
1522 mutex_unlock(&chip
->open_mutex
);
1525 snd_pcm_limit_hw_rates(runtime
);
1527 if (snd_BUG_ON(!runtime
->hw
.channels_min
) ||
1528 snd_BUG_ON(!runtime
->hw
.channels_max
) ||
1529 snd_BUG_ON(!runtime
->hw
.formats
) ||
1530 snd_BUG_ON(!runtime
->hw
.rates
)) {
1531 azx_release_device(azx_dev
);
1532 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1533 snd_hda_power_down(apcm
->codec
);
1534 mutex_unlock(&chip
->open_mutex
);
1537 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1538 azx_dev
->substream
= substream
;
1539 azx_dev
->running
= 0;
1540 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1542 runtime
->private_data
= azx_dev
;
1543 snd_pcm_set_sync(substream
);
1544 mutex_unlock(&chip
->open_mutex
);
1548 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1550 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1551 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1552 struct azx
*chip
= apcm
->chip
;
1553 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1554 unsigned long flags
;
1556 mutex_lock(&chip
->open_mutex
);
1557 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1558 azx_dev
->substream
= NULL
;
1559 azx_dev
->running
= 0;
1560 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1561 azx_release_device(azx_dev
);
1562 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1563 snd_hda_power_down(apcm
->codec
);
1564 mutex_unlock(&chip
->open_mutex
);
1568 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1569 struct snd_pcm_hw_params
*hw_params
)
1571 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1573 azx_dev
->bufsize
= 0;
1574 azx_dev
->period_bytes
= 0;
1575 azx_dev
->format_val
= 0;
1576 return snd_pcm_lib_malloc_pages(substream
,
1577 params_buffer_bytes(hw_params
));
1580 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1582 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1583 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1584 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1586 /* reset BDL address */
1587 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1588 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1589 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1590 azx_dev
->bufsize
= 0;
1591 azx_dev
->period_bytes
= 0;
1592 azx_dev
->format_val
= 0;
1594 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1596 return snd_pcm_lib_free_pages(substream
);
1599 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1601 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1602 struct azx
*chip
= apcm
->chip
;
1603 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1604 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1605 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1606 unsigned int bufsize
, period_bytes
, format_val
;
1609 azx_stream_reset(chip
, azx_dev
);
1610 format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1615 snd_printk(KERN_ERR SFX
1616 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1617 runtime
->rate
, runtime
->channels
, runtime
->format
);
1621 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1622 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1624 snd_printdd(SFX
"azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1625 bufsize
, format_val
);
1627 if (bufsize
!= azx_dev
->bufsize
||
1628 period_bytes
!= azx_dev
->period_bytes
||
1629 format_val
!= azx_dev
->format_val
) {
1630 azx_dev
->bufsize
= bufsize
;
1631 azx_dev
->period_bytes
= period_bytes
;
1632 azx_dev
->format_val
= format_val
;
1633 err
= azx_setup_periods(chip
, substream
, azx_dev
);
1638 azx_dev
->min_jiffies
= (runtime
->period_size
* HZ
) /
1639 (runtime
->rate
* 2);
1640 azx_setup_controller(chip
, azx_dev
);
1641 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1642 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1644 azx_dev
->fifo_size
= 0;
1646 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1647 azx_dev
->format_val
, substream
);
1650 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1652 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1653 struct azx
*chip
= apcm
->chip
;
1654 struct azx_dev
*azx_dev
;
1655 struct snd_pcm_substream
*s
;
1656 int rstart
= 0, start
, nsync
= 0, sbits
= 0;
1660 case SNDRV_PCM_TRIGGER_START
:
1662 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1663 case SNDRV_PCM_TRIGGER_RESUME
:
1666 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1667 case SNDRV_PCM_TRIGGER_SUSPEND
:
1668 case SNDRV_PCM_TRIGGER_STOP
:
1675 snd_pcm_group_for_each_entry(s
, substream
) {
1676 if (s
->pcm
->card
!= substream
->pcm
->card
)
1678 azx_dev
= get_azx_dev(s
);
1679 sbits
|= 1 << azx_dev
->index
;
1681 snd_pcm_trigger_done(s
, substream
);
1684 spin_lock(&chip
->reg_lock
);
1686 /* first, set SYNC bits of corresponding streams */
1687 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) | sbits
);
1689 snd_pcm_group_for_each_entry(s
, substream
) {
1690 if (s
->pcm
->card
!= substream
->pcm
->card
)
1692 azx_dev
= get_azx_dev(s
);
1694 azx_dev
->start_flag
= 1;
1695 azx_dev
->start_jiffies
= jiffies
+ azx_dev
->min_jiffies
;
1698 azx_stream_start(chip
, azx_dev
);
1700 azx_stream_stop(chip
, azx_dev
);
1701 azx_dev
->running
= start
;
1703 spin_unlock(&chip
->reg_lock
);
1707 /* wait until all FIFOs get ready */
1708 for (timeout
= 5000; timeout
; timeout
--) {
1710 snd_pcm_group_for_each_entry(s
, substream
) {
1711 if (s
->pcm
->card
!= substream
->pcm
->card
)
1713 azx_dev
= get_azx_dev(s
);
1714 if (!(azx_sd_readb(azx_dev
, SD_STS
) &
1723 /* wait until all RUN bits are cleared */
1724 for (timeout
= 5000; timeout
; timeout
--) {
1726 snd_pcm_group_for_each_entry(s
, substream
) {
1727 if (s
->pcm
->card
!= substream
->pcm
->card
)
1729 azx_dev
= get_azx_dev(s
);
1730 if (azx_sd_readb(azx_dev
, SD_CTL
) &
1740 spin_lock(&chip
->reg_lock
);
1741 /* reset SYNC bits */
1742 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) & ~sbits
);
1743 spin_unlock(&chip
->reg_lock
);
1748 /* get the current DMA position with correction on VIA chips */
1749 static unsigned int azx_via_get_position(struct azx
*chip
,
1750 struct azx_dev
*azx_dev
)
1752 unsigned int link_pos
, mini_pos
, bound_pos
;
1753 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
1754 unsigned int fifo_size
;
1756 link_pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1757 if (azx_dev
->index
>= 4) {
1758 /* Playback, no problem using link position */
1764 * use mod to get the DMA position just like old chipset
1766 mod_dma_pos
= le32_to_cpu(*azx_dev
->posbuf
);
1767 mod_dma_pos
%= azx_dev
->period_bytes
;
1769 /* azx_dev->fifo_size can't get FIFO size of in stream.
1770 * Get from base address + offset.
1772 fifo_size
= readw(chip
->remap_addr
+ VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
1774 if (azx_dev
->insufficient
) {
1775 /* Link position never gather than FIFO size */
1776 if (link_pos
<= fifo_size
)
1779 azx_dev
->insufficient
= 0;
1782 if (link_pos
<= fifo_size
)
1783 mini_pos
= azx_dev
->bufsize
+ link_pos
- fifo_size
;
1785 mini_pos
= link_pos
- fifo_size
;
1787 /* Find nearest previous boudary */
1788 mod_mini_pos
= mini_pos
% azx_dev
->period_bytes
;
1789 mod_link_pos
= link_pos
% azx_dev
->period_bytes
;
1790 if (mod_link_pos
>= fifo_size
)
1791 bound_pos
= link_pos
- mod_link_pos
;
1792 else if (mod_dma_pos
>= mod_mini_pos
)
1793 bound_pos
= mini_pos
- mod_mini_pos
;
1795 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->period_bytes
;
1796 if (bound_pos
>= azx_dev
->bufsize
)
1800 /* Calculate real DMA position we want */
1801 return bound_pos
+ mod_dma_pos
;
1804 static unsigned int azx_get_position(struct azx
*chip
,
1805 struct azx_dev
*azx_dev
)
1809 if (chip
->via_dmapos_patch
)
1810 pos
= azx_via_get_position(chip
, azx_dev
);
1811 else if (chip
->position_fix
== POS_FIX_POSBUF
||
1812 chip
->position_fix
== POS_FIX_AUTO
) {
1813 /* use the position buffer */
1814 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1817 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1819 if (pos
>= azx_dev
->bufsize
)
1824 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1826 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1827 struct azx
*chip
= apcm
->chip
;
1828 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1829 return bytes_to_frames(substream
->runtime
,
1830 azx_get_position(chip
, azx_dev
));
1834 * Check whether the current DMA position is acceptable for updating
1835 * periods. Returns non-zero if it's OK.
1837 * Many HD-audio controllers appear pretty inaccurate about
1838 * the update-IRQ timing. The IRQ is issued before actually the
1839 * data is processed. So, we need to process it afterwords in a
1842 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
1846 if (azx_dev
->start_flag
&&
1847 time_before_eq(jiffies
, azx_dev
->start_jiffies
))
1848 return -1; /* bogus (too early) interrupt */
1849 azx_dev
->start_flag
= 0;
1851 pos
= azx_get_position(chip
, azx_dev
);
1852 if (chip
->position_fix
== POS_FIX_AUTO
) {
1855 "hda-intel: Invalid position buffer, "
1856 "using LPIB read method instead.\n");
1857 chip
->position_fix
= POS_FIX_LPIB
;
1858 pos
= azx_get_position(chip
, azx_dev
);
1860 chip
->position_fix
= POS_FIX_POSBUF
;
1863 if (!bdl_pos_adj
[chip
->dev_index
])
1864 return 1; /* no delayed ack */
1865 if (WARN_ONCE(!azx_dev
->period_bytes
,
1866 "hda-intel: zero azx_dev->period_bytes"))
1867 return 0; /* this shouldn't happen! */
1868 if (pos
% azx_dev
->period_bytes
> azx_dev
->period_bytes
/ 2)
1869 return 0; /* NG - it's below the period boundary */
1870 return 1; /* OK, it's fine */
1874 * The work for pending PCM period updates.
1876 static void azx_irq_pending_work(struct work_struct
*work
)
1878 struct azx
*chip
= container_of(work
, struct azx
, irq_pending_work
);
1881 if (!chip
->irq_pending_warned
) {
1883 "hda-intel: IRQ timing workaround is activated "
1884 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1885 chip
->card
->number
);
1886 chip
->irq_pending_warned
= 1;
1891 spin_lock_irq(&chip
->reg_lock
);
1892 for (i
= 0; i
< chip
->num_streams
; i
++) {
1893 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1894 if (!azx_dev
->irq_pending
||
1895 !azx_dev
->substream
||
1898 if (azx_position_ok(chip
, azx_dev
)) {
1899 azx_dev
->irq_pending
= 0;
1900 spin_unlock(&chip
->reg_lock
);
1901 snd_pcm_period_elapsed(azx_dev
->substream
);
1902 spin_lock(&chip
->reg_lock
);
1906 spin_unlock_irq(&chip
->reg_lock
);
1913 /* clear irq_pending flags and assure no on-going workq */
1914 static void azx_clear_irq_pending(struct azx
*chip
)
1918 spin_lock_irq(&chip
->reg_lock
);
1919 for (i
= 0; i
< chip
->num_streams
; i
++)
1920 chip
->azx_dev
[i
].irq_pending
= 0;
1921 spin_unlock_irq(&chip
->reg_lock
);
1924 static struct snd_pcm_ops azx_pcm_ops
= {
1925 .open
= azx_pcm_open
,
1926 .close
= azx_pcm_close
,
1927 .ioctl
= snd_pcm_lib_ioctl
,
1928 .hw_params
= azx_pcm_hw_params
,
1929 .hw_free
= azx_pcm_hw_free
,
1930 .prepare
= azx_pcm_prepare
,
1931 .trigger
= azx_pcm_trigger
,
1932 .pointer
= azx_pcm_pointer
,
1933 .page
= snd_pcm_sgbuf_ops_page
,
1936 static void azx_pcm_free(struct snd_pcm
*pcm
)
1938 struct azx_pcm
*apcm
= pcm
->private_data
;
1940 apcm
->chip
->pcm
[pcm
->device
] = NULL
;
1946 azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1947 struct hda_pcm
*cpcm
)
1949 struct azx
*chip
= bus
->private_data
;
1950 struct snd_pcm
*pcm
;
1951 struct azx_pcm
*apcm
;
1952 int pcm_dev
= cpcm
->device
;
1955 if (pcm_dev
>= AZX_MAX_PCMS
) {
1956 snd_printk(KERN_ERR SFX
"Invalid PCM device number %d\n",
1960 if (chip
->pcm
[pcm_dev
]) {
1961 snd_printk(KERN_ERR SFX
"PCM %d already exists\n", pcm_dev
);
1964 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1965 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
1966 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
1970 strlcpy(pcm
->name
, cpcm
->name
, sizeof(pcm
->name
));
1971 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
1975 apcm
->codec
= codec
;
1976 pcm
->private_data
= apcm
;
1977 pcm
->private_free
= azx_pcm_free
;
1978 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
1979 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1980 chip
->pcm
[pcm_dev
] = pcm
;
1982 for (s
= 0; s
< 2; s
++) {
1983 apcm
->hinfo
[s
] = &cpcm
->stream
[s
];
1984 if (cpcm
->stream
[s
].substreams
)
1985 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
1987 /* buffer pre-allocation */
1988 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV_SG
,
1989 snd_dma_pci_data(chip
->pci
),
1990 1024 * 64, 32 * 1024 * 1024);
1995 * mixer creation - all stuff is implemented in hda module
1997 static int __devinit
azx_mixer_create(struct azx
*chip
)
1999 return snd_hda_build_controls(chip
->bus
);
2004 * initialize SD streams
2006 static int __devinit
azx_init_stream(struct azx
*chip
)
2010 /* initialize each stream (aka device)
2011 * assign the starting bdl address to each stream (device)
2014 for (i
= 0; i
< chip
->num_streams
; i
++) {
2015 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
2016 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
2017 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2018 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
2019 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2020 azx_dev
->sd_int_sta_mask
= 1 << i
;
2021 /* stream tag: must be non-zero and unique */
2023 azx_dev
->stream_tag
= i
+ 1;
2029 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
2031 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
2032 chip
->msi
? 0 : IRQF_SHARED
,
2033 "HDA Intel", chip
)) {
2034 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
2035 "disabling device\n", chip
->pci
->irq
);
2037 snd_card_disconnect(chip
->card
);
2040 chip
->irq
= chip
->pci
->irq
;
2041 pci_intx(chip
->pci
, !chip
->msi
);
2046 static void azx_stop_chip(struct azx
*chip
)
2048 if (!chip
->initialized
)
2051 /* disable interrupts */
2052 azx_int_disable(chip
);
2053 azx_int_clear(chip
);
2055 /* disable CORB/RIRB */
2056 azx_free_cmd_io(chip
);
2058 /* disable position buffer */
2059 azx_writel(chip
, DPLBASE
, 0);
2060 azx_writel(chip
, DPUBASE
, 0);
2062 chip
->initialized
= 0;
2065 #ifdef CONFIG_SND_HDA_POWER_SAVE
2066 /* power-up/down the controller */
2067 static void azx_power_notify(struct hda_bus
*bus
)
2069 struct azx
*chip
= bus
->private_data
;
2070 struct hda_codec
*c
;
2073 list_for_each_entry(c
, &bus
->codec_list
, list
) {
2080 azx_init_chip(chip
);
2081 else if (chip
->running
&& power_save_controller
)
2082 azx_stop_chip(chip
);
2084 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2091 static int snd_hda_codecs_inuse(struct hda_bus
*bus
)
2093 struct hda_codec
*codec
;
2095 list_for_each_entry(codec
, &bus
->codec_list
, list
) {
2096 if (snd_hda_codec_needs_resume(codec
))
2102 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
2104 struct snd_card
*card
= pci_get_drvdata(pci
);
2105 struct azx
*chip
= card
->private_data
;
2108 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2109 azx_clear_irq_pending(chip
);
2110 for (i
= 0; i
< AZX_MAX_PCMS
; i
++)
2111 snd_pcm_suspend_all(chip
->pcm
[i
]);
2112 if (chip
->initialized
)
2113 snd_hda_suspend(chip
->bus
);
2114 azx_stop_chip(chip
);
2115 if (chip
->irq
>= 0) {
2116 free_irq(chip
->irq
, chip
);
2120 pci_disable_msi(chip
->pci
);
2121 pci_disable_device(pci
);
2122 pci_save_state(pci
);
2123 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
2127 static int azx_resume(struct pci_dev
*pci
)
2129 struct snd_card
*card
= pci_get_drvdata(pci
);
2130 struct azx
*chip
= card
->private_data
;
2132 pci_set_power_state(pci
, PCI_D0
);
2133 pci_restore_state(pci
);
2134 if (pci_enable_device(pci
) < 0) {
2135 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
2136 "disabling device\n");
2137 snd_card_disconnect(card
);
2140 pci_set_master(pci
);
2142 if (pci_enable_msi(pci
) < 0)
2144 if (azx_acquire_irq(chip
, 1) < 0)
2148 if (snd_hda_codecs_inuse(chip
->bus
))
2149 azx_init_chip(chip
);
2151 snd_hda_resume(chip
->bus
);
2152 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2155 #endif /* CONFIG_PM */
2159 * reboot notifier for hang-up problem at power-down
2161 static int azx_halt(struct notifier_block
*nb
, unsigned long event
, void *buf
)
2163 struct azx
*chip
= container_of(nb
, struct azx
, reboot_notifier
);
2164 azx_stop_chip(chip
);
2168 static void azx_notifier_register(struct azx
*chip
)
2170 chip
->reboot_notifier
.notifier_call
= azx_halt
;
2171 register_reboot_notifier(&chip
->reboot_notifier
);
2174 static void azx_notifier_unregister(struct azx
*chip
)
2176 if (chip
->reboot_notifier
.notifier_call
)
2177 unregister_reboot_notifier(&chip
->reboot_notifier
);
2183 static int azx_free(struct azx
*chip
)
2187 azx_notifier_unregister(chip
);
2189 if (chip
->initialized
) {
2190 azx_clear_irq_pending(chip
);
2191 for (i
= 0; i
< chip
->num_streams
; i
++)
2192 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
2193 azx_stop_chip(chip
);
2197 free_irq(chip
->irq
, (void*)chip
);
2199 pci_disable_msi(chip
->pci
);
2200 if (chip
->remap_addr
)
2201 iounmap(chip
->remap_addr
);
2203 if (chip
->azx_dev
) {
2204 for (i
= 0; i
< chip
->num_streams
; i
++)
2205 if (chip
->azx_dev
[i
].bdl
.area
)
2206 snd_dma_free_pages(&chip
->azx_dev
[i
].bdl
);
2209 snd_dma_free_pages(&chip
->rb
);
2210 if (chip
->posbuf
.area
)
2211 snd_dma_free_pages(&chip
->posbuf
);
2212 pci_release_regions(chip
->pci
);
2213 pci_disable_device(chip
->pci
);
2214 kfree(chip
->azx_dev
);
2220 static int azx_dev_free(struct snd_device
*device
)
2222 return azx_free(device
->device_data
);
2226 * white/black-listing for position_fix
2228 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
2229 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB
),
2230 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
2231 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
2232 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB
),
2233 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB
),
2234 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
2235 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB
),
2236 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB
),
2237 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB
),
2238 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB
),
2239 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB
),
2240 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB
),
2241 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB
),
2242 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB
),
2243 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB
),
2244 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB
),
2245 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB
),
2246 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB
),
2250 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
2252 const struct snd_pci_quirk
*q
;
2256 case POS_FIX_POSBUF
:
2260 /* Check VIA/ATI HD Audio Controller exist */
2261 switch (chip
->driver_type
) {
2262 case AZX_DRIVER_VIA
:
2263 case AZX_DRIVER_ATI
:
2264 chip
->via_dmapos_patch
= 1;
2265 /* Use link position directly, avoid any transfer problem. */
2266 return POS_FIX_LPIB
;
2268 chip
->via_dmapos_patch
= 0;
2270 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
2273 "hda_intel: position_fix set to %d "
2274 "for device %04x:%04x\n",
2275 q
->value
, q
->subvendor
, q
->subdevice
);
2278 return POS_FIX_AUTO
;
2282 * black-lists for probe_mask
2284 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
2285 /* Thinkpad often breaks the controller communication when accessing
2286 * to the non-working (or non-existing) modem codec slot.
2288 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2289 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2290 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2292 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2293 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2294 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2295 /* forced codec slots */
2296 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2297 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2301 #define AZX_FORCE_CODEC_MASK 0x100
2303 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
2305 const struct snd_pci_quirk
*q
;
2307 chip
->codec_probe_mask
= probe_mask
[dev
];
2308 if (chip
->codec_probe_mask
== -1) {
2309 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
2312 "hda_intel: probe_mask set to 0x%x "
2313 "for device %04x:%04x\n",
2314 q
->value
, q
->subvendor
, q
->subdevice
);
2315 chip
->codec_probe_mask
= q
->value
;
2319 /* check forced option */
2320 if (chip
->codec_probe_mask
!= -1 &&
2321 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
2322 chip
->codec_mask
= chip
->codec_probe_mask
& 0xff;
2323 printk(KERN_INFO
"hda_intel: codec_mask forced to 0x%x\n",
2329 * white-list for enable_msi
2331 static struct snd_pci_quirk msi_white_list
[] __devinitdata
= {
2332 SND_PCI_QUIRK(0x103c, 0x30f7, "HP Pavilion dv4t-1300", 1),
2333 SND_PCI_QUIRK(0x103c, 0x3607, "HP Compa CQ40", 1),
2334 SND_PCI_QUIRK(0x107b, 0x0380, "Gateway M-6866", 1),
2338 static void __devinit
check_msi(struct azx
*chip
)
2340 const struct snd_pci_quirk
*q
;
2342 chip
->msi
= enable_msi
;
2345 q
= snd_pci_quirk_lookup(chip
->pci
, msi_white_list
);
2348 "hda_intel: msi for device %04x:%04x set to %d\n",
2349 q
->subvendor
, q
->subdevice
, q
->value
);
2350 chip
->msi
= q
->value
;
2354 /* NVidia chipsets seem to cause troubles with MSI */
2355 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
) {
2356 printk(KERN_INFO
"hda_intel: Disable MSI for Nvidia chipset\n");
2365 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
2366 int dev
, int driver_type
,
2371 unsigned short gcap
;
2372 static struct snd_device_ops ops
= {
2373 .dev_free
= azx_dev_free
,
2378 err
= pci_enable_device(pci
);
2382 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2384 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
2385 pci_disable_device(pci
);
2389 spin_lock_init(&chip
->reg_lock
);
2390 mutex_init(&chip
->open_mutex
);
2394 chip
->driver_type
= driver_type
;
2396 chip
->dev_index
= dev
;
2397 INIT_WORK(&chip
->irq_pending_work
, azx_irq_pending_work
);
2399 chip
->position_fix
= check_position_fix(chip
, position_fix
[dev
]);
2400 check_probe_mask(chip
, dev
);
2402 chip
->single_cmd
= single_cmd
;
2404 if (bdl_pos_adj
[dev
] < 0) {
2405 switch (chip
->driver_type
) {
2406 case AZX_DRIVER_ICH
:
2407 case AZX_DRIVER_PCH
:
2408 bdl_pos_adj
[dev
] = 1;
2411 bdl_pos_adj
[dev
] = 32;
2416 #if BITS_PER_LONG != 64
2417 /* Fix up base address on ULI M5461 */
2418 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
2420 pci_read_config_word(pci
, 0x40, &tmp3
);
2421 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
2422 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
2426 err
= pci_request_regions(pci
, "ICH HD audio");
2429 pci_disable_device(pci
);
2433 chip
->addr
= pci_resource_start(pci
, 0);
2434 chip
->remap_addr
= pci_ioremap_bar(pci
, 0);
2435 if (chip
->remap_addr
== NULL
) {
2436 snd_printk(KERN_ERR SFX
"ioremap error\n");
2442 if (pci_enable_msi(pci
) < 0)
2445 if (azx_acquire_irq(chip
, 0) < 0) {
2450 pci_set_master(pci
);
2451 synchronize_irq(chip
->irq
);
2453 gcap
= azx_readw(chip
, GCAP
);
2454 snd_printdd(SFX
"chipset global capabilities = 0x%x\n", gcap
);
2456 /* disable SB600 64bit support for safety */
2457 if ((chip
->driver_type
== AZX_DRIVER_ATI
) ||
2458 (chip
->driver_type
== AZX_DRIVER_ATIHDMI
)) {
2459 struct pci_dev
*p_smbus
;
2460 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
2461 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2464 if (p_smbus
->revision
< 0x30)
2465 gcap
&= ~ICH6_GCAP_64OK
;
2466 pci_dev_put(p_smbus
);
2470 /* disable 64bit DMA address for Teradici */
2471 /* it does not work with device 6549:1200 subsys e4a2:040b */
2472 if (chip
->driver_type
== AZX_DRIVER_TERA
)
2473 gcap
&= ~ICH6_GCAP_64OK
;
2475 /* allow 64bit DMA address if supported by H/W */
2476 if ((gcap
& ICH6_GCAP_64OK
) && !pci_set_dma_mask(pci
, DMA_BIT_MASK(64)))
2477 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(64));
2479 pci_set_dma_mask(pci
, DMA_BIT_MASK(32));
2480 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(32));
2483 /* read number of streams from GCAP register instead of using
2486 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
2487 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
2488 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
2489 /* gcap didn't give any info, switching to old method */
2491 switch (chip
->driver_type
) {
2492 case AZX_DRIVER_ULI
:
2493 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
2494 chip
->capture_streams
= ULI_NUM_CAPTURE
;
2496 case AZX_DRIVER_ATIHDMI
:
2497 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
2498 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
2500 case AZX_DRIVER_GENERIC
:
2502 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
2503 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
2507 chip
->capture_index_offset
= 0;
2508 chip
->playback_index_offset
= chip
->capture_streams
;
2509 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
2510 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
2512 if (!chip
->azx_dev
) {
2513 snd_printk(KERN_ERR SFX
"cannot malloc azx_dev\n");
2517 for (i
= 0; i
< chip
->num_streams
; i
++) {
2518 /* allocate memory for the BDL for each stream */
2519 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2520 snd_dma_pci_data(chip
->pci
),
2521 BDL_SIZE
, &chip
->azx_dev
[i
].bdl
);
2523 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
2527 /* allocate memory for the position buffer */
2528 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2529 snd_dma_pci_data(chip
->pci
),
2530 chip
->num_streams
* 8, &chip
->posbuf
);
2532 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
2535 /* allocate CORB/RIRB */
2536 err
= azx_alloc_cmd_io(chip
);
2540 /* initialize streams */
2541 azx_init_stream(chip
);
2543 /* initialize chip */
2545 azx_init_chip(chip
);
2547 /* codec detection */
2548 if (!chip
->codec_mask
) {
2549 snd_printk(KERN_ERR SFX
"no codecs found!\n");
2554 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
2556 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
2560 strcpy(card
->driver
, "HDA-Intel");
2561 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
2562 sizeof(card
->shortname
));
2563 snprintf(card
->longname
, sizeof(card
->longname
),
2564 "%s at 0x%lx irq %i",
2565 card
->shortname
, chip
->addr
, chip
->irq
);
2575 static void power_down_all_codecs(struct azx
*chip
)
2577 #ifdef CONFIG_SND_HDA_POWER_SAVE
2578 /* The codecs were powered up in snd_hda_codec_new().
2579 * Now all initialization done, so turn them down if possible
2581 struct hda_codec
*codec
;
2582 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
2583 snd_hda_power_down(codec
);
2588 static int __devinit
azx_probe(struct pci_dev
*pci
,
2589 const struct pci_device_id
*pci_id
)
2592 struct snd_card
*card
;
2596 if (dev
>= SNDRV_CARDS
)
2603 err
= snd_card_create(index
[dev
], id
[dev
], THIS_MODULE
, 0, &card
);
2605 snd_printk(KERN_ERR SFX
"Error creating card!\n");
2609 /* set this here since it's referred in snd_hda_load_patch() */
2610 snd_card_set_dev(card
, &pci
->dev
);
2612 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2615 card
->private_data
= chip
;
2617 /* create codec instances */
2618 err
= azx_codec_create(chip
, model
[dev
]);
2621 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2623 snd_printk(KERN_ERR SFX
"Applying patch firmware '%s'\n",
2625 err
= snd_hda_load_patch(chip
->bus
, patch
[dev
]);
2630 if (!probe_only
[dev
]) {
2631 err
= azx_codec_configure(chip
);
2636 /* create PCM streams */
2637 err
= snd_hda_build_pcms(chip
->bus
);
2641 /* create mixer controls */
2642 err
= azx_mixer_create(chip
);
2646 err
= snd_card_register(card
);
2650 pci_set_drvdata(pci
, card
);
2652 power_down_all_codecs(chip
);
2653 azx_notifier_register(chip
);
2658 snd_card_free(card
);
2662 static void __devexit
azx_remove(struct pci_dev
*pci
)
2664 snd_card_free(pci_get_drvdata(pci
));
2665 pci_set_drvdata(pci
, NULL
);
2669 static struct pci_device_id azx_ids
[] = {
2671 { PCI_DEVICE(0x8086, 0x2668), .driver_data
= AZX_DRIVER_ICH
},
2672 { PCI_DEVICE(0x8086, 0x27d8), .driver_data
= AZX_DRIVER_ICH
},
2673 { PCI_DEVICE(0x8086, 0x269a), .driver_data
= AZX_DRIVER_ICH
},
2674 { PCI_DEVICE(0x8086, 0x284b), .driver_data
= AZX_DRIVER_ICH
},
2675 { PCI_DEVICE(0x8086, 0x2911), .driver_data
= AZX_DRIVER_ICH
},
2676 { PCI_DEVICE(0x8086, 0x293e), .driver_data
= AZX_DRIVER_ICH
},
2677 { PCI_DEVICE(0x8086, 0x293f), .driver_data
= AZX_DRIVER_ICH
},
2678 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data
= AZX_DRIVER_ICH
},
2679 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data
= AZX_DRIVER_ICH
},
2681 { PCI_DEVICE(0x8086, 0x3b56), .driver_data
= AZX_DRIVER_ICH
},
2682 { PCI_DEVICE(0x8086, 0x3b57), .driver_data
= AZX_DRIVER_ICH
},
2684 { PCI_DEVICE(0x8086, 0x1c20), .driver_data
= AZX_DRIVER_PCH
},
2686 { PCI_DEVICE(0x8086, 0x811b), .driver_data
= AZX_DRIVER_SCH
},
2687 /* ATI SB 450/600 */
2688 { PCI_DEVICE(0x1002, 0x437b), .driver_data
= AZX_DRIVER_ATI
},
2689 { PCI_DEVICE(0x1002, 0x4383), .driver_data
= AZX_DRIVER_ATI
},
2691 { PCI_DEVICE(0x1002, 0x793b), .driver_data
= AZX_DRIVER_ATIHDMI
},
2692 { PCI_DEVICE(0x1002, 0x7919), .driver_data
= AZX_DRIVER_ATIHDMI
},
2693 { PCI_DEVICE(0x1002, 0x960f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2694 { PCI_DEVICE(0x1002, 0x970f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2695 { PCI_DEVICE(0x1002, 0xaa00), .driver_data
= AZX_DRIVER_ATIHDMI
},
2696 { PCI_DEVICE(0x1002, 0xaa08), .driver_data
= AZX_DRIVER_ATIHDMI
},
2697 { PCI_DEVICE(0x1002, 0xaa10), .driver_data
= AZX_DRIVER_ATIHDMI
},
2698 { PCI_DEVICE(0x1002, 0xaa18), .driver_data
= AZX_DRIVER_ATIHDMI
},
2699 { PCI_DEVICE(0x1002, 0xaa20), .driver_data
= AZX_DRIVER_ATIHDMI
},
2700 { PCI_DEVICE(0x1002, 0xaa28), .driver_data
= AZX_DRIVER_ATIHDMI
},
2701 { PCI_DEVICE(0x1002, 0xaa30), .driver_data
= AZX_DRIVER_ATIHDMI
},
2702 { PCI_DEVICE(0x1002, 0xaa38), .driver_data
= AZX_DRIVER_ATIHDMI
},
2703 { PCI_DEVICE(0x1002, 0xaa40), .driver_data
= AZX_DRIVER_ATIHDMI
},
2704 { PCI_DEVICE(0x1002, 0xaa48), .driver_data
= AZX_DRIVER_ATIHDMI
},
2705 /* VIA VT8251/VT8237A */
2706 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2708 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2710 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2712 { PCI_DEVICE(0x10de, 0x026c), .driver_data
= AZX_DRIVER_NVIDIA
},
2713 { PCI_DEVICE(0x10de, 0x0371), .driver_data
= AZX_DRIVER_NVIDIA
},
2714 { PCI_DEVICE(0x10de, 0x03e4), .driver_data
= AZX_DRIVER_NVIDIA
},
2715 { PCI_DEVICE(0x10de, 0x03f0), .driver_data
= AZX_DRIVER_NVIDIA
},
2716 { PCI_DEVICE(0x10de, 0x044a), .driver_data
= AZX_DRIVER_NVIDIA
},
2717 { PCI_DEVICE(0x10de, 0x044b), .driver_data
= AZX_DRIVER_NVIDIA
},
2718 { PCI_DEVICE(0x10de, 0x055c), .driver_data
= AZX_DRIVER_NVIDIA
},
2719 { PCI_DEVICE(0x10de, 0x055d), .driver_data
= AZX_DRIVER_NVIDIA
},
2720 { PCI_DEVICE(0x10de, 0x0590), .driver_data
= AZX_DRIVER_NVIDIA
},
2721 { PCI_DEVICE(0x10de, 0x0774), .driver_data
= AZX_DRIVER_NVIDIA
},
2722 { PCI_DEVICE(0x10de, 0x0775), .driver_data
= AZX_DRIVER_NVIDIA
},
2723 { PCI_DEVICE(0x10de, 0x0776), .driver_data
= AZX_DRIVER_NVIDIA
},
2724 { PCI_DEVICE(0x10de, 0x0777), .driver_data
= AZX_DRIVER_NVIDIA
},
2725 { PCI_DEVICE(0x10de, 0x07fc), .driver_data
= AZX_DRIVER_NVIDIA
},
2726 { PCI_DEVICE(0x10de, 0x07fd), .driver_data
= AZX_DRIVER_NVIDIA
},
2727 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data
= AZX_DRIVER_NVIDIA
},
2728 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data
= AZX_DRIVER_NVIDIA
},
2729 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data
= AZX_DRIVER_NVIDIA
},
2730 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data
= AZX_DRIVER_NVIDIA
},
2731 { PCI_DEVICE(0x10de, 0x0be2), .driver_data
= AZX_DRIVER_NVIDIA
},
2732 { PCI_DEVICE(0x10de, 0x0be3), .driver_data
= AZX_DRIVER_NVIDIA
},
2733 { PCI_DEVICE(0x10de, 0x0be4), .driver_data
= AZX_DRIVER_NVIDIA
},
2734 { PCI_DEVICE(0x10de, 0x0d94), .driver_data
= AZX_DRIVER_NVIDIA
},
2735 { PCI_DEVICE(0x10de, 0x0d95), .driver_data
= AZX_DRIVER_NVIDIA
},
2736 { PCI_DEVICE(0x10de, 0x0d96), .driver_data
= AZX_DRIVER_NVIDIA
},
2737 { PCI_DEVICE(0x10de, 0x0d97), .driver_data
= AZX_DRIVER_NVIDIA
},
2739 { PCI_DEVICE(0x6549, 0x1200), .driver_data
= AZX_DRIVER_TERA
},
2740 /* Creative X-Fi (CA0110-IBG) */
2741 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2742 /* the following entry conflicts with snd-ctxfi driver,
2743 * as ctxfi driver mutates from HD-audio to native mode with
2744 * a special command sequence.
2746 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
2747 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2748 .class_mask
= 0xffffff,
2749 .driver_data
= AZX_DRIVER_GENERIC
},
2751 /* this entry seems still valid -- i.e. without emu20kx chip */
2752 { PCI_DEVICE(0x1102, 0x0009), .driver_data
= AZX_DRIVER_GENERIC
},
2754 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2755 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2756 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2757 .class_mask
= 0xffffff,
2758 .driver_data
= AZX_DRIVER_GENERIC
},
2759 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
),
2760 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2761 .class_mask
= 0xffffff,
2762 .driver_data
= AZX_DRIVER_GENERIC
},
2765 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2767 /* pci_driver definition */
2768 static struct pci_driver driver
= {
2769 .name
= "HDA Intel",
2770 .id_table
= azx_ids
,
2772 .remove
= __devexit_p(azx_remove
),
2774 .suspend
= azx_suspend
,
2775 .resume
= azx_resume
,
2779 static int __init
alsa_card_azx_init(void)
2781 return pci_register_driver(&driver
);
2784 static void __exit
alsa_card_azx_exit(void)
2786 pci_unregister_driver(&driver
);
2789 module_init(alsa_card_azx_init
)
2790 module_exit(alsa_card_azx_exit
)