arch/powerpc/platforms/cell/cbe_regs.h

   1 /*
   2  * cbe_regs.h
   3  *
   4  * This file is intended to hold the various register definitions for CBE
   5  * on-chip system devices (memory controller, IO controller, etc...)
   6  *
   7  * (C) Copyright IBM Corporation 2001,2006
   8  *
   9  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
  10  *          David J. Erb (djerb@us.ibm.com)
  11  *
  12  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
  13  */
  14
  15 #ifndef CBE_REGS_H
  16 #define CBE_REGS_H
  17
  18 /*
  19  *
  20  * Some HID register definitions
  21  *
  22  */
  23
  24 /* CBE specific HID0 bits */
  25 #define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
  26 #define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
  27 #define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
  28 #define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
  29
  30 #define MAX_CBE         2
  31
  32 /*
  33  *
  34  * Pervasive unit register definitions
  35  *
  36  */
  37
  38 union spe_reg {
  39         u64 val;
  40         u8 spe[8];
  41 };
  42
  43 union ppe_spe_reg {
  44         u64 val;
  45         struct {
  46                 u32 ppe;
  47                 u32 spe;
  48         };
  49 };
  50
  51
  52 struct cbe_pmd_regs {
  53         /* Debug Bus Control */
  54         u64     pad_0x0000;                                     /* 0x0000 */
  55
  56         u64     group_control;                                  /* 0x0008 */
  57
  58         u8      pad_0x0010_0x00a8 [0x00a8 - 0x0010];            /* 0x0010 */
  59
  60         u64     debug_bus_control;                              /* 0x00a8 */
  61
  62         u8      pad_0x00b0_0x0100 [0x0100 - 0x00b0];            /* 0x00b0 */
  63
  64         u64     trace_aux_data;                                 /* 0x0100 */
  65         u64     trace_buffer_0_63;                              /* 0x0108 */
  66         u64     trace_buffer_64_127;                            /* 0x0110 */
  67         u64     trace_address;                                  /* 0x0118 */
  68         u64     ext_tr_timer;                                   /* 0x0120 */
  69
  70         u8      pad_0x0128_0x0400 [0x0400 - 0x0128];            /* 0x0128 */
  71
  72         /* Performance Monitor */
  73         u64     pm_status;                                      /* 0x0400 */
  74         u64     pm_control;                                     /* 0x0408 */
  75         u64     pm_interval;                                    /* 0x0410 */
  76         u64     pm_ctr[4];                                      /* 0x0418 */
  77         u64     pm_start_stop;                                  /* 0x0438 */
  78         u64     pm07_control[8];                                /* 0x0440 */
  79
  80         u8      pad_0x0480_0x0800 [0x0800 - 0x0480];            /* 0x0480 */
  81
  82         /* Thermal Sensor Registers */
  83         union   spe_reg ts_ctsr1;                               /* 0x0800 */
  84         u64     ts_ctsr2;                                       /* 0x0808 */
  85         union   spe_reg ts_mtsr1;                               /* 0x0810 */
  86         u64     ts_mtsr2;                                       /* 0x0818 */
  87         union   spe_reg ts_itr1;                                /* 0x0820 */
  88         u64     ts_itr2;                                        /* 0x0828 */
  89         u64     ts_gitr;                                        /* 0x0830 */
  90         u64     ts_isr;                                         /* 0x0838 */
  91         u64     ts_imr;                                         /* 0x0840 */
  92         union   spe_reg tm_cr1;                                 /* 0x0848 */
  93         u64     tm_cr2;                                         /* 0x0850 */
  94         u64     tm_simr;                                        /* 0x0858 */
  95         union   ppe_spe_reg tm_tpr;                             /* 0x0860 */
  96         union   spe_reg tm_str1;                                /* 0x0868 */
  97         u64     tm_str2;                                        /* 0x0870 */
  98         union   ppe_spe_reg tm_tsr;                             /* 0x0878 */
  99
 100         /* Power Management */
 101         u64     pmcr;                                           /* 0x0880 */
 102 #define CBE_PMD_PAUSE_ZERO_CONTROL      0x10000
 103         u64     pmsr;                                           /* 0x0888 */
 104
 105         /* Time Base Register */
 106         u64     tbr;                                            /* 0x0890 */
 107
 108         u8      pad_0x0898_0x0c00 [0x0c00 - 0x0898];            /* 0x0898 */
 109
 110         /* Fault Isolation Registers */
 111         u64     checkstop_fir;                                  /* 0x0c00 */
 112         u64     recoverable_fir;                                /* 0x0c08 */
 113         u64     spec_att_mchk_fir;                              /* 0x0c10 */
 114         u64     fir_mode_reg;                                   /* 0x0c18 */
 115         u64     fir_enable_mask;                                /* 0x0c20 */
 116
 117         u8      pad_0x0c28_0x1000 [0x1000 - 0x0c28];            /* 0x0c28 */
 118 };
 119
 120 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
 121 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
 122
 123 /*
 124  * PMU shadow registers
 125  *
 126  * Many of the registers in the performance monitoring unit are write-only,
 127  * so we need to save a copy of what we write to those registers.
 128  *
 129  * The actual data counters are read/write. However, writing to the counters
 130  * only takes effect if the PMU is enabled. Otherwise the value is stored in
 131  * a hardware latch until the next time the PMU is enabled. So we save a copy
 132  * of the counter values if we need to read them back while the PMU is
 133  * disabled. The counter_value_in_latch field is a bitmap indicating which
 134  * counters currently have a value waiting to be written.
 135  */
 136
 137 #define NR_PHYS_CTRS    4
 138 #define NR_CTRS         (NR_PHYS_CTRS * 2)
 139
 140 struct cbe_pmd_shadow_regs {
 141         u32 group_control;
 142         u32 debug_bus_control;
 143         u32 trace_address;
 144         u32 ext_tr_timer;
 145         u32 pm_status;
 146         u32 pm_control;
 147         u32 pm_interval;
 148         u32 pm_start_stop;
 149         u32 pm07_control[NR_CTRS];
 150
 151         u32 pm_ctr[NR_PHYS_CTRS];
 152         u32 counter_value_in_latch;
 153 };
 154
 155 extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
 156 extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
 157
 158 /*
 159  *
 160  * IIC unit register definitions
 161  *
 162  */
 163
 164 struct cbe_iic_pending_bits {
 165         u32 data;
 166         u8 flags;
 167         u8 class;
 168         u8 source;
 169         u8 prio;
 170 };
 171
 172 #define CBE_IIC_IRQ_VALID       0x80
 173 #define CBE_IIC_IRQ_IPI         0x40
 174
 175 struct cbe_iic_thread_regs {
 176         struct cbe_iic_pending_bits pending;
 177         struct cbe_iic_pending_bits pending_destr;
 178         u64 generate;
 179         u64 prio;
 180 };
 181
 182 struct cbe_iic_regs {
 183         u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
 184
 185         /* IIC interrupt registers */
 186         struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
 187
 188         u64     iic_ir;                                         /* 0x0440 */
 189         u64     iic_is;                                         /* 0x0448 */
 190 #define CBE_IIC_IS_PMI          0x2
 191
 192         u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
 193
 194         /* IOC FIR */
 195         u64     ioc_fir_reset;                                  /* 0x0500 */
 196         u64     ioc_fir_set;                                    /* 0x0508 */
 197         u64     ioc_checkstop_enable;                           /* 0x0510 */
 198         u64     ioc_fir_error_mask;                             /* 0x0518 */
 199         u64     ioc_syserr_enable;                              /* 0x0520 */
 200         u64     ioc_fir;                                        /* 0x0528 */
 201
 202         u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
 203 };
 204
 205 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
 206 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
 207
 208
 209 struct cbe_mic_tm_regs {
 210         u8      pad_0x0000_0x0040[0x0040 - 0x0000];             /* 0x0000 */
 211
 212         u64     mic_ctl_cnfg2;                                  /* 0x0040 */
 213 #define CBE_MIC_ENABLE_AUX_TRC          0x8000000000000000LL
 214 #define CBE_MIC_DISABLE_PWR_SAV_2       0x0200000000000000LL
 215 #define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
 216 #define CBE_MIC_ENABLE_AUX_TRC_INT      0x0080000000000000LL
 217
 218         u64     pad_0x0048;                                     /* 0x0048 */
 219
 220         u64     mic_aux_trc_base;                               /* 0x0050 */
 221         u64     mic_aux_trc_max_addr;                           /* 0x0058 */
 222         u64     mic_aux_trc_cur_addr;                           /* 0x0060 */
 223         u64     mic_aux_trc_grf_addr;                           /* 0x0068 */
 224         u64     mic_aux_trc_grf_data;                           /* 0x0070 */
 225
 226         u64     pad_0x0078;                                     /* 0x0078 */
 227
 228         u64     mic_ctl_cnfg_0;                                 /* 0x0080 */
 229 #define CBE_MIC_DISABLE_PWR_SAV_0       0x8000000000000000LL
 230
 231         u64     pad_0x0088;                                     /* 0x0088 */
 232
 233         u64     slow_fast_timer_0;                              /* 0x0090 */
 234         u64     slow_next_timer_0;                              /* 0x0098 */
 235
 236         u8      pad_0x00a0_0x01c0[0x01c0 - 0x0a0];              /* 0x00a0 */
 237
 238         u64     mic_ctl_cnfg_1;                                 /* 0x01c0 */
 239 #define CBE_MIC_DISABLE_PWR_SAV_1       0x8000000000000000LL
 240         u64     pad_0x01c8;                                     /* 0x01c8 */
 241
 242         u64     slow_fast_timer_1;                              /* 0x01d0 */
 243         u64     slow_next_timer_1;                              /* 0x01d8 */
 244
 245         u8      pad_0x01e0_0x1000[0x1000 - 0x01e0];             /* 0x01e0 */
 246 };
 247
 248 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 249 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 250
 251 /* Init this module early */
 252 extern void cbe_regs_init(void);
 253
 254
 255 #endif /* CBE_REGS_H */