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thinkpad-acpi: make driver events work in NVRAM poll mode
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / synclink.c
blobafd0b26ca05681210edd0cc0f22b01497eea3e37
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
81 #include <linux/mm.h>
82 #include <linux/seq_file.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
85 #include <linux/netdevice.h>
86 #include <linux/vmalloc.h>
87 #include <linux/init.h>
88 #include <linux/ioctl.h>
89 #include <linux/synclink.h>
90
91 #include <asm/system.h>
92 #include <asm/io.h>
93 #include <asm/irq.h>
94 #include <asm/dma.h>
95 #include <linux/bitops.h>
96 #include <asm/types.h>
97 #include <linux/termios.h>
98 #include <linux/workqueue.h>
99 #include <linux/hdlc.h>
100 #include <linux/dma-mapping.h>
101
102 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
103 #define SYNCLINK_GENERIC_HDLC 1
104 #else
105 #define SYNCLINK_GENERIC_HDLC 0
106 #endif
107
108 #define GET_USER(error,value,addr) error = get_user(value,addr)
109 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
110 #define PUT_USER(error,value,addr) error = put_user(value,addr)
111 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112
113 #include <asm/uaccess.h>
114
115 #define RCLRVALUE 0xffff
116
117 static MGSL_PARAMS default_params = {
118 MGSL_MODE_HDLC, /* unsigned long mode */
119 0, /* unsigned char loopback; */
120 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
121 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
122 0, /* unsigned long clock_speed; */
123 0xff, /* unsigned char addr_filter; */
124 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
125 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
126 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
127 9600, /* unsigned long data_rate; */
128 8, /* unsigned char data_bits; */
129 1, /* unsigned char stop_bits; */
130 ASYNC_PARITY_NONE /* unsigned char parity; */
131 };
132
133 #define SHARED_MEM_ADDRESS_SIZE 0x40000
134 #define BUFFERLISTSIZE 4096
135 #define DMABUFFERSIZE 4096
136 #define MAXRXFRAMES 7
137
138 typedef struct _DMABUFFERENTRY
139 {
140 u32 phys_addr; /* 32-bit flat physical address of data buffer */
141 volatile u16 count; /* buffer size/data count */
142 volatile u16 status; /* Control/status field */
143 volatile u16 rcc; /* character count field */
144 u16 reserved; /* padding required by 16C32 */
145 u32 link; /* 32-bit flat link to next buffer entry */
146 char *virt_addr; /* virtual address of data buffer */
147 u32 phys_entry; /* physical address of this buffer entry */
148 dma_addr_t dma_addr;
149 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
150
151 /* The queue of BH actions to be performed */
152
153 #define BH_RECEIVE 1
154 #define BH_TRANSMIT 2
155 #define BH_STATUS 4
156
157 #define IO_PIN_SHUTDOWN_LIMIT 100
158
159 struct _input_signal_events {
160 int ri_up;
161 int ri_down;
162 int dsr_up;
163 int dsr_down;
164 int dcd_up;
165 int dcd_down;
166 int cts_up;
167 int cts_down;
168 };
169
170 /* transmit holding buffer definitions*/
171 #define MAX_TX_HOLDING_BUFFERS 5
172 struct tx_holding_buffer {
173 int buffer_size;
174 unsigned char * buffer;
175 };
176
177
178 /*
179 * Device instance data structure
180 */
181
182 struct mgsl_struct {
183 int magic;
184 struct tty_port port;
185 int line;
186 int hw_version;
187
188 struct mgsl_icount icount;
189
190 int timeout;
191 int x_char; /* xon/xoff character */
192 u16 read_status_mask;
193 u16 ignore_status_mask;
194 unsigned char *xmit_buf;
195 int xmit_head;
196 int xmit_tail;
197 int xmit_cnt;
198
199 wait_queue_head_t status_event_wait_q;
200 wait_queue_head_t event_wait_q;
201 struct timer_list tx_timer; /* HDLC transmit timeout timer */
202 struct mgsl_struct *next_device; /* device list link */
203
204 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
205 struct work_struct task; /* task structure for scheduling bh */
206
207 u32 EventMask; /* event trigger mask */
208 u32 RecordedEvents; /* pending events */
209
210 u32 max_frame_size; /* as set by device config */
211
212 u32 pending_bh;
213
214 bool bh_running; /* Protection from multiple */
215 int isr_overflow;
216 bool bh_requested;
217
218 int dcd_chkcount; /* check counts to prevent */
219 int cts_chkcount; /* too many IRQs if a signal */
220 int dsr_chkcount; /* is floating */
221 int ri_chkcount;
222
223 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
224 u32 buffer_list_phys;
225 dma_addr_t buffer_list_dma_addr;
226
227 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
228 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
229 unsigned int current_rx_buffer;
230
231 int num_tx_dma_buffers; /* number of tx dma frames required */
232 int tx_dma_buffers_used;
233 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
234 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
235 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
236 int current_tx_buffer; /* next tx dma buffer to be loaded */
237
238 unsigned char *intermediate_rxbuffer;
239
240 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
241 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
242 int put_tx_holding_index; /* next tx holding buffer to store user request */
243 int tx_holding_count; /* number of tx holding buffers waiting */
244 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
245
246 bool rx_enabled;
247 bool rx_overflow;
248 bool rx_rcc_underrun;
249
250 bool tx_enabled;
251 bool tx_active;
252 u32 idle_mode;
253
254 u16 cmr_value;
255 u16 tcsr_value;
256
257 char device_name[25]; /* device instance name */
258
259 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
260 unsigned char bus; /* expansion bus number (zero based) */
261 unsigned char function; /* PCI device number */
262
263 unsigned int io_base; /* base I/O address of adapter */
264 unsigned int io_addr_size; /* size of the I/O address range */
265 bool io_addr_requested; /* true if I/O address requested */
266
267 unsigned int irq_level; /* interrupt level */
268 unsigned long irq_flags;
269 bool irq_requested; /* true if IRQ requested */
270
271 unsigned int dma_level; /* DMA channel */
272 bool dma_requested; /* true if dma channel requested */
273
274 u16 mbre_bit;
275 u16 loopback_bits;
276 u16 usc_idle_mode;
277
278 MGSL_PARAMS params; /* communications parameters */
279
280 unsigned char serial_signals; /* current serial signal states */
281
282 bool irq_occurred; /* for diagnostics use */
283 unsigned int init_error; /* Initialization startup error (DIAGS) */
284 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
285
286 u32 last_mem_alloc;
287 unsigned char* memory_base; /* shared memory address (PCI only) */
288 u32 phys_memory_base;
289 bool shared_mem_requested;
290
291 unsigned char* lcr_base; /* local config registers (PCI only) */
292 u32 phys_lcr_base;
293 u32 lcr_offset;
294 bool lcr_mem_requested;
295
296 u32 misc_ctrl_value;
297 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
298 char char_buf[MAX_ASYNC_BUFFER_SIZE];
299 bool drop_rts_on_tx_done;
300
301 bool loopmode_insert_requested;
302 bool loopmode_send_done_requested;
303
304 struct _input_signal_events input_signal_events;
305
306 /* generic HDLC device parts */
307 int netcount;
308 spinlock_t netlock;
309
310 #if SYNCLINK_GENERIC_HDLC
311 struct net_device *netdev;
312 #endif
313 };
314
315 #define MGSL_MAGIC 0x5401
316
317 /*
318 * The size of the serial xmit buffer is 1 page, or 4096 bytes
319 */
320 #ifndef SERIAL_XMIT_SIZE
321 #define SERIAL_XMIT_SIZE 4096
322 #endif
323
324 /*
325 * These macros define the offsets used in calculating the
326 * I/O address of the specified USC registers.
327 */
328
329
330 #define DCPIN 2 /* Bit 1 of I/O address */
331 #define SDPIN 4 /* Bit 2 of I/O address */
332
333 #define DCAR 0 /* DMA command/address register */
334 #define CCAR SDPIN /* channel command/address register */
335 #define DATAREG DCPIN + SDPIN /* serial data register */
336 #define MSBONLY 0x41
337 #define LSBONLY 0x40
338
339 /*
340 * These macros define the register address (ordinal number)
341 * used for writing address/value pairs to the USC.
342 */
343
344 #define CMR 0x02 /* Channel mode Register */
345 #define CCSR 0x04 /* Channel Command/status Register */
346 #define CCR 0x06 /* Channel Control Register */
347 #define PSR 0x08 /* Port status Register */
348 #define PCR 0x0a /* Port Control Register */
349 #define TMDR 0x0c /* Test mode Data Register */
350 #define TMCR 0x0e /* Test mode Control Register */
351 #define CMCR 0x10 /* Clock mode Control Register */
352 #define HCR 0x12 /* Hardware Configuration Register */
353 #define IVR 0x14 /* Interrupt Vector Register */
354 #define IOCR 0x16 /* Input/Output Control Register */
355 #define ICR 0x18 /* Interrupt Control Register */
356 #define DCCR 0x1a /* Daisy Chain Control Register */
357 #define MISR 0x1c /* Misc Interrupt status Register */
358 #define SICR 0x1e /* status Interrupt Control Register */
359 #define RDR 0x20 /* Receive Data Register */
360 #define RMR 0x22 /* Receive mode Register */
361 #define RCSR 0x24 /* Receive Command/status Register */
362 #define RICR 0x26 /* Receive Interrupt Control Register */
363 #define RSR 0x28 /* Receive Sync Register */
364 #define RCLR 0x2a /* Receive count Limit Register */
365 #define RCCR 0x2c /* Receive Character count Register */
366 #define TC0R 0x2e /* Time Constant 0 Register */
367 #define TDR 0x30 /* Transmit Data Register */
368 #define TMR 0x32 /* Transmit mode Register */
369 #define TCSR 0x34 /* Transmit Command/status Register */
370 #define TICR 0x36 /* Transmit Interrupt Control Register */
371 #define TSR 0x38 /* Transmit Sync Register */
372 #define TCLR 0x3a /* Transmit count Limit Register */
373 #define TCCR 0x3c /* Transmit Character count Register */
374 #define TC1R 0x3e /* Time Constant 1 Register */
375
376
377 /*
378 * MACRO DEFINITIONS FOR DMA REGISTERS
379 */
380
381 #define DCR 0x06 /* DMA Control Register (shared) */
382 #define DACR 0x08 /* DMA Array count Register (shared) */
383 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
384 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
385 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
386 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
387 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
388
389 #define TDMR 0x02 /* Transmit DMA mode Register */
390 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
391 #define TBCR 0x2a /* Transmit Byte count Register */
392 #define TARL 0x2c /* Transmit Address Register (low) */
393 #define TARU 0x2e /* Transmit Address Register (high) */
394 #define NTBCR 0x3a /* Next Transmit Byte count Register */
395 #define NTARL 0x3c /* Next Transmit Address Register (low) */
396 #define NTARU 0x3e /* Next Transmit Address Register (high) */
397
398 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
399 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
400 #define RBCR 0xaa /* Receive Byte count Register */
401 #define RARL 0xac /* Receive Address Register (low) */
402 #define RARU 0xae /* Receive Address Register (high) */
403 #define NRBCR 0xba /* Next Receive Byte count Register */
404 #define NRARL 0xbc /* Next Receive Address Register (low) */
405 #define NRARU 0xbe /* Next Receive Address Register (high) */
406
407
408 /*
409 * MACRO DEFINITIONS FOR MODEM STATUS BITS
410 */
411
412 #define MODEMSTATUS_DTR 0x80
413 #define MODEMSTATUS_DSR 0x40
414 #define MODEMSTATUS_RTS 0x20
415 #define MODEMSTATUS_CTS 0x10
416 #define MODEMSTATUS_RI 0x04
417 #define MODEMSTATUS_DCD 0x01
418
419
420 /*
421 * Channel Command/Address Register (CCAR) Command Codes
422 */
423
424 #define RTCmd_Null 0x0000
425 #define RTCmd_ResetHighestIus 0x1000
426 #define RTCmd_TriggerChannelLoadDma 0x2000
427 #define RTCmd_TriggerRxDma 0x2800
428 #define RTCmd_TriggerTxDma 0x3000
429 #define RTCmd_TriggerRxAndTxDma 0x3800
430 #define RTCmd_PurgeRxFifo 0x4800
431 #define RTCmd_PurgeTxFifo 0x5000
432 #define RTCmd_PurgeRxAndTxFifo 0x5800
433 #define RTCmd_LoadRcc 0x6800
434 #define RTCmd_LoadTcc 0x7000
435 #define RTCmd_LoadRccAndTcc 0x7800
436 #define RTCmd_LoadTC0 0x8800
437 #define RTCmd_LoadTC1 0x9000
438 #define RTCmd_LoadTC0AndTC1 0x9800
439 #define RTCmd_SerialDataLSBFirst 0xa000
440 #define RTCmd_SerialDataMSBFirst 0xa800
441 #define RTCmd_SelectBigEndian 0xb000
442 #define RTCmd_SelectLittleEndian 0xb800
443
444
445 /*
446 * DMA Command/Address Register (DCAR) Command Codes
447 */
448
449 #define DmaCmd_Null 0x0000
450 #define DmaCmd_ResetTxChannel 0x1000
451 #define DmaCmd_ResetRxChannel 0x1200
452 #define DmaCmd_StartTxChannel 0x2000
453 #define DmaCmd_StartRxChannel 0x2200
454 #define DmaCmd_ContinueTxChannel 0x3000
455 #define DmaCmd_ContinueRxChannel 0x3200
456 #define DmaCmd_PauseTxChannel 0x4000
457 #define DmaCmd_PauseRxChannel 0x4200
458 #define DmaCmd_AbortTxChannel 0x5000
459 #define DmaCmd_AbortRxChannel 0x5200
460 #define DmaCmd_InitTxChannel 0x7000
461 #define DmaCmd_InitRxChannel 0x7200
462 #define DmaCmd_ResetHighestDmaIus 0x8000
463 #define DmaCmd_ResetAllChannels 0x9000
464 #define DmaCmd_StartAllChannels 0xa000
465 #define DmaCmd_ContinueAllChannels 0xb000
466 #define DmaCmd_PauseAllChannels 0xc000
467 #define DmaCmd_AbortAllChannels 0xd000
468 #define DmaCmd_InitAllChannels 0xf000
469
470 #define TCmd_Null 0x0000
471 #define TCmd_ClearTxCRC 0x2000
472 #define TCmd_SelectTicrTtsaData 0x4000
473 #define TCmd_SelectTicrTxFifostatus 0x5000
474 #define TCmd_SelectTicrIntLevel 0x6000
475 #define TCmd_SelectTicrdma_level 0x7000
476 #define TCmd_SendFrame 0x8000
477 #define TCmd_SendAbort 0x9000
478 #define TCmd_EnableDleInsertion 0xc000
479 #define TCmd_DisableDleInsertion 0xd000
480 #define TCmd_ClearEofEom 0xe000
481 #define TCmd_SetEofEom 0xf000
482
483 #define RCmd_Null 0x0000
484 #define RCmd_ClearRxCRC 0x2000
485 #define RCmd_EnterHuntmode 0x3000
486 #define RCmd_SelectRicrRtsaData 0x4000
487 #define RCmd_SelectRicrRxFifostatus 0x5000
488 #define RCmd_SelectRicrIntLevel 0x6000
489 #define RCmd_SelectRicrdma_level 0x7000
490
491 /*
492 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
493 */
494
495 #define RECEIVE_STATUS BIT5
496 #define RECEIVE_DATA BIT4
497 #define TRANSMIT_STATUS BIT3
498 #define TRANSMIT_DATA BIT2
499 #define IO_PIN BIT1
500 #define MISC BIT0
501
502
503 /*
504 * Receive status Bits in Receive Command/status Register RCSR
505 */
506
507 #define RXSTATUS_SHORT_FRAME BIT8
508 #define RXSTATUS_CODE_VIOLATION BIT8
509 #define RXSTATUS_EXITED_HUNT BIT7
510 #define RXSTATUS_IDLE_RECEIVED BIT6
511 #define RXSTATUS_BREAK_RECEIVED BIT5
512 #define RXSTATUS_ABORT_RECEIVED BIT5
513 #define RXSTATUS_RXBOUND BIT4
514 #define RXSTATUS_CRC_ERROR BIT3
515 #define RXSTATUS_FRAMING_ERROR BIT3
516 #define RXSTATUS_ABORT BIT2
517 #define RXSTATUS_PARITY_ERROR BIT2
518 #define RXSTATUS_OVERRUN BIT1
519 #define RXSTATUS_DATA_AVAILABLE BIT0
520 #define RXSTATUS_ALL 0x01f6
521 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
522
523 /*
524 * Values for setting transmit idle mode in
525 * Transmit Control/status Register (TCSR)
526 */
527 #define IDLEMODE_FLAGS 0x0000
528 #define IDLEMODE_ALT_ONE_ZERO 0x0100
529 #define IDLEMODE_ZERO 0x0200
530 #define IDLEMODE_ONE 0x0300
531 #define IDLEMODE_ALT_MARK_SPACE 0x0500
532 #define IDLEMODE_SPACE 0x0600
533 #define IDLEMODE_MARK 0x0700
534 #define IDLEMODE_MASK 0x0700
535
536 /*
537 * IUSC revision identifiers
538 */
539 #define IUSC_SL1660 0x4d44
540 #define IUSC_PRE_SL1660 0x4553
541
542 /*
543 * Transmit status Bits in Transmit Command/status Register (TCSR)
544 */
545
546 #define TCSR_PRESERVE 0x0F00
547
548 #define TCSR_UNDERWAIT BIT11
549 #define TXSTATUS_PREAMBLE_SENT BIT7
550 #define TXSTATUS_IDLE_SENT BIT6
551 #define TXSTATUS_ABORT_SENT BIT5
552 #define TXSTATUS_EOF_SENT BIT4
553 #define TXSTATUS_EOM_SENT BIT4
554 #define TXSTATUS_CRC_SENT BIT3
555 #define TXSTATUS_ALL_SENT BIT2
556 #define TXSTATUS_UNDERRUN BIT1
557 #define TXSTATUS_FIFO_EMPTY BIT0
558 #define TXSTATUS_ALL 0x00fa
559 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
560
561
562 #define MISCSTATUS_RXC_LATCHED BIT15
563 #define MISCSTATUS_RXC BIT14
564 #define MISCSTATUS_TXC_LATCHED BIT13
565 #define MISCSTATUS_TXC BIT12
566 #define MISCSTATUS_RI_LATCHED BIT11
567 #define MISCSTATUS_RI BIT10
568 #define MISCSTATUS_DSR_LATCHED BIT9
569 #define MISCSTATUS_DSR BIT8
570 #define MISCSTATUS_DCD_LATCHED BIT7
571 #define MISCSTATUS_DCD BIT6
572 #define MISCSTATUS_CTS_LATCHED BIT5
573 #define MISCSTATUS_CTS BIT4
574 #define MISCSTATUS_RCC_UNDERRUN BIT3
575 #define MISCSTATUS_DPLL_NO_SYNC BIT2
576 #define MISCSTATUS_BRG1_ZERO BIT1
577 #define MISCSTATUS_BRG0_ZERO BIT0
578
579 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
580 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581
582 #define SICR_RXC_ACTIVE BIT15
583 #define SICR_RXC_INACTIVE BIT14
584 #define SICR_RXC (BIT15+BIT14)
585 #define SICR_TXC_ACTIVE BIT13
586 #define SICR_TXC_INACTIVE BIT12
587 #define SICR_TXC (BIT13+BIT12)
588 #define SICR_RI_ACTIVE BIT11
589 #define SICR_RI_INACTIVE BIT10
590 #define SICR_RI (BIT11+BIT10)
591 #define SICR_DSR_ACTIVE BIT9
592 #define SICR_DSR_INACTIVE BIT8
593 #define SICR_DSR (BIT9+BIT8)
594 #define SICR_DCD_ACTIVE BIT7
595 #define SICR_DCD_INACTIVE BIT6
596 #define SICR_DCD (BIT7+BIT6)
597 #define SICR_CTS_ACTIVE BIT5
598 #define SICR_CTS_INACTIVE BIT4
599 #define SICR_CTS (BIT5+BIT4)
600 #define SICR_RCC_UNDERFLOW BIT3
601 #define SICR_DPLL_NO_SYNC BIT2
602 #define SICR_BRG1_ZERO BIT1
603 #define SICR_BRG0_ZERO BIT0
604
605 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
606 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
607 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
608 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
610
611 #define usc_EnableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613
614 #define usc_DisableInterrupts( a, b ) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616
617 #define usc_EnableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619
620 #define usc_DisableMasterIrqBit(a) \
621 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622
623 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
624
625 /*
626 * Transmit status Bits in Transmit Control status Register (TCSR)
627 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
628 */
629
630 #define TXSTATUS_PREAMBLE_SENT BIT7
631 #define TXSTATUS_IDLE_SENT BIT6
632 #define TXSTATUS_ABORT_SENT BIT5
633 #define TXSTATUS_EOF BIT4
634 #define TXSTATUS_CRC_SENT BIT3
635 #define TXSTATUS_ALL_SENT BIT2
636 #define TXSTATUS_UNDERRUN BIT1
637 #define TXSTATUS_FIFO_EMPTY BIT0
638
639 #define DICR_MASTER BIT15
640 #define DICR_TRANSMIT BIT0
641 #define DICR_RECEIVE BIT1
642
643 #define usc_EnableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645
646 #define usc_DisableDmaInterrupts(a,b) \
647 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648
649 #define usc_EnableStatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651
652 #define usc_DisablestatusIrqs(a,b) \
653 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654
655 /* Transmit status Bits in Transmit Control status Register (TCSR) */
656 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
657
658
659 #define DISABLE_UNCONDITIONAL 0
660 #define DISABLE_END_OF_FRAME 1
661 #define ENABLE_UNCONDITIONAL 2
662 #define ENABLE_AUTO_CTS 3
663 #define ENABLE_AUTO_DCD 3
664 #define usc_EnableTransmitter(a,b) \
665 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
666 #define usc_EnableReceiver(a,b) \
667 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668
669 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
670 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
671 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
672
673 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
674 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
675 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
676 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
677 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
678
679 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
680 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681
682 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683
684 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
685 static void usc_start_receiver( struct mgsl_struct *info );
686 static void usc_stop_receiver( struct mgsl_struct *info );
687
688 static void usc_start_transmitter( struct mgsl_struct *info );
689 static void usc_stop_transmitter( struct mgsl_struct *info );
690 static void usc_set_txidle( struct mgsl_struct *info );
691 static void usc_load_txfifo( struct mgsl_struct *info );
692
693 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
694 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
695
696 static void usc_get_serial_signals( struct mgsl_struct *info );
697 static void usc_set_serial_signals( struct mgsl_struct *info );
698
699 static void usc_reset( struct mgsl_struct *info );
700
701 static void usc_set_sync_mode( struct mgsl_struct *info );
702 static void usc_set_sdlc_mode( struct mgsl_struct *info );
703 static void usc_set_async_mode( struct mgsl_struct *info );
704 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705
706 static void usc_loopback_frame( struct mgsl_struct *info );
707
708 static void mgsl_tx_timeout(unsigned long context);
709
710
711 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
712 static void usc_loopmode_insert_request( struct mgsl_struct * info );
713 static int usc_loopmode_active( struct mgsl_struct * info);
714 static void usc_loopmode_send_done( struct mgsl_struct * info );
715
716 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
717
718 #if SYNCLINK_GENERIC_HDLC
719 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
720 static void hdlcdev_tx_done(struct mgsl_struct *info);
721 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
722 static int hdlcdev_init(struct mgsl_struct *info);
723 static void hdlcdev_exit(struct mgsl_struct *info);
724 #endif
725
726 /*
727 * Defines a BUS descriptor value for the PCI adapter
728 * local bus address ranges.
729 */
730
731 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
732 (0x00400020 + \
733 ((WrHold) << 30) + \
734 ((WrDly) << 28) + \
735 ((RdDly) << 26) + \
736 ((Nwdd) << 20) + \
737 ((Nwad) << 15) + \
738 ((Nxda) << 13) + \
739 ((Nrdd) << 11) + \
740 ((Nrad) << 6) )
741
742 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
743
744 /*
745 * Adapter diagnostic routines
746 */
747 static bool mgsl_register_test( struct mgsl_struct *info );
748 static bool mgsl_irq_test( struct mgsl_struct *info );
749 static bool mgsl_dma_test( struct mgsl_struct *info );
750 static bool mgsl_memory_test( struct mgsl_struct *info );
751 static int mgsl_adapter_test( struct mgsl_struct *info );
752
753 /*
754 * device and resource management routines
755 */
756 static int mgsl_claim_resources(struct mgsl_struct *info);
757 static void mgsl_release_resources(struct mgsl_struct *info);
758 static void mgsl_add_device(struct mgsl_struct *info);
759 static struct mgsl_struct* mgsl_allocate_device(void);
760
761 /*
762 * DMA buffer manupulation functions.
763 */
764 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
765 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
766 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
767 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
768 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
769 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
770 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
771 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
772
773 /*
774 * DMA and Shared Memory buffer allocation and formatting
775 */
776 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
777 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
778 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
779 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
781 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
782 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
783 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
785 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
786 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
787 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
788
789 /*
790 * Bottom half interrupt handlers
791 */
792 static void mgsl_bh_handler(struct work_struct *work);
793 static void mgsl_bh_receive(struct mgsl_struct *info);
794 static void mgsl_bh_transmit(struct mgsl_struct *info);
795 static void mgsl_bh_status(struct mgsl_struct *info);
796
797 /*
798 * Interrupt handler routines and dispatch table.
799 */
800 static void mgsl_isr_null( struct mgsl_struct *info );
801 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
802 static void mgsl_isr_receive_data( struct mgsl_struct *info );
803 static void mgsl_isr_receive_status( struct mgsl_struct *info );
804 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
805 static void mgsl_isr_io_pin( struct mgsl_struct *info );
806 static void mgsl_isr_misc( struct mgsl_struct *info );
807 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
808 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
809
810 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811
812 static isr_dispatch_func UscIsrTable[7] =
813 {
814 mgsl_isr_null,
815 mgsl_isr_misc,
816 mgsl_isr_io_pin,
817 mgsl_isr_transmit_data,
818 mgsl_isr_transmit_status,
819 mgsl_isr_receive_data,
820 mgsl_isr_receive_status
821 };
822
823 /*
824 * ioctl call handlers
825 */
826 static int tiocmget(struct tty_struct *tty, struct file *file);
827 static int tiocmset(struct tty_struct *tty, struct file *file,
828 unsigned int set, unsigned int clear);
829 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
830 __user *user_icount);
831 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
832 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
833 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
834 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
835 static int mgsl_txenable(struct mgsl_struct * info, int enable);
836 static int mgsl_txabort(struct mgsl_struct * info);
837 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
838 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
839 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840
841 /* set non-zero on successful registration with PCI subsystem */
842 static bool pci_registered;
843
844 /*
845 * Global linked list of SyncLink devices
846 */
847 static struct mgsl_struct *mgsl_device_list;
848 static int mgsl_device_count;
849
850 /*
851 * Set this param to non-zero to load eax with the
852 * .text section address and breakpoint on module load.
853 * This is useful for use with gdb and add-symbol-file command.
854 */
855 static int break_on_load;
856
857 /*
858 * Driver major number, defaults to zero to get auto
859 * assigned major number. May be forced as module parameter.
860 */
861 static int ttymajor;
862
863 /*
864 * Array of user specified options for ISA adapters.
865 */
866 static int io[MAX_ISA_DEVICES];
867 static int irq[MAX_ISA_DEVICES];
868 static int dma[MAX_ISA_DEVICES];
869 static int debug_level;
870 static int maxframe[MAX_TOTAL_DEVICES];
871 static int txdmabufs[MAX_TOTAL_DEVICES];
872 static int txholdbufs[MAX_TOTAL_DEVICES];
873
874 module_param(break_on_load, bool, 0);
875 module_param(ttymajor, int, 0);
876 module_param_array(io, int, NULL, 0);
877 module_param_array(irq, int, NULL, 0);
878 module_param_array(dma, int, NULL, 0);
879 module_param(debug_level, int, 0);
880 module_param_array(maxframe, int, NULL, 0);
881 module_param_array(txdmabufs, int, NULL, 0);
882 module_param_array(txholdbufs, int, NULL, 0);
883
884 static char *driver_name = "SyncLink serial driver";
885 static char *driver_version = "$Revision: 4.38 $";
886
887 static int synclink_init_one (struct pci_dev *dev,
888 const struct pci_device_id *ent);
889 static void synclink_remove_one (struct pci_dev *dev);
890
891 static struct pci_device_id synclink_pci_tbl[] = {
892 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
893 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
894 { 0, }, /* terminate list */
895 };
896 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
897
898 MODULE_LICENSE("GPL");
899
900 static struct pci_driver synclink_pci_driver = {
901 .name = "synclink",
902 .id_table = synclink_pci_tbl,
903 .probe = synclink_init_one,
904 .remove = __devexit_p(synclink_remove_one),
905 };
906
907 static struct tty_driver *serial_driver;
908
909 /* number of characters left in xmit buffer before we ask for more */
910 #define WAKEUP_CHARS 256
911
912
913 static void mgsl_change_params(struct mgsl_struct *info);
914 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
915
916 /*
917 * 1st function defined in .text section. Calling this function in
918 * init_module() followed by a breakpoint allows a remote debugger
919 * (gdb) to get the .text address for the add-symbol-file command.
920 * This allows remote debugging of dynamically loadable modules.
921 */
922 static void* mgsl_get_text_ptr(void)
923 {
924 return mgsl_get_text_ptr;
925 }
926
927 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
928 char *name, const char *routine)
929 {
930 #ifdef MGSL_PARANOIA_CHECK
931 static const char *badmagic =
932 "Warning: bad magic number for mgsl struct (%s) in %s\n";
933 static const char *badinfo =
934 "Warning: null mgsl_struct for (%s) in %s\n";
935
936 if (!info) {
937 printk(badinfo, name, routine);
938 return 1;
939 }
940 if (info->magic != MGSL_MAGIC) {
941 printk(badmagic, name, routine);
942 return 1;
943 }
944 #else
945 if (!info)
946 return 1;
947 #endif
948 return 0;
949 }
950
951 /**
952 * line discipline callback wrappers
953 *
954 * The wrappers maintain line discipline references
955 * while calling into the line discipline.
956 *
957 * ldisc_receive_buf - pass receive data to line discipline
958 */
959
960 static void ldisc_receive_buf(struct tty_struct *tty,
961 const __u8 *data, char *flags, int count)
962 {
963 struct tty_ldisc *ld;
964 if (!tty)
965 return;
966 ld = tty_ldisc_ref(tty);
967 if (ld) {
968 if (ld->ops->receive_buf)
969 ld->ops->receive_buf(tty, data, flags, count);
970 tty_ldisc_deref(ld);
971 }
972 }
973
974 /* mgsl_stop() throttle (stop) transmitter
975 *
976 * Arguments: tty pointer to tty info structure
977 * Return Value: None
978 */
979 static void mgsl_stop(struct tty_struct *tty)
980 {
981 struct mgsl_struct *info = tty->driver_data;
982 unsigned long flags;
983
984 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
985 return;
986
987 if ( debug_level >= DEBUG_LEVEL_INFO )
988 printk("mgsl_stop(%s)\n",info->device_name);
989
990 spin_lock_irqsave(&info->irq_spinlock,flags);
991 if (info->tx_enabled)
992 usc_stop_transmitter(info);
993 spin_unlock_irqrestore(&info->irq_spinlock,flags);
994
995 } /* end of mgsl_stop() */
996
997 /* mgsl_start() release (start) transmitter
998 *
999 * Arguments: tty pointer to tty info structure
1000 * Return Value: None
1001 */
1002 static void mgsl_start(struct tty_struct *tty)
1003 {
1004 struct mgsl_struct *info = tty->driver_data;
1005 unsigned long flags;
1006
1007 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1008 return;
1009
1010 if ( debug_level >= DEBUG_LEVEL_INFO )
1011 printk("mgsl_start(%s)\n",info->device_name);
1012
1013 spin_lock_irqsave(&info->irq_spinlock,flags);
1014 if (!info->tx_enabled)
1015 usc_start_transmitter(info);
1016 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1017
1018 } /* end of mgsl_start() */
1019
1020 /*
1021 * Bottom half work queue access functions
1022 */
1023
1024 /* mgsl_bh_action() Return next bottom half action to perform.
1025 * Return Value: BH action code or 0 if nothing to do.
1026 */
1027 static int mgsl_bh_action(struct mgsl_struct *info)
1028 {
1029 unsigned long flags;
1030 int rc = 0;
1031
1032 spin_lock_irqsave(&info->irq_spinlock,flags);
1033
1034 if (info->pending_bh & BH_RECEIVE) {
1035 info->pending_bh &= ~BH_RECEIVE;
1036 rc = BH_RECEIVE;
1037 } else if (info->pending_bh & BH_TRANSMIT) {
1038 info->pending_bh &= ~BH_TRANSMIT;
1039 rc = BH_TRANSMIT;
1040 } else if (info->pending_bh & BH_STATUS) {
1041 info->pending_bh &= ~BH_STATUS;
1042 rc = BH_STATUS;
1043 }
1044
1045 if (!rc) {
1046 /* Mark BH routine as complete */
1047 info->bh_running = false;
1048 info->bh_requested = false;
1049 }
1050
1051 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1052
1053 return rc;
1054 }
1055
1056 /*
1057 * Perform bottom half processing of work items queued by ISR.
1058 */
1059 static void mgsl_bh_handler(struct work_struct *work)
1060 {
1061 struct mgsl_struct *info =
1062 container_of(work, struct mgsl_struct, task);
1063 int action;
1064
1065 if (!info)
1066 return;
1067
1068 if ( debug_level >= DEBUG_LEVEL_BH )
1069 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1070 __FILE__,__LINE__,info->device_name);
1071
1072 info->bh_running = true;
1073
1074 while((action = mgsl_bh_action(info)) != 0) {
1075
1076 /* Process work item */
1077 if ( debug_level >= DEBUG_LEVEL_BH )
1078 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1079 __FILE__,__LINE__,action);
1080
1081 switch (action) {
1082
1083 case BH_RECEIVE:
1084 mgsl_bh_receive(info);
1085 break;
1086 case BH_TRANSMIT:
1087 mgsl_bh_transmit(info);
1088 break;
1089 case BH_STATUS:
1090 mgsl_bh_status(info);
1091 break;
1092 default:
1093 /* unknown work item ID */
1094 printk("Unknown work item ID=%08X!\n", action);
1095 break;
1096 }
1097 }
1098
1099 if ( debug_level >= DEBUG_LEVEL_BH )
1100 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1101 __FILE__,__LINE__,info->device_name);
1102 }
1103
1104 static void mgsl_bh_receive(struct mgsl_struct *info)
1105 {
1106 bool (*get_rx_frame)(struct mgsl_struct *info) =
1107 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1108
1109 if ( debug_level >= DEBUG_LEVEL_BH )
1110 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1111 __FILE__,__LINE__,info->device_name);
1112
1113 do
1114 {
1115 if (info->rx_rcc_underrun) {
1116 unsigned long flags;
1117 spin_lock_irqsave(&info->irq_spinlock,flags);
1118 usc_start_receiver(info);
1119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1120 return;
1121 }
1122 } while(get_rx_frame(info));
1123 }
1124
1125 static void mgsl_bh_transmit(struct mgsl_struct *info)
1126 {
1127 struct tty_struct *tty = info->port.tty;
1128 unsigned long flags;
1129
1130 if ( debug_level >= DEBUG_LEVEL_BH )
1131 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1132 __FILE__,__LINE__,info->device_name);
1133
1134 if (tty)
1135 tty_wakeup(tty);
1136
1137 /* if transmitter idle and loopmode_send_done_requested
1138 * then start echoing RxD to TxD
1139 */
1140 spin_lock_irqsave(&info->irq_spinlock,flags);
1141 if ( !info->tx_active && info->loopmode_send_done_requested )
1142 usc_loopmode_send_done( info );
1143 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1144 }
1145
1146 static void mgsl_bh_status(struct mgsl_struct *info)
1147 {
1148 if ( debug_level >= DEBUG_LEVEL_BH )
1149 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1150 __FILE__,__LINE__,info->device_name);
1151
1152 info->ri_chkcount = 0;
1153 info->dsr_chkcount = 0;
1154 info->dcd_chkcount = 0;
1155 info->cts_chkcount = 0;
1156 }
1157
1158 /* mgsl_isr_receive_status()
1159 *
1160 * Service a receive status interrupt. The type of status
1161 * interrupt is indicated by the state of the RCSR.
1162 * This is only used for HDLC mode.
1163 *
1164 * Arguments: info pointer to device instance data
1165 * Return Value: None
1166 */
1167 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1168 {
1169 u16 status = usc_InReg( info, RCSR );
1170
1171 if ( debug_level >= DEBUG_LEVEL_ISR )
1172 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1173 __FILE__,__LINE__,status);
1174
1175 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1176 info->loopmode_insert_requested &&
1177 usc_loopmode_active(info) )
1178 {
1179 ++info->icount.rxabort;
1180 info->loopmode_insert_requested = false;
1181
1182 /* clear CMR:13 to start echoing RxD to TxD */
1183 info->cmr_value &= ~BIT13;
1184 usc_OutReg(info, CMR, info->cmr_value);
1185
1186 /* disable received abort irq (no longer required) */
1187 usc_OutReg(info, RICR,
1188 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1189 }
1190
1191 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1192 if (status & RXSTATUS_EXITED_HUNT)
1193 info->icount.exithunt++;
1194 if (status & RXSTATUS_IDLE_RECEIVED)
1195 info->icount.rxidle++;
1196 wake_up_interruptible(&info->event_wait_q);
1197 }
1198
1199 if (status & RXSTATUS_OVERRUN){
1200 info->icount.rxover++;
1201 usc_process_rxoverrun_sync( info );
1202 }
1203
1204 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1205 usc_UnlatchRxstatusBits( info, status );
1206
1207 } /* end of mgsl_isr_receive_status() */
1208
1209 /* mgsl_isr_transmit_status()
1210 *
1211 * Service a transmit status interrupt
1212 * HDLC mode :end of transmit frame
1213 * Async mode:all data is sent
1214 * transmit status is indicated by bits in the TCSR.
1215 *
1216 * Arguments: info pointer to device instance data
1217 * Return Value: None
1218 */
1219 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1220 {
1221 u16 status = usc_InReg( info, TCSR );
1222
1223 if ( debug_level >= DEBUG_LEVEL_ISR )
1224 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1225 __FILE__,__LINE__,status);
1226
1227 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1228 usc_UnlatchTxstatusBits( info, status );
1229
1230 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1231 {
1232 /* finished sending HDLC abort. This may leave */
1233 /* the TxFifo with data from the aborted frame */
1234 /* so purge the TxFifo. Also shutdown the DMA */
1235 /* channel in case there is data remaining in */
1236 /* the DMA buffer */
1237 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1238 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1239 }
1240
1241 if ( status & TXSTATUS_EOF_SENT )
1242 info->icount.txok++;
1243 else if ( status & TXSTATUS_UNDERRUN )
1244 info->icount.txunder++;
1245 else if ( status & TXSTATUS_ABORT_SENT )
1246 info->icount.txabort++;
1247 else
1248 info->icount.txunder++;
1249
1250 info->tx_active = false;
1251 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1252 del_timer(&info->tx_timer);
1253
1254 if ( info->drop_rts_on_tx_done ) {
1255 usc_get_serial_signals( info );
1256 if ( info->serial_signals & SerialSignal_RTS ) {
1257 info->serial_signals &= ~SerialSignal_RTS;
1258 usc_set_serial_signals( info );
1259 }
1260 info->drop_rts_on_tx_done = false;
1261 }
1262
1263 #if SYNCLINK_GENERIC_HDLC
1264 if (info->netcount)
1265 hdlcdev_tx_done(info);
1266 else
1267 #endif
1268 {
1269 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1270 usc_stop_transmitter(info);
1271 return;
1272 }
1273 info->pending_bh |= BH_TRANSMIT;
1274 }
1275
1276 } /* end of mgsl_isr_transmit_status() */
1277
1278 /* mgsl_isr_io_pin()
1279 *
1280 * Service an Input/Output pin interrupt. The type of
1281 * interrupt is indicated by bits in the MISR
1282 *
1283 * Arguments: info pointer to device instance data
1284 * Return Value: None
1285 */
1286 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1287 {
1288 struct mgsl_icount *icount;
1289 u16 status = usc_InReg( info, MISR );
1290
1291 if ( debug_level >= DEBUG_LEVEL_ISR )
1292 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1293 __FILE__,__LINE__,status);
1294
1295 usc_ClearIrqPendingBits( info, IO_PIN );
1296 usc_UnlatchIostatusBits( info, status );
1297
1298 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1299 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1300 icount = &info->icount;
1301 /* update input line counters */
1302 if (status & MISCSTATUS_RI_LATCHED) {
1303 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1304 usc_DisablestatusIrqs(info,SICR_RI);
1305 icount->rng++;
1306 if ( status & MISCSTATUS_RI )
1307 info->input_signal_events.ri_up++;
1308 else
1309 info->input_signal_events.ri_down++;
1310 }
1311 if (status & MISCSTATUS_DSR_LATCHED) {
1312 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1313 usc_DisablestatusIrqs(info,SICR_DSR);
1314 icount->dsr++;
1315 if ( status & MISCSTATUS_DSR )
1316 info->input_signal_events.dsr_up++;
1317 else
1318 info->input_signal_events.dsr_down++;
1319 }
1320 if (status & MISCSTATUS_DCD_LATCHED) {
1321 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1322 usc_DisablestatusIrqs(info,SICR_DCD);
1323 icount->dcd++;
1324 if (status & MISCSTATUS_DCD) {
1325 info->input_signal_events.dcd_up++;
1326 } else
1327 info->input_signal_events.dcd_down++;
1328 #if SYNCLINK_GENERIC_HDLC
1329 if (info->netcount) {
1330 if (status & MISCSTATUS_DCD)
1331 netif_carrier_on(info->netdev);
1332 else
1333 netif_carrier_off(info->netdev);
1334 }
1335 #endif
1336 }
1337 if (status & MISCSTATUS_CTS_LATCHED)
1338 {
1339 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340 usc_DisablestatusIrqs(info,SICR_CTS);
1341 icount->cts++;
1342 if ( status & MISCSTATUS_CTS )
1343 info->input_signal_events.cts_up++;
1344 else
1345 info->input_signal_events.cts_down++;
1346 }
1347 wake_up_interruptible(&info->status_event_wait_q);
1348 wake_up_interruptible(&info->event_wait_q);
1349
1350 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1351 (status & MISCSTATUS_DCD_LATCHED) ) {
1352 if ( debug_level >= DEBUG_LEVEL_ISR )
1353 printk("%s CD now %s...", info->device_name,
1354 (status & MISCSTATUS_DCD) ? "on" : "off");
1355 if (status & MISCSTATUS_DCD)
1356 wake_up_interruptible(&info->port.open_wait);
1357 else {
1358 if ( debug_level >= DEBUG_LEVEL_ISR )
1359 printk("doing serial hangup...");
1360 if (info->port.tty)
1361 tty_hangup(info->port.tty);
1362 }
1363 }
1364
1365 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1366 (status & MISCSTATUS_CTS_LATCHED) ) {
1367 if (info->port.tty->hw_stopped) {
1368 if (status & MISCSTATUS_CTS) {
1369 if ( debug_level >= DEBUG_LEVEL_ISR )
1370 printk("CTS tx start...");
1371 if (info->port.tty)
1372 info->port.tty->hw_stopped = 0;
1373 usc_start_transmitter(info);
1374 info->pending_bh |= BH_TRANSMIT;
1375 return;
1376 }
1377 } else {
1378 if (!(status & MISCSTATUS_CTS)) {
1379 if ( debug_level >= DEBUG_LEVEL_ISR )
1380 printk("CTS tx stop...");
1381 if (info->port.tty)
1382 info->port.tty->hw_stopped = 1;
1383 usc_stop_transmitter(info);
1384 }
1385 }
1386 }
1387 }
1388
1389 info->pending_bh |= BH_STATUS;
1390
1391 /* for diagnostics set IRQ flag */
1392 if ( status & MISCSTATUS_TXC_LATCHED ){
1393 usc_OutReg( info, SICR,
1394 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1395 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1396 info->irq_occurred = true;
1397 }
1398
1399 } /* end of mgsl_isr_io_pin() */
1400
1401 /* mgsl_isr_transmit_data()
1402 *
1403 * Service a transmit data interrupt (async mode only).
1404 *
1405 * Arguments: info pointer to device instance data
1406 * Return Value: None
1407 */
1408 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1409 {
1410 if ( debug_level >= DEBUG_LEVEL_ISR )
1411 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1412 __FILE__,__LINE__,info->xmit_cnt);
1413
1414 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1415
1416 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1417 usc_stop_transmitter(info);
1418 return;
1419 }
1420
1421 if ( info->xmit_cnt )
1422 usc_load_txfifo( info );
1423 else
1424 info->tx_active = false;
1425
1426 if (info->xmit_cnt < WAKEUP_CHARS)
1427 info->pending_bh |= BH_TRANSMIT;
1428
1429 } /* end of mgsl_isr_transmit_data() */
1430
1431 /* mgsl_isr_receive_data()
1432 *
1433 * Service a receive data interrupt. This occurs
1434 * when operating in asynchronous interrupt transfer mode.
1435 * The receive data FIFO is flushed to the receive data buffers.
1436 *
1437 * Arguments: info pointer to device instance data
1438 * Return Value: None
1439 */
1440 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1441 {
1442 int Fifocount;
1443 u16 status;
1444 int work = 0;
1445 unsigned char DataByte;
1446 struct tty_struct *tty = info->port.tty;
1447 struct mgsl_icount *icount = &info->icount;
1448
1449 if ( debug_level >= DEBUG_LEVEL_ISR )
1450 printk("%s(%d):mgsl_isr_receive_data\n",
1451 __FILE__,__LINE__);
1452
1453 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1454
1455 /* select FIFO status for RICR readback */
1456 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1457
1458 /* clear the Wordstatus bit so that status readback */
1459 /* only reflects the status of this byte */
1460 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1461
1462 /* flush the receive FIFO */
1463
1464 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1465 int flag;
1466
1467 /* read one byte from RxFIFO */
1468 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1469 info->io_base + CCAR );
1470 DataByte = inb( info->io_base + CCAR );
1471
1472 /* get the status of the received byte */
1473 status = usc_InReg(info, RCSR);
1474 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1475 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1476 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1477
1478 icount->rx++;
1479
1480 flag = 0;
1481 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1482 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1483 printk("rxerr=%04X\n",status);
1484 /* update error statistics */
1485 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1486 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1487 icount->brk++;
1488 } else if (status & RXSTATUS_PARITY_ERROR)
1489 icount->parity++;
1490 else if (status & RXSTATUS_FRAMING_ERROR)
1491 icount->frame++;
1492 else if (status & RXSTATUS_OVERRUN) {
1493 /* must issue purge fifo cmd before */
1494 /* 16C32 accepts more receive chars */
1495 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1496 icount->overrun++;
1497 }
1498
1499 /* discard char if tty control flags say so */
1500 if (status & info->ignore_status_mask)
1501 continue;
1502
1503 status &= info->read_status_mask;
1504
1505 if (status & RXSTATUS_BREAK_RECEIVED) {
1506 flag = TTY_BREAK;
1507 if (info->port.flags & ASYNC_SAK)
1508 do_SAK(tty);
1509 } else if (status & RXSTATUS_PARITY_ERROR)
1510 flag = TTY_PARITY;
1511 else if (status & RXSTATUS_FRAMING_ERROR)
1512 flag = TTY_FRAME;
1513 } /* end of if (error) */
1514 tty_insert_flip_char(tty, DataByte, flag);
1515 if (status & RXSTATUS_OVERRUN) {
1516 /* Overrun is special, since it's
1517 * reported immediately, and doesn't
1518 * affect the current character
1519 */
1520 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1521 }
1522 }
1523
1524 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1525 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1526 __FILE__,__LINE__,icount->rx,icount->brk,
1527 icount->parity,icount->frame,icount->overrun);
1528 }
1529
1530 if(work)
1531 tty_flip_buffer_push(tty);
1532 }
1533
1534 /* mgsl_isr_misc()
1535 *
1536 * Service a miscellaneous interrupt source.
1537 *
1538 * Arguments: info pointer to device extension (instance data)
1539 * Return Value: None
1540 */
1541 static void mgsl_isr_misc( struct mgsl_struct *info )
1542 {
1543 u16 status = usc_InReg( info, MISR );
1544
1545 if ( debug_level >= DEBUG_LEVEL_ISR )
1546 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1547 __FILE__,__LINE__,status);
1548
1549 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1550 (info->params.mode == MGSL_MODE_HDLC)) {
1551
1552 /* turn off receiver and rx DMA */
1553 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1554 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1555 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1556 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1557 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1558
1559 /* schedule BH handler to restart receiver */
1560 info->pending_bh |= BH_RECEIVE;
1561 info->rx_rcc_underrun = true;
1562 }
1563
1564 usc_ClearIrqPendingBits( info, MISC );
1565 usc_UnlatchMiscstatusBits( info, status );
1566
1567 } /* end of mgsl_isr_misc() */
1568
1569 /* mgsl_isr_null()
1570 *
1571 * Services undefined interrupt vectors from the
1572 * USC. (hence this function SHOULD never be called)
1573 *
1574 * Arguments: info pointer to device extension (instance data)
1575 * Return Value: None
1576 */
1577 static void mgsl_isr_null( struct mgsl_struct *info )
1578 {
1579
1580 } /* end of mgsl_isr_null() */
1581
1582 /* mgsl_isr_receive_dma()
1583 *
1584 * Service a receive DMA channel interrupt.
1585 * For this driver there are two sources of receive DMA interrupts
1586 * as identified in the Receive DMA mode Register (RDMR):
1587 *
1588 * BIT3 EOA/EOL End of List, all receive buffers in receive
1589 * buffer list have been filled (no more free buffers
1590 * available). The DMA controller has shut down.
1591 *
1592 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1593 * DMA buffer is terminated in response to completion
1594 * of a good frame or a frame with errors. The status
1595 * of the frame is stored in the buffer entry in the
1596 * list of receive buffer entries.
1597 *
1598 * Arguments: info pointer to device instance data
1599 * Return Value: None
1600 */
1601 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1602 {
1603 u16 status;
1604
1605 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1606 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1607
1608 /* Read the receive DMA status to identify interrupt type. */
1609 /* This also clears the status bits. */
1610 status = usc_InDmaReg( info, RDMR );
1611
1612 if ( debug_level >= DEBUG_LEVEL_ISR )
1613 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1614 __FILE__,__LINE__,info->device_name,status);
1615
1616 info->pending_bh |= BH_RECEIVE;
1617
1618 if ( status & BIT3 ) {
1619 info->rx_overflow = true;
1620 info->icount.buf_overrun++;
1621 }
1622
1623 } /* end of mgsl_isr_receive_dma() */
1624
1625 /* mgsl_isr_transmit_dma()
1626 *
1627 * This function services a transmit DMA channel interrupt.
1628 *
1629 * For this driver there is one source of transmit DMA interrupts
1630 * as identified in the Transmit DMA Mode Register (TDMR):
1631 *
1632 * BIT2 EOB End of Buffer. This interrupt occurs when a
1633 * transmit DMA buffer has been emptied.
1634 *
1635 * The driver maintains enough transmit DMA buffers to hold at least
1636 * one max frame size transmit frame. When operating in a buffered
1637 * transmit mode, there may be enough transmit DMA buffers to hold at
1638 * least two or more max frame size frames. On an EOB condition,
1639 * determine if there are any queued transmit buffers and copy into
1640 * transmit DMA buffers if we have room.
1641 *
1642 * Arguments: info pointer to device instance data
1643 * Return Value: None
1644 */
1645 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1646 {
1647 u16 status;
1648
1649 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1650 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1651
1652 /* Read the transmit DMA status to identify interrupt type. */
1653 /* This also clears the status bits. */
1654
1655 status = usc_InDmaReg( info, TDMR );
1656
1657 if ( debug_level >= DEBUG_LEVEL_ISR )
1658 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1659 __FILE__,__LINE__,info->device_name,status);
1660
1661 if ( status & BIT2 ) {
1662 --info->tx_dma_buffers_used;
1663
1664 /* if there are transmit frames queued,
1665 * try to load the next one
1666 */
1667 if ( load_next_tx_holding_buffer(info) ) {
1668 /* if call returns non-zero value, we have
1669 * at least one free tx holding buffer
1670 */
1671 info->pending_bh |= BH_TRANSMIT;
1672 }
1673 }
1674
1675 } /* end of mgsl_isr_transmit_dma() */
1676
1677 /* mgsl_interrupt()
1678 *
1679 * Interrupt service routine entry point.
1680 *
1681 * Arguments:
1682 *
1683 * irq interrupt number that caused interrupt
1684 * dev_id device ID supplied during interrupt registration
1685 *
1686 * Return Value: None
1687 */
1688 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1689 {
1690 struct mgsl_struct *info = dev_id;
1691 u16 UscVector;
1692 u16 DmaVector;
1693
1694 if ( debug_level >= DEBUG_LEVEL_ISR )
1695 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1696 __FILE__, __LINE__, info->irq_level);
1697
1698 spin_lock(&info->irq_spinlock);
1699
1700 for(;;) {
1701 /* Read the interrupt vectors from hardware. */
1702 UscVector = usc_InReg(info, IVR) >> 9;
1703 DmaVector = usc_InDmaReg(info, DIVR);
1704
1705 if ( debug_level >= DEBUG_LEVEL_ISR )
1706 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1707 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1708
1709 if ( !UscVector && !DmaVector )
1710 break;
1711
1712 /* Dispatch interrupt vector */
1713 if ( UscVector )
1714 (*UscIsrTable[UscVector])(info);
1715 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1716 mgsl_isr_transmit_dma(info);
1717 else
1718 mgsl_isr_receive_dma(info);
1719
1720 if ( info->isr_overflow ) {
1721 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1722 __FILE__, __LINE__, info->device_name, info->irq_level);
1723 usc_DisableMasterIrqBit(info);
1724 usc_DisableDmaInterrupts(info,DICR_MASTER);
1725 break;
1726 }
1727 }
1728
1729 /* Request bottom half processing if there's something
1730 * for it to do and the bh is not already running
1731 */
1732
1733 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1734 if ( debug_level >= DEBUG_LEVEL_ISR )
1735 printk("%s(%d):%s queueing bh task.\n",
1736 __FILE__,__LINE__,info->device_name);
1737 schedule_work(&info->task);
1738 info->bh_requested = true;
1739 }
1740
1741 spin_unlock(&info->irq_spinlock);
1742
1743 if ( debug_level >= DEBUG_LEVEL_ISR )
1744 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1745 __FILE__, __LINE__, info->irq_level);
1746
1747 return IRQ_HANDLED;
1748 } /* end of mgsl_interrupt() */
1749
1750 /* startup()
1751 *
1752 * Initialize and start device.
1753 *
1754 * Arguments: info pointer to device instance data
1755 * Return Value: 0 if success, otherwise error code
1756 */
1757 static int startup(struct mgsl_struct * info)
1758 {
1759 int retval = 0;
1760
1761 if ( debug_level >= DEBUG_LEVEL_INFO )
1762 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1763
1764 if (info->port.flags & ASYNC_INITIALIZED)
1765 return 0;
1766
1767 if (!info->xmit_buf) {
1768 /* allocate a page of memory for a transmit buffer */
1769 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1770 if (!info->xmit_buf) {
1771 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1772 __FILE__,__LINE__,info->device_name);
1773 return -ENOMEM;
1774 }
1775 }
1776
1777 info->pending_bh = 0;
1778
1779 memset(&info->icount, 0, sizeof(info->icount));
1780
1781 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1782
1783 /* Allocate and claim adapter resources */
1784 retval = mgsl_claim_resources(info);
1785
1786 /* perform existence check and diagnostics */
1787 if ( !retval )
1788 retval = mgsl_adapter_test(info);
1789
1790 if ( retval ) {
1791 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1792 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1793 mgsl_release_resources(info);
1794 return retval;
1795 }
1796
1797 /* program hardware for current parameters */
1798 mgsl_change_params(info);
1799
1800 if (info->port.tty)
1801 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1802
1803 info->port.flags |= ASYNC_INITIALIZED;
1804
1805 return 0;
1806
1807 } /* end of startup() */
1808
1809 /* shutdown()
1810 *
1811 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1812 *
1813 * Arguments: info pointer to device instance data
1814 * Return Value: None
1815 */
1816 static void shutdown(struct mgsl_struct * info)
1817 {
1818 unsigned long flags;
1819
1820 if (!(info->port.flags & ASYNC_INITIALIZED))
1821 return;
1822
1823 if (debug_level >= DEBUG_LEVEL_INFO)
1824 printk("%s(%d):mgsl_shutdown(%s)\n",
1825 __FILE__,__LINE__, info->device_name );
1826
1827 /* clear status wait queue because status changes */
1828 /* can't happen after shutting down the hardware */
1829 wake_up_interruptible(&info->status_event_wait_q);
1830 wake_up_interruptible(&info->event_wait_q);
1831
1832 del_timer_sync(&info->tx_timer);
1833
1834 if (info->xmit_buf) {
1835 free_page((unsigned long) info->xmit_buf);
1836 info->xmit_buf = NULL;
1837 }
1838
1839 spin_lock_irqsave(&info->irq_spinlock,flags);
1840 usc_DisableMasterIrqBit(info);
1841 usc_stop_receiver(info);
1842 usc_stop_transmitter(info);
1843 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1844 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1845 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1846
1847 /* Disable DMAEN (Port 7, Bit 14) */
1848 /* This disconnects the DMA request signal from the ISA bus */
1849 /* on the ISA adapter. This has no effect for the PCI adapter */
1850 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1851
1852 /* Disable INTEN (Port 6, Bit12) */
1853 /* This disconnects the IRQ request signal to the ISA bus */
1854 /* on the ISA adapter. This has no effect for the PCI adapter */
1855 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1856
1857 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1858 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1859 usc_set_serial_signals(info);
1860 }
1861
1862 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1863
1864 mgsl_release_resources(info);
1865
1866 if (info->port.tty)
1867 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1868
1869 info->port.flags &= ~ASYNC_INITIALIZED;
1870
1871 } /* end of shutdown() */
1872
1873 static void mgsl_program_hw(struct mgsl_struct *info)
1874 {
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&info->irq_spinlock,flags);
1878
1879 usc_stop_receiver(info);
1880 usc_stop_transmitter(info);
1881 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1882
1883 if (info->params.mode == MGSL_MODE_HDLC ||
1884 info->params.mode == MGSL_MODE_RAW ||
1885 info->netcount)
1886 usc_set_sync_mode(info);
1887 else
1888 usc_set_async_mode(info);
1889
1890 usc_set_serial_signals(info);
1891
1892 info->dcd_chkcount = 0;
1893 info->cts_chkcount = 0;
1894 info->ri_chkcount = 0;
1895 info->dsr_chkcount = 0;
1896
1897 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1898 usc_EnableInterrupts(info, IO_PIN);
1899 usc_get_serial_signals(info);
1900
1901 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1902 usc_start_receiver(info);
1903
1904 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1905 }
1906
1907 /* Reconfigure adapter based on new parameters
1908 */
1909 static void mgsl_change_params(struct mgsl_struct *info)
1910 {
1911 unsigned cflag;
1912 int bits_per_char;
1913
1914 if (!info->port.tty || !info->port.tty->termios)
1915 return;
1916
1917 if (debug_level >= DEBUG_LEVEL_INFO)
1918 printk("%s(%d):mgsl_change_params(%s)\n",
1919 __FILE__,__LINE__, info->device_name );
1920
1921 cflag = info->port.tty->termios->c_cflag;
1922
1923 /* if B0 rate (hangup) specified then negate DTR and RTS */
1924 /* otherwise assert DTR and RTS */
1925 if (cflag & CBAUD)
1926 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1927 else
1928 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1929
1930 /* byte size and parity */
1931
1932 switch (cflag & CSIZE) {
1933 case CS5: info->params.data_bits = 5; break;
1934 case CS6: info->params.data_bits = 6; break;
1935 case CS7: info->params.data_bits = 7; break;
1936 case CS8: info->params.data_bits = 8; break;
1937 /* Never happens, but GCC is too dumb to figure it out */
1938 default: info->params.data_bits = 7; break;
1939 }
1940
1941 if (cflag & CSTOPB)
1942 info->params.stop_bits = 2;
1943 else
1944 info->params.stop_bits = 1;
1945
1946 info->params.parity = ASYNC_PARITY_NONE;
1947 if (cflag & PARENB) {
1948 if (cflag & PARODD)
1949 info->params.parity = ASYNC_PARITY_ODD;
1950 else
1951 info->params.parity = ASYNC_PARITY_EVEN;
1952 #ifdef CMSPAR
1953 if (cflag & CMSPAR)
1954 info->params.parity = ASYNC_PARITY_SPACE;
1955 #endif
1956 }
1957
1958 /* calculate number of jiffies to transmit a full
1959 * FIFO (32 bytes) at specified data rate
1960 */
1961 bits_per_char = info->params.data_bits +
1962 info->params.stop_bits + 1;
1963
1964 /* if port data rate is set to 460800 or less then
1965 * allow tty settings to override, otherwise keep the
1966 * current data rate.
1967 */
1968 if (info->params.data_rate <= 460800)
1969 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1970
1971 if ( info->params.data_rate ) {
1972 info->timeout = (32*HZ*bits_per_char) /
1973 info->params.data_rate;
1974 }
1975 info->timeout += HZ/50; /* Add .02 seconds of slop */
1976
1977 if (cflag & CRTSCTS)
1978 info->port.flags |= ASYNC_CTS_FLOW;
1979 else
1980 info->port.flags &= ~ASYNC_CTS_FLOW;
1981
1982 if (cflag & CLOCAL)
1983 info->port.flags &= ~ASYNC_CHECK_CD;
1984 else
1985 info->port.flags |= ASYNC_CHECK_CD;
1986
1987 /* process tty input control flags */
1988
1989 info->read_status_mask = RXSTATUS_OVERRUN;
1990 if (I_INPCK(info->port.tty))
1991 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1992 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1993 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1994
1995 if (I_IGNPAR(info->port.tty))
1996 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1997 if (I_IGNBRK(info->port.tty)) {
1998 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1999 /* If ignoring parity and break indicators, ignore
2000 * overruns too. (For real raw support).
2001 */
2002 if (I_IGNPAR(info->port.tty))
2003 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2004 }
2005
2006 mgsl_program_hw(info);
2007
2008 } /* end of mgsl_change_params() */
2009
2010 /* mgsl_put_char()
2011 *
2012 * Add a character to the transmit buffer.
2013 *
2014 * Arguments: tty pointer to tty information structure
2015 * ch character to add to transmit buffer
2016 *
2017 * Return Value: None
2018 */
2019 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2020 {
2021 struct mgsl_struct *info = tty->driver_data;
2022 unsigned long flags;
2023 int ret = 0;
2024
2025 if (debug_level >= DEBUG_LEVEL_INFO) {
2026 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2027 __FILE__, __LINE__, ch, info->device_name);
2028 }
2029
2030 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2031 return 0;
2032
2033 if (!tty || !info->xmit_buf)
2034 return 0;
2035
2036 spin_lock_irqsave(&info->irq_spinlock, flags);
2037
2038 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2039 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2040 info->xmit_buf[info->xmit_head++] = ch;
2041 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2042 info->xmit_cnt++;
2043 ret = 1;
2044 }
2045 }
2046 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2047 return ret;
2048
2049 } /* end of mgsl_put_char() */
2050
2051 /* mgsl_flush_chars()
2052 *
2053 * Enable transmitter so remaining characters in the
2054 * transmit buffer are sent.
2055 *
2056 * Arguments: tty pointer to tty information structure
2057 * Return Value: None
2058 */
2059 static void mgsl_flush_chars(struct tty_struct *tty)
2060 {
2061 struct mgsl_struct *info = tty->driver_data;
2062 unsigned long flags;
2063
2064 if ( debug_level >= DEBUG_LEVEL_INFO )
2065 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2066 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2067
2068 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2069 return;
2070
2071 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2072 !info->xmit_buf)
2073 return;
2074
2075 if ( debug_level >= DEBUG_LEVEL_INFO )
2076 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2077 __FILE__,__LINE__,info->device_name );
2078
2079 spin_lock_irqsave(&info->irq_spinlock,flags);
2080
2081 if (!info->tx_active) {
2082 if ( (info->params.mode == MGSL_MODE_HDLC ||
2083 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2084 /* operating in synchronous (frame oriented) mode */
2085 /* copy data from circular xmit_buf to */
2086 /* transmit DMA buffer. */
2087 mgsl_load_tx_dma_buffer(info,
2088 info->xmit_buf,info->xmit_cnt);
2089 }
2090 usc_start_transmitter(info);
2091 }
2092
2093 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2094
2095 } /* end of mgsl_flush_chars() */
2096
2097 /* mgsl_write()
2098 *
2099 * Send a block of data
2100 *
2101 * Arguments:
2102 *
2103 * tty pointer to tty information structure
2104 * buf pointer to buffer containing send data
2105 * count size of send data in bytes
2106 *
2107 * Return Value: number of characters written
2108 */
2109 static int mgsl_write(struct tty_struct * tty,
2110 const unsigned char *buf, int count)
2111 {
2112 int c, ret = 0;
2113 struct mgsl_struct *info = tty->driver_data;
2114 unsigned long flags;
2115
2116 if ( debug_level >= DEBUG_LEVEL_INFO )
2117 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2118 __FILE__,__LINE__,info->device_name,count);
2119
2120 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2121 goto cleanup;
2122
2123 if (!tty || !info->xmit_buf)
2124 goto cleanup;
2125
2126 if ( info->params.mode == MGSL_MODE_HDLC ||
2127 info->params.mode == MGSL_MODE_RAW ) {
2128 /* operating in synchronous (frame oriented) mode */
2129 /* operating in synchronous (frame oriented) mode */
2130 if (info->tx_active) {
2131
2132 if ( info->params.mode == MGSL_MODE_HDLC ) {
2133 ret = 0;
2134 goto cleanup;
2135 }
2136 /* transmitter is actively sending data -
2137 * if we have multiple transmit dma and
2138 * holding buffers, attempt to queue this
2139 * frame for transmission at a later time.
2140 */
2141 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2142 /* no tx holding buffers available */
2143 ret = 0;
2144 goto cleanup;
2145 }
2146
2147 /* queue transmit frame request */
2148 ret = count;
2149 save_tx_buffer_request(info,buf,count);
2150
2151 /* if we have sufficient tx dma buffers,
2152 * load the next buffered tx request
2153 */
2154 spin_lock_irqsave(&info->irq_spinlock,flags);
2155 load_next_tx_holding_buffer(info);
2156 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2157 goto cleanup;
2158 }
2159
2160 /* if operating in HDLC LoopMode and the adapter */
2161 /* has yet to be inserted into the loop, we can't */
2162 /* transmit */
2163
2164 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2165 !usc_loopmode_active(info) )
2166 {
2167 ret = 0;
2168 goto cleanup;
2169 }
2170
2171 if ( info->xmit_cnt ) {
2172 /* Send accumulated from send_char() calls */
2173 /* as frame and wait before accepting more data. */
2174 ret = 0;
2175
2176 /* copy data from circular xmit_buf to */
2177 /* transmit DMA buffer. */
2178 mgsl_load_tx_dma_buffer(info,
2179 info->xmit_buf,info->xmit_cnt);
2180 if ( debug_level >= DEBUG_LEVEL_INFO )
2181 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2182 __FILE__,__LINE__,info->device_name);
2183 } else {
2184 if ( debug_level >= DEBUG_LEVEL_INFO )
2185 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2186 __FILE__,__LINE__,info->device_name);
2187 ret = count;
2188 info->xmit_cnt = count;
2189 mgsl_load_tx_dma_buffer(info,buf,count);
2190 }
2191 } else {
2192 while (1) {
2193 spin_lock_irqsave(&info->irq_spinlock,flags);
2194 c = min_t(int, count,
2195 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2196 SERIAL_XMIT_SIZE - info->xmit_head));
2197 if (c <= 0) {
2198 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2199 break;
2200 }
2201 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2202 info->xmit_head = ((info->xmit_head + c) &
2203 (SERIAL_XMIT_SIZE-1));
2204 info->xmit_cnt += c;
2205 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2206 buf += c;
2207 count -= c;
2208 ret += c;
2209 }
2210 }
2211
2212 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2213 spin_lock_irqsave(&info->irq_spinlock,flags);
2214 if (!info->tx_active)
2215 usc_start_transmitter(info);
2216 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2217 }
2218 cleanup:
2219 if ( debug_level >= DEBUG_LEVEL_INFO )
2220 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2221 __FILE__,__LINE__,info->device_name,ret);
2222
2223 return ret;
2224
2225 } /* end of mgsl_write() */
2226
2227 /* mgsl_write_room()
2228 *
2229 * Return the count of free bytes in transmit buffer
2230 *
2231 * Arguments: tty pointer to tty info structure
2232 * Return Value: None
2233 */
2234 static int mgsl_write_room(struct tty_struct *tty)
2235 {
2236 struct mgsl_struct *info = tty->driver_data;
2237 int ret;
2238
2239 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2240 return 0;
2241 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2242 if (ret < 0)
2243 ret = 0;
2244
2245 if (debug_level >= DEBUG_LEVEL_INFO)
2246 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2247 __FILE__,__LINE__, info->device_name,ret );
2248
2249 if ( info->params.mode == MGSL_MODE_HDLC ||
2250 info->params.mode == MGSL_MODE_RAW ) {
2251 /* operating in synchronous (frame oriented) mode */
2252 if ( info->tx_active )
2253 return 0;
2254 else
2255 return HDLC_MAX_FRAME_SIZE;
2256 }
2257
2258 return ret;
2259
2260 } /* end of mgsl_write_room() */
2261
2262 /* mgsl_chars_in_buffer()
2263 *
2264 * Return the count of bytes in transmit buffer
2265 *
2266 * Arguments: tty pointer to tty info structure
2267 * Return Value: None
2268 */
2269 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2270 {
2271 struct mgsl_struct *info = tty->driver_data;
2272
2273 if (debug_level >= DEBUG_LEVEL_INFO)
2274 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2275 __FILE__,__LINE__, info->device_name );
2276
2277 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2278 return 0;
2279
2280 if (debug_level >= DEBUG_LEVEL_INFO)
2281 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2282 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2283
2284 if ( info->params.mode == MGSL_MODE_HDLC ||
2285 info->params.mode == MGSL_MODE_RAW ) {
2286 /* operating in synchronous (frame oriented) mode */
2287 if ( info->tx_active )
2288 return info->max_frame_size;
2289 else
2290 return 0;
2291 }
2292
2293 return info->xmit_cnt;
2294 } /* end of mgsl_chars_in_buffer() */
2295
2296 /* mgsl_flush_buffer()
2297 *
2298 * Discard all data in the send buffer
2299 *
2300 * Arguments: tty pointer to tty info structure
2301 * Return Value: None
2302 */
2303 static void mgsl_flush_buffer(struct tty_struct *tty)
2304 {
2305 struct mgsl_struct *info = tty->driver_data;
2306 unsigned long flags;
2307
2308 if (debug_level >= DEBUG_LEVEL_INFO)
2309 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2310 __FILE__,__LINE__, info->device_name );
2311
2312 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2313 return;
2314
2315 spin_lock_irqsave(&info->irq_spinlock,flags);
2316 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2317 del_timer(&info->tx_timer);
2318 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2319
2320 tty_wakeup(tty);
2321 }
2322
2323 /* mgsl_send_xchar()
2324 *
2325 * Send a high-priority XON/XOFF character
2326 *
2327 * Arguments: tty pointer to tty info structure
2328 * ch character to send
2329 * Return Value: None
2330 */
2331 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2332 {
2333 struct mgsl_struct *info = tty->driver_data;
2334 unsigned long flags;
2335
2336 if (debug_level >= DEBUG_LEVEL_INFO)
2337 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2338 __FILE__,__LINE__, info->device_name, ch );
2339
2340 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2341 return;
2342
2343 info->x_char = ch;
2344 if (ch) {
2345 /* Make sure transmit interrupts are on */
2346 spin_lock_irqsave(&info->irq_spinlock,flags);
2347 if (!info->tx_enabled)
2348 usc_start_transmitter(info);
2349 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2350 }
2351 } /* end of mgsl_send_xchar() */
2352
2353 /* mgsl_throttle()
2354 *
2355 * Signal remote device to throttle send data (our receive data)
2356 *
2357 * Arguments: tty pointer to tty info structure
2358 * Return Value: None
2359 */
2360 static void mgsl_throttle(struct tty_struct * tty)
2361 {
2362 struct mgsl_struct *info = tty->driver_data;
2363 unsigned long flags;
2364
2365 if (debug_level >= DEBUG_LEVEL_INFO)
2366 printk("%s(%d):mgsl_throttle(%s) entry\n",
2367 __FILE__,__LINE__, info->device_name );
2368
2369 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2370 return;
2371
2372 if (I_IXOFF(tty))
2373 mgsl_send_xchar(tty, STOP_CHAR(tty));
2374
2375 if (tty->termios->c_cflag & CRTSCTS) {
2376 spin_lock_irqsave(&info->irq_spinlock,flags);
2377 info->serial_signals &= ~SerialSignal_RTS;
2378 usc_set_serial_signals(info);
2379 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2380 }
2381 } /* end of mgsl_throttle() */
2382
2383 /* mgsl_unthrottle()
2384 *
2385 * Signal remote device to stop throttling send data (our receive data)
2386 *
2387 * Arguments: tty pointer to tty info structure
2388 * Return Value: None
2389 */
2390 static void mgsl_unthrottle(struct tty_struct * tty)
2391 {
2392 struct mgsl_struct *info = tty->driver_data;
2393 unsigned long flags;
2394
2395 if (debug_level >= DEBUG_LEVEL_INFO)
2396 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2397 __FILE__,__LINE__, info->device_name );
2398
2399 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2400 return;
2401
2402 if (I_IXOFF(tty)) {
2403 if (info->x_char)
2404 info->x_char = 0;
2405 else
2406 mgsl_send_xchar(tty, START_CHAR(tty));
2407 }
2408
2409 if (tty->termios->c_cflag & CRTSCTS) {
2410 spin_lock_irqsave(&info->irq_spinlock,flags);
2411 info->serial_signals |= SerialSignal_RTS;
2412 usc_set_serial_signals(info);
2413 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2414 }
2415
2416 } /* end of mgsl_unthrottle() */
2417
2418 /* mgsl_get_stats()
2419 *
2420 * get the current serial parameters information
2421 *
2422 * Arguments: info pointer to device instance data
2423 * user_icount pointer to buffer to hold returned stats
2424 *
2425 * Return Value: 0 if success, otherwise error code
2426 */
2427 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2428 {
2429 int err;
2430
2431 if (debug_level >= DEBUG_LEVEL_INFO)
2432 printk("%s(%d):mgsl_get_params(%s)\n",
2433 __FILE__,__LINE__, info->device_name);
2434
2435 if (!user_icount) {
2436 memset(&info->icount, 0, sizeof(info->icount));
2437 } else {
2438 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2439 if (err)
2440 return -EFAULT;
2441 }
2442
2443 return 0;
2444
2445 } /* end of mgsl_get_stats() */
2446
2447 /* mgsl_get_params()
2448 *
2449 * get the current serial parameters information
2450 *
2451 * Arguments: info pointer to device instance data
2452 * user_params pointer to buffer to hold returned params
2453 *
2454 * Return Value: 0 if success, otherwise error code
2455 */
2456 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2457 {
2458 int err;
2459 if (debug_level >= DEBUG_LEVEL_INFO)
2460 printk("%s(%d):mgsl_get_params(%s)\n",
2461 __FILE__,__LINE__, info->device_name);
2462
2463 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2464 if (err) {
2465 if ( debug_level >= DEBUG_LEVEL_INFO )
2466 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2467 __FILE__,__LINE__,info->device_name);
2468 return -EFAULT;
2469 }
2470
2471 return 0;
2472
2473 } /* end of mgsl_get_params() */
2474
2475 /* mgsl_set_params()
2476 *
2477 * set the serial parameters
2478 *
2479 * Arguments:
2480 *
2481 * info pointer to device instance data
2482 * new_params user buffer containing new serial params
2483 *
2484 * Return Value: 0 if success, otherwise error code
2485 */
2486 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2487 {
2488 unsigned long flags;
2489 MGSL_PARAMS tmp_params;
2490 int err;
2491
2492 if (debug_level >= DEBUG_LEVEL_INFO)
2493 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2494 info->device_name );
2495 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2496 if (err) {
2497 if ( debug_level >= DEBUG_LEVEL_INFO )
2498 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2499 __FILE__,__LINE__,info->device_name);
2500 return -EFAULT;
2501 }
2502
2503 spin_lock_irqsave(&info->irq_spinlock,flags);
2504 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2505 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2506
2507 mgsl_change_params(info);
2508
2509 return 0;
2510
2511 } /* end of mgsl_set_params() */
2512
2513 /* mgsl_get_txidle()
2514 *
2515 * get the current transmit idle mode
2516 *
2517 * Arguments: info pointer to device instance data
2518 * idle_mode pointer to buffer to hold returned idle mode
2519 *
2520 * Return Value: 0 if success, otherwise error code
2521 */
2522 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2523 {
2524 int err;
2525
2526 if (debug_level >= DEBUG_LEVEL_INFO)
2527 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2528 __FILE__,__LINE__, info->device_name, info->idle_mode);
2529
2530 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2531 if (err) {
2532 if ( debug_level >= DEBUG_LEVEL_INFO )
2533 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2534 __FILE__,__LINE__,info->device_name);
2535 return -EFAULT;
2536 }
2537
2538 return 0;
2539
2540 } /* end of mgsl_get_txidle() */
2541
2542 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2543 *
2544 * Arguments: info pointer to device instance data
2545 * idle_mode new idle mode
2546 *
2547 * Return Value: 0 if success, otherwise error code
2548 */
2549 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2550 {
2551 unsigned long flags;
2552
2553 if (debug_level >= DEBUG_LEVEL_INFO)
2554 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2555 info->device_name, idle_mode );
2556
2557 spin_lock_irqsave(&info->irq_spinlock,flags);
2558 info->idle_mode = idle_mode;
2559 usc_set_txidle( info );
2560 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2561 return 0;
2562
2563 } /* end of mgsl_set_txidle() */
2564
2565 /* mgsl_txenable()
2566 *
2567 * enable or disable the transmitter
2568 *
2569 * Arguments:
2570 *
2571 * info pointer to device instance data
2572 * enable 1 = enable, 0 = disable
2573 *
2574 * Return Value: 0 if success, otherwise error code
2575 */
2576 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2577 {
2578 unsigned long flags;
2579
2580 if (debug_level >= DEBUG_LEVEL_INFO)
2581 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2582 info->device_name, enable);
2583
2584 spin_lock_irqsave(&info->irq_spinlock,flags);
2585 if ( enable ) {
2586 if ( !info->tx_enabled ) {
2587
2588 usc_start_transmitter(info);
2589 /*--------------------------------------------------
2590 * if HDLC/SDLC Loop mode, attempt to insert the
2591 * station in the 'loop' by setting CMR:13. Upon
2592 * receipt of the next GoAhead (RxAbort) sequence,
2593 * the OnLoop indicator (CCSR:7) should go active
2594 * to indicate that we are on the loop
2595 *--------------------------------------------------*/
2596 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2597 usc_loopmode_insert_request( info );
2598 }
2599 } else {
2600 if ( info->tx_enabled )
2601 usc_stop_transmitter(info);
2602 }
2603 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2604 return 0;
2605
2606 } /* end of mgsl_txenable() */
2607
2608 /* mgsl_txabort() abort send HDLC frame
2609 *
2610 * Arguments: info pointer to device instance data
2611 * Return Value: 0 if success, otherwise error code
2612 */
2613 static int mgsl_txabort(struct mgsl_struct * info)
2614 {
2615 unsigned long flags;
2616
2617 if (debug_level >= DEBUG_LEVEL_INFO)
2618 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2619 info->device_name);
2620
2621 spin_lock_irqsave(&info->irq_spinlock,flags);
2622 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2623 {
2624 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2625 usc_loopmode_cancel_transmit( info );
2626 else
2627 usc_TCmd(info,TCmd_SendAbort);
2628 }
2629 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2630 return 0;
2631
2632 } /* end of mgsl_txabort() */
2633
2634 /* mgsl_rxenable() enable or disable the receiver
2635 *
2636 * Arguments: info pointer to device instance data
2637 * enable 1 = enable, 0 = disable
2638 * Return Value: 0 if success, otherwise error code
2639 */
2640 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2641 {
2642 unsigned long flags;
2643
2644 if (debug_level >= DEBUG_LEVEL_INFO)
2645 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2646 info->device_name, enable);
2647
2648 spin_lock_irqsave(&info->irq_spinlock,flags);
2649 if ( enable ) {
2650 if ( !info->rx_enabled )
2651 usc_start_receiver(info);
2652 } else {
2653 if ( info->rx_enabled )
2654 usc_stop_receiver(info);
2655 }
2656 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2657 return 0;
2658
2659 } /* end of mgsl_rxenable() */
2660
2661 /* mgsl_wait_event() wait for specified event to occur
2662 *
2663 * Arguments: info pointer to device instance data
2664 * mask pointer to bitmask of events to wait for
2665 * Return Value: 0 if successful and bit mask updated with
2666 * of events triggerred,
2667 * otherwise error code
2668 */
2669 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2670 {
2671 unsigned long flags;
2672 int s;
2673 int rc=0;
2674 struct mgsl_icount cprev, cnow;
2675 int events;
2676 int mask;
2677 struct _input_signal_events oldsigs, newsigs;
2678 DECLARE_WAITQUEUE(wait, current);
2679
2680 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2681 if (rc) {
2682 return -EFAULT;
2683 }
2684
2685 if (debug_level >= DEBUG_LEVEL_INFO)
2686 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2687 info->device_name, mask);
2688
2689 spin_lock_irqsave(&info->irq_spinlock,flags);
2690
2691 /* return immediately if state matches requested events */
2692 usc_get_serial_signals(info);
2693 s = info->serial_signals;
2694 events = mask &
2695 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2696 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2697 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2698 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2699 if (events) {
2700 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2701 goto exit;
2702 }
2703
2704 /* save current irq counts */
2705 cprev = info->icount;
2706 oldsigs = info->input_signal_events;
2707
2708 /* enable hunt and idle irqs if needed */
2709 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2710 u16 oldreg = usc_InReg(info,RICR);
2711 u16 newreg = oldreg +
2712 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2713 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2714 if (oldreg != newreg)
2715 usc_OutReg(info, RICR, newreg);
2716 }
2717
2718 set_current_state(TASK_INTERRUPTIBLE);
2719 add_wait_queue(&info->event_wait_q, &wait);
2720
2721 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2722
2723
2724 for(;;) {
2725 schedule();
2726 if (signal_pending(current)) {
2727 rc = -ERESTARTSYS;
2728 break;
2729 }
2730
2731 /* get current irq counts */
2732 spin_lock_irqsave(&info->irq_spinlock,flags);
2733 cnow = info->icount;
2734 newsigs = info->input_signal_events;
2735 set_current_state(TASK_INTERRUPTIBLE);
2736 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2737
2738 /* if no change, wait aborted for some reason */
2739 if (newsigs.dsr_up == oldsigs.dsr_up &&
2740 newsigs.dsr_down == oldsigs.dsr_down &&
2741 newsigs.dcd_up == oldsigs.dcd_up &&
2742 newsigs.dcd_down == oldsigs.dcd_down &&
2743 newsigs.cts_up == oldsigs.cts_up &&
2744 newsigs.cts_down == oldsigs.cts_down &&
2745 newsigs.ri_up == oldsigs.ri_up &&
2746 newsigs.ri_down == oldsigs.ri_down &&
2747 cnow.exithunt == cprev.exithunt &&
2748 cnow.rxidle == cprev.rxidle) {
2749 rc = -EIO;
2750 break;
2751 }
2752
2753 events = mask &
2754 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2755 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2756 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2757 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2758 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2759 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2760 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2761 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2762 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2763 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2764 if (events)
2765 break;
2766
2767 cprev = cnow;
2768 oldsigs = newsigs;
2769 }
2770
2771 remove_wait_queue(&info->event_wait_q, &wait);
2772 set_current_state(TASK_RUNNING);
2773
2774 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2775 spin_lock_irqsave(&info->irq_spinlock,flags);
2776 if (!waitqueue_active(&info->event_wait_q)) {
2777 /* disable enable exit hunt mode/idle rcvd IRQs */
2778 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2779 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2780 }
2781 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2782 }
2783 exit:
2784 if ( rc == 0 )
2785 PUT_USER(rc, events, mask_ptr);
2786
2787 return rc;
2788
2789 } /* end of mgsl_wait_event() */
2790
2791 static int modem_input_wait(struct mgsl_struct *info,int arg)
2792 {
2793 unsigned long flags;
2794 int rc;
2795 struct mgsl_icount cprev, cnow;
2796 DECLARE_WAITQUEUE(wait, current);
2797
2798 /* save current irq counts */
2799 spin_lock_irqsave(&info->irq_spinlock,flags);
2800 cprev = info->icount;
2801 add_wait_queue(&info->status_event_wait_q, &wait);
2802 set_current_state(TASK_INTERRUPTIBLE);
2803 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2804
2805 for(;;) {
2806 schedule();
2807 if (signal_pending(current)) {
2808 rc = -ERESTARTSYS;
2809 break;
2810 }
2811
2812 /* get new irq counts */
2813 spin_lock_irqsave(&info->irq_spinlock,flags);
2814 cnow = info->icount;
2815 set_current_state(TASK_INTERRUPTIBLE);
2816 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2817
2818 /* if no change, wait aborted for some reason */
2819 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2820 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2821 rc = -EIO;
2822 break;
2823 }
2824
2825 /* check for change in caller specified modem input */
2826 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2827 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2828 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2829 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2830 rc = 0;
2831 break;
2832 }
2833
2834 cprev = cnow;
2835 }
2836 remove_wait_queue(&info->status_event_wait_q, &wait);
2837 set_current_state(TASK_RUNNING);
2838 return rc;
2839 }
2840
2841 /* return the state of the serial control and status signals
2842 */
2843 static int tiocmget(struct tty_struct *tty, struct file *file)
2844 {
2845 struct mgsl_struct *info = tty->driver_data;
2846 unsigned int result;
2847 unsigned long flags;
2848
2849 spin_lock_irqsave(&info->irq_spinlock,flags);
2850 usc_get_serial_signals(info);
2851 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2852
2853 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2854 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2855 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2856 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2857 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2858 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2859
2860 if (debug_level >= DEBUG_LEVEL_INFO)
2861 printk("%s(%d):%s tiocmget() value=%08X\n",
2862 __FILE__,__LINE__, info->device_name, result );
2863 return result;
2864 }
2865
2866 /* set modem control signals (DTR/RTS)
2867 */
2868 static int tiocmset(struct tty_struct *tty, struct file *file,
2869 unsigned int set, unsigned int clear)
2870 {
2871 struct mgsl_struct *info = tty->driver_data;
2872 unsigned long flags;
2873
2874 if (debug_level >= DEBUG_LEVEL_INFO)
2875 printk("%s(%d):%s tiocmset(%x,%x)\n",
2876 __FILE__,__LINE__,info->device_name, set, clear);
2877
2878 if (set & TIOCM_RTS)
2879 info->serial_signals |= SerialSignal_RTS;
2880 if (set & TIOCM_DTR)
2881 info->serial_signals |= SerialSignal_DTR;
2882 if (clear & TIOCM_RTS)
2883 info->serial_signals &= ~SerialSignal_RTS;
2884 if (clear & TIOCM_DTR)
2885 info->serial_signals &= ~SerialSignal_DTR;
2886
2887 spin_lock_irqsave(&info->irq_spinlock,flags);
2888 usc_set_serial_signals(info);
2889 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2890
2891 return 0;
2892 }
2893
2894 /* mgsl_break() Set or clear transmit break condition
2895 *
2896 * Arguments: tty pointer to tty instance data
2897 * break_state -1=set break condition, 0=clear
2898 * Return Value: error code
2899 */
2900 static int mgsl_break(struct tty_struct *tty, int break_state)
2901 {
2902 struct mgsl_struct * info = tty->driver_data;
2903 unsigned long flags;
2904
2905 if (debug_level >= DEBUG_LEVEL_INFO)
2906 printk("%s(%d):mgsl_break(%s,%d)\n",
2907 __FILE__,__LINE__, info->device_name, break_state);
2908
2909 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2910 return -EINVAL;
2911
2912 spin_lock_irqsave(&info->irq_spinlock,flags);
2913 if (break_state == -1)
2914 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2915 else
2916 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2917 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2918 return 0;
2919
2920 } /* end of mgsl_break() */
2921
2922 /* mgsl_ioctl() Service an IOCTL request
2923 *
2924 * Arguments:
2925 *
2926 * tty pointer to tty instance data
2927 * file pointer to associated file object for device
2928 * cmd IOCTL command code
2929 * arg command argument/context
2930 *
2931 * Return Value: 0 if success, otherwise error code
2932 */
2933 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2934 unsigned int cmd, unsigned long arg)
2935 {
2936 struct mgsl_struct * info = tty->driver_data;
2937 int ret;
2938
2939 if (debug_level >= DEBUG_LEVEL_INFO)
2940 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2941 info->device_name, cmd );
2942
2943 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2944 return -ENODEV;
2945
2946 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2947 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2948 if (tty->flags & (1 << TTY_IO_ERROR))
2949 return -EIO;
2950 }
2951
2952 lock_kernel();
2953 ret = mgsl_ioctl_common(info, cmd, arg);
2954 unlock_kernel();
2955 return ret;
2956 }
2957
2958 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2959 {
2960 int error;
2961 struct mgsl_icount cnow; /* kernel counter temps */
2962 void __user *argp = (void __user *)arg;
2963 struct serial_icounter_struct __user *p_cuser; /* user space */
2964 unsigned long flags;
2965
2966 switch (cmd) {
2967 case MGSL_IOCGPARAMS:
2968 return mgsl_get_params(info, argp);
2969 case MGSL_IOCSPARAMS:
2970 return mgsl_set_params(info, argp);
2971 case MGSL_IOCGTXIDLE:
2972 return mgsl_get_txidle(info, argp);
2973 case MGSL_IOCSTXIDLE:
2974 return mgsl_set_txidle(info,(int)arg);
2975 case MGSL_IOCTXENABLE:
2976 return mgsl_txenable(info,(int)arg);
2977 case MGSL_IOCRXENABLE:
2978 return mgsl_rxenable(info,(int)arg);
2979 case MGSL_IOCTXABORT:
2980 return mgsl_txabort(info);
2981 case MGSL_IOCGSTATS:
2982 return mgsl_get_stats(info, argp);
2983 case MGSL_IOCWAITEVENT:
2984 return mgsl_wait_event(info, argp);
2985 case MGSL_IOCLOOPTXDONE:
2986 return mgsl_loopmode_send_done(info);
2987 /* Wait for modem input (DCD,RI,DSR,CTS) change
2988 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2989 */
2990 case TIOCMIWAIT:
2991 return modem_input_wait(info,(int)arg);
2992
2993 /*
2994 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2995 * Return: write counters to the user passed counter struct
2996 * NB: both 1->0 and 0->1 transitions are counted except for
2997 * RI where only 0->1 is counted.
2998 */
2999 case TIOCGICOUNT:
3000 spin_lock_irqsave(&info->irq_spinlock,flags);
3001 cnow = info->icount;
3002 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3003 p_cuser = argp;
3004 PUT_USER(error,cnow.cts, &p_cuser->cts);
3005 if (error) return error;
3006 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3007 if (error) return error;
3008 PUT_USER(error,cnow.rng, &p_cuser->rng);
3009 if (error) return error;
3010 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3011 if (error) return error;
3012 PUT_USER(error,cnow.rx, &p_cuser->rx);
3013 if (error) return error;
3014 PUT_USER(error,cnow.tx, &p_cuser->tx);
3015 if (error) return error;
3016 PUT_USER(error,cnow.frame, &p_cuser->frame);
3017 if (error) return error;
3018 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3019 if (error) return error;
3020 PUT_USER(error,cnow.parity, &p_cuser->parity);
3021 if (error) return error;
3022 PUT_USER(error,cnow.brk, &p_cuser->brk);
3023 if (error) return error;
3024 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3025 if (error) return error;
3026 return 0;
3027 default:
3028 return -ENOIOCTLCMD;
3029 }
3030 return 0;
3031 }
3032
3033 /* mgsl_set_termios()
3034 *
3035 * Set new termios settings
3036 *
3037 * Arguments:
3038 *
3039 * tty pointer to tty structure
3040 * termios pointer to buffer to hold returned old termios
3041 *
3042 * Return Value: None
3043 */
3044 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3045 {
3046 struct mgsl_struct *info = tty->driver_data;
3047 unsigned long flags;
3048
3049 if (debug_level >= DEBUG_LEVEL_INFO)
3050 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3051 tty->driver->name );
3052
3053 mgsl_change_params(info);
3054
3055 /* Handle transition to B0 status */
3056 if (old_termios->c_cflag & CBAUD &&
3057 !(tty->termios->c_cflag & CBAUD)) {
3058 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3059 spin_lock_irqsave(&info->irq_spinlock,flags);
3060 usc_set_serial_signals(info);
3061 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3062 }
3063
3064 /* Handle transition away from B0 status */
3065 if (!(old_termios->c_cflag & CBAUD) &&
3066 tty->termios->c_cflag & CBAUD) {
3067 info->serial_signals |= SerialSignal_DTR;
3068 if (!(tty->termios->c_cflag & CRTSCTS) ||
3069 !test_bit(TTY_THROTTLED, &tty->flags)) {
3070 info->serial_signals |= SerialSignal_RTS;
3071 }
3072 spin_lock_irqsave(&info->irq_spinlock,flags);
3073 usc_set_serial_signals(info);
3074 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3075 }
3076
3077 /* Handle turning off CRTSCTS */
3078 if (old_termios->c_cflag & CRTSCTS &&
3079 !(tty->termios->c_cflag & CRTSCTS)) {
3080 tty->hw_stopped = 0;
3081 mgsl_start(tty);
3082 }
3083
3084 } /* end of mgsl_set_termios() */
3085
3086 /* mgsl_close()
3087 *
3088 * Called when port is closed. Wait for remaining data to be
3089 * sent. Disable port and free resources.
3090 *
3091 * Arguments:
3092 *
3093 * tty pointer to open tty structure
3094 * filp pointer to open file object
3095 *
3096 * Return Value: None
3097 */
3098 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3099 {
3100 struct mgsl_struct * info = tty->driver_data;
3101
3102 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3103 return;
3104
3105 if (debug_level >= DEBUG_LEVEL_INFO)
3106 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3107 __FILE__,__LINE__, info->device_name, info->port.count);
3108
3109 if (tty_port_close_start(&info->port, tty, filp) == 0)
3110 goto cleanup;
3111
3112 if (info->port.flags & ASYNC_INITIALIZED)
3113 mgsl_wait_until_sent(tty, info->timeout);
3114 mgsl_flush_buffer(tty);
3115 tty_ldisc_flush(tty);
3116 shutdown(info);
3117
3118 tty_port_close_end(&info->port, tty);
3119 info->port.tty = NULL;
3120 cleanup:
3121 if (debug_level >= DEBUG_LEVEL_INFO)
3122 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3123 tty->driver->name, info->port.count);
3124
3125 } /* end of mgsl_close() */
3126
3127 /* mgsl_wait_until_sent()
3128 *
3129 * Wait until the transmitter is empty.
3130 *
3131 * Arguments:
3132 *
3133 * tty pointer to tty info structure
3134 * timeout time to wait for send completion
3135 *
3136 * Return Value: None
3137 */
3138 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3139 {
3140 struct mgsl_struct * info = tty->driver_data;
3141 unsigned long orig_jiffies, char_time;
3142
3143 if (!info )
3144 return;
3145
3146 if (debug_level >= DEBUG_LEVEL_INFO)
3147 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3148 __FILE__,__LINE__, info->device_name );
3149
3150 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3151 return;
3152
3153 if (!(info->port.flags & ASYNC_INITIALIZED))
3154 goto exit;
3155
3156 orig_jiffies = jiffies;
3157
3158 /* Set check interval to 1/5 of estimated time to
3159 * send a character, and make it at least 1. The check
3160 * interval should also be less than the timeout.
3161 * Note: use tight timings here to satisfy the NIST-PCTS.
3162 */
3163
3164 lock_kernel();
3165 if ( info->params.data_rate ) {
3166 char_time = info->timeout/(32 * 5);
3167 if (!char_time)
3168 char_time++;
3169 } else
3170 char_time = 1;
3171
3172 if (timeout)
3173 char_time = min_t(unsigned long, char_time, timeout);
3174
3175 if ( info->params.mode == MGSL_MODE_HDLC ||
3176 info->params.mode == MGSL_MODE_RAW ) {
3177 while (info->tx_active) {
3178 msleep_interruptible(jiffies_to_msecs(char_time));
3179 if (signal_pending(current))
3180 break;
3181 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3182 break;
3183 }
3184 } else {
3185 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3186 info->tx_enabled) {
3187 msleep_interruptible(jiffies_to_msecs(char_time));
3188 if (signal_pending(current))
3189 break;
3190 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3191 break;
3192 }
3193 }
3194 unlock_kernel();
3195
3196 exit:
3197 if (debug_level >= DEBUG_LEVEL_INFO)
3198 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3199 __FILE__,__LINE__, info->device_name );
3200
3201 } /* end of mgsl_wait_until_sent() */
3202
3203 /* mgsl_hangup()
3204 *
3205 * Called by tty_hangup() when a hangup is signaled.
3206 * This is the same as to closing all open files for the port.
3207 *
3208 * Arguments: tty pointer to associated tty object
3209 * Return Value: None
3210 */
3211 static void mgsl_hangup(struct tty_struct *tty)
3212 {
3213 struct mgsl_struct * info = tty->driver_data;
3214
3215 if (debug_level >= DEBUG_LEVEL_INFO)
3216 printk("%s(%d):mgsl_hangup(%s)\n",
3217 __FILE__,__LINE__, info->device_name );
3218
3219 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3220 return;
3221
3222 mgsl_flush_buffer(tty);
3223 shutdown(info);
3224
3225 info->port.count = 0;
3226 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3227 info->port.tty = NULL;
3228
3229 wake_up_interruptible(&info->port.open_wait);
3230
3231 } /* end of mgsl_hangup() */
3232
3233 /*
3234 * carrier_raised()
3235 *
3236 * Return true if carrier is raised
3237 */
3238
3239 static int carrier_raised(struct tty_port *port)
3240 {
3241 unsigned long flags;
3242 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3243
3244 spin_lock_irqsave(&info->irq_spinlock, flags);
3245 usc_get_serial_signals(info);
3246 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3247 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3248 }
3249
3250 static void raise_dtr_rts(struct tty_port *port)
3251 {
3252 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3253 unsigned long flags;
3254
3255 spin_lock_irqsave(&info->irq_spinlock,flags);
3256 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3257 usc_set_serial_signals(info);
3258 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3259 }
3260
3261
3262 /* block_til_ready()
3263 *
3264 * Block the current process until the specified port
3265 * is ready to be opened.
3266 *
3267 * Arguments:
3268 *
3269 * tty pointer to tty info structure
3270 * filp pointer to open file object
3271 * info pointer to device instance data
3272 *
3273 * Return Value: 0 if success, otherwise error code
3274 */
3275 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3276 struct mgsl_struct *info)
3277 {
3278 DECLARE_WAITQUEUE(wait, current);
3279 int retval;
3280 bool do_clocal = false;
3281 bool extra_count = false;
3282 unsigned long flags;
3283 int dcd;
3284 struct tty_port *port = &info->port;
3285
3286 if (debug_level >= DEBUG_LEVEL_INFO)
3287 printk("%s(%d):block_til_ready on %s\n",
3288 __FILE__,__LINE__, tty->driver->name );
3289
3290 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3291 /* nonblock mode is set or port is not enabled */
3292 port->flags |= ASYNC_NORMAL_ACTIVE;
3293 return 0;
3294 }
3295
3296 if (tty->termios->c_cflag & CLOCAL)
3297 do_clocal = true;
3298
3299 /* Wait for carrier detect and the line to become
3300 * free (i.e., not in use by the callout). While we are in
3301 * this loop, port->count is dropped by one, so that
3302 * mgsl_close() knows when to free things. We restore it upon
3303 * exit, either normal or abnormal.
3304 */
3305
3306 retval = 0;
3307 add_wait_queue(&port->open_wait, &wait);
3308
3309 if (debug_level >= DEBUG_LEVEL_INFO)
3310 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3311 __FILE__,__LINE__, tty->driver->name, port->count );
3312
3313 spin_lock_irqsave(&info->irq_spinlock, flags);
3314 if (!tty_hung_up_p(filp)) {
3315 extra_count = true;
3316 port->count--;
3317 }
3318 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3319 port->blocked_open++;
3320
3321 while (1) {
3322 if (tty->termios->c_cflag & CBAUD)
3323 tty_port_raise_dtr_rts(port);
3324
3325 set_current_state(TASK_INTERRUPTIBLE);
3326
3327 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3328 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3329 -EAGAIN : -ERESTARTSYS;
3330 break;
3331 }
3332
3333 dcd = tty_port_carrier_raised(&info->port);
3334
3335 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3336 break;
3337
3338 if (signal_pending(current)) {
3339 retval = -ERESTARTSYS;
3340 break;
3341 }
3342
3343 if (debug_level >= DEBUG_LEVEL_INFO)
3344 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3345 __FILE__,__LINE__, tty->driver->name, port->count );
3346
3347 schedule();
3348 }
3349
3350 set_current_state(TASK_RUNNING);
3351 remove_wait_queue(&port->open_wait, &wait);
3352
3353 /* FIXME: Racy on hangup during close wait */
3354 if (extra_count)
3355 port->count++;
3356 port->blocked_open--;
3357
3358 if (debug_level >= DEBUG_LEVEL_INFO)
3359 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3360 __FILE__,__LINE__, tty->driver->name, port->count );
3361
3362 if (!retval)
3363 port->flags |= ASYNC_NORMAL_ACTIVE;
3364
3365 return retval;
3366
3367 } /* end of block_til_ready() */
3368
3369 /* mgsl_open()
3370 *
3371 * Called when a port is opened. Init and enable port.
3372 * Perform serial-specific initialization for the tty structure.
3373 *
3374 * Arguments: tty pointer to tty info structure
3375 * filp associated file pointer
3376 *
3377 * Return Value: 0 if success, otherwise error code
3378 */
3379 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3380 {
3381 struct mgsl_struct *info;
3382 int retval, line;
3383 unsigned long flags;
3384
3385 /* verify range of specified line number */
3386 line = tty->index;
3387 if ((line < 0) || (line >= mgsl_device_count)) {
3388 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3389 __FILE__,__LINE__,line);
3390 return -ENODEV;
3391 }
3392
3393 /* find the info structure for the specified line */
3394 info = mgsl_device_list;
3395 while(info && info->line != line)
3396 info = info->next_device;
3397 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3398 return -ENODEV;
3399
3400 tty->driver_data = info;
3401 info->port.tty = tty;
3402
3403 if (debug_level >= DEBUG_LEVEL_INFO)
3404 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3405 __FILE__,__LINE__,tty->driver->name, info->port.count);
3406
3407 /* If port is closing, signal caller to try again */
3408 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3409 if (info->port.flags & ASYNC_CLOSING)
3410 interruptible_sleep_on(&info->port.close_wait);
3411 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3412 -EAGAIN : -ERESTARTSYS);
3413 goto cleanup;
3414 }
3415
3416 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3417
3418 spin_lock_irqsave(&info->netlock, flags);
3419 if (info->netcount) {
3420 retval = -EBUSY;
3421 spin_unlock_irqrestore(&info->netlock, flags);
3422 goto cleanup;
3423 }
3424 info->port.count++;
3425 spin_unlock_irqrestore(&info->netlock, flags);
3426
3427 if (info->port.count == 1) {
3428 /* 1st open on this device, init hardware */
3429 retval = startup(info);
3430 if (retval < 0)
3431 goto cleanup;
3432 }
3433
3434 retval = block_til_ready(tty, filp, info);
3435 if (retval) {
3436 if (debug_level >= DEBUG_LEVEL_INFO)
3437 printk("%s(%d):block_til_ready(%s) returned %d\n",
3438 __FILE__,__LINE__, info->device_name, retval);
3439 goto cleanup;
3440 }
3441
3442 if (debug_level >= DEBUG_LEVEL_INFO)
3443 printk("%s(%d):mgsl_open(%s) success\n",
3444 __FILE__,__LINE__, info->device_name);
3445 retval = 0;
3446
3447 cleanup:
3448 if (retval) {
3449 if (tty->count == 1)
3450 info->port.tty = NULL; /* tty layer will release tty struct */
3451 if(info->port.count)
3452 info->port.count--;
3453 }
3454
3455 return retval;
3456
3457 } /* end of mgsl_open() */
3458
3459 /*
3460 * /proc fs routines....
3461 */
3462
3463 static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3464 {
3465 char stat_buf[30];
3466 unsigned long flags;
3467
3468 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3469 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3470 info->device_name, info->io_base, info->irq_level,
3471 info->phys_memory_base, info->phys_lcr_base);
3472 } else {
3473 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3474 info->device_name, info->io_base,
3475 info->irq_level, info->dma_level);
3476 }
3477
3478 /* output current serial signal states */
3479 spin_lock_irqsave(&info->irq_spinlock,flags);
3480 usc_get_serial_signals(info);
3481 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3482
3483 stat_buf[0] = 0;
3484 stat_buf[1] = 0;
3485 if (info->serial_signals & SerialSignal_RTS)
3486 strcat(stat_buf, "|RTS");
3487 if (info->serial_signals & SerialSignal_CTS)
3488 strcat(stat_buf, "|CTS");
3489 if (info->serial_signals & SerialSignal_DTR)
3490 strcat(stat_buf, "|DTR");
3491 if (info->serial_signals & SerialSignal_DSR)
3492 strcat(stat_buf, "|DSR");
3493 if (info->serial_signals & SerialSignal_DCD)
3494 strcat(stat_buf, "|CD");
3495 if (info->serial_signals & SerialSignal_RI)
3496 strcat(stat_buf, "|RI");
3497
3498 if (info->params.mode == MGSL_MODE_HDLC ||
3499 info->params.mode == MGSL_MODE_RAW ) {
3500 seq_printf(m, " HDLC txok:%d rxok:%d",
3501 info->icount.txok, info->icount.rxok);
3502 if (info->icount.txunder)
3503 seq_printf(m, " txunder:%d", info->icount.txunder);
3504 if (info->icount.txabort)
3505 seq_printf(m, " txabort:%d", info->icount.txabort);
3506 if (info->icount.rxshort)
3507 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3508 if (info->icount.rxlong)
3509 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3510 if (info->icount.rxover)
3511 seq_printf(m, " rxover:%d", info->icount.rxover);
3512 if (info->icount.rxcrc)
3513 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3514 } else {
3515 seq_printf(m, " ASYNC tx:%d rx:%d",
3516 info->icount.tx, info->icount.rx);
3517 if (info->icount.frame)
3518 seq_printf(m, " fe:%d", info->icount.frame);
3519 if (info->icount.parity)
3520 seq_printf(m, " pe:%d", info->icount.parity);
3521 if (info->icount.brk)
3522 seq_printf(m, " brk:%d", info->icount.brk);
3523 if (info->icount.overrun)
3524 seq_printf(m, " oe:%d", info->icount.overrun);
3525 }
3526
3527 /* Append serial signal status to end */
3528 seq_printf(m, " %s\n", stat_buf+1);
3529
3530 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3531 info->tx_active,info->bh_requested,info->bh_running,
3532 info->pending_bh);
3533
3534 spin_lock_irqsave(&info->irq_spinlock,flags);
3535 {
3536 u16 Tcsr = usc_InReg( info, TCSR );
3537 u16 Tdmr = usc_InDmaReg( info, TDMR );
3538 u16 Ticr = usc_InReg( info, TICR );
3539 u16 Rscr = usc_InReg( info, RCSR );
3540 u16 Rdmr = usc_InDmaReg( info, RDMR );
3541 u16 Ricr = usc_InReg( info, RICR );
3542 u16 Icr = usc_InReg( info, ICR );
3543 u16 Dccr = usc_InReg( info, DCCR );
3544 u16 Tmr = usc_InReg( info, TMR );
3545 u16 Tccr = usc_InReg( info, TCCR );
3546 u16 Ccar = inw( info->io_base + CCAR );
3547 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3548 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3549 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3550 }
3551 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3552 }
3553
3554 /* Called to print information about devices */
3555 static int mgsl_proc_show(struct seq_file *m, void *v)
3556 {
3557 struct mgsl_struct *info;
3558
3559 seq_printf(m, "synclink driver:%s\n", driver_version);
3560
3561 info = mgsl_device_list;
3562 while( info ) {
3563 line_info(m, info);
3564 info = info->next_device;
3565 }
3566 return 0;
3567 }
3568
3569 static int mgsl_proc_open(struct inode *inode, struct file *file)
3570 {
3571 return single_open(file, mgsl_proc_show, NULL);
3572 }
3573
3574 static const struct file_operations mgsl_proc_fops = {
3575 .owner = THIS_MODULE,
3576 .open = mgsl_proc_open,
3577 .read = seq_read,
3578 .llseek = seq_lseek,
3579 .release = single_release,
3580 };
3581
3582 /* mgsl_allocate_dma_buffers()
3583 *
3584 * Allocate and format DMA buffers (ISA adapter)
3585 * or format shared memory buffers (PCI adapter).
3586 *
3587 * Arguments: info pointer to device instance data
3588 * Return Value: 0 if success, otherwise error
3589 */
3590 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3591 {
3592 unsigned short BuffersPerFrame;
3593
3594 info->last_mem_alloc = 0;
3595
3596 /* Calculate the number of DMA buffers necessary to hold the */
3597 /* largest allowable frame size. Note: If the max frame size is */
3598 /* not an even multiple of the DMA buffer size then we need to */
3599 /* round the buffer count per frame up one. */
3600
3601 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3602 if ( info->max_frame_size % DMABUFFERSIZE )
3603 BuffersPerFrame++;
3604
3605 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3606 /*
3607 * The PCI adapter has 256KBytes of shared memory to use.
3608 * This is 64 PAGE_SIZE buffers.
3609 *
3610 * The first page is used for padding at this time so the
3611 * buffer list does not begin at offset 0 of the PCI
3612 * adapter's shared memory.
3613 *
3614 * The 2nd page is used for the buffer list. A 4K buffer
3615 * list can hold 128 DMA_BUFFER structures at 32 bytes
3616 * each.
3617 *
3618 * This leaves 62 4K pages.
3619 *
3620 * The next N pages are used for transmit frame(s). We
3621 * reserve enough 4K page blocks to hold the required
3622 * number of transmit dma buffers (num_tx_dma_buffers),
3623 * each of MaxFrameSize size.
3624 *
3625 * Of the remaining pages (62-N), determine how many can
3626 * be used to receive full MaxFrameSize inbound frames
3627 */
3628 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3629 info->rx_buffer_count = 62 - info->tx_buffer_count;
3630 } else {
3631 /* Calculate the number of PAGE_SIZE buffers needed for */
3632 /* receive and transmit DMA buffers. */
3633
3634
3635 /* Calculate the number of DMA buffers necessary to */
3636 /* hold 7 max size receive frames and one max size transmit frame. */
3637 /* The receive buffer count is bumped by one so we avoid an */
3638 /* End of List condition if all receive buffers are used when */
3639 /* using linked list DMA buffers. */
3640
3641 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3642 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3643
3644 /*
3645 * limit total TxBuffers & RxBuffers to 62 4K total
3646 * (ala PCI Allocation)
3647 */
3648
3649 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3650 info->rx_buffer_count = 62 - info->tx_buffer_count;
3651
3652 }
3653
3654 if ( debug_level >= DEBUG_LEVEL_INFO )
3655 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3656 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3657
3658 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3659 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3660 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3661 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3662 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3663 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3664 return -ENOMEM;
3665 }
3666
3667 mgsl_reset_rx_dma_buffers( info );
3668 mgsl_reset_tx_dma_buffers( info );
3669
3670 return 0;
3671
3672 } /* end of mgsl_allocate_dma_buffers() */
3673
3674 /*
3675 * mgsl_alloc_buffer_list_memory()
3676 *
3677 * Allocate a common DMA buffer for use as the
3678 * receive and transmit buffer lists.
3679 *
3680 * A buffer list is a set of buffer entries where each entry contains
3681 * a pointer to an actual buffer and a pointer to the next buffer entry
3682 * (plus some other info about the buffer).
3683 *
3684 * The buffer entries for a list are built to form a circular list so
3685 * that when the entire list has been traversed you start back at the
3686 * beginning.
3687 *
3688 * This function allocates memory for just the buffer entries.
3689 * The links (pointer to next entry) are filled in with the physical
3690 * address of the next entry so the adapter can navigate the list
3691 * using bus master DMA. The pointers to the actual buffers are filled
3692 * out later when the actual buffers are allocated.
3693 *
3694 * Arguments: info pointer to device instance data
3695 * Return Value: 0 if success, otherwise error
3696 */
3697 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3698 {
3699 unsigned int i;
3700
3701 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3702 /* PCI adapter uses shared memory. */
3703 info->buffer_list = info->memory_base + info->last_mem_alloc;
3704 info->buffer_list_phys = info->last_mem_alloc;
3705 info->last_mem_alloc += BUFFERLISTSIZE;
3706 } else {
3707 /* ISA adapter uses system memory. */
3708 /* The buffer lists are allocated as a common buffer that both */
3709 /* the processor and adapter can access. This allows the driver to */
3710 /* inspect portions of the buffer while other portions are being */
3711 /* updated by the adapter using Bus Master DMA. */
3712
3713 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3714 if (info->buffer_list == NULL)
3715 return -ENOMEM;
3716 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3717 }
3718
3719 /* We got the memory for the buffer entry lists. */
3720 /* Initialize the memory block to all zeros. */
3721 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3722
3723 /* Save virtual address pointers to the receive and */
3724 /* transmit buffer lists. (Receive 1st). These pointers will */
3725 /* be used by the processor to access the lists. */
3726 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3727 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3728 info->tx_buffer_list += info->rx_buffer_count;
3729
3730 /*
3731 * Build the links for the buffer entry lists such that
3732 * two circular lists are built. (Transmit and Receive).
3733 *
3734 * Note: the links are physical addresses
3735 * which are read by the adapter to determine the next
3736 * buffer entry to use.
3737 */
3738
3739 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3740 /* calculate and store physical address of this buffer entry */
3741 info->rx_buffer_list[i].phys_entry =
3742 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3743
3744 /* calculate and store physical address of */
3745 /* next entry in cirular list of entries */
3746
3747 info->rx_buffer_list[i].link = info->buffer_list_phys;
3748
3749 if ( i < info->rx_buffer_count - 1 )
3750 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3751 }
3752
3753 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3754 /* calculate and store physical address of this buffer entry */
3755 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3756 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3757
3758 /* calculate and store physical address of */
3759 /* next entry in cirular list of entries */
3760
3761 info->tx_buffer_list[i].link = info->buffer_list_phys +
3762 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3763
3764 if ( i < info->tx_buffer_count - 1 )
3765 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3766 }
3767
3768 return 0;
3769
3770 } /* end of mgsl_alloc_buffer_list_memory() */
3771
3772 /* Free DMA buffers allocated for use as the
3773 * receive and transmit buffer lists.
3774 * Warning:
3775 *
3776 * The data transfer buffers associated with the buffer list
3777 * MUST be freed before freeing the buffer list itself because
3778 * the buffer list contains the information necessary to free
3779 * the individual buffers!
3780 */
3781 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3782 {
3783 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3784 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3785
3786 info->buffer_list = NULL;
3787 info->rx_buffer_list = NULL;
3788 info->tx_buffer_list = NULL;
3789
3790 } /* end of mgsl_free_buffer_list_memory() */
3791
3792 /*
3793 * mgsl_alloc_frame_memory()
3794 *
3795 * Allocate the frame DMA buffers used by the specified buffer list.
3796 * Each DMA buffer will be one memory page in size. This is necessary
3797 * because memory can fragment enough that it may be impossible
3798 * contiguous pages.
3799 *
3800 * Arguments:
3801 *
3802 * info pointer to device instance data
3803 * BufferList pointer to list of buffer entries
3804 * Buffercount count of buffer entries in buffer list
3805 *
3806 * Return Value: 0 if success, otherwise -ENOMEM
3807 */
3808 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3809 {
3810 int i;
3811 u32 phys_addr;
3812
3813 /* Allocate page sized buffers for the receive buffer list */
3814
3815 for ( i = 0; i < Buffercount; i++ ) {
3816 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3817 /* PCI adapter uses shared memory buffers. */
3818 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3819 phys_addr = info->last_mem_alloc;
3820 info->last_mem_alloc += DMABUFFERSIZE;
3821 } else {
3822 /* ISA adapter uses system memory. */
3823 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3824 if (BufferList[i].virt_addr == NULL)
3825 return -ENOMEM;
3826 phys_addr = (u32)(BufferList[i].dma_addr);
3827 }
3828 BufferList[i].phys_addr = phys_addr;
3829 }
3830
3831 return 0;
3832
3833 } /* end of mgsl_alloc_frame_memory() */
3834
3835 /*
3836 * mgsl_free_frame_memory()
3837 *
3838 * Free the buffers associated with
3839 * each buffer entry of a buffer list.
3840 *
3841 * Arguments:
3842 *
3843 * info pointer to device instance data
3844 * BufferList pointer to list of buffer entries
3845 * Buffercount count of buffer entries in buffer list
3846 *
3847 * Return Value: None
3848 */
3849 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3850 {
3851 int i;
3852
3853 if ( BufferList ) {
3854 for ( i = 0 ; i < Buffercount ; i++ ) {
3855 if ( BufferList[i].virt_addr ) {
3856 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3857 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3858 BufferList[i].virt_addr = NULL;
3859 }
3860 }
3861 }
3862
3863 } /* end of mgsl_free_frame_memory() */
3864
3865 /* mgsl_free_dma_buffers()
3866 *
3867 * Free DMA buffers
3868 *
3869 * Arguments: info pointer to device instance data
3870 * Return Value: None
3871 */
3872 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3873 {
3874 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3875 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3876 mgsl_free_buffer_list_memory( info );
3877
3878 } /* end of mgsl_free_dma_buffers() */
3879
3880
3881 /*
3882 * mgsl_alloc_intermediate_rxbuffer_memory()
3883 *
3884 * Allocate a buffer large enough to hold max_frame_size. This buffer
3885 * is used to pass an assembled frame to the line discipline.
3886 *
3887 * Arguments:
3888 *
3889 * info pointer to device instance data
3890 *
3891 * Return Value: 0 if success, otherwise -ENOMEM
3892 */
3893 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3894 {
3895 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3896 if ( info->intermediate_rxbuffer == NULL )
3897 return -ENOMEM;
3898
3899 return 0;
3900
3901 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3902
3903 /*
3904 * mgsl_free_intermediate_rxbuffer_memory()
3905 *
3906 *
3907 * Arguments:
3908 *
3909 * info pointer to device instance data
3910 *
3911 * Return Value: None
3912 */
3913 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3914 {
3915 kfree(info->intermediate_rxbuffer);
3916 info->intermediate_rxbuffer = NULL;
3917
3918 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3919
3920 /*
3921 * mgsl_alloc_intermediate_txbuffer_memory()
3922 *
3923 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3924 * This buffer is used to load transmit frames into the adapter's dma transfer
3925 * buffers when there is sufficient space.
3926 *
3927 * Arguments:
3928 *
3929 * info pointer to device instance data
3930 *
3931 * Return Value: 0 if success, otherwise -ENOMEM
3932 */
3933 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3934 {
3935 int i;
3936
3937 if ( debug_level >= DEBUG_LEVEL_INFO )
3938 printk("%s %s(%d) allocating %d tx holding buffers\n",
3939 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3940
3941 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3942
3943 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3944 info->tx_holding_buffers[i].buffer =
3945 kmalloc(info->max_frame_size, GFP_KERNEL);
3946 if (info->tx_holding_buffers[i].buffer == NULL) {
3947 for (--i; i >= 0; i--) {
3948 kfree(info->tx_holding_buffers[i].buffer);
3949 info->tx_holding_buffers[i].buffer = NULL;
3950 }
3951 return -ENOMEM;
3952 }
3953 }
3954
3955 return 0;
3956
3957 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3958
3959 /*
3960 * mgsl_free_intermediate_txbuffer_memory()
3961 *
3962 *
3963 * Arguments:
3964 *
3965 * info pointer to device instance data
3966 *
3967 * Return Value: None
3968 */
3969 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3970 {
3971 int i;
3972
3973 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3974 kfree(info->tx_holding_buffers[i].buffer);
3975 info->tx_holding_buffers[i].buffer = NULL;
3976 }
3977
3978 info->get_tx_holding_index = 0;
3979 info->put_tx_holding_index = 0;
3980 info->tx_holding_count = 0;
3981
3982 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3983
3984
3985 /*
3986 * load_next_tx_holding_buffer()
3987 *
3988 * attempts to load the next buffered tx request into the
3989 * tx dma buffers
3990 *
3991 * Arguments:
3992 *
3993 * info pointer to device instance data
3994 *
3995 * Return Value: true if next buffered tx request loaded
3996 * into adapter's tx dma buffer,
3997 * false otherwise
3998 */
3999 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4000 {
4001 bool ret = false;
4002
4003 if ( info->tx_holding_count ) {
4004 /* determine if we have enough tx dma buffers
4005 * to accommodate the next tx frame
4006 */
4007 struct tx_holding_buffer *ptx =
4008 &info->tx_holding_buffers[info->get_tx_holding_index];
4009 int num_free = num_free_tx_dma_buffers(info);
4010 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4011 if ( ptx->buffer_size % DMABUFFERSIZE )
4012 ++num_needed;
4013
4014 if (num_needed <= num_free) {
4015 info->xmit_cnt = ptx->buffer_size;
4016 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4017
4018 --info->tx_holding_count;
4019 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4020 info->get_tx_holding_index=0;
4021
4022 /* restart transmit timer */
4023 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4024
4025 ret = true;
4026 }
4027 }
4028
4029 return ret;
4030 }
4031
4032 /*
4033 * save_tx_buffer_request()
4034 *
4035 * attempt to store transmit frame request for later transmission
4036 *
4037 * Arguments:
4038 *
4039 * info pointer to device instance data
4040 * Buffer pointer to buffer containing frame to load
4041 * BufferSize size in bytes of frame in Buffer
4042 *
4043 * Return Value: 1 if able to store, 0 otherwise
4044 */
4045 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4046 {
4047 struct tx_holding_buffer *ptx;
4048
4049 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4050 return 0; /* all buffers in use */
4051 }
4052
4053 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4054 ptx->buffer_size = BufferSize;
4055 memcpy( ptx->buffer, Buffer, BufferSize);
4056
4057 ++info->tx_holding_count;
4058 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4059 info->put_tx_holding_index=0;
4060
4061 return 1;
4062 }
4063
4064 static int mgsl_claim_resources(struct mgsl_struct *info)
4065 {
4066 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4067 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4068 __FILE__,__LINE__,info->device_name, info->io_base);
4069 return -ENODEV;
4070 }
4071 info->io_addr_requested = true;
4072
4073 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4074 info->device_name, info ) < 0 ) {
4075 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4076 __FILE__,__LINE__,info->device_name, info->irq_level );
4077 goto errout;
4078 }
4079 info->irq_requested = true;
4080
4081 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4082 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4083 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4084 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4085 goto errout;
4086 }
4087 info->shared_mem_requested = true;
4088 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4089 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4090 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4091 goto errout;
4092 }
4093 info->lcr_mem_requested = true;
4094
4095 info->memory_base = ioremap_nocache(info->phys_memory_base,
4096 0x40000);
4097 if (!info->memory_base) {
4098 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4099 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4100 goto errout;
4101 }
4102
4103 if ( !mgsl_memory_test(info) ) {
4104 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4105 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4106 goto errout;
4107 }
4108
4109 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4110 PAGE_SIZE);
4111 if (!info->lcr_base) {
4112 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4113 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4114 goto errout;
4115 }
4116 info->lcr_base += info->lcr_offset;
4117
4118 } else {
4119 /* claim DMA channel */
4120
4121 if (request_dma(info->dma_level,info->device_name) < 0){
4122 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4123 __FILE__,__LINE__,info->device_name, info->dma_level );
4124 mgsl_release_resources( info );
4125 return -ENODEV;
4126 }
4127 info->dma_requested = true;
4128
4129 /* ISA adapter uses bus master DMA */
4130 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4131 enable_dma(info->dma_level);
4132 }
4133
4134 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4135 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4136 __FILE__,__LINE__,info->device_name, info->dma_level );
4137 goto errout;
4138 }
4139
4140 return 0;
4141 errout:
4142 mgsl_release_resources(info);
4143 return -ENODEV;
4144
4145 } /* end of mgsl_claim_resources() */
4146
4147 static void mgsl_release_resources(struct mgsl_struct *info)
4148 {
4149 if ( debug_level >= DEBUG_LEVEL_INFO )
4150 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4151 __FILE__,__LINE__,info->device_name );
4152
4153 if ( info->irq_requested ) {
4154 free_irq(info->irq_level, info);
4155 info->irq_requested = false;
4156 }
4157 if ( info->dma_requested ) {
4158 disable_dma(info->dma_level);
4159 free_dma(info->dma_level);
4160 info->dma_requested = false;
4161 }
4162 mgsl_free_dma_buffers(info);
4163 mgsl_free_intermediate_rxbuffer_memory(info);
4164 mgsl_free_intermediate_txbuffer_memory(info);
4165
4166 if ( info->io_addr_requested ) {
4167 release_region(info->io_base,info->io_addr_size);
4168 info->io_addr_requested = false;
4169 }
4170 if ( info->shared_mem_requested ) {
4171 release_mem_region(info->phys_memory_base,0x40000);
4172 info->shared_mem_requested = false;
4173 }
4174 if ( info->lcr_mem_requested ) {
4175 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4176 info->lcr_mem_requested = false;
4177 }
4178 if (info->memory_base){
4179 iounmap(info->memory_base);
4180 info->memory_base = NULL;
4181 }
4182 if (info->lcr_base){
4183 iounmap(info->lcr_base - info->lcr_offset);
4184 info->lcr_base = NULL;
4185 }
4186
4187 if ( debug_level >= DEBUG_LEVEL_INFO )
4188 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4189 __FILE__,__LINE__,info->device_name );
4190
4191 } /* end of mgsl_release_resources() */
4192
4193 /* mgsl_add_device()
4194 *
4195 * Add the specified device instance data structure to the
4196 * global linked list of devices and increment the device count.
4197 *
4198 * Arguments: info pointer to device instance data
4199 * Return Value: None
4200 */
4201 static void mgsl_add_device( struct mgsl_struct *info )
4202 {
4203 info->next_device = NULL;
4204 info->line = mgsl_device_count;
4205 sprintf(info->device_name,"ttySL%d",info->line);
4206
4207 if (info->line < MAX_TOTAL_DEVICES) {
4208 if (maxframe[info->line])
4209 info->max_frame_size = maxframe[info->line];
4210
4211 if (txdmabufs[info->line]) {
4212 info->num_tx_dma_buffers = txdmabufs[info->line];
4213 if (info->num_tx_dma_buffers < 1)
4214 info->num_tx_dma_buffers = 1;
4215 }
4216
4217 if (txholdbufs[info->line]) {
4218 info->num_tx_holding_buffers = txholdbufs[info->line];
4219 if (info->num_tx_holding_buffers < 1)
4220 info->num_tx_holding_buffers = 1;
4221 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4222 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4223 }
4224 }
4225
4226 mgsl_device_count++;
4227
4228 if ( !mgsl_device_list )
4229 mgsl_device_list = info;
4230 else {
4231 struct mgsl_struct *current_dev = mgsl_device_list;
4232 while( current_dev->next_device )
4233 current_dev = current_dev->next_device;
4234 current_dev->next_device = info;
4235 }
4236
4237 if ( info->max_frame_size < 4096 )
4238 info->max_frame_size = 4096;
4239 else if ( info->max_frame_size > 65535 )
4240 info->max_frame_size = 65535;
4241
4242 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4243 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4244 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4245 info->phys_memory_base, info->phys_lcr_base,
4246 info->max_frame_size );
4247 } else {
4248 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4249 info->device_name, info->io_base, info->irq_level, info->dma_level,
4250 info->max_frame_size );
4251 }
4252
4253 #if SYNCLINK_GENERIC_HDLC
4254 hdlcdev_init(info);
4255 #endif
4256
4257 } /* end of mgsl_add_device() */
4258
4259 static const struct tty_port_operations mgsl_port_ops = {
4260 .carrier_raised = carrier_raised,
4261 .raise_dtr_rts = raise_dtr_rts,
4262 };
4263
4264
4265 /* mgsl_allocate_device()
4266 *
4267 * Allocate and initialize a device instance structure
4268 *
4269 * Arguments: none
4270 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4271 */
4272 static struct mgsl_struct* mgsl_allocate_device(void)
4273 {
4274 struct mgsl_struct *info;
4275
4276 info = kzalloc(sizeof(struct mgsl_struct),
4277 GFP_KERNEL);
4278
4279 if (!info) {
4280 printk("Error can't allocate device instance data\n");
4281 } else {
4282 tty_port_init(&info->port);
4283 info->port.ops = &mgsl_port_ops;
4284 info->magic = MGSL_MAGIC;
4285 INIT_WORK(&info->task, mgsl_bh_handler);
4286 info->max_frame_size = 4096;
4287 info->port.close_delay = 5*HZ/10;
4288 info->port.closing_wait = 30*HZ;
4289 init_waitqueue_head(&info->status_event_wait_q);
4290 init_waitqueue_head(&info->event_wait_q);
4291 spin_lock_init(&info->irq_spinlock);
4292 spin_lock_init(&info->netlock);
4293 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4294 info->idle_mode = HDLC_TXIDLE_FLAGS;
4295 info->num_tx_dma_buffers = 1;
4296 info->num_tx_holding_buffers = 0;
4297 }
4298
4299 return info;
4300
4301 } /* end of mgsl_allocate_device()*/
4302
4303 static const struct tty_operations mgsl_ops = {
4304 .open = mgsl_open,
4305 .close = mgsl_close,
4306 .write = mgsl_write,
4307 .put_char = mgsl_put_char,
4308 .flush_chars = mgsl_flush_chars,
4309 .write_room = mgsl_write_room,
4310 .chars_in_buffer = mgsl_chars_in_buffer,
4311 .flush_buffer = mgsl_flush_buffer,
4312 .ioctl = mgsl_ioctl,
4313 .throttle = mgsl_throttle,
4314 .unthrottle = mgsl_unthrottle,
4315 .send_xchar = mgsl_send_xchar,
4316 .break_ctl = mgsl_break,
4317 .wait_until_sent = mgsl_wait_until_sent,
4318 .set_termios = mgsl_set_termios,
4319 .stop = mgsl_stop,
4320 .start = mgsl_start,
4321 .hangup = mgsl_hangup,
4322 .tiocmget = tiocmget,
4323 .tiocmset = tiocmset,
4324 .proc_fops = &mgsl_proc_fops,
4325 };
4326
4327 /*
4328 * perform tty device initialization
4329 */
4330 static int mgsl_init_tty(void)
4331 {
4332 int rc;
4333
4334 serial_driver = alloc_tty_driver(128);
4335 if (!serial_driver)
4336 return -ENOMEM;
4337
4338 serial_driver->owner = THIS_MODULE;
4339 serial_driver->driver_name = "synclink";
4340 serial_driver->name = "ttySL";
4341 serial_driver->major = ttymajor;
4342 serial_driver->minor_start = 64;
4343 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4344 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4345 serial_driver->init_termios = tty_std_termios;
4346 serial_driver->init_termios.c_cflag =
4347 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4348 serial_driver->init_termios.c_ispeed = 9600;
4349 serial_driver->init_termios.c_ospeed = 9600;
4350 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4351 tty_set_operations(serial_driver, &mgsl_ops);
4352 if ((rc = tty_register_driver(serial_driver)) < 0) {
4353 printk("%s(%d):Couldn't register serial driver\n",
4354 __FILE__,__LINE__);
4355 put_tty_driver(serial_driver);
4356 serial_driver = NULL;
4357 return rc;
4358 }
4359
4360 printk("%s %s, tty major#%d\n",
4361 driver_name, driver_version,
4362 serial_driver->major);
4363 return 0;
4364 }
4365
4366 /* enumerate user specified ISA adapters
4367 */
4368 static void mgsl_enum_isa_devices(void)
4369 {
4370 struct mgsl_struct *info;
4371 int i;
4372
4373 /* Check for user specified ISA devices */
4374
4375 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4376 if ( debug_level >= DEBUG_LEVEL_INFO )
4377 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4378 io[i], irq[i], dma[i] );
4379
4380 info = mgsl_allocate_device();
4381 if ( !info ) {
4382 /* error allocating device instance data */
4383 if ( debug_level >= DEBUG_LEVEL_ERROR )
4384 printk( "can't allocate device instance data.\n");
4385 continue;
4386 }
4387
4388 /* Copy user configuration info to device instance data */
4389 info->io_base = (unsigned int)io[i];
4390 info->irq_level = (unsigned int)irq[i];
4391 info->irq_level = irq_canonicalize(info->irq_level);
4392 info->dma_level = (unsigned int)dma[i];
4393 info->bus_type = MGSL_BUS_TYPE_ISA;
4394 info->io_addr_size = 16;
4395 info->irq_flags = 0;
4396
4397 mgsl_add_device( info );
4398 }
4399 }
4400
4401 static void synclink_cleanup(void)
4402 {
4403 int rc;
4404 struct mgsl_struct *info;
4405 struct mgsl_struct *tmp;
4406
4407 printk("Unloading %s: %s\n", driver_name, driver_version);
4408
4409 if (serial_driver) {
4410 if ((rc = tty_unregister_driver(serial_driver)))
4411 printk("%s(%d) failed to unregister tty driver err=%d\n",
4412 __FILE__,__LINE__,rc);
4413 put_tty_driver(serial_driver);
4414 }
4415
4416 info = mgsl_device_list;
4417 while(info) {
4418 #if SYNCLINK_GENERIC_HDLC
4419 hdlcdev_exit(info);
4420 #endif
4421 mgsl_release_resources(info);
4422 tmp = info;
4423 info = info->next_device;
4424 kfree(tmp);
4425 }
4426
4427 if (pci_registered)
4428 pci_unregister_driver(&synclink_pci_driver);
4429 }
4430
4431 static int __init synclink_init(void)
4432 {
4433 int rc;
4434
4435 if (break_on_load) {
4436 mgsl_get_text_ptr();
4437 BREAKPOINT();
4438 }
4439
4440 printk("%s %s\n", driver_name, driver_version);
4441
4442 mgsl_enum_isa_devices();
4443 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4444 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4445 else
4446 pci_registered = true;
4447
4448 if ((rc = mgsl_init_tty()) < 0)
4449 goto error;
4450
4451 return 0;
4452
4453 error:
4454 synclink_cleanup();
4455 return rc;
4456 }
4457
4458 static void __exit synclink_exit(void)
4459 {
4460 synclink_cleanup();
4461 }
4462
4463 module_init(synclink_init);
4464 module_exit(synclink_exit);
4465
4466 /*
4467 * usc_RTCmd()
4468 *
4469 * Issue a USC Receive/Transmit command to the
4470 * Channel Command/Address Register (CCAR).
4471 *
4472 * Notes:
4473 *
4474 * The command is encoded in the most significant 5 bits <15..11>
4475 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4476 * and Bits <6..0> must be written as zeros.
4477 *
4478 * Arguments:
4479 *
4480 * info pointer to device information structure
4481 * Cmd command mask (use symbolic macros)
4482 *
4483 * Return Value:
4484 *
4485 * None
4486 */
4487 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4488 {
4489 /* output command to CCAR in bits <15..11> */
4490 /* preserve bits <10..7>, bits <6..0> must be zero */
4491
4492 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4493
4494 /* Read to flush write to CCAR */
4495 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4496 inw( info->io_base + CCAR );
4497
4498 } /* end of usc_RTCmd() */
4499
4500 /*
4501 * usc_DmaCmd()
4502 *
4503 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4504 *
4505 * Arguments:
4506 *
4507 * info pointer to device information structure
4508 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4509 *
4510 * Return Value:
4511 *
4512 * None
4513 */
4514 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4515 {
4516 /* write command mask to DCAR */
4517 outw( Cmd + info->mbre_bit, info->io_base );
4518
4519 /* Read to flush write to DCAR */
4520 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4521 inw( info->io_base );
4522
4523 } /* end of usc_DmaCmd() */
4524
4525 /*
4526 * usc_OutDmaReg()
4527 *
4528 * Write a 16-bit value to a USC DMA register
4529 *
4530 * Arguments:
4531 *
4532 * info pointer to device info structure
4533 * RegAddr register address (number) for write
4534 * RegValue 16-bit value to write to register
4535 *
4536 * Return Value:
4537 *
4538 * None
4539 *
4540 */
4541 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4542 {
4543 /* Note: The DCAR is located at the adapter base address */
4544 /* Note: must preserve state of BIT8 in DCAR */
4545
4546 outw( RegAddr + info->mbre_bit, info->io_base );
4547 outw( RegValue, info->io_base );
4548
4549 /* Read to flush write to DCAR */
4550 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4551 inw( info->io_base );
4552
4553 } /* end of usc_OutDmaReg() */
4554
4555 /*
4556 * usc_InDmaReg()
4557 *
4558 * Read a 16-bit value from a DMA register
4559 *
4560 * Arguments:
4561 *
4562 * info pointer to device info structure
4563 * RegAddr register address (number) to read from
4564 *
4565 * Return Value:
4566 *
4567 * The 16-bit value read from register
4568 *
4569 */
4570 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4571 {
4572 /* Note: The DCAR is located at the adapter base address */
4573 /* Note: must preserve state of BIT8 in DCAR */
4574
4575 outw( RegAddr + info->mbre_bit, info->io_base );
4576 return inw( info->io_base );
4577
4578 } /* end of usc_InDmaReg() */
4579
4580 /*
4581 *
4582 * usc_OutReg()
4583 *
4584 * Write a 16-bit value to a USC serial channel register
4585 *
4586 * Arguments:
4587 *
4588 * info pointer to device info structure
4589 * RegAddr register address (number) to write to
4590 * RegValue 16-bit value to write to register
4591 *
4592 * Return Value:
4593 *
4594 * None
4595 *
4596 */
4597 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4598 {
4599 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4600 outw( RegValue, info->io_base + CCAR );
4601
4602 /* Read to flush write to CCAR */
4603 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4604 inw( info->io_base + CCAR );
4605
4606 } /* end of usc_OutReg() */
4607
4608 /*
4609 * usc_InReg()
4610 *
4611 * Reads a 16-bit value from a USC serial channel register
4612 *
4613 * Arguments:
4614 *
4615 * info pointer to device extension
4616 * RegAddr register address (number) to read from
4617 *
4618 * Return Value:
4619 *
4620 * 16-bit value read from register
4621 */
4622 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4623 {
4624 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4625 return inw( info->io_base + CCAR );
4626
4627 } /* end of usc_InReg() */
4628
4629 /* usc_set_sdlc_mode()
4630 *
4631 * Set up the adapter for SDLC DMA communications.
4632 *
4633 * Arguments: info pointer to device instance data
4634 * Return Value: NONE
4635 */
4636 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4637 {
4638 u16 RegValue;
4639 bool PreSL1660;
4640
4641 /*
4642 * determine if the IUSC on the adapter is pre-SL1660. If
4643 * not, take advantage of the UnderWait feature of more
4644 * modern chips. If an underrun occurs and this bit is set,
4645 * the transmitter will idle the programmed idle pattern
4646 * until the driver has time to service the underrun. Otherwise,
4647 * the dma controller may get the cycles previously requested
4648 * and begin transmitting queued tx data.
4649 */
4650 usc_OutReg(info,TMCR,0x1f);
4651 RegValue=usc_InReg(info,TMDR);
4652 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4653
4654 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4655 {
4656 /*
4657 ** Channel Mode Register (CMR)
4658 **
4659 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4660 ** <13> 0 0 = Transmit Disabled (initially)
4661 ** <12> 0 1 = Consecutive Idles share common 0
4662 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4663 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4664 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4665 **
4666 ** 1000 1110 0000 0110 = 0x8e06
4667 */
4668 RegValue = 0x8e06;
4669
4670 /*--------------------------------------------------
4671 * ignore user options for UnderRun Actions and
4672 * preambles
4673 *--------------------------------------------------*/
4674 }
4675 else
4676 {
4677 /* Channel mode Register (CMR)
4678 *
4679 * <15..14> 00 Tx Sub modes, Underrun Action
4680 * <13> 0 1 = Send Preamble before opening flag
4681 * <12> 0 1 = Consecutive Idles share common 0
4682 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4683 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4684 * <3..0> 0110 Receiver mode = HDLC/SDLC
4685 *
4686 * 0000 0110 0000 0110 = 0x0606
4687 */
4688 if (info->params.mode == MGSL_MODE_RAW) {
4689 RegValue = 0x0001; /* Set Receive mode = external sync */
4690
4691 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4692 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4693
4694 /*
4695 * TxSubMode:
4696 * CMR <15> 0 Don't send CRC on Tx Underrun
4697 * CMR <14> x undefined
4698 * CMR <13> 0 Send preamble before openning sync
4699 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4700 *
4701 * TxMode:
4702 * CMR <11-8) 0100 MonoSync
4703 *
4704 * 0x00 0100 xxxx xxxx 04xx
4705 */
4706 RegValue |= 0x0400;
4707 }
4708 else {
4709
4710 RegValue = 0x0606;
4711
4712 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4713 RegValue |= BIT14;
4714 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4715 RegValue |= BIT15;
4716 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4717 RegValue |= BIT15 + BIT14;
4718 }
4719
4720 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4721 RegValue |= BIT13;
4722 }
4723
4724 if ( info->params.mode == MGSL_MODE_HDLC &&
4725 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4726 RegValue |= BIT12;
4727
4728 if ( info->params.addr_filter != 0xff )
4729 {
4730 /* set up receive address filtering */
4731 usc_OutReg( info, RSR, info->params.addr_filter );
4732 RegValue |= BIT4;
4733 }
4734
4735 usc_OutReg( info, CMR, RegValue );
4736 info->cmr_value = RegValue;
4737
4738 /* Receiver mode Register (RMR)
4739 *
4740 * <15..13> 000 encoding
4741 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4742 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4743 * <9> 0 1 = Include Receive chars in CRC
4744 * <8> 1 1 = Use Abort/PE bit as abort indicator
4745 * <7..6> 00 Even parity
4746 * <5> 0 parity disabled
4747 * <4..2> 000 Receive Char Length = 8 bits
4748 * <1..0> 00 Disable Receiver
4749 *
4750 * 0000 0101 0000 0000 = 0x0500
4751 */
4752
4753 RegValue = 0x0500;
4754
4755 switch ( info->params.encoding ) {
4756 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4757 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4758 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4759 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4760 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4761 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4762 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4763 }
4764
4765 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4766 RegValue |= BIT9;
4767 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4768 RegValue |= ( BIT12 | BIT10 | BIT9 );
4769
4770 usc_OutReg( info, RMR, RegValue );
4771
4772 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4773 /* When an opening flag of an SDLC frame is recognized the */
4774 /* Receive Character count (RCC) is loaded with the value in */
4775 /* RCLR. The RCC is decremented for each received byte. The */
4776 /* value of RCC is stored after the closing flag of the frame */
4777 /* allowing the frame size to be computed. */
4778
4779 usc_OutReg( info, RCLR, RCLRVALUE );
4780
4781 usc_RCmd( info, RCmd_SelectRicrdma_level );
4782
4783 /* Receive Interrupt Control Register (RICR)
4784 *
4785 * <15..8> ? RxFIFO DMA Request Level
4786 * <7> 0 Exited Hunt IA (Interrupt Arm)
4787 * <6> 0 Idle Received IA
4788 * <5> 0 Break/Abort IA
4789 * <4> 0 Rx Bound IA
4790 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4791 * <2> 0 Abort/PE IA
4792 * <1> 1 Rx Overrun IA
4793 * <0> 0 Select TC0 value for readback
4794 *
4795 * 0000 0000 0000 1000 = 0x000a
4796 */
4797
4798 /* Carry over the Exit Hunt and Idle Received bits */
4799 /* in case they have been armed by usc_ArmEvents. */
4800
4801 RegValue = usc_InReg( info, RICR ) & 0xc0;
4802
4803 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4804 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4805 else
4806 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4807
4808 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4809
4810 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4811 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4812
4813 /* Transmit mode Register (TMR)
4814 *
4815 * <15..13> 000 encoding
4816 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4817 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4818 * <9> 0 1 = Tx CRC Enabled
4819 * <8> 0 1 = Append CRC to end of transmit frame
4820 * <7..6> 00 Transmit parity Even
4821 * <5> 0 Transmit parity Disabled
4822 * <4..2> 000 Tx Char Length = 8 bits
4823 * <1..0> 00 Disable Transmitter
4824 *
4825 * 0000 0100 0000 0000 = 0x0400
4826 */
4827
4828 RegValue = 0x0400;
4829
4830 switch ( info->params.encoding ) {
4831 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4832 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4833 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4834 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4835 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4836 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4837 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4838 }
4839
4840 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4841 RegValue |= BIT9 + BIT8;
4842 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4843 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4844
4845 usc_OutReg( info, TMR, RegValue );
4846
4847 usc_set_txidle( info );
4848
4849
4850 usc_TCmd( info, TCmd_SelectTicrdma_level );
4851
4852 /* Transmit Interrupt Control Register (TICR)
4853 *
4854 * <15..8> ? Transmit FIFO DMA Level
4855 * <7> 0 Present IA (Interrupt Arm)
4856 * <6> 0 Idle Sent IA
4857 * <5> 1 Abort Sent IA
4858 * <4> 1 EOF/EOM Sent IA
4859 * <3> 0 CRC Sent IA
4860 * <2> 1 1 = Wait for SW Trigger to Start Frame
4861 * <1> 1 Tx Underrun IA
4862 * <0> 0 TC0 constant on read back
4863 *
4864 * 0000 0000 0011 0110 = 0x0036
4865 */
4866
4867 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4868 usc_OutReg( info, TICR, 0x0736 );
4869 else
4870 usc_OutReg( info, TICR, 0x1436 );
4871
4872 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4873 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4874
4875 /*
4876 ** Transmit Command/Status Register (TCSR)
4877 **
4878 ** <15..12> 0000 TCmd
4879 ** <11> 0/1 UnderWait
4880 ** <10..08> 000 TxIdle
4881 ** <7> x PreSent
4882 ** <6> x IdleSent
4883 ** <5> x AbortSent
4884 ** <4> x EOF/EOM Sent
4885 ** <3> x CRC Sent
4886 ** <2> x All Sent
4887 ** <1> x TxUnder
4888 ** <0> x TxEmpty
4889 **
4890 ** 0000 0000 0000 0000 = 0x0000
4891 */
4892 info->tcsr_value = 0;
4893
4894 if ( !PreSL1660 )
4895 info->tcsr_value |= TCSR_UNDERWAIT;
4896
4897 usc_OutReg( info, TCSR, info->tcsr_value );
4898
4899 /* Clock mode Control Register (CMCR)
4900 *
4901 * <15..14> 00 counter 1 Source = Disabled
4902 * <13..12> 00 counter 0 Source = Disabled
4903 * <11..10> 11 BRG1 Input is TxC Pin
4904 * <9..8> 11 BRG0 Input is TxC Pin
4905 * <7..6> 01 DPLL Input is BRG1 Output
4906 * <5..3> XXX TxCLK comes from Port 0
4907 * <2..0> XXX RxCLK comes from Port 1
4908 *
4909 * 0000 1111 0111 0111 = 0x0f77
4910 */
4911
4912 RegValue = 0x0f40;
4913
4914 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4915 RegValue |= 0x0003; /* RxCLK from DPLL */
4916 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4917 RegValue |= 0x0004; /* RxCLK from BRG0 */
4918 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4919 RegValue |= 0x0006; /* RxCLK from TXC Input */
4920 else
4921 RegValue |= 0x0007; /* RxCLK from Port1 */
4922
4923 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4924 RegValue |= 0x0018; /* TxCLK from DPLL */
4925 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4926 RegValue |= 0x0020; /* TxCLK from BRG0 */
4927 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4928 RegValue |= 0x0038; /* RxCLK from TXC Input */
4929 else
4930 RegValue |= 0x0030; /* TxCLK from Port0 */
4931
4932 usc_OutReg( info, CMCR, RegValue );
4933
4934
4935 /* Hardware Configuration Register (HCR)
4936 *
4937 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4938 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4939 * <12> 0 CVOK:0=report code violation in biphase
4940 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4941 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4942 * <7..6> 00 reserved
4943 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4944 * <4> X BRG1 Enable
4945 * <3..2> 00 reserved
4946 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4947 * <0> 0 BRG0 Enable
4948 */
4949
4950 RegValue = 0x0000;
4951
4952 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4953 u32 XtalSpeed;
4954 u32 DpllDivisor;
4955 u16 Tc;
4956
4957 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4958 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4959
4960 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4961 XtalSpeed = 11059200;
4962 else
4963 XtalSpeed = 14745600;
4964
4965 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4966 DpllDivisor = 16;
4967 RegValue |= BIT10;
4968 }
4969 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4970 DpllDivisor = 8;
4971 RegValue |= BIT11;
4972 }
4973 else
4974 DpllDivisor = 32;
4975
4976 /* Tc = (Xtal/Speed) - 1 */
4977 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4978 /* then rounding up gives a more precise time constant. Instead */
4979 /* of rounding up and then subtracting 1 we just don't subtract */
4980 /* the one in this case. */
4981
4982 /*--------------------------------------------------
4983 * ejz: for DPLL mode, application should use the
4984 * same clock speed as the partner system, even
4985 * though clocking is derived from the input RxData.
4986 * In case the user uses a 0 for the clock speed,
4987 * default to 0xffffffff and don't try to divide by
4988 * zero
4989 *--------------------------------------------------*/
4990 if ( info->params.clock_speed )
4991 {
4992 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4993 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4994 / info->params.clock_speed) )
4995 Tc--;
4996 }
4997 else
4998 Tc = -1;
4999
5000
5001 /* Write 16-bit Time Constant for BRG1 */
5002 usc_OutReg( info, TC1R, Tc );
5003
5004 RegValue |= BIT4; /* enable BRG1 */
5005
5006 switch ( info->params.encoding ) {
5007 case HDLC_ENCODING_NRZ:
5008 case HDLC_ENCODING_NRZB:
5009 case HDLC_ENCODING_NRZI_MARK:
5010 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5011 case HDLC_ENCODING_BIPHASE_MARK:
5012 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5013 case HDLC_ENCODING_BIPHASE_LEVEL:
5014 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5015 }
5016 }
5017
5018 usc_OutReg( info, HCR, RegValue );
5019
5020
5021 /* Channel Control/status Register (CCSR)
5022 *
5023 * <15> X RCC FIFO Overflow status (RO)
5024 * <14> X RCC FIFO Not Empty status (RO)
5025 * <13> 0 1 = Clear RCC FIFO (WO)
5026 * <12> X DPLL Sync (RW)
5027 * <11> X DPLL 2 Missed Clocks status (RO)
5028 * <10> X DPLL 1 Missed Clock status (RO)
5029 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5030 * <7> X SDLC Loop On status (RO)
5031 * <6> X SDLC Loop Send status (RO)
5032 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5033 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5034 * <1..0> 00 reserved
5035 *
5036 * 0000 0000 0010 0000 = 0x0020
5037 */
5038
5039 usc_OutReg( info, CCSR, 0x1020 );
5040
5041
5042 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5043 usc_OutReg( info, SICR,
5044 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5045 }
5046
5047
5048 /* enable Master Interrupt Enable bit (MIE) */
5049 usc_EnableMasterIrqBit( info );
5050
5051 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5052 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5053
5054 /* arm RCC underflow interrupt */
5055 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5056 usc_EnableInterrupts(info, MISC);
5057
5058 info->mbre_bit = 0;
5059 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5060 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5061 info->mbre_bit = BIT8;
5062 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5063
5064 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5065 /* Enable DMAEN (Port 7, Bit 14) */
5066 /* This connects the DMA request signal to the ISA bus */
5067 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5068 }
5069
5070 /* DMA Control Register (DCR)
5071 *
5072 * <15..14> 10 Priority mode = Alternating Tx/Rx
5073 * 01 Rx has priority
5074 * 00 Tx has priority
5075 *
5076 * <13> 1 Enable Priority Preempt per DCR<15..14>
5077 * (WARNING DCR<11..10> must be 00 when this is 1)
5078 * 0 Choose activate channel per DCR<11..10>
5079 *
5080 * <12> 0 Little Endian for Array/List
5081 * <11..10> 00 Both Channels can use each bus grant
5082 * <9..6> 0000 reserved
5083 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5084 * <4> 0 1 = drive D/C and S/D pins
5085 * <3> 1 1 = Add one wait state to all DMA cycles.
5086 * <2> 0 1 = Strobe /UAS on every transfer.
5087 * <1..0> 11 Addr incrementing only affects LS24 bits
5088 *
5089 * 0110 0000 0000 1011 = 0x600b
5090 */
5091
5092 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5093 /* PCI adapter does not need DMA wait state */
5094 usc_OutDmaReg( info, DCR, 0xa00b );
5095 }
5096 else
5097 usc_OutDmaReg( info, DCR, 0x800b );
5098
5099
5100 /* Receive DMA mode Register (RDMR)
5101 *
5102 * <15..14> 11 DMA mode = Linked List Buffer mode
5103 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5104 * <12> 1 Clear count of List Entry after fetching
5105 * <11..10> 00 Address mode = Increment
5106 * <9> 1 Terminate Buffer on RxBound
5107 * <8> 0 Bus Width = 16bits
5108 * <7..0> ? status Bits (write as 0s)
5109 *
5110 * 1111 0010 0000 0000 = 0xf200
5111 */
5112
5113 usc_OutDmaReg( info, RDMR, 0xf200 );
5114
5115
5116 /* Transmit DMA mode Register (TDMR)
5117 *
5118 * <15..14> 11 DMA mode = Linked List Buffer mode
5119 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5120 * <12> 1 Clear count of List Entry after fetching
5121 * <11..10> 00 Address mode = Increment
5122 * <9> 1 Terminate Buffer on end of frame
5123 * <8> 0 Bus Width = 16bits
5124 * <7..0> ? status Bits (Read Only so write as 0)
5125 *
5126 * 1111 0010 0000 0000 = 0xf200
5127 */
5128
5129 usc_OutDmaReg( info, TDMR, 0xf200 );
5130
5131
5132 /* DMA Interrupt Control Register (DICR)
5133 *
5134 * <15> 1 DMA Interrupt Enable
5135 * <14> 0 1 = Disable IEO from USC
5136 * <13> 0 1 = Don't provide vector during IntAck
5137 * <12> 1 1 = Include status in Vector
5138 * <10..2> 0 reserved, Must be 0s
5139 * <1> 0 1 = Rx DMA Interrupt Enabled
5140 * <0> 0 1 = Tx DMA Interrupt Enabled
5141 *
5142 * 1001 0000 0000 0000 = 0x9000
5143 */
5144
5145 usc_OutDmaReg( info, DICR, 0x9000 );
5146
5147 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5148 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5149 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5150
5151 /* Channel Control Register (CCR)
5152 *
5153 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5154 * <13> 0 Trigger Tx on SW Command Disabled
5155 * <12> 0 Flag Preamble Disabled
5156 * <11..10> 00 Preamble Length
5157 * <9..8> 00 Preamble Pattern
5158 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5159 * <5> 0 Trigger Rx on SW Command Disabled
5160 * <4..0> 0 reserved
5161 *
5162 * 1000 0000 1000 0000 = 0x8080
5163 */
5164
5165 RegValue = 0x8080;
5166
5167 switch ( info->params.preamble_length ) {
5168 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5169 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5170 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5171 }
5172
5173 switch ( info->params.preamble ) {
5174 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5175 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5176 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5177 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5178 }
5179
5180 usc_OutReg( info, CCR, RegValue );
5181
5182
5183 /*
5184 * Burst/Dwell Control Register
5185 *
5186 * <15..8> 0x20 Maximum number of transfers per bus grant
5187 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5188 */
5189
5190 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5191 /* don't limit bus occupancy on PCI adapter */
5192 usc_OutDmaReg( info, BDCR, 0x0000 );
5193 }
5194 else
5195 usc_OutDmaReg( info, BDCR, 0x2000 );
5196
5197 usc_stop_transmitter(info);
5198 usc_stop_receiver(info);
5199
5200 } /* end of usc_set_sdlc_mode() */
5201
5202 /* usc_enable_loopback()
5203 *
5204 * Set the 16C32 for internal loopback mode.
5205 * The TxCLK and RxCLK signals are generated from the BRG0 and
5206 * the TxD is looped back to the RxD internally.
5207 *
5208 * Arguments: info pointer to device instance data
5209 * enable 1 = enable loopback, 0 = disable
5210 * Return Value: None
5211 */
5212 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5213 {
5214 if (enable) {
5215 /* blank external TXD output */
5216 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5217
5218 /* Clock mode Control Register (CMCR)
5219 *
5220 * <15..14> 00 counter 1 Disabled
5221 * <13..12> 00 counter 0 Disabled
5222 * <11..10> 11 BRG1 Input is TxC Pin
5223 * <9..8> 11 BRG0 Input is TxC Pin
5224 * <7..6> 01 DPLL Input is BRG1 Output
5225 * <5..3> 100 TxCLK comes from BRG0
5226 * <2..0> 100 RxCLK comes from BRG0
5227 *
5228 * 0000 1111 0110 0100 = 0x0f64
5229 */
5230
5231 usc_OutReg( info, CMCR, 0x0f64 );
5232
5233 /* Write 16-bit Time Constant for BRG0 */
5234 /* use clock speed if available, otherwise use 8 for diagnostics */
5235 if (info->params.clock_speed) {
5236 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5237 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5238 else
5239 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5240 } else
5241 usc_OutReg(info, TC0R, (u16)8);
5242
5243 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5244 mode = Continuous Set Bit 0 to enable BRG0. */
5245 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5246
5247 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5248 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5249
5250 /* set Internal Data loopback mode */
5251 info->loopback_bits = 0x300;
5252 outw( 0x0300, info->io_base + CCAR );
5253 } else {
5254 /* enable external TXD output */
5255 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5256
5257 /* clear Internal Data loopback mode */
5258 info->loopback_bits = 0;
5259 outw( 0,info->io_base + CCAR );
5260 }
5261
5262 } /* end of usc_enable_loopback() */
5263
5264 /* usc_enable_aux_clock()
5265 *
5266 * Enabled the AUX clock output at the specified frequency.
5267 *
5268 * Arguments:
5269 *
5270 * info pointer to device extension
5271 * data_rate data rate of clock in bits per second
5272 * A data rate of 0 disables the AUX clock.
5273 *
5274 * Return Value: None
5275 */
5276 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5277 {
5278 u32 XtalSpeed;
5279 u16 Tc;
5280
5281 if ( data_rate ) {
5282 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5283 XtalSpeed = 11059200;
5284 else
5285 XtalSpeed = 14745600;
5286
5287
5288 /* Tc = (Xtal/Speed) - 1 */
5289 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5290 /* then rounding up gives a more precise time constant. Instead */
5291 /* of rounding up and then subtracting 1 we just don't subtract */
5292 /* the one in this case. */
5293
5294
5295 Tc = (u16)(XtalSpeed/data_rate);
5296 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5297 Tc--;
5298
5299 /* Write 16-bit Time Constant for BRG0 */
5300 usc_OutReg( info, TC0R, Tc );
5301
5302 /*
5303 * Hardware Configuration Register (HCR)
5304 * Clear Bit 1, BRG0 mode = Continuous
5305 * Set Bit 0 to enable BRG0.
5306 */
5307
5308 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5309
5310 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5311 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5312 } else {
5313 /* data rate == 0 so turn off BRG0 */
5314 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5315 }
5316
5317 } /* end of usc_enable_aux_clock() */
5318
5319 /*
5320 *
5321 * usc_process_rxoverrun_sync()
5322 *
5323 * This function processes a receive overrun by resetting the
5324 * receive DMA buffers and issuing a Purge Rx FIFO command
5325 * to allow the receiver to continue receiving.
5326 *
5327 * Arguments:
5328 *
5329 * info pointer to device extension
5330 *
5331 * Return Value: None
5332 */
5333 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5334 {
5335 int start_index;
5336 int end_index;
5337 int frame_start_index;
5338 bool start_of_frame_found = false;
5339 bool end_of_frame_found = false;
5340 bool reprogram_dma = false;
5341
5342 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5343 u32 phys_addr;
5344
5345 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5346 usc_RCmd( info, RCmd_EnterHuntmode );
5347 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5348
5349 /* CurrentRxBuffer points to the 1st buffer of the next */
5350 /* possibly available receive frame. */
5351
5352 frame_start_index = start_index = end_index = info->current_rx_buffer;
5353
5354 /* Search for an unfinished string of buffers. This means */
5355 /* that a receive frame started (at least one buffer with */
5356 /* count set to zero) but there is no terminiting buffer */
5357 /* (status set to non-zero). */
5358
5359 while( !buffer_list[end_index].count )
5360 {
5361 /* Count field has been reset to zero by 16C32. */
5362 /* This buffer is currently in use. */
5363
5364 if ( !start_of_frame_found )
5365 {
5366 start_of_frame_found = true;
5367 frame_start_index = end_index;
5368 end_of_frame_found = false;
5369 }
5370
5371 if ( buffer_list[end_index].status )
5372 {
5373 /* Status field has been set by 16C32. */
5374 /* This is the last buffer of a received frame. */
5375
5376 /* We want to leave the buffers for this frame intact. */
5377 /* Move on to next possible frame. */
5378
5379 start_of_frame_found = false;
5380 end_of_frame_found = true;
5381 }
5382
5383 /* advance to next buffer entry in linked list */
5384 end_index++;
5385 if ( end_index == info->rx_buffer_count )
5386 end_index = 0;
5387
5388 if ( start_index == end_index )
5389 {
5390 /* The entire list has been searched with all Counts == 0 and */
5391 /* all Status == 0. The receive buffers are */
5392 /* completely screwed, reset all receive buffers! */
5393 mgsl_reset_rx_dma_buffers( info );
5394 frame_start_index = 0;
5395 start_of_frame_found = false;
5396 reprogram_dma = true;
5397 break;
5398 }
5399 }
5400
5401 if ( start_of_frame_found && !end_of_frame_found )
5402 {
5403 /* There is an unfinished string of receive DMA buffers */
5404 /* as a result of the receiver overrun. */
5405
5406 /* Reset the buffers for the unfinished frame */
5407 /* and reprogram the receive DMA controller to start */
5408 /* at the 1st buffer of unfinished frame. */
5409
5410 start_index = frame_start_index;
5411
5412 do
5413 {
5414 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5415
5416 /* Adjust index for wrap around. */
5417 if ( start_index == info->rx_buffer_count )
5418 start_index = 0;
5419
5420 } while( start_index != end_index );
5421
5422 reprogram_dma = true;
5423 }
5424
5425 if ( reprogram_dma )
5426 {
5427 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5428 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5429 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5430
5431 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5432
5433 /* This empties the receive FIFO and loads the RCC with RCLR */
5434 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5435
5436 /* program 16C32 with physical address of 1st DMA buffer entry */
5437 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5438 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5439 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5440
5441 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5442 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5443 usc_EnableInterrupts( info, RECEIVE_STATUS );
5444
5445 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5446 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5447
5448 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5449 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5450 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5451 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5452 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5453 else
5454 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5455 }
5456 else
5457 {
5458 /* This empties the receive FIFO and loads the RCC with RCLR */
5459 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5460 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5461 }
5462
5463 } /* end of usc_process_rxoverrun_sync() */
5464
5465 /* usc_stop_receiver()
5466 *
5467 * Disable USC receiver
5468 *
5469 * Arguments: info pointer to device instance data
5470 * Return Value: None
5471 */
5472 static void usc_stop_receiver( struct mgsl_struct *info )
5473 {
5474 if (debug_level >= DEBUG_LEVEL_ISR)
5475 printk("%s(%d):usc_stop_receiver(%s)\n",
5476 __FILE__,__LINE__, info->device_name );
5477
5478 /* Disable receive DMA channel. */
5479 /* This also disables receive DMA channel interrupts */
5480 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5481
5482 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5483 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5484 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5485
5486 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5487
5488 /* This empties the receive FIFO and loads the RCC with RCLR */
5489 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5490 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5491
5492 info->rx_enabled = false;
5493 info->rx_overflow = false;
5494 info->rx_rcc_underrun = false;
5495
5496 } /* end of stop_receiver() */
5497
5498 /* usc_start_receiver()
5499 *
5500 * Enable the USC receiver
5501 *
5502 * Arguments: info pointer to device instance data
5503 * Return Value: None
5504 */
5505 static void usc_start_receiver( struct mgsl_struct *info )
5506 {
5507 u32 phys_addr;
5508
5509 if (debug_level >= DEBUG_LEVEL_ISR)
5510 printk("%s(%d):usc_start_receiver(%s)\n",
5511 __FILE__,__LINE__, info->device_name );
5512
5513 mgsl_reset_rx_dma_buffers( info );
5514 usc_stop_receiver( info );
5515
5516 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5517 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5518
5519 if ( info->params.mode == MGSL_MODE_HDLC ||
5520 info->params.mode == MGSL_MODE_RAW ) {
5521 /* DMA mode Transfers */
5522 /* Program the DMA controller. */
5523 /* Enable the DMA controller end of buffer interrupt. */
5524
5525 /* program 16C32 with physical address of 1st DMA buffer entry */
5526 phys_addr = info->rx_buffer_list[0].phys_entry;
5527 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5528 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5529
5530 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5531 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5532 usc_EnableInterrupts( info, RECEIVE_STATUS );
5533
5534 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5535 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5536
5537 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5538 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5539 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5540 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5541 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5542 else
5543 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5544 } else {
5545 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5546 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5547 usc_EnableInterrupts(info, RECEIVE_DATA);
5548
5549 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5550 usc_RCmd( info, RCmd_EnterHuntmode );
5551
5552 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5553 }
5554
5555 usc_OutReg( info, CCSR, 0x1020 );
5556
5557 info->rx_enabled = true;
5558
5559 } /* end of usc_start_receiver() */
5560
5561 /* usc_start_transmitter()
5562 *
5563 * Enable the USC transmitter and send a transmit frame if
5564 * one is loaded in the DMA buffers.
5565 *
5566 * Arguments: info pointer to device instance data
5567 * Return Value: None
5568 */
5569 static void usc_start_transmitter( struct mgsl_struct *info )
5570 {
5571 u32 phys_addr;
5572 unsigned int FrameSize;
5573
5574 if (debug_level >= DEBUG_LEVEL_ISR)
5575 printk("%s(%d):usc_start_transmitter(%s)\n",
5576 __FILE__,__LINE__, info->device_name );
5577
5578 if ( info->xmit_cnt ) {
5579
5580 /* If auto RTS enabled and RTS is inactive, then assert */
5581 /* RTS and set a flag indicating that the driver should */
5582 /* negate RTS when the transmission completes. */
5583
5584 info->drop_rts_on_tx_done = false;
5585
5586 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5587 usc_get_serial_signals( info );
5588 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5589 info->serial_signals |= SerialSignal_RTS;
5590 usc_set_serial_signals( info );
5591 info->drop_rts_on_tx_done = true;
5592 }
5593 }
5594
5595
5596 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5597 if ( !info->tx_active ) {
5598 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5599 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5600 usc_EnableInterrupts(info, TRANSMIT_DATA);
5601 usc_load_txfifo(info);
5602 }
5603 } else {
5604 /* Disable transmit DMA controller while programming. */
5605 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5606
5607 /* Transmit DMA buffer is loaded, so program USC */
5608 /* to send the frame contained in the buffers. */
5609
5610 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5611
5612 /* if operating in Raw sync mode, reset the rcc component
5613 * of the tx dma buffer entry, otherwise, the serial controller
5614 * will send a closing sync char after this count.
5615 */
5616 if ( info->params.mode == MGSL_MODE_RAW )
5617 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5618
5619 /* Program the Transmit Character Length Register (TCLR) */
5620 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5621 usc_OutReg( info, TCLR, (u16)FrameSize );
5622
5623 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5624
5625 /* Program the address of the 1st DMA Buffer Entry in linked list */
5626 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5627 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5628 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5629
5630 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5631 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5632 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5633
5634 if ( info->params.mode == MGSL_MODE_RAW &&
5635 info->num_tx_dma_buffers > 1 ) {
5636 /* When running external sync mode, attempt to 'stream' transmit */
5637 /* by filling tx dma buffers as they become available. To do this */
5638 /* we need to enable Tx DMA EOB Status interrupts : */
5639 /* */
5640 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5641 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5642
5643 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5644 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5645 }
5646
5647 /* Initialize Transmit DMA Channel */
5648 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5649
5650 usc_TCmd( info, TCmd_SendFrame );
5651
5652 mod_timer(&info->tx_timer, jiffies +
5653 msecs_to_jiffies(5000));
5654 }
5655 info->tx_active = true;
5656 }
5657
5658 if ( !info->tx_enabled ) {
5659 info->tx_enabled = true;
5660 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5661 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5662 else
5663 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5664 }
5665
5666 } /* end of usc_start_transmitter() */
5667
5668 /* usc_stop_transmitter()
5669 *
5670 * Stops the transmitter and DMA
5671 *
5672 * Arguments: info pointer to device isntance data
5673 * Return Value: None
5674 */
5675 static void usc_stop_transmitter( struct mgsl_struct *info )
5676 {
5677 if (debug_level >= DEBUG_LEVEL_ISR)
5678 printk("%s(%d):usc_stop_transmitter(%s)\n",
5679 __FILE__,__LINE__, info->device_name );
5680
5681 del_timer(&info->tx_timer);
5682
5683 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5684 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5685 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5686
5687 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5688 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5689 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5690
5691 info->tx_enabled = false;
5692 info->tx_active = false;
5693
5694 } /* end of usc_stop_transmitter() */
5695
5696 /* usc_load_txfifo()
5697 *
5698 * Fill the transmit FIFO until the FIFO is full or
5699 * there is no more data to load.
5700 *
5701 * Arguments: info pointer to device extension (instance data)
5702 * Return Value: None
5703 */
5704 static void usc_load_txfifo( struct mgsl_struct *info )
5705 {
5706 int Fifocount;
5707 u8 TwoBytes[2];
5708
5709 if ( !info->xmit_cnt && !info->x_char )
5710 return;
5711
5712 /* Select transmit FIFO status readback in TICR */
5713 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5714
5715 /* load the Transmit FIFO until FIFOs full or all data sent */
5716
5717 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5718 /* there is more space in the transmit FIFO and */
5719 /* there is more data in transmit buffer */
5720
5721 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5722 /* write a 16-bit word from transmit buffer to 16C32 */
5723
5724 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5725 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5726 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5727 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5728
5729 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5730
5731 info->xmit_cnt -= 2;
5732 info->icount.tx += 2;
5733 } else {
5734 /* only 1 byte left to transmit or 1 FIFO slot left */
5735
5736 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5737 info->io_base + CCAR );
5738
5739 if (info->x_char) {
5740 /* transmit pending high priority char */
5741 outw( info->x_char,info->io_base + CCAR );
5742 info->x_char = 0;
5743 } else {
5744 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5745 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5746 info->xmit_cnt--;
5747 }
5748 info->icount.tx++;
5749 }
5750 }
5751
5752 } /* end of usc_load_txfifo() */
5753
5754 /* usc_reset()
5755 *
5756 * Reset the adapter to a known state and prepare it for further use.
5757 *
5758 * Arguments: info pointer to device instance data
5759 * Return Value: None
5760 */
5761 static void usc_reset( struct mgsl_struct *info )
5762 {
5763 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5764 int i;
5765 u32 readval;
5766
5767 /* Set BIT30 of Misc Control Register */
5768 /* (Local Control Register 0x50) to force reset of USC. */
5769
5770 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5771 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5772
5773 info->misc_ctrl_value |= BIT30;
5774 *MiscCtrl = info->misc_ctrl_value;
5775
5776 /*
5777 * Force at least 170ns delay before clearing
5778 * reset bit. Each read from LCR takes at least
5779 * 30ns so 10 times for 300ns to be safe.
5780 */
5781 for(i=0;i<10;i++)
5782 readval = *MiscCtrl;
5783
5784 info->misc_ctrl_value &= ~BIT30;
5785 *MiscCtrl = info->misc_ctrl_value;
5786
5787 *LCR0BRDR = BUS_DESCRIPTOR(
5788 1, // Write Strobe Hold (0-3)
5789 2, // Write Strobe Delay (0-3)
5790 2, // Read Strobe Delay (0-3)
5791 0, // NWDD (Write data-data) (0-3)
5792 4, // NWAD (Write Addr-data) (0-31)
5793 0, // NXDA (Read/Write Data-Addr) (0-3)
5794 0, // NRDD (Read Data-Data) (0-3)
5795 5 // NRAD (Read Addr-Data) (0-31)
5796 );
5797 } else {
5798 /* do HW reset */
5799 outb( 0,info->io_base + 8 );
5800 }
5801
5802 info->mbre_bit = 0;
5803 info->loopback_bits = 0;
5804 info->usc_idle_mode = 0;
5805
5806 /*
5807 * Program the Bus Configuration Register (BCR)
5808 *
5809 * <15> 0 Don't use separate address
5810 * <14..6> 0 reserved
5811 * <5..4> 00 IAckmode = Default, don't care
5812 * <3> 1 Bus Request Totem Pole output
5813 * <2> 1 Use 16 Bit data bus
5814 * <1> 0 IRQ Totem Pole output
5815 * <0> 0 Don't Shift Right Addr
5816 *
5817 * 0000 0000 0000 1100 = 0x000c
5818 *
5819 * By writing to io_base + SDPIN the Wait/Ack pin is
5820 * programmed to work as a Wait pin.
5821 */
5822
5823 outw( 0x000c,info->io_base + SDPIN );
5824
5825
5826 outw( 0,info->io_base );
5827 outw( 0,info->io_base + CCAR );
5828
5829 /* select little endian byte ordering */
5830 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5831
5832
5833 /* Port Control Register (PCR)
5834 *
5835 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5836 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5837 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5838 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5839 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5840 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5841 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5842 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5843 *
5844 * 1111 0000 1111 0101 = 0xf0f5
5845 */
5846
5847 usc_OutReg( info, PCR, 0xf0f5 );
5848
5849
5850 /*
5851 * Input/Output Control Register
5852 *
5853 * <15..14> 00 CTS is active low input
5854 * <13..12> 00 DCD is active low input
5855 * <11..10> 00 TxREQ pin is input (DSR)
5856 * <9..8> 00 RxREQ pin is input (RI)
5857 * <7..6> 00 TxD is output (Transmit Data)
5858 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5859 * <2..0> 100 RxC is Output (drive with BRG0)
5860 *
5861 * 0000 0000 0000 0100 = 0x0004
5862 */
5863
5864 usc_OutReg( info, IOCR, 0x0004 );
5865
5866 } /* end of usc_reset() */
5867
5868 /* usc_set_async_mode()
5869 *
5870 * Program adapter for asynchronous communications.
5871 *
5872 * Arguments: info pointer to device instance data
5873 * Return Value: None
5874 */
5875 static void usc_set_async_mode( struct mgsl_struct *info )
5876 {
5877 u16 RegValue;
5878
5879 /* disable interrupts while programming USC */
5880 usc_DisableMasterIrqBit( info );
5881
5882 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5883 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5884
5885 usc_loopback_frame( info );
5886
5887 /* Channel mode Register (CMR)
5888 *
5889 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5890 * <13..12> 00 00 = 16X Clock
5891 * <11..8> 0000 Transmitter mode = Asynchronous
5892 * <7..6> 00 reserved?
5893 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5894 * <3..0> 0000 Receiver mode = Asynchronous
5895 *
5896 * 0000 0000 0000 0000 = 0x0
5897 */
5898
5899 RegValue = 0;
5900 if ( info->params.stop_bits != 1 )
5901 RegValue |= BIT14;
5902 usc_OutReg( info, CMR, RegValue );
5903
5904
5905 /* Receiver mode Register (RMR)
5906 *
5907 * <15..13> 000 encoding = None
5908 * <12..08> 00000 reserved (Sync Only)
5909 * <7..6> 00 Even parity
5910 * <5> 0 parity disabled
5911 * <4..2> 000 Receive Char Length = 8 bits
5912 * <1..0> 00 Disable Receiver
5913 *
5914 * 0000 0000 0000 0000 = 0x0
5915 */
5916
5917 RegValue = 0;
5918
5919 if ( info->params.data_bits != 8 )
5920 RegValue |= BIT4+BIT3+BIT2;
5921
5922 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5923 RegValue |= BIT5;
5924 if ( info->params.parity != ASYNC_PARITY_ODD )
5925 RegValue |= BIT6;
5926 }
5927
5928 usc_OutReg( info, RMR, RegValue );
5929
5930
5931 /* Set IRQ trigger level */
5932
5933 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5934
5935
5936 /* Receive Interrupt Control Register (RICR)
5937 *
5938 * <15..8> ? RxFIFO IRQ Request Level
5939 *
5940 * Note: For async mode the receive FIFO level must be set
5941 * to 0 to avoid the situation where the FIFO contains fewer bytes
5942 * than the trigger level and no more data is expected.
5943 *
5944 * <7> 0 Exited Hunt IA (Interrupt Arm)
5945 * <6> 0 Idle Received IA
5946 * <5> 0 Break/Abort IA
5947 * <4> 0 Rx Bound IA
5948 * <3> 0 Queued status reflects oldest byte in FIFO
5949 * <2> 0 Abort/PE IA
5950 * <1> 0 Rx Overrun IA
5951 * <0> 0 Select TC0 value for readback
5952 *
5953 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5954 */
5955
5956 usc_OutReg( info, RICR, 0x0000 );
5957
5958 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5959 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5960
5961
5962 /* Transmit mode Register (TMR)
5963 *
5964 * <15..13> 000 encoding = None
5965 * <12..08> 00000 reserved (Sync Only)
5966 * <7..6> 00 Transmit parity Even
5967 * <5> 0 Transmit parity Disabled
5968 * <4..2> 000 Tx Char Length = 8 bits
5969 * <1..0> 00 Disable Transmitter
5970 *
5971 * 0000 0000 0000 0000 = 0x0
5972 */
5973
5974 RegValue = 0;
5975
5976 if ( info->params.data_bits != 8 )
5977 RegValue |= BIT4+BIT3+BIT2;
5978
5979 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5980 RegValue |= BIT5;
5981 if ( info->params.parity != ASYNC_PARITY_ODD )
5982 RegValue |= BIT6;
5983 }
5984
5985 usc_OutReg( info, TMR, RegValue );
5986
5987 usc_set_txidle( info );
5988
5989
5990 /* Set IRQ trigger level */
5991
5992 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5993
5994
5995 /* Transmit Interrupt Control Register (TICR)
5996 *
5997 * <15..8> ? Transmit FIFO IRQ Level
5998 * <7> 0 Present IA (Interrupt Arm)
5999 * <6> 1 Idle Sent IA
6000 * <5> 0 Abort Sent IA
6001 * <4> 0 EOF/EOM Sent IA
6002 * <3> 0 CRC Sent IA
6003 * <2> 0 1 = Wait for SW Trigger to Start Frame
6004 * <1> 0 Tx Underrun IA
6005 * <0> 0 TC0 constant on read back
6006 *
6007 * 0000 0000 0100 0000 = 0x0040
6008 */
6009
6010 usc_OutReg( info, TICR, 0x1f40 );
6011
6012 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6013 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6014
6015 usc_enable_async_clock( info, info->params.data_rate );
6016
6017
6018 /* Channel Control/status Register (CCSR)
6019 *
6020 * <15> X RCC FIFO Overflow status (RO)
6021 * <14> X RCC FIFO Not Empty status (RO)
6022 * <13> 0 1 = Clear RCC FIFO (WO)
6023 * <12> X DPLL in Sync status (RO)
6024 * <11> X DPLL 2 Missed Clocks status (RO)
6025 * <10> X DPLL 1 Missed Clock status (RO)
6026 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6027 * <7> X SDLC Loop On status (RO)
6028 * <6> X SDLC Loop Send status (RO)
6029 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6030 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6031 * <1..0> 00 reserved
6032 *
6033 * 0000 0000 0010 0000 = 0x0020
6034 */
6035
6036 usc_OutReg( info, CCSR, 0x0020 );
6037
6038 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6039 RECEIVE_DATA + RECEIVE_STATUS );
6040
6041 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6042 RECEIVE_DATA + RECEIVE_STATUS );
6043
6044 usc_EnableMasterIrqBit( info );
6045
6046 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6047 /* Enable INTEN (Port 6, Bit12) */
6048 /* This connects the IRQ request signal to the ISA bus */
6049 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6050 }
6051
6052 if (info->params.loopback) {
6053 info->loopback_bits = 0x300;
6054 outw(0x0300, info->io_base + CCAR);
6055 }
6056
6057 } /* end of usc_set_async_mode() */
6058
6059 /* usc_loopback_frame()
6060 *
6061 * Loop back a small (2 byte) dummy SDLC frame.
6062 * Interrupts and DMA are NOT used. The purpose of this is to
6063 * clear any 'stale' status info left over from running in async mode.
6064 *
6065 * The 16C32 shows the strange behaviour of marking the 1st
6066 * received SDLC frame with a CRC error even when there is no
6067 * CRC error. To get around this a small dummy from of 2 bytes
6068 * is looped back when switching from async to sync mode.
6069 *
6070 * Arguments: info pointer to device instance data
6071 * Return Value: None
6072 */
6073 static void usc_loopback_frame( struct mgsl_struct *info )
6074 {
6075 int i;
6076 unsigned long oldmode = info->params.mode;
6077
6078 info->params.mode = MGSL_MODE_HDLC;
6079
6080 usc_DisableMasterIrqBit( info );
6081
6082 usc_set_sdlc_mode( info );
6083 usc_enable_loopback( info, 1 );
6084
6085 /* Write 16-bit Time Constant for BRG0 */
6086 usc_OutReg( info, TC0R, 0 );
6087
6088 /* Channel Control Register (CCR)
6089 *
6090 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6091 * <13> 0 Trigger Tx on SW Command Disabled
6092 * <12> 0 Flag Preamble Disabled
6093 * <11..10> 00 Preamble Length = 8-Bits
6094 * <9..8> 01 Preamble Pattern = flags
6095 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6096 * <5> 0 Trigger Rx on SW Command Disabled
6097 * <4..0> 0 reserved
6098 *
6099 * 0000 0001 0000 0000 = 0x0100
6100 */
6101
6102 usc_OutReg( info, CCR, 0x0100 );
6103
6104 /* SETUP RECEIVER */
6105 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6106 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6107
6108 /* SETUP TRANSMITTER */
6109 /* Program the Transmit Character Length Register (TCLR) */
6110 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6111 usc_OutReg( info, TCLR, 2 );
6112 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6113
6114 /* unlatch Tx status bits, and start transmit channel. */
6115 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6116 outw(0,info->io_base + DATAREG);
6117
6118 /* ENABLE TRANSMITTER */
6119 usc_TCmd( info, TCmd_SendFrame );
6120 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6121
6122 /* WAIT FOR RECEIVE COMPLETE */
6123 for (i=0 ; i<1000 ; i++)
6124 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6125 break;
6126
6127 /* clear Internal Data loopback mode */
6128 usc_enable_loopback(info, 0);
6129
6130 usc_EnableMasterIrqBit(info);
6131
6132 info->params.mode = oldmode;
6133
6134 } /* end of usc_loopback_frame() */
6135
6136 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6137 *
6138 * Arguments: info pointer to adapter info structure
6139 * Return Value: None
6140 */
6141 static void usc_set_sync_mode( struct mgsl_struct *info )
6142 {
6143 usc_loopback_frame( info );
6144 usc_set_sdlc_mode( info );
6145
6146 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6147 /* Enable INTEN (Port 6, Bit12) */
6148 /* This connects the IRQ request signal to the ISA bus */
6149 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6150 }
6151
6152 usc_enable_aux_clock(info, info->params.clock_speed);
6153
6154 if (info->params.loopback)
6155 usc_enable_loopback(info,1);
6156
6157 } /* end of mgsl_set_sync_mode() */
6158
6159 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6160 *
6161 * Arguments: info pointer to device instance data
6162 * Return Value: None
6163 */
6164 static void usc_set_txidle( struct mgsl_struct *info )
6165 {
6166 u16 usc_idle_mode = IDLEMODE_FLAGS;
6167
6168 /* Map API idle mode to USC register bits */
6169
6170 switch( info->idle_mode ){
6171 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6172 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6173 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6174 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6175 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6176 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6177 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6178 }
6179
6180 info->usc_idle_mode = usc_idle_mode;
6181 //usc_OutReg(info, TCSR, usc_idle_mode);
6182 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6183 info->tcsr_value += usc_idle_mode;
6184 usc_OutReg(info, TCSR, info->tcsr_value);
6185
6186 /*
6187 * if SyncLink WAN adapter is running in external sync mode, the
6188 * transmitter has been set to Monosync in order to try to mimic
6189 * a true raw outbound bit stream. Monosync still sends an open/close
6190 * sync char at the start/end of a frame. Try to match those sync
6191 * patterns to the idle mode set here
6192 */
6193 if ( info->params.mode == MGSL_MODE_RAW ) {
6194 unsigned char syncpat = 0;
6195 switch( info->idle_mode ) {
6196 case HDLC_TXIDLE_FLAGS:
6197 syncpat = 0x7e;
6198 break;
6199 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6200 syncpat = 0x55;
6201 break;
6202 case HDLC_TXIDLE_ZEROS:
6203 case HDLC_TXIDLE_SPACE:
6204 syncpat = 0x00;
6205 break;
6206 case HDLC_TXIDLE_ONES:
6207 case HDLC_TXIDLE_MARK:
6208 syncpat = 0xff;
6209 break;
6210 case HDLC_TXIDLE_ALT_MARK_SPACE:
6211 syncpat = 0xaa;
6212 break;
6213 }
6214
6215 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6216 }
6217
6218 } /* end of usc_set_txidle() */
6219
6220 /* usc_get_serial_signals()
6221 *
6222 * Query the adapter for the state of the V24 status (input) signals.
6223 *
6224 * Arguments: info pointer to device instance data
6225 * Return Value: None
6226 */
6227 static void usc_get_serial_signals( struct mgsl_struct *info )
6228 {
6229 u16 status;
6230
6231 /* clear all serial signals except DTR and RTS */
6232 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6233
6234 /* Read the Misc Interrupt status Register (MISR) to get */
6235 /* the V24 status signals. */
6236
6237 status = usc_InReg( info, MISR );
6238
6239 /* set serial signal bits to reflect MISR */
6240
6241 if ( status & MISCSTATUS_CTS )
6242 info->serial_signals |= SerialSignal_CTS;
6243
6244 if ( status & MISCSTATUS_DCD )
6245 info->serial_signals |= SerialSignal_DCD;
6246
6247 if ( status & MISCSTATUS_RI )
6248 info->serial_signals |= SerialSignal_RI;
6249
6250 if ( status & MISCSTATUS_DSR )
6251 info->serial_signals |= SerialSignal_DSR;
6252
6253 } /* end of usc_get_serial_signals() */
6254
6255 /* usc_set_serial_signals()
6256 *
6257 * Set the state of DTR and RTS based on contents of
6258 * serial_signals member of device extension.
6259 *
6260 * Arguments: info pointer to device instance data
6261 * Return Value: None
6262 */
6263 static void usc_set_serial_signals( struct mgsl_struct *info )
6264 {
6265 u16 Control;
6266 unsigned char V24Out = info->serial_signals;
6267
6268 /* get the current value of the Port Control Register (PCR) */
6269
6270 Control = usc_InReg( info, PCR );
6271
6272 if ( V24Out & SerialSignal_RTS )
6273 Control &= ~(BIT6);
6274 else
6275 Control |= BIT6;
6276
6277 if ( V24Out & SerialSignal_DTR )
6278 Control &= ~(BIT4);
6279 else
6280 Control |= BIT4;
6281
6282 usc_OutReg( info, PCR, Control );
6283
6284 } /* end of usc_set_serial_signals() */
6285
6286 /* usc_enable_async_clock()
6287 *
6288 * Enable the async clock at the specified frequency.
6289 *
6290 * Arguments: info pointer to device instance data
6291 * data_rate data rate of clock in bps
6292 * 0 disables the AUX clock.
6293 * Return Value: None
6294 */
6295 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6296 {
6297 if ( data_rate ) {
6298 /*
6299 * Clock mode Control Register (CMCR)
6300 *
6301 * <15..14> 00 counter 1 Disabled
6302 * <13..12> 00 counter 0 Disabled
6303 * <11..10> 11 BRG1 Input is TxC Pin
6304 * <9..8> 11 BRG0 Input is TxC Pin
6305 * <7..6> 01 DPLL Input is BRG1 Output
6306 * <5..3> 100 TxCLK comes from BRG0
6307 * <2..0> 100 RxCLK comes from BRG0
6308 *
6309 * 0000 1111 0110 0100 = 0x0f64
6310 */
6311
6312 usc_OutReg( info, CMCR, 0x0f64 );
6313
6314
6315 /*
6316 * Write 16-bit Time Constant for BRG0
6317 * Time Constant = (ClkSpeed / data_rate) - 1
6318 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6319 */
6320
6321 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6322 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6323 else
6324 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6325
6326
6327 /*
6328 * Hardware Configuration Register (HCR)
6329 * Clear Bit 1, BRG0 mode = Continuous
6330 * Set Bit 0 to enable BRG0.
6331 */
6332
6333 usc_OutReg( info, HCR,
6334 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6335
6336
6337 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6338
6339 usc_OutReg( info, IOCR,
6340 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6341 } else {
6342 /* data rate == 0 so turn off BRG0 */
6343 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6344 }
6345
6346 } /* end of usc_enable_async_clock() */
6347
6348 /*
6349 * Buffer Structures:
6350 *
6351 * Normal memory access uses virtual addresses that can make discontiguous
6352 * physical memory pages appear to be contiguous in the virtual address
6353 * space (the processors memory mapping handles the conversions).
6354 *
6355 * DMA transfers require physically contiguous memory. This is because
6356 * the DMA system controller and DMA bus masters deal with memory using
6357 * only physical addresses.
6358 *
6359 * This causes a problem under Windows NT when large DMA buffers are
6360 * needed. Fragmentation of the nonpaged pool prevents allocations of
6361 * physically contiguous buffers larger than the PAGE_SIZE.
6362 *
6363 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6364 * allows DMA transfers to physically discontiguous buffers. Information
6365 * about each data transfer buffer is contained in a memory structure
6366 * called a 'buffer entry'. A list of buffer entries is maintained
6367 * to track and control the use of the data transfer buffers.
6368 *
6369 * To support this strategy we will allocate sufficient PAGE_SIZE
6370 * contiguous memory buffers to allow for the total required buffer
6371 * space.
6372 *
6373 * The 16C32 accesses the list of buffer entries using Bus Master
6374 * DMA. Control information is read from the buffer entries by the
6375 * 16C32 to control data transfers. status information is written to
6376 * the buffer entries by the 16C32 to indicate the status of completed
6377 * transfers.
6378 *
6379 * The CPU writes control information to the buffer entries to control
6380 * the 16C32 and reads status information from the buffer entries to
6381 * determine information about received and transmitted frames.
6382 *
6383 * Because the CPU and 16C32 (adapter) both need simultaneous access
6384 * to the buffer entries, the buffer entry memory is allocated with
6385 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6386 * entry list to PAGE_SIZE.
6387 *
6388 * The actual data buffers on the other hand will only be accessed
6389 * by the CPU or the adapter but not by both simultaneously. This allows
6390 * Scatter/Gather packet based DMA procedures for using physically
6391 * discontiguous pages.
6392 */
6393
6394 /*
6395 * mgsl_reset_tx_dma_buffers()
6396 *
6397 * Set the count for all transmit buffers to 0 to indicate the
6398 * buffer is available for use and set the current buffer to the
6399 * first buffer. This effectively makes all buffers free and
6400 * discards any data in buffers.
6401 *
6402 * Arguments: info pointer to device instance data
6403 * Return Value: None
6404 */
6405 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6406 {
6407 unsigned int i;
6408
6409 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6410 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6411 }
6412
6413 info->current_tx_buffer = 0;
6414 info->start_tx_dma_buffer = 0;
6415 info->tx_dma_buffers_used = 0;
6416
6417 info->get_tx_holding_index = 0;
6418 info->put_tx_holding_index = 0;
6419 info->tx_holding_count = 0;
6420
6421 } /* end of mgsl_reset_tx_dma_buffers() */
6422
6423 /*
6424 * num_free_tx_dma_buffers()
6425 *
6426 * returns the number of free tx dma buffers available
6427 *
6428 * Arguments: info pointer to device instance data
6429 * Return Value: number of free tx dma buffers
6430 */
6431 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6432 {
6433 return info->tx_buffer_count - info->tx_dma_buffers_used;
6434 }
6435
6436 /*
6437 * mgsl_reset_rx_dma_buffers()
6438 *
6439 * Set the count for all receive buffers to DMABUFFERSIZE
6440 * and set the current buffer to the first buffer. This effectively
6441 * makes all buffers free and discards any data in buffers.
6442 *
6443 * Arguments: info pointer to device instance data
6444 * Return Value: None
6445 */
6446 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6447 {
6448 unsigned int i;
6449
6450 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6451 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6452 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6453 // info->rx_buffer_list[i].status = 0;
6454 }
6455
6456 info->current_rx_buffer = 0;
6457
6458 } /* end of mgsl_reset_rx_dma_buffers() */
6459
6460 /*
6461 * mgsl_free_rx_frame_buffers()
6462 *
6463 * Free the receive buffers used by a received SDLC
6464 * frame such that the buffers can be reused.
6465 *
6466 * Arguments:
6467 *
6468 * info pointer to device instance data
6469 * StartIndex index of 1st receive buffer of frame
6470 * EndIndex index of last receive buffer of frame
6471 *
6472 * Return Value: None
6473 */
6474 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6475 {
6476 bool Done = false;
6477 DMABUFFERENTRY *pBufEntry;
6478 unsigned int Index;
6479
6480 /* Starting with 1st buffer entry of the frame clear the status */
6481 /* field and set the count field to DMA Buffer Size. */
6482
6483 Index = StartIndex;
6484
6485 while( !Done ) {
6486 pBufEntry = &(info->rx_buffer_list[Index]);
6487
6488 if ( Index == EndIndex ) {
6489 /* This is the last buffer of the frame! */
6490 Done = true;
6491 }
6492
6493 /* reset current buffer for reuse */
6494 // pBufEntry->status = 0;
6495 // pBufEntry->count = DMABUFFERSIZE;
6496 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6497
6498 /* advance to next buffer entry in linked list */
6499 Index++;
6500 if ( Index == info->rx_buffer_count )
6501 Index = 0;
6502 }
6503
6504 /* set current buffer to next buffer after last buffer of frame */
6505 info->current_rx_buffer = Index;
6506
6507 } /* end of free_rx_frame_buffers() */
6508
6509 /* mgsl_get_rx_frame()
6510 *
6511 * This function attempts to return a received SDLC frame from the
6512 * receive DMA buffers. Only frames received without errors are returned.
6513 *
6514 * Arguments: info pointer to device extension
6515 * Return Value: true if frame returned, otherwise false
6516 */
6517 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6518 {
6519 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6520 unsigned short status;
6521 DMABUFFERENTRY *pBufEntry;
6522 unsigned int framesize = 0;
6523 bool ReturnCode = false;
6524 unsigned long flags;
6525 struct tty_struct *tty = info->port.tty;
6526 bool return_frame = false;
6527
6528 /*
6529 * current_rx_buffer points to the 1st buffer of the next available
6530 * receive frame. To find the last buffer of the frame look for
6531 * a non-zero status field in the buffer entries. (The status
6532 * field is set by the 16C32 after completing a receive frame.
6533 */
6534
6535 StartIndex = EndIndex = info->current_rx_buffer;
6536
6537 while( !info->rx_buffer_list[EndIndex].status ) {
6538 /*
6539 * If the count field of the buffer entry is non-zero then
6540 * this buffer has not been used. (The 16C32 clears the count
6541 * field when it starts using the buffer.) If an unused buffer
6542 * is encountered then there are no frames available.
6543 */
6544
6545 if ( info->rx_buffer_list[EndIndex].count )
6546 goto Cleanup;
6547
6548 /* advance to next buffer entry in linked list */
6549 EndIndex++;
6550 if ( EndIndex == info->rx_buffer_count )
6551 EndIndex = 0;
6552
6553 /* if entire list searched then no frame available */
6554 if ( EndIndex == StartIndex ) {
6555 /* If this occurs then something bad happened,
6556 * all buffers have been 'used' but none mark
6557 * the end of a frame. Reset buffers and receiver.
6558 */
6559
6560 if ( info->rx_enabled ){
6561 spin_lock_irqsave(&info->irq_spinlock,flags);
6562 usc_start_receiver(info);
6563 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6564 }
6565 goto Cleanup;
6566 }
6567 }
6568
6569
6570 /* check status of receive frame */
6571
6572 status = info->rx_buffer_list[EndIndex].status;
6573
6574 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6575 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6576 if ( status & RXSTATUS_SHORT_FRAME )
6577 info->icount.rxshort++;
6578 else if ( status & RXSTATUS_ABORT )
6579 info->icount.rxabort++;
6580 else if ( status & RXSTATUS_OVERRUN )
6581 info->icount.rxover++;
6582 else {
6583 info->icount.rxcrc++;
6584 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6585 return_frame = true;
6586 }
6587 framesize = 0;
6588 #if SYNCLINK_GENERIC_HDLC
6589 {
6590 info->netdev->stats.rx_errors++;
6591 info->netdev->stats.rx_frame_errors++;
6592 }
6593 #endif
6594 } else
6595 return_frame = true;
6596
6597 if ( return_frame ) {
6598 /* receive frame has no errors, get frame size.
6599 * The frame size is the starting value of the RCC (which was
6600 * set to 0xffff) minus the ending value of the RCC (decremented
6601 * once for each receive character) minus 2 for the 16-bit CRC.
6602 */
6603
6604 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6605
6606 /* adjust frame size for CRC if any */
6607 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6608 framesize -= 2;
6609 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6610 framesize -= 4;
6611 }
6612
6613 if ( debug_level >= DEBUG_LEVEL_BH )
6614 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6615 __FILE__,__LINE__,info->device_name,status,framesize);
6616
6617 if ( debug_level >= DEBUG_LEVEL_DATA )
6618 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6619 min_t(int, framesize, DMABUFFERSIZE),0);
6620
6621 if (framesize) {
6622 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6623 ((framesize+1) > info->max_frame_size) ) ||
6624 (framesize > info->max_frame_size) )
6625 info->icount.rxlong++;
6626 else {
6627 /* copy dma buffer(s) to contiguous intermediate buffer */
6628 int copy_count = framesize;
6629 int index = StartIndex;
6630 unsigned char *ptmp = info->intermediate_rxbuffer;
6631
6632 if ( !(status & RXSTATUS_CRC_ERROR))
6633 info->icount.rxok++;
6634
6635 while(copy_count) {
6636 int partial_count;
6637 if ( copy_count > DMABUFFERSIZE )
6638 partial_count = DMABUFFERSIZE;
6639 else
6640 partial_count = copy_count;
6641
6642 pBufEntry = &(info->rx_buffer_list[index]);
6643 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6644 ptmp += partial_count;
6645 copy_count -= partial_count;
6646
6647 if ( ++index == info->rx_buffer_count )
6648 index = 0;
6649 }
6650
6651 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6652 ++framesize;
6653 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6654 RX_CRC_ERROR :
6655 RX_OK);
6656
6657 if ( debug_level >= DEBUG_LEVEL_DATA )
6658 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6659 __FILE__,__LINE__,info->device_name,
6660 *ptmp);
6661 }
6662
6663 #if SYNCLINK_GENERIC_HDLC
6664 if (info->netcount)
6665 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6666 else
6667 #endif
6668 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6669 }
6670 }
6671 /* Free the buffers used by this frame. */
6672 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6673
6674 ReturnCode = true;
6675
6676 Cleanup:
6677
6678 if ( info->rx_enabled && info->rx_overflow ) {
6679 /* The receiver needs to restarted because of
6680 * a receive overflow (buffer or FIFO). If the
6681 * receive buffers are now empty, then restart receiver.
6682 */
6683
6684 if ( !info->rx_buffer_list[EndIndex].status &&
6685 info->rx_buffer_list[EndIndex].count ) {
6686 spin_lock_irqsave(&info->irq_spinlock,flags);
6687 usc_start_receiver(info);
6688 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6689 }
6690 }
6691
6692 return ReturnCode;
6693
6694 } /* end of mgsl_get_rx_frame() */
6695
6696 /* mgsl_get_raw_rx_frame()
6697 *
6698 * This function attempts to return a received frame from the
6699 * receive DMA buffers when running in external loop mode. In this mode,
6700 * we will return at most one DMABUFFERSIZE frame to the application.
6701 * The USC receiver is triggering off of DCD going active to start a new
6702 * frame, and DCD going inactive to terminate the frame (similar to
6703 * processing a closing flag character).
6704 *
6705 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6706 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6707 * status field and the RCC field will indicate the length of the
6708 * entire received frame. We take this RCC field and get the modulus
6709 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6710 * last Rx DMA buffer and return that last portion of the frame.
6711 *
6712 * Arguments: info pointer to device extension
6713 * Return Value: true if frame returned, otherwise false
6714 */
6715 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6716 {
6717 unsigned int CurrentIndex, NextIndex;
6718 unsigned short status;
6719 DMABUFFERENTRY *pBufEntry;
6720 unsigned int framesize = 0;
6721 bool ReturnCode = false;
6722 unsigned long flags;
6723 struct tty_struct *tty = info->port.tty;
6724
6725 /*
6726 * current_rx_buffer points to the 1st buffer of the next available
6727 * receive frame. The status field is set by the 16C32 after
6728 * completing a receive frame. If the status field of this buffer
6729 * is zero, either the USC is still filling this buffer or this
6730 * is one of a series of buffers making up a received frame.
6731 *
6732 * If the count field of this buffer is zero, the USC is either
6733 * using this buffer or has used this buffer. Look at the count
6734 * field of the next buffer. If that next buffer's count is
6735 * non-zero, the USC is still actively using the current buffer.
6736 * Otherwise, if the next buffer's count field is zero, the
6737 * current buffer is complete and the USC is using the next
6738 * buffer.
6739 */
6740 CurrentIndex = NextIndex = info->current_rx_buffer;
6741 ++NextIndex;
6742 if ( NextIndex == info->rx_buffer_count )
6743 NextIndex = 0;
6744
6745 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6746 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6747 info->rx_buffer_list[NextIndex].count == 0)) {
6748 /*
6749 * Either the status field of this dma buffer is non-zero
6750 * (indicating the last buffer of a receive frame) or the next
6751 * buffer is marked as in use -- implying this buffer is complete
6752 * and an intermediate buffer for this received frame.
6753 */
6754
6755 status = info->rx_buffer_list[CurrentIndex].status;
6756
6757 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6758 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6759 if ( status & RXSTATUS_SHORT_FRAME )
6760 info->icount.rxshort++;
6761 else if ( status & RXSTATUS_ABORT )
6762 info->icount.rxabort++;
6763 else if ( status & RXSTATUS_OVERRUN )
6764 info->icount.rxover++;
6765 else
6766 info->icount.rxcrc++;
6767 framesize = 0;
6768 } else {
6769 /*
6770 * A receive frame is available, get frame size and status.
6771 *
6772 * The frame size is the starting value of the RCC (which was
6773 * set to 0xffff) minus the ending value of the RCC (decremented
6774 * once for each receive character) minus 2 or 4 for the 16-bit
6775 * or 32-bit CRC.
6776 *
6777 * If the status field is zero, this is an intermediate buffer.
6778 * It's size is 4K.
6779 *
6780 * If the DMA Buffer Entry's Status field is non-zero, the
6781 * receive operation completed normally (ie: DCD dropped). The
6782 * RCC field is valid and holds the received frame size.
6783 * It is possible that the RCC field will be zero on a DMA buffer
6784 * entry with a non-zero status. This can occur if the total
6785 * frame size (number of bytes between the time DCD goes active
6786 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6787 * case the 16C32 has underrun on the RCC count and appears to
6788 * stop updating this counter to let us know the actual received
6789 * frame size. If this happens (non-zero status and zero RCC),
6790 * simply return the entire RxDMA Buffer
6791 */
6792 if ( status ) {
6793 /*
6794 * In the event that the final RxDMA Buffer is
6795 * terminated with a non-zero status and the RCC
6796 * field is zero, we interpret this as the RCC
6797 * having underflowed (received frame > 65535 bytes).
6798 *
6799 * Signal the event to the user by passing back
6800 * a status of RxStatus_CrcError returning the full
6801 * buffer and let the app figure out what data is
6802 * actually valid
6803 */
6804 if ( info->rx_buffer_list[CurrentIndex].rcc )
6805 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6806 else
6807 framesize = DMABUFFERSIZE;
6808 }
6809 else
6810 framesize = DMABUFFERSIZE;
6811 }
6812
6813 if ( framesize > DMABUFFERSIZE ) {
6814 /*
6815 * if running in raw sync mode, ISR handler for
6816 * End Of Buffer events terminates all buffers at 4K.
6817 * If this frame size is said to be >4K, get the
6818 * actual number of bytes of the frame in this buffer.
6819 */
6820 framesize = framesize % DMABUFFERSIZE;
6821 }
6822
6823
6824 if ( debug_level >= DEBUG_LEVEL_BH )
6825 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6826 __FILE__,__LINE__,info->device_name,status,framesize);
6827
6828 if ( debug_level >= DEBUG_LEVEL_DATA )
6829 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6830 min_t(int, framesize, DMABUFFERSIZE),0);
6831
6832 if (framesize) {
6833 /* copy dma buffer(s) to contiguous intermediate buffer */
6834 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6835
6836 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6837 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6838 info->icount.rxok++;
6839
6840 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6841 }
6842
6843 /* Free the buffers used by this frame. */
6844 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6845
6846 ReturnCode = true;
6847 }
6848
6849
6850 if ( info->rx_enabled && info->rx_overflow ) {
6851 /* The receiver needs to restarted because of
6852 * a receive overflow (buffer or FIFO). If the
6853 * receive buffers are now empty, then restart receiver.
6854 */
6855
6856 if ( !info->rx_buffer_list[CurrentIndex].status &&
6857 info->rx_buffer_list[CurrentIndex].count ) {
6858 spin_lock_irqsave(&info->irq_spinlock,flags);
6859 usc_start_receiver(info);
6860 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6861 }
6862 }
6863
6864 return ReturnCode;
6865
6866 } /* end of mgsl_get_raw_rx_frame() */
6867
6868 /* mgsl_load_tx_dma_buffer()
6869 *
6870 * Load the transmit DMA buffer with the specified data.
6871 *
6872 * Arguments:
6873 *
6874 * info pointer to device extension
6875 * Buffer pointer to buffer containing frame to load
6876 * BufferSize size in bytes of frame in Buffer
6877 *
6878 * Return Value: None
6879 */
6880 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6881 const char *Buffer, unsigned int BufferSize)
6882 {
6883 unsigned short Copycount;
6884 unsigned int i = 0;
6885 DMABUFFERENTRY *pBufEntry;
6886
6887 if ( debug_level >= DEBUG_LEVEL_DATA )
6888 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6889
6890 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6891 /* set CMR:13 to start transmit when
6892 * next GoAhead (abort) is received
6893 */
6894 info->cmr_value |= BIT13;
6895 }
6896
6897 /* begin loading the frame in the next available tx dma
6898 * buffer, remember it's starting location for setting
6899 * up tx dma operation
6900 */
6901 i = info->current_tx_buffer;
6902 info->start_tx_dma_buffer = i;
6903
6904 /* Setup the status and RCC (Frame Size) fields of the 1st */
6905 /* buffer entry in the transmit DMA buffer list. */
6906
6907 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6908 info->tx_buffer_list[i].rcc = BufferSize;
6909 info->tx_buffer_list[i].count = BufferSize;
6910
6911 /* Copy frame data from 1st source buffer to the DMA buffers. */
6912 /* The frame data may span multiple DMA buffers. */
6913
6914 while( BufferSize ){
6915 /* Get a pointer to next DMA buffer entry. */
6916 pBufEntry = &info->tx_buffer_list[i++];
6917
6918 if ( i == info->tx_buffer_count )
6919 i=0;
6920
6921 /* Calculate the number of bytes that can be copied from */
6922 /* the source buffer to this DMA buffer. */
6923 if ( BufferSize > DMABUFFERSIZE )
6924 Copycount = DMABUFFERSIZE;
6925 else
6926 Copycount = BufferSize;
6927
6928 /* Actually copy data from source buffer to DMA buffer. */
6929 /* Also set the data count for this individual DMA buffer. */
6930 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6931 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6932 else
6933 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6934
6935 pBufEntry->count = Copycount;
6936
6937 /* Advance source pointer and reduce remaining data count. */
6938 Buffer += Copycount;
6939 BufferSize -= Copycount;
6940
6941 ++info->tx_dma_buffers_used;
6942 }
6943
6944 /* remember next available tx dma buffer */
6945 info->current_tx_buffer = i;
6946
6947 } /* end of mgsl_load_tx_dma_buffer() */
6948
6949 /*
6950 * mgsl_register_test()
6951 *
6952 * Performs a register test of the 16C32.
6953 *
6954 * Arguments: info pointer to device instance data
6955 * Return Value: true if test passed, otherwise false
6956 */
6957 static bool mgsl_register_test( struct mgsl_struct *info )
6958 {
6959 static unsigned short BitPatterns[] =
6960 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6961 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6962 unsigned int i;
6963 bool rc = true;
6964 unsigned long flags;
6965
6966 spin_lock_irqsave(&info->irq_spinlock,flags);
6967 usc_reset(info);
6968
6969 /* Verify the reset state of some registers. */
6970
6971 if ( (usc_InReg( info, SICR ) != 0) ||
6972 (usc_InReg( info, IVR ) != 0) ||
6973 (usc_InDmaReg( info, DIVR ) != 0) ){
6974 rc = false;
6975 }
6976
6977 if ( rc ){
6978 /* Write bit patterns to various registers but do it out of */
6979 /* sync, then read back and verify values. */
6980
6981 for ( i = 0 ; i < Patterncount ; i++ ) {
6982 usc_OutReg( info, TC0R, BitPatterns[i] );
6983 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6984 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6985 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6986 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6987 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6988
6989 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6990 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6991 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6992 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6993 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6994 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6995 rc = false;
6996 break;
6997 }
6998 }
6999 }
7000
7001 usc_reset(info);
7002 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7003
7004 return rc;
7005
7006 } /* end of mgsl_register_test() */
7007
7008 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7009 *
7010 * Arguments: info pointer to device instance data
7011 * Return Value: true if test passed, otherwise false
7012 */
7013 static bool mgsl_irq_test( struct mgsl_struct *info )
7014 {
7015 unsigned long EndTime;
7016 unsigned long flags;
7017
7018 spin_lock_irqsave(&info->irq_spinlock,flags);
7019 usc_reset(info);
7020
7021 /*
7022 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7023 * The ISR sets irq_occurred to true.
7024 */
7025
7026 info->irq_occurred = false;
7027
7028 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7029 /* Enable INTEN (Port 6, Bit12) */
7030 /* This connects the IRQ request signal to the ISA bus */
7031 /* on the ISA adapter. This has no effect for the PCI adapter */
7032 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7033
7034 usc_EnableMasterIrqBit(info);
7035 usc_EnableInterrupts(info, IO_PIN);
7036 usc_ClearIrqPendingBits(info, IO_PIN);
7037
7038 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7039 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7040
7041 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7042
7043 EndTime=100;
7044 while( EndTime-- && !info->irq_occurred ) {
7045 msleep_interruptible(10);
7046 }
7047
7048 spin_lock_irqsave(&info->irq_spinlock,flags);
7049 usc_reset(info);
7050 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7051
7052 return info->irq_occurred;
7053
7054 } /* end of mgsl_irq_test() */
7055
7056 /* mgsl_dma_test()
7057 *
7058 * Perform a DMA test of the 16C32. A small frame is
7059 * transmitted via DMA from a transmit buffer to a receive buffer
7060 * using single buffer DMA mode.
7061 *
7062 * Arguments: info pointer to device instance data
7063 * Return Value: true if test passed, otherwise false
7064 */
7065 static bool mgsl_dma_test( struct mgsl_struct *info )
7066 {
7067 unsigned short FifoLevel;
7068 unsigned long phys_addr;
7069 unsigned int FrameSize;
7070 unsigned int i;
7071 char *TmpPtr;
7072 bool rc = true;
7073 unsigned short status=0;
7074 unsigned long EndTime;
7075 unsigned long flags;
7076 MGSL_PARAMS tmp_params;
7077
7078 /* save current port options */
7079 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7080 /* load default port options */
7081 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7082
7083 #define TESTFRAMESIZE 40
7084
7085 spin_lock_irqsave(&info->irq_spinlock,flags);
7086
7087 /* setup 16C32 for SDLC DMA transfer mode */
7088
7089 usc_reset(info);
7090 usc_set_sdlc_mode(info);
7091 usc_enable_loopback(info,1);
7092
7093 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7094 * field of the buffer entry after fetching buffer address. This
7095 * way we can detect a DMA failure for a DMA read (which should be
7096 * non-destructive to system memory) before we try and write to
7097 * memory (where a failure could corrupt system memory).
7098 */
7099
7100 /* Receive DMA mode Register (RDMR)
7101 *
7102 * <15..14> 11 DMA mode = Linked List Buffer mode
7103 * <13> 1 RSBinA/L = store Rx status Block in List entry
7104 * <12> 0 1 = Clear count of List Entry after fetching
7105 * <11..10> 00 Address mode = Increment
7106 * <9> 1 Terminate Buffer on RxBound
7107 * <8> 0 Bus Width = 16bits
7108 * <7..0> ? status Bits (write as 0s)
7109 *
7110 * 1110 0010 0000 0000 = 0xe200
7111 */
7112
7113 usc_OutDmaReg( info, RDMR, 0xe200 );
7114
7115 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7116
7117
7118 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7119
7120 FrameSize = TESTFRAMESIZE;
7121
7122 /* setup 1st transmit buffer entry: */
7123 /* with frame size and transmit control word */
7124
7125 info->tx_buffer_list[0].count = FrameSize;
7126 info->tx_buffer_list[0].rcc = FrameSize;
7127 info->tx_buffer_list[0].status = 0x4000;
7128
7129 /* build a transmit frame in 1st transmit DMA buffer */
7130
7131 TmpPtr = info->tx_buffer_list[0].virt_addr;
7132 for (i = 0; i < FrameSize; i++ )
7133 *TmpPtr++ = i;
7134
7135 /* setup 1st receive buffer entry: */
7136 /* clear status, set max receive buffer size */
7137
7138 info->rx_buffer_list[0].status = 0;
7139 info->rx_buffer_list[0].count = FrameSize + 4;
7140
7141 /* zero out the 1st receive buffer */
7142
7143 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7144
7145 /* Set count field of next buffer entries to prevent */
7146 /* 16C32 from using buffers after the 1st one. */
7147
7148 info->tx_buffer_list[1].count = 0;
7149 info->rx_buffer_list[1].count = 0;
7150
7151
7152 /***************************/
7153 /* Program 16C32 receiver. */
7154 /***************************/
7155
7156 spin_lock_irqsave(&info->irq_spinlock,flags);
7157
7158 /* setup DMA transfers */
7159 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7160
7161 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7162 phys_addr = info->rx_buffer_list[0].phys_entry;
7163 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7164 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7165
7166 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7167 usc_InDmaReg( info, RDMR );
7168 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7169
7170 /* Enable Receiver (RMR <1..0> = 10) */
7171 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7172
7173 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7174
7175
7176 /*************************************************************/
7177 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7178 /*************************************************************/
7179
7180 /* Wait 100ms for interrupt. */
7181 EndTime = jiffies + msecs_to_jiffies(100);
7182
7183 for(;;) {
7184 if (time_after(jiffies, EndTime)) {
7185 rc = false;
7186 break;
7187 }
7188
7189 spin_lock_irqsave(&info->irq_spinlock,flags);
7190 status = usc_InDmaReg( info, RDMR );
7191 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7192
7193 if ( !(status & BIT4) && (status & BIT5) ) {
7194 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7195 /* BUSY (BIT 5) is active (channel still active). */
7196 /* This means the buffer entry read has completed. */
7197 break;
7198 }
7199 }
7200
7201
7202 /******************************/
7203 /* Program 16C32 transmitter. */
7204 /******************************/
7205
7206 spin_lock_irqsave(&info->irq_spinlock,flags);
7207
7208 /* Program the Transmit Character Length Register (TCLR) */
7209 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7210
7211 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7212 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7213
7214 /* Program the address of the 1st DMA Buffer Entry in linked list */
7215
7216 phys_addr = info->tx_buffer_list[0].phys_entry;
7217 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7218 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7219
7220 /* unlatch Tx status bits, and start transmit channel. */
7221
7222 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7223 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7224
7225 /* wait for DMA controller to fill transmit FIFO */
7226
7227 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7228
7229 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7230
7231
7232 /**********************************/
7233 /* WAIT FOR TRANSMIT FIFO TO FILL */
7234 /**********************************/
7235
7236 /* Wait 100ms */
7237 EndTime = jiffies + msecs_to_jiffies(100);
7238
7239 for(;;) {
7240 if (time_after(jiffies, EndTime)) {
7241 rc = false;
7242 break;
7243 }
7244
7245 spin_lock_irqsave(&info->irq_spinlock,flags);
7246 FifoLevel = usc_InReg(info, TICR) >> 8;
7247 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7248
7249 if ( FifoLevel < 16 )
7250 break;
7251 else
7252 if ( FrameSize < 32 ) {
7253 /* This frame is smaller than the entire transmit FIFO */
7254 /* so wait for the entire frame to be loaded. */
7255 if ( FifoLevel <= (32 - FrameSize) )
7256 break;
7257 }
7258 }
7259
7260
7261 if ( rc )
7262 {
7263 /* Enable 16C32 transmitter. */
7264
7265 spin_lock_irqsave(&info->irq_spinlock,flags);
7266
7267 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7268 usc_TCmd( info, TCmd_SendFrame );
7269 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7270
7271 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7272
7273
7274 /******************************/
7275 /* WAIT FOR TRANSMIT COMPLETE */
7276 /******************************/
7277
7278 /* Wait 100ms */
7279 EndTime = jiffies + msecs_to_jiffies(100);
7280
7281 /* While timer not expired wait for transmit complete */
7282
7283 spin_lock_irqsave(&info->irq_spinlock,flags);
7284 status = usc_InReg( info, TCSR );
7285 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7286
7287 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7288 if (time_after(jiffies, EndTime)) {
7289 rc = false;
7290 break;
7291 }
7292
7293 spin_lock_irqsave(&info->irq_spinlock,flags);
7294 status = usc_InReg( info, TCSR );
7295 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7296 }
7297 }
7298
7299
7300 if ( rc ){
7301 /* CHECK FOR TRANSMIT ERRORS */
7302 if ( status & (BIT5 + BIT1) )
7303 rc = false;
7304 }
7305
7306 if ( rc ) {
7307 /* WAIT FOR RECEIVE COMPLETE */
7308
7309 /* Wait 100ms */
7310 EndTime = jiffies + msecs_to_jiffies(100);
7311
7312 /* Wait for 16C32 to write receive status to buffer entry. */
7313 status=info->rx_buffer_list[0].status;
7314 while ( status == 0 ) {
7315 if (time_after(jiffies, EndTime)) {
7316 rc = false;
7317 break;
7318 }
7319 status=info->rx_buffer_list[0].status;
7320 }
7321 }
7322
7323
7324 if ( rc ) {
7325 /* CHECK FOR RECEIVE ERRORS */
7326 status = info->rx_buffer_list[0].status;
7327
7328 if ( status & (BIT8 + BIT3 + BIT1) ) {
7329 /* receive error has occurred */
7330 rc = false;
7331 } else {
7332 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7333 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7334 rc = false;
7335 }
7336 }
7337 }
7338
7339 spin_lock_irqsave(&info->irq_spinlock,flags);
7340 usc_reset( info );
7341 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7342
7343 /* restore current port options */
7344 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7345
7346 return rc;
7347
7348 } /* end of mgsl_dma_test() */
7349
7350 /* mgsl_adapter_test()
7351 *
7352 * Perform the register, IRQ, and DMA tests for the 16C32.
7353 *
7354 * Arguments: info pointer to device instance data
7355 * Return Value: 0 if success, otherwise -ENODEV
7356 */
7357 static int mgsl_adapter_test( struct mgsl_struct *info )
7358 {
7359 if ( debug_level >= DEBUG_LEVEL_INFO )
7360 printk( "%s(%d):Testing device %s\n",
7361 __FILE__,__LINE__,info->device_name );
7362
7363 if ( !mgsl_register_test( info ) ) {
7364 info->init_error = DiagStatus_AddressFailure;
7365 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7366 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7367 return -ENODEV;
7368 }
7369
7370 if ( !mgsl_irq_test( info ) ) {
7371 info->init_error = DiagStatus_IrqFailure;
7372 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7373 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7374 return -ENODEV;
7375 }
7376
7377 if ( !mgsl_dma_test( info ) ) {
7378 info->init_error = DiagStatus_DmaFailure;
7379 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7380 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7381 return -ENODEV;
7382 }
7383
7384 if ( debug_level >= DEBUG_LEVEL_INFO )
7385 printk( "%s(%d):device %s passed diagnostics\n",
7386 __FILE__,__LINE__,info->device_name );
7387
7388 return 0;
7389
7390 } /* end of mgsl_adapter_test() */
7391
7392 /* mgsl_memory_test()
7393 *
7394 * Test the shared memory on a PCI adapter.
7395 *
7396 * Arguments: info pointer to device instance data
7397 * Return Value: true if test passed, otherwise false
7398 */
7399 static bool mgsl_memory_test( struct mgsl_struct *info )
7400 {
7401 static unsigned long BitPatterns[] =
7402 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7403 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7404 unsigned long i;
7405 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7406 unsigned long * TestAddr;
7407
7408 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7409 return true;
7410
7411 TestAddr = (unsigned long *)info->memory_base;
7412
7413 /* Test data lines with test pattern at one location. */
7414
7415 for ( i = 0 ; i < Patterncount ; i++ ) {
7416 *TestAddr = BitPatterns[i];
7417 if ( *TestAddr != BitPatterns[i] )
7418 return false;
7419 }
7420
7421 /* Test address lines with incrementing pattern over */
7422 /* entire address range. */
7423
7424 for ( i = 0 ; i < TestLimit ; i++ ) {
7425 *TestAddr = i * 4;
7426 TestAddr++;
7427 }
7428
7429 TestAddr = (unsigned long *)info->memory_base;
7430
7431 for ( i = 0 ; i < TestLimit ; i++ ) {
7432 if ( *TestAddr != i * 4 )
7433 return false;
7434 TestAddr++;
7435 }
7436
7437 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7438
7439 return true;
7440
7441 } /* End Of mgsl_memory_test() */
7442
7443
7444 /* mgsl_load_pci_memory()
7445 *
7446 * Load a large block of data into the PCI shared memory.
7447 * Use this instead of memcpy() or memmove() to move data
7448 * into the PCI shared memory.
7449 *
7450 * Notes:
7451 *
7452 * This function prevents the PCI9050 interface chip from hogging
7453 * the adapter local bus, which can starve the 16C32 by preventing
7454 * 16C32 bus master cycles.
7455 *
7456 * The PCI9050 documentation says that the 9050 will always release
7457 * control of the local bus after completing the current read
7458 * or write operation.
7459 *
7460 * It appears that as long as the PCI9050 write FIFO is full, the
7461 * PCI9050 treats all of the writes as a single burst transaction
7462 * and will not release the bus. This causes DMA latency problems
7463 * at high speeds when copying large data blocks to the shared
7464 * memory.
7465 *
7466 * This function in effect, breaks the a large shared memory write
7467 * into multiple transations by interleaving a shared memory read
7468 * which will flush the write FIFO and 'complete' the write
7469 * transation. This allows any pending DMA request to gain control
7470 * of the local bus in a timely fasion.
7471 *
7472 * Arguments:
7473 *
7474 * TargetPtr pointer to target address in PCI shared memory
7475 * SourcePtr pointer to source buffer for data
7476 * count count in bytes of data to copy
7477 *
7478 * Return Value: None
7479 */
7480 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7481 unsigned short count )
7482 {
7483 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7484 #define PCI_LOAD_INTERVAL 64
7485
7486 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7487 unsigned short Index;
7488 unsigned long Dummy;
7489
7490 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7491 {
7492 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7493 Dummy = *((volatile unsigned long *)TargetPtr);
7494 TargetPtr += PCI_LOAD_INTERVAL;
7495 SourcePtr += PCI_LOAD_INTERVAL;
7496 }
7497
7498 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7499
7500 } /* End Of mgsl_load_pci_memory() */
7501
7502 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7503 {
7504 int i;
7505 int linecount;
7506 if (xmit)
7507 printk("%s tx data:\n",info->device_name);
7508 else
7509 printk("%s rx data:\n",info->device_name);
7510
7511 while(count) {
7512 if (count > 16)
7513 linecount = 16;
7514 else
7515 linecount = count;
7516
7517 for(i=0;i<linecount;i++)
7518 printk("%02X ",(unsigned char)data[i]);
7519 for(;i<17;i++)
7520 printk(" ");
7521 for(i=0;i<linecount;i++) {
7522 if (data[i]>=040 && data[i]<=0176)
7523 printk("%c",data[i]);
7524 else
7525 printk(".");
7526 }
7527 printk("\n");
7528
7529 data += linecount;
7530 count -= linecount;
7531 }
7532 } /* end of mgsl_trace_block() */
7533
7534 /* mgsl_tx_timeout()
7535 *
7536 * called when HDLC frame times out
7537 * update stats and do tx completion processing
7538 *
7539 * Arguments: context pointer to device instance data
7540 * Return Value: None
7541 */
7542 static void mgsl_tx_timeout(unsigned long context)
7543 {
7544 struct mgsl_struct *info = (struct mgsl_struct*)context;
7545 unsigned long flags;
7546
7547 if ( debug_level >= DEBUG_LEVEL_INFO )
7548 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7549 __FILE__,__LINE__,info->device_name);
7550 if(info->tx_active &&
7551 (info->params.mode == MGSL_MODE_HDLC ||
7552 info->params.mode == MGSL_MODE_RAW) ) {
7553 info->icount.txtimeout++;
7554 }
7555 spin_lock_irqsave(&info->irq_spinlock,flags);
7556 info->tx_active = false;
7557 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7558
7559 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7560 usc_loopmode_cancel_transmit( info );
7561
7562 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7563
7564 #if SYNCLINK_GENERIC_HDLC
7565 if (info->netcount)
7566 hdlcdev_tx_done(info);
7567 else
7568 #endif
7569 mgsl_bh_transmit(info);
7570
7571 } /* end of mgsl_tx_timeout() */
7572
7573 /* signal that there are no more frames to send, so that
7574 * line is 'released' by echoing RxD to TxD when current
7575 * transmission is complete (or immediately if no tx in progress).
7576 */
7577 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7578 {
7579 unsigned long flags;
7580
7581 spin_lock_irqsave(&info->irq_spinlock,flags);
7582 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7583 if (info->tx_active)
7584 info->loopmode_send_done_requested = true;
7585 else
7586 usc_loopmode_send_done(info);
7587 }
7588 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7589
7590 return 0;
7591 }
7592
7593 /* release the line by echoing RxD to TxD
7594 * upon completion of a transmit frame
7595 */
7596 static void usc_loopmode_send_done( struct mgsl_struct * info )
7597 {
7598 info->loopmode_send_done_requested = false;
7599 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7600 info->cmr_value &= ~BIT13;
7601 usc_OutReg(info, CMR, info->cmr_value);
7602 }
7603
7604 /* abort a transmit in progress while in HDLC LoopMode
7605 */
7606 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7607 {
7608 /* reset tx dma channel and purge TxFifo */
7609 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7610 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7611 usc_loopmode_send_done( info );
7612 }
7613
7614 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7615 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7616 * we must clear CMR:13 to begin repeating TxData to RxData
7617 */
7618 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7619 {
7620 info->loopmode_insert_requested = true;
7621
7622 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7623 * begin repeating TxData on RxData (complete insertion)
7624 */
7625 usc_OutReg( info, RICR,
7626 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7627
7628 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7629 info->cmr_value |= BIT13;
7630 usc_OutReg(info, CMR, info->cmr_value);
7631 }
7632
7633 /* return 1 if station is inserted into the loop, otherwise 0
7634 */
7635 static int usc_loopmode_active( struct mgsl_struct * info)
7636 {
7637 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7638 }
7639
7640 #if SYNCLINK_GENERIC_HDLC
7641
7642 /**
7643 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7644 * set encoding and frame check sequence (FCS) options
7645 *
7646 * dev pointer to network device structure
7647 * encoding serial encoding setting
7648 * parity FCS setting
7649 *
7650 * returns 0 if success, otherwise error code
7651 */
7652 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7653 unsigned short parity)
7654 {
7655 struct mgsl_struct *info = dev_to_port(dev);
7656 unsigned char new_encoding;
7657 unsigned short new_crctype;
7658
7659 /* return error if TTY interface open */
7660 if (info->port.count)
7661 return -EBUSY;
7662
7663 switch (encoding)
7664 {
7665 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7666 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7667 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7668 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7669 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7670 default: return -EINVAL;
7671 }
7672
7673 switch (parity)
7674 {
7675 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7676 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7677 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7678 default: return -EINVAL;
7679 }
7680
7681 info->params.encoding = new_encoding;
7682 info->params.crc_type = new_crctype;
7683
7684 /* if network interface up, reprogram hardware */
7685 if (info->netcount)
7686 mgsl_program_hw(info);
7687
7688 return 0;
7689 }
7690
7691 /**
7692 * called by generic HDLC layer to send frame
7693 *
7694 * skb socket buffer containing HDLC frame
7695 * dev pointer to network device structure
7696 *
7697 * returns 0 if success, otherwise error code
7698 */
7699 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7700 {
7701 struct mgsl_struct *info = dev_to_port(dev);
7702 unsigned long flags;
7703
7704 if (debug_level >= DEBUG_LEVEL_INFO)
7705 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7706
7707 /* stop sending until this frame completes */
7708 netif_stop_queue(dev);
7709
7710 /* copy data to device buffers */
7711 info->xmit_cnt = skb->len;
7712 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7713
7714 /* update network statistics */
7715 dev->stats.tx_packets++;
7716 dev->stats.tx_bytes += skb->len;
7717
7718 /* done with socket buffer, so free it */
7719 dev_kfree_skb(skb);
7720
7721 /* save start time for transmit timeout detection */
7722 dev->trans_start = jiffies;
7723
7724 /* start hardware transmitter if necessary */
7725 spin_lock_irqsave(&info->irq_spinlock,flags);
7726 if (!info->tx_active)
7727 usc_start_transmitter(info);
7728 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7729
7730 return 0;
7731 }
7732
7733 /**
7734 * called by network layer when interface enabled
7735 * claim resources and initialize hardware
7736 *
7737 * dev pointer to network device structure
7738 *
7739 * returns 0 if success, otherwise error code
7740 */
7741 static int hdlcdev_open(struct net_device *dev)
7742 {
7743 struct mgsl_struct *info = dev_to_port(dev);
7744 int rc;
7745 unsigned long flags;
7746
7747 if (debug_level >= DEBUG_LEVEL_INFO)
7748 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7749
7750 /* generic HDLC layer open processing */
7751 if ((rc = hdlc_open(dev)))
7752 return rc;
7753
7754 /* arbitrate between network and tty opens */
7755 spin_lock_irqsave(&info->netlock, flags);
7756 if (info->port.count != 0 || info->netcount != 0) {
7757 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7758 spin_unlock_irqrestore(&info->netlock, flags);
7759 return -EBUSY;
7760 }
7761 info->netcount=1;
7762 spin_unlock_irqrestore(&info->netlock, flags);
7763
7764 /* claim resources and init adapter */
7765 if ((rc = startup(info)) != 0) {
7766 spin_lock_irqsave(&info->netlock, flags);
7767 info->netcount=0;
7768 spin_unlock_irqrestore(&info->netlock, flags);
7769 return rc;
7770 }
7771
7772 /* assert DTR and RTS, apply hardware settings */
7773 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7774 mgsl_program_hw(info);
7775
7776 /* enable network layer transmit */
7777 dev->trans_start = jiffies;
7778 netif_start_queue(dev);
7779
7780 /* inform generic HDLC layer of current DCD status */
7781 spin_lock_irqsave(&info->irq_spinlock, flags);
7782 usc_get_serial_signals(info);
7783 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7784 if (info->serial_signals & SerialSignal_DCD)
7785 netif_carrier_on(dev);
7786 else
7787 netif_carrier_off(dev);
7788 return 0;
7789 }
7790
7791 /**
7792 * called by network layer when interface is disabled
7793 * shutdown hardware and release resources
7794 *
7795 * dev pointer to network device structure
7796 *
7797 * returns 0 if success, otherwise error code
7798 */
7799 static int hdlcdev_close(struct net_device *dev)
7800 {
7801 struct mgsl_struct *info = dev_to_port(dev);
7802 unsigned long flags;
7803
7804 if (debug_level >= DEBUG_LEVEL_INFO)
7805 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7806
7807 netif_stop_queue(dev);
7808
7809 /* shutdown adapter and release resources */
7810 shutdown(info);
7811
7812 hdlc_close(dev);
7813
7814 spin_lock_irqsave(&info->netlock, flags);
7815 info->netcount=0;
7816 spin_unlock_irqrestore(&info->netlock, flags);
7817
7818 return 0;
7819 }
7820
7821 /**
7822 * called by network layer to process IOCTL call to network device
7823 *
7824 * dev pointer to network device structure
7825 * ifr pointer to network interface request structure
7826 * cmd IOCTL command code
7827 *
7828 * returns 0 if success, otherwise error code
7829 */
7830 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7831 {
7832 const size_t size = sizeof(sync_serial_settings);
7833 sync_serial_settings new_line;
7834 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7835 struct mgsl_struct *info = dev_to_port(dev);
7836 unsigned int flags;
7837
7838 if (debug_level >= DEBUG_LEVEL_INFO)
7839 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7840
7841 /* return error if TTY interface open */
7842 if (info->port.count)
7843 return -EBUSY;
7844
7845 if (cmd != SIOCWANDEV)
7846 return hdlc_ioctl(dev, ifr, cmd);
7847
7848 switch(ifr->ifr_settings.type) {
7849 case IF_GET_IFACE: /* return current sync_serial_settings */
7850
7851 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7852 if (ifr->ifr_settings.size < size) {
7853 ifr->ifr_settings.size = size; /* data size wanted */
7854 return -ENOBUFS;
7855 }
7856
7857 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7858 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7859 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7860 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7861
7862 switch (flags){
7863 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7864 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7865 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7866 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7867 default: new_line.clock_type = CLOCK_DEFAULT;
7868 }
7869
7870 new_line.clock_rate = info->params.clock_speed;
7871 new_line.loopback = info->params.loopback ? 1:0;
7872
7873 if (copy_to_user(line, &new_line, size))
7874 return -EFAULT;
7875 return 0;
7876
7877 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7878
7879 if(!capable(CAP_NET_ADMIN))
7880 return -EPERM;
7881 if (copy_from_user(&new_line, line, size))
7882 return -EFAULT;
7883
7884 switch (new_line.clock_type)
7885 {
7886 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7887 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7888 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7889 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7890 case CLOCK_DEFAULT: flags = info->params.flags &
7891 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7892 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7893 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7894 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7895 default: return -EINVAL;
7896 }
7897
7898 if (new_line.loopback != 0 && new_line.loopback != 1)
7899 return -EINVAL;
7900
7901 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7902 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7903 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7904 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7905 info->params.flags |= flags;
7906
7907 info->params.loopback = new_line.loopback;
7908
7909 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7910 info->params.clock_speed = new_line.clock_rate;
7911 else
7912 info->params.clock_speed = 0;
7913
7914 /* if network interface up, reprogram hardware */
7915 if (info->netcount)
7916 mgsl_program_hw(info);
7917 return 0;
7918
7919 default:
7920 return hdlc_ioctl(dev, ifr, cmd);
7921 }
7922 }
7923
7924 /**
7925 * called by network layer when transmit timeout is detected
7926 *
7927 * dev pointer to network device structure
7928 */
7929 static void hdlcdev_tx_timeout(struct net_device *dev)
7930 {
7931 struct mgsl_struct *info = dev_to_port(dev);
7932 unsigned long flags;
7933
7934 if (debug_level >= DEBUG_LEVEL_INFO)
7935 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7936
7937 dev->stats.tx_errors++;
7938 dev->stats.tx_aborted_errors++;
7939
7940 spin_lock_irqsave(&info->irq_spinlock,flags);
7941 usc_stop_transmitter(info);
7942 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7943
7944 netif_wake_queue(dev);
7945 }
7946
7947 /**
7948 * called by device driver when transmit completes
7949 * reenable network layer transmit if stopped
7950 *
7951 * info pointer to device instance information
7952 */
7953 static void hdlcdev_tx_done(struct mgsl_struct *info)
7954 {
7955 if (netif_queue_stopped(info->netdev))
7956 netif_wake_queue(info->netdev);
7957 }
7958
7959 /**
7960 * called by device driver when frame received
7961 * pass frame to network layer
7962 *
7963 * info pointer to device instance information
7964 * buf pointer to buffer contianing frame data
7965 * size count of data bytes in buf
7966 */
7967 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7968 {
7969 struct sk_buff *skb = dev_alloc_skb(size);
7970 struct net_device *dev = info->netdev;
7971
7972 if (debug_level >= DEBUG_LEVEL_INFO)
7973 printk("hdlcdev_rx(%s)\n", dev->name);
7974
7975 if (skb == NULL) {
7976 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7977 dev->name);
7978 dev->stats.rx_dropped++;
7979 return;
7980 }
7981
7982 memcpy(skb_put(skb, size), buf, size);
7983
7984 skb->protocol = hdlc_type_trans(skb, dev);
7985
7986 dev->stats.rx_packets++;
7987 dev->stats.rx_bytes += size;
7988
7989 netif_rx(skb);
7990 }
7991
7992 static const struct net_device_ops hdlcdev_ops = {
7993 .ndo_open = hdlcdev_open,
7994 .ndo_stop = hdlcdev_close,
7995 .ndo_change_mtu = hdlc_change_mtu,
7996 .ndo_start_xmit = hdlc_start_xmit,
7997 .ndo_do_ioctl = hdlcdev_ioctl,
7998 .ndo_tx_timeout = hdlcdev_tx_timeout,
7999 };
8000
8001 /**
8002 * called by device driver when adding device instance
8003 * do generic HDLC initialization
8004 *
8005 * info pointer to device instance information
8006 *
8007 * returns 0 if success, otherwise error code
8008 */
8009 static int hdlcdev_init(struct mgsl_struct *info)
8010 {
8011 int rc;
8012 struct net_device *dev;
8013 hdlc_device *hdlc;
8014
8015 /* allocate and initialize network and HDLC layer objects */
8016
8017 if (!(dev = alloc_hdlcdev(info))) {
8018 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8019 return -ENOMEM;
8020 }
8021
8022 /* for network layer reporting purposes only */
8023 dev->base_addr = info->io_base;
8024 dev->irq = info->irq_level;
8025 dev->dma = info->dma_level;
8026
8027 /* network layer callbacks and settings */
8028 dev->netdev_ops = &hdlcdev_ops;
8029 dev->watchdog_timeo = 10 * HZ;
8030 dev->tx_queue_len = 50;
8031
8032 /* generic HDLC layer callbacks and settings */
8033 hdlc = dev_to_hdlc(dev);
8034 hdlc->attach = hdlcdev_attach;
8035 hdlc->xmit = hdlcdev_xmit;
8036
8037 /* register objects with HDLC layer */
8038 if ((rc = register_hdlc_device(dev))) {
8039 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8040 free_netdev(dev);
8041 return rc;
8042 }
8043
8044 info->netdev = dev;
8045 return 0;
8046 }
8047
8048 /**
8049 * called by device driver when removing device instance
8050 * do generic HDLC cleanup
8051 *
8052 * info pointer to device instance information
8053 */
8054 static void hdlcdev_exit(struct mgsl_struct *info)
8055 {
8056 unregister_hdlc_device(info->netdev);
8057 free_netdev(info->netdev);
8058 info->netdev = NULL;
8059 }
8060
8061 #endif /* CONFIG_HDLC */
8062
8063
8064 static int __devinit synclink_init_one (struct pci_dev *dev,
8065 const struct pci_device_id *ent)
8066 {
8067 struct mgsl_struct *info;
8068
8069 if (pci_enable_device(dev)) {
8070 printk("error enabling pci device %p\n", dev);
8071 return -EIO;
8072 }
8073
8074 if (!(info = mgsl_allocate_device())) {
8075 printk("can't allocate device instance data.\n");
8076 return -EIO;
8077 }
8078
8079 /* Copy user configuration info to device instance data */
8080
8081 info->io_base = pci_resource_start(dev, 2);
8082 info->irq_level = dev->irq;
8083 info->phys_memory_base = pci_resource_start(dev, 3);
8084
8085 /* Because veremap only works on page boundaries we must map
8086 * a larger area than is actually implemented for the LCR
8087 * memory range. We map a full page starting at the page boundary.
8088 */
8089 info->phys_lcr_base = pci_resource_start(dev, 0);
8090 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8091 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8092
8093 info->bus_type = MGSL_BUS_TYPE_PCI;
8094 info->io_addr_size = 8;
8095 info->irq_flags = IRQF_SHARED;
8096
8097 if (dev->device == 0x0210) {
8098 /* Version 1 PCI9030 based universal PCI adapter */
8099 info->misc_ctrl_value = 0x007c4080;
8100 info->hw_version = 1;
8101 } else {
8102 /* Version 0 PCI9050 based 5V PCI adapter
8103 * A PCI9050 bug prevents reading LCR registers if
8104 * LCR base address bit 7 is set. Maintain shadow
8105 * value so we can write to LCR misc control reg.
8106 */
8107 info->misc_ctrl_value = 0x087e4546;
8108 info->hw_version = 0;
8109 }
8110
8111 mgsl_add_device(info);
8112
8113 return 0;
8114 }
8115
8116 static void __devexit synclink_remove_one (struct pci_dev *dev)
8117 {
8118 }
8119
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