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mfd: htc-i2cpld depends on GPIOLIB
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / pmac_zilog.c
blobf020de1cdd5035155bbb4f3c95ba847e81b1c52b
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/module.h>
46 #include <linux/tty.h>
47
48 #include <linux/tty_flip.h>
49 #include <linux/major.h>
50 #include <linux/string.h>
51 #include <linux/fcntl.h>
52 #include <linux/mm.h>
53 #include <linux/kernel.h>
54 #include <linux/delay.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
57 #include <linux/slab.h>
58 #include <linux/adb.h>
59 #include <linux/pmu.h>
60 #include <linux/bitops.h>
61 #include <linux/sysrq.h>
62 #include <linux/mutex.h>
63 #include <asm/sections.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66
67 #ifdef CONFIG_PPC_PMAC
68 #include <asm/prom.h>
69 #include <asm/machdep.h>
70 #include <asm/pmac_feature.h>
71 #include <asm/dbdma.h>
72 #include <asm/macio.h>
73 #else
74 #include <linux/platform_device.h>
75 #define of_machine_is_compatible(x) (0)
76 #endif
77
78 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79 #define SUPPORT_SYSRQ
80 #endif
81
82 #include <linux/serial.h>
83 #include <linux/serial_core.h>
84
85 #include "pmac_zilog.h"
86
87 /* Not yet implemented */
88 #undef HAS_DBDMA
89
90 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
91 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
92 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
93 MODULE_LICENSE("GPL");
94
95 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
96 #define PMACZILOG_MAJOR TTY_MAJOR
97 #define PMACZILOG_MINOR 64
98 #define PMACZILOG_NAME "ttyS"
99 #else
100 #define PMACZILOG_MAJOR 204
101 #define PMACZILOG_MINOR 192
102 #define PMACZILOG_NAME "ttyPZ"
103 #endif
104
105
106 /*
107 * For the sake of early serial console, we can do a pre-probe
108 * (optional) of the ports at rather early boot time.
109 */
110 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
111 static int pmz_ports_count;
112 static DEFINE_MUTEX(pmz_irq_mutex);
113
114 static struct uart_driver pmz_uart_reg = {
115 .owner = THIS_MODULE,
116 .driver_name = PMACZILOG_NAME,
117 .dev_name = PMACZILOG_NAME,
118 .major = PMACZILOG_MAJOR,
119 .minor = PMACZILOG_MINOR,
120 };
121
122
123 /*
124 * Load all registers to reprogram the port
125 * This function must only be called when the TX is not busy. The UART
126 * port lock must be held and local interrupts disabled.
127 */
128 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
129 {
130 int i;
131
132 if (ZS_IS_ASLEEP(uap))
133 return;
134
135 /* Let pending transmits finish. */
136 for (i = 0; i < 1000; i++) {
137 unsigned char stat = read_zsreg(uap, R1);
138 if (stat & ALL_SNT)
139 break;
140 udelay(100);
141 }
142
143 ZS_CLEARERR(uap);
144 zssync(uap);
145 ZS_CLEARFIFO(uap);
146 zssync(uap);
147 ZS_CLEARERR(uap);
148
149 /* Disable all interrupts. */
150 write_zsreg(uap, R1,
151 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
152
153 /* Set parity, sync config, stop bits, and clock divisor. */
154 write_zsreg(uap, R4, regs[R4]);
155
156 /* Set misc. TX/RX control bits. */
157 write_zsreg(uap, R10, regs[R10]);
158
159 /* Set TX/RX controls sans the enable bits. */
160 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
161 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
162
163 /* now set R7 "prime" on ESCC */
164 write_zsreg(uap, R15, regs[R15] | EN85C30);
165 write_zsreg(uap, R7, regs[R7P]);
166
167 /* make sure we use R7 "non-prime" on ESCC */
168 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
169
170 /* Synchronous mode config. */
171 write_zsreg(uap, R6, regs[R6]);
172 write_zsreg(uap, R7, regs[R7]);
173
174 /* Disable baud generator. */
175 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
176
177 /* Clock mode control. */
178 write_zsreg(uap, R11, regs[R11]);
179
180 /* Lower and upper byte of baud rate generator divisor. */
181 write_zsreg(uap, R12, regs[R12]);
182 write_zsreg(uap, R13, regs[R13]);
183
184 /* Now rewrite R14, with BRENAB (if set). */
185 write_zsreg(uap, R14, regs[R14]);
186
187 /* Reset external status interrupts. */
188 write_zsreg(uap, R0, RES_EXT_INT);
189 write_zsreg(uap, R0, RES_EXT_INT);
190
191 /* Rewrite R3/R5, this time without enables masked. */
192 write_zsreg(uap, R3, regs[R3]);
193 write_zsreg(uap, R5, regs[R5]);
194
195 /* Rewrite R1, this time without IRQ enabled masked. */
196 write_zsreg(uap, R1, regs[R1]);
197
198 /* Enable interrupts */
199 write_zsreg(uap, R9, regs[R9]);
200 }
201
202 /*
203 * We do like sunzilog to avoid disrupting pending Tx
204 * Reprogram the Zilog channel HW registers with the copies found in the
205 * software state struct. If the transmitter is busy, we defer this update
206 * until the next TX complete interrupt. Else, we do it right now.
207 *
208 * The UART port lock must be held and local interrupts disabled.
209 */
210 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
211 {
212 if (!ZS_REGS_HELD(uap)) {
213 if (ZS_TX_ACTIVE(uap)) {
214 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
215 } else {
216 pmz_debug("pmz: maybe_update_regs: updating\n");
217 pmz_load_zsregs(uap, uap->curregs);
218 }
219 }
220 }
221
222 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
223 {
224 struct tty_struct *tty = NULL;
225 unsigned char ch, r1, drop, error, flag;
226 int loops = 0;
227
228 /* The interrupt can be enabled when the port isn't open, typically
229 * that happens when using one port is open and the other closed (stale
230 * interrupt) or when one port is used as a console.
231 */
232 if (!ZS_IS_OPEN(uap)) {
233 pmz_debug("pmz: draining input\n");
234 /* Port is closed, drain input data */
235 for (;;) {
236 if ((++loops) > 1000)
237 goto flood;
238 (void)read_zsreg(uap, R1);
239 write_zsreg(uap, R0, ERR_RES);
240 (void)read_zsdata(uap);
241 ch = read_zsreg(uap, R0);
242 if (!(ch & Rx_CH_AV))
243 break;
244 }
245 return NULL;
246 }
247
248 /* Sanity check, make sure the old bug is no longer happening */
249 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
250 WARN_ON(1);
251 (void)read_zsdata(uap);
252 return NULL;
253 }
254 tty = uap->port.state->port.tty;
255
256 while (1) {
257 error = 0;
258 drop = 0;
259
260 r1 = read_zsreg(uap, R1);
261 ch = read_zsdata(uap);
262
263 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
264 write_zsreg(uap, R0, ERR_RES);
265 zssync(uap);
266 }
267
268 ch &= uap->parity_mask;
269 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
270 uap->flags &= ~PMACZILOG_FLAG_BREAK;
271 }
272
273 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
274 #ifdef USE_CTRL_O_SYSRQ
275 /* Handle the SysRq ^O Hack */
276 if (ch == '\x0f') {
277 uap->port.sysrq = jiffies + HZ*5;
278 goto next_char;
279 }
280 #endif /* USE_CTRL_O_SYSRQ */
281 if (uap->port.sysrq) {
282 int swallow;
283 spin_unlock(&uap->port.lock);
284 swallow = uart_handle_sysrq_char(&uap->port, ch);
285 spin_lock(&uap->port.lock);
286 if (swallow)
287 goto next_char;
288 }
289 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
290
291 /* A real serial line, record the character and status. */
292 if (drop)
293 goto next_char;
294
295 flag = TTY_NORMAL;
296 uap->port.icount.rx++;
297
298 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
299 error = 1;
300 if (r1 & BRK_ABRT) {
301 pmz_debug("pmz: got break !\n");
302 r1 &= ~(PAR_ERR | CRC_ERR);
303 uap->port.icount.brk++;
304 if (uart_handle_break(&uap->port))
305 goto next_char;
306 }
307 else if (r1 & PAR_ERR)
308 uap->port.icount.parity++;
309 else if (r1 & CRC_ERR)
310 uap->port.icount.frame++;
311 if (r1 & Rx_OVR)
312 uap->port.icount.overrun++;
313 r1 &= uap->port.read_status_mask;
314 if (r1 & BRK_ABRT)
315 flag = TTY_BREAK;
316 else if (r1 & PAR_ERR)
317 flag = TTY_PARITY;
318 else if (r1 & CRC_ERR)
319 flag = TTY_FRAME;
320 }
321
322 if (uap->port.ignore_status_mask == 0xff ||
323 (r1 & uap->port.ignore_status_mask) == 0) {
324 tty_insert_flip_char(tty, ch, flag);
325 }
326 if (r1 & Rx_OVR)
327 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
328 next_char:
329 /* We can get stuck in an infinite loop getting char 0 when the
330 * line is in a wrong HW state, we break that here.
331 * When that happens, I disable the receive side of the driver.
332 * Note that what I've been experiencing is a real irq loop where
333 * I'm getting flooded regardless of the actual port speed.
334 * Something stange is going on with the HW
335 */
336 if ((++loops) > 1000)
337 goto flood;
338 ch = read_zsreg(uap, R0);
339 if (!(ch & Rx_CH_AV))
340 break;
341 }
342
343 return tty;
344 flood:
345 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
346 write_zsreg(uap, R1, uap->curregs[R1]);
347 zssync(uap);
348 pmz_error("pmz: rx irq flood !\n");
349 return tty;
350 }
351
352 static void pmz_status_handle(struct uart_pmac_port *uap)
353 {
354 unsigned char status;
355
356 status = read_zsreg(uap, R0);
357 write_zsreg(uap, R0, RES_EXT_INT);
358 zssync(uap);
359
360 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
361 if (status & SYNC_HUNT)
362 uap->port.icount.dsr++;
363
364 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
365 * But it does not tell us which bit has changed, we have to keep
366 * track of this ourselves.
367 * The CTS input is inverted for some reason. -- paulus
368 */
369 if ((status ^ uap->prev_status) & DCD)
370 uart_handle_dcd_change(&uap->port,
371 (status & DCD));
372 if ((status ^ uap->prev_status) & CTS)
373 uart_handle_cts_change(&uap->port,
374 !(status & CTS));
375
376 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
377 }
378
379 if (status & BRK_ABRT)
380 uap->flags |= PMACZILOG_FLAG_BREAK;
381
382 uap->prev_status = status;
383 }
384
385 static void pmz_transmit_chars(struct uart_pmac_port *uap)
386 {
387 struct circ_buf *xmit;
388
389 if (ZS_IS_ASLEEP(uap))
390 return;
391 if (ZS_IS_CONS(uap)) {
392 unsigned char status = read_zsreg(uap, R0);
393
394 /* TX still busy? Just wait for the next TX done interrupt.
395 *
396 * It can occur because of how we do serial console writes. It would
397 * be nice to transmit console writes just like we normally would for
398 * a TTY line. (ie. buffered and TX interrupt driven). That is not
399 * easy because console writes cannot sleep. One solution might be
400 * to poll on enough port->xmit space becomming free. -DaveM
401 */
402 if (!(status & Tx_BUF_EMP))
403 return;
404 }
405
406 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
407
408 if (ZS_REGS_HELD(uap)) {
409 pmz_load_zsregs(uap, uap->curregs);
410 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
411 }
412
413 if (ZS_TX_STOPPED(uap)) {
414 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
415 goto ack_tx_int;
416 }
417
418 /* Under some circumstances, we see interrupts reported for
419 * a closed channel. The interrupt mask in R1 is clear, but
420 * R3 still signals the interrupts and we see them when taking
421 * an interrupt for the other channel (this could be a qemu
422 * bug but since the ESCC doc doesn't specify precsiely whether
423 * R3 interrup status bits are masked by R1 interrupt enable
424 * bits, better safe than sorry). --BenH.
425 */
426 if (!ZS_IS_OPEN(uap))
427 goto ack_tx_int;
428
429 if (uap->port.x_char) {
430 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
431 write_zsdata(uap, uap->port.x_char);
432 zssync(uap);
433 uap->port.icount.tx++;
434 uap->port.x_char = 0;
435 return;
436 }
437
438 if (uap->port.state == NULL)
439 goto ack_tx_int;
440 xmit = &uap->port.state->xmit;
441 if (uart_circ_empty(xmit)) {
442 uart_write_wakeup(&uap->port);
443 goto ack_tx_int;
444 }
445 if (uart_tx_stopped(&uap->port))
446 goto ack_tx_int;
447
448 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
449 write_zsdata(uap, xmit->buf[xmit->tail]);
450 zssync(uap);
451
452 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
453 uap->port.icount.tx++;
454
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(&uap->port);
457
458 return;
459
460 ack_tx_int:
461 write_zsreg(uap, R0, RES_Tx_P);
462 zssync(uap);
463 }
464
465 /* Hrm... we register that twice, fixme later.... */
466 static irqreturn_t pmz_interrupt(int irq, void *dev_id)
467 {
468 struct uart_pmac_port *uap = dev_id;
469 struct uart_pmac_port *uap_a;
470 struct uart_pmac_port *uap_b;
471 int rc = IRQ_NONE;
472 struct tty_struct *tty;
473 u8 r3;
474
475 uap_a = pmz_get_port_A(uap);
476 uap_b = uap_a->mate;
477
478 spin_lock(&uap_a->port.lock);
479 r3 = read_zsreg(uap_a, R3);
480
481 #ifdef DEBUG_HARD
482 pmz_debug("irq, r3: %x\n", r3);
483 #endif
484 /* Channel A */
485 tty = NULL;
486 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
487 write_zsreg(uap_a, R0, RES_H_IUS);
488 zssync(uap_a);
489 if (r3 & CHAEXT)
490 pmz_status_handle(uap_a);
491 if (r3 & CHARxIP)
492 tty = pmz_receive_chars(uap_a);
493 if (r3 & CHATxIP)
494 pmz_transmit_chars(uap_a);
495 rc = IRQ_HANDLED;
496 }
497 spin_unlock(&uap_a->port.lock);
498 if (tty != NULL)
499 tty_flip_buffer_push(tty);
500
501 if (uap_b->node == NULL)
502 goto out;
503
504 spin_lock(&uap_b->port.lock);
505 tty = NULL;
506 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
507 write_zsreg(uap_b, R0, RES_H_IUS);
508 zssync(uap_b);
509 if (r3 & CHBEXT)
510 pmz_status_handle(uap_b);
511 if (r3 & CHBRxIP)
512 tty = pmz_receive_chars(uap_b);
513 if (r3 & CHBTxIP)
514 pmz_transmit_chars(uap_b);
515 rc = IRQ_HANDLED;
516 }
517 spin_unlock(&uap_b->port.lock);
518 if (tty != NULL)
519 tty_flip_buffer_push(tty);
520
521 out:
522 #ifdef DEBUG_HARD
523 pmz_debug("irq done.\n");
524 #endif
525 return rc;
526 }
527
528 /*
529 * Peek the status register, lock not held by caller
530 */
531 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
532 {
533 unsigned long flags;
534 u8 status;
535
536 spin_lock_irqsave(&uap->port.lock, flags);
537 status = read_zsreg(uap, R0);
538 spin_unlock_irqrestore(&uap->port.lock, flags);
539
540 return status;
541 }
542
543 /*
544 * Check if transmitter is empty
545 * The port lock is not held.
546 */
547 static unsigned int pmz_tx_empty(struct uart_port *port)
548 {
549 struct uart_pmac_port *uap = to_pmz(port);
550 unsigned char status;
551
552 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
553 return TIOCSER_TEMT;
554
555 status = pmz_peek_status(to_pmz(port));
556 if (status & Tx_BUF_EMP)
557 return TIOCSER_TEMT;
558 return 0;
559 }
560
561 /*
562 * Set Modem Control (RTS & DTR) bits
563 * The port lock is held and interrupts are disabled.
564 * Note: Shall we really filter out RTS on external ports or
565 * should that be dealt at higher level only ?
566 */
567 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
568 {
569 struct uart_pmac_port *uap = to_pmz(port);
570 unsigned char set_bits, clear_bits;
571
572 /* Do nothing for irda for now... */
573 if (ZS_IS_IRDA(uap))
574 return;
575 /* We get called during boot with a port not up yet */
576 if (ZS_IS_ASLEEP(uap) ||
577 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
578 return;
579
580 set_bits = clear_bits = 0;
581
582 if (ZS_IS_INTMODEM(uap)) {
583 if (mctrl & TIOCM_RTS)
584 set_bits |= RTS;
585 else
586 clear_bits |= RTS;
587 }
588 if (mctrl & TIOCM_DTR)
589 set_bits |= DTR;
590 else
591 clear_bits |= DTR;
592
593 /* NOTE: Not subject to 'transmitter active' rule. */
594 uap->curregs[R5] |= set_bits;
595 uap->curregs[R5] &= ~clear_bits;
596 if (ZS_IS_ASLEEP(uap))
597 return;
598 write_zsreg(uap, R5, uap->curregs[R5]);
599 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
600 set_bits, clear_bits, uap->curregs[R5]);
601 zssync(uap);
602 }
603
604 /*
605 * Get Modem Control bits (only the input ones, the core will
606 * or that with a cached value of the control ones)
607 * The port lock is held and interrupts are disabled.
608 */
609 static unsigned int pmz_get_mctrl(struct uart_port *port)
610 {
611 struct uart_pmac_port *uap = to_pmz(port);
612 unsigned char status;
613 unsigned int ret;
614
615 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
616 return 0;
617
618 status = read_zsreg(uap, R0);
619
620 ret = 0;
621 if (status & DCD)
622 ret |= TIOCM_CAR;
623 if (status & SYNC_HUNT)
624 ret |= TIOCM_DSR;
625 if (!(status & CTS))
626 ret |= TIOCM_CTS;
627
628 return ret;
629 }
630
631 /*
632 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
633 * though for DMA, we will have to do a bit more.
634 * The port lock is held and interrupts are disabled.
635 */
636 static void pmz_stop_tx(struct uart_port *port)
637 {
638 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
639 }
640
641 /*
642 * Kick the Tx side.
643 * The port lock is held and interrupts are disabled.
644 */
645 static void pmz_start_tx(struct uart_port *port)
646 {
647 struct uart_pmac_port *uap = to_pmz(port);
648 unsigned char status;
649
650 pmz_debug("pmz: start_tx()\n");
651
652 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
653 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
654
655 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
656 return;
657
658 status = read_zsreg(uap, R0);
659
660 /* TX busy? Just wait for the TX done interrupt. */
661 if (!(status & Tx_BUF_EMP))
662 return;
663
664 /* Send the first character to jump-start the TX done
665 * IRQ sending engine.
666 */
667 if (port->x_char) {
668 write_zsdata(uap, port->x_char);
669 zssync(uap);
670 port->icount.tx++;
671 port->x_char = 0;
672 } else {
673 struct circ_buf *xmit = &port->state->xmit;
674
675 write_zsdata(uap, xmit->buf[xmit->tail]);
676 zssync(uap);
677 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
678 port->icount.tx++;
679
680 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
681 uart_write_wakeup(&uap->port);
682 }
683 pmz_debug("pmz: start_tx() done.\n");
684 }
685
686 /*
687 * Stop Rx side, basically disable emitting of
688 * Rx interrupts on the port. We don't disable the rx
689 * side of the chip proper though
690 * The port lock is held.
691 */
692 static void pmz_stop_rx(struct uart_port *port)
693 {
694 struct uart_pmac_port *uap = to_pmz(port);
695
696 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
697 return;
698
699 pmz_debug("pmz: stop_rx()()\n");
700
701 /* Disable all RX interrupts. */
702 uap->curregs[R1] &= ~RxINT_MASK;
703 pmz_maybe_update_regs(uap);
704
705 pmz_debug("pmz: stop_rx() done.\n");
706 }
707
708 /*
709 * Enable modem status change interrupts
710 * The port lock is held.
711 */
712 static void pmz_enable_ms(struct uart_port *port)
713 {
714 struct uart_pmac_port *uap = to_pmz(port);
715 unsigned char new_reg;
716
717 if (ZS_IS_IRDA(uap) || uap->node == NULL)
718 return;
719 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
720 if (new_reg != uap->curregs[R15]) {
721 uap->curregs[R15] = new_reg;
722
723 if (ZS_IS_ASLEEP(uap))
724 return;
725 /* NOTE: Not subject to 'transmitter active' rule. */
726 write_zsreg(uap, R15, uap->curregs[R15]);
727 }
728 }
729
730 /*
731 * Control break state emission
732 * The port lock is not held.
733 */
734 static void pmz_break_ctl(struct uart_port *port, int break_state)
735 {
736 struct uart_pmac_port *uap = to_pmz(port);
737 unsigned char set_bits, clear_bits, new_reg;
738 unsigned long flags;
739
740 if (uap->node == NULL)
741 return;
742 set_bits = clear_bits = 0;
743
744 if (break_state)
745 set_bits |= SND_BRK;
746 else
747 clear_bits |= SND_BRK;
748
749 spin_lock_irqsave(&port->lock, flags);
750
751 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
752 if (new_reg != uap->curregs[R5]) {
753 uap->curregs[R5] = new_reg;
754
755 /* NOTE: Not subject to 'transmitter active' rule. */
756 if (ZS_IS_ASLEEP(uap))
757 return;
758 write_zsreg(uap, R5, uap->curregs[R5]);
759 }
760
761 spin_unlock_irqrestore(&port->lock, flags);
762 }
763
764 #ifdef CONFIG_PPC_PMAC
765
766 /*
767 * Turn power on or off to the SCC and associated stuff
768 * (port drivers, modem, IR port, etc.)
769 * Returns the number of milliseconds we should wait before
770 * trying to use the port.
771 */
772 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
773 {
774 int delay = 0;
775 int rc;
776
777 if (state) {
778 rc = pmac_call_feature(
779 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
780 pmz_debug("port power on result: %d\n", rc);
781 if (ZS_IS_INTMODEM(uap)) {
782 rc = pmac_call_feature(
783 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
784 delay = 2500; /* wait for 2.5s before using */
785 pmz_debug("modem power result: %d\n", rc);
786 }
787 } else {
788 /* TODO: Make that depend on a timer, don't power down
789 * immediately
790 */
791 if (ZS_IS_INTMODEM(uap)) {
792 rc = pmac_call_feature(
793 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
794 pmz_debug("port power off result: %d\n", rc);
795 }
796 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
797 }
798 return delay;
799 }
800
801 #else
802
803 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
804 {
805 return 0;
806 }
807
808 #endif /* !CONFIG_PPC_PMAC */
809
810 /*
811 * FixZeroBug....Works around a bug in the SCC receving channel.
812 * Inspired from Darwin code, 15 Sept. 2000 -DanM
813 *
814 * The following sequence prevents a problem that is seen with O'Hare ASICs
815 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
816 * at the input to the receiver becomes 'stuck' and locks up the receiver.
817 * This problem can occur as a result of a zero bit at the receiver input
818 * coincident with any of the following events:
819 *
820 * The SCC is initialized (hardware or software).
821 * A framing error is detected.
822 * The clocking option changes from synchronous or X1 asynchronous
823 * clocking to X16, X32, or X64 asynchronous clocking.
824 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
825 *
826 * This workaround attempts to recover from the lockup condition by placing
827 * the SCC in synchronous loopback mode with a fast clock before programming
828 * any of the asynchronous modes.
829 */
830 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
831 {
832 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
833 zssync(uap);
834 udelay(10);
835 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
836 zssync(uap);
837
838 write_zsreg(uap, 4, X1CLK | MONSYNC);
839 write_zsreg(uap, 3, Rx8);
840 write_zsreg(uap, 5, Tx8 | RTS);
841 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
842 write_zsreg(uap, 11, RCBR | TCBR);
843 write_zsreg(uap, 12, 0);
844 write_zsreg(uap, 13, 0);
845 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
846 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
847 write_zsreg(uap, 3, Rx8 | RxENABLE);
848 write_zsreg(uap, 0, RES_EXT_INT);
849 write_zsreg(uap, 0, RES_EXT_INT);
850 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
851
852 /* The channel should be OK now, but it is probably receiving
853 * loopback garbage.
854 * Switch to asynchronous mode, disable the receiver,
855 * and discard everything in the receive buffer.
856 */
857 write_zsreg(uap, 9, NV);
858 write_zsreg(uap, 4, X16CLK | SB_MASK);
859 write_zsreg(uap, 3, Rx8);
860
861 while (read_zsreg(uap, 0) & Rx_CH_AV) {
862 (void)read_zsreg(uap, 8);
863 write_zsreg(uap, 0, RES_EXT_INT);
864 write_zsreg(uap, 0, ERR_RES);
865 }
866 }
867
868 /*
869 * Real startup routine, powers up the hardware and sets up
870 * the SCC. Returns a delay in ms where you need to wait before
871 * actually using the port, this is typically the internal modem
872 * powerup delay. This routine expect the lock to be taken.
873 */
874 static int __pmz_startup(struct uart_pmac_port *uap)
875 {
876 int pwr_delay = 0;
877
878 memset(&uap->curregs, 0, sizeof(uap->curregs));
879
880 /* Power up the SCC & underlying hardware (modem/irda) */
881 pwr_delay = pmz_set_scc_power(uap, 1);
882
883 /* Nice buggy HW ... */
884 pmz_fix_zero_bug_scc(uap);
885
886 /* Reset the channel */
887 uap->curregs[R9] = 0;
888 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
889 zssync(uap);
890 udelay(10);
891 write_zsreg(uap, 9, 0);
892 zssync(uap);
893
894 /* Clear the interrupt registers */
895 write_zsreg(uap, R1, 0);
896 write_zsreg(uap, R0, ERR_RES);
897 write_zsreg(uap, R0, ERR_RES);
898 write_zsreg(uap, R0, RES_H_IUS);
899 write_zsreg(uap, R0, RES_H_IUS);
900
901 /* Setup some valid baud rate */
902 uap->curregs[R4] = X16CLK | SB1;
903 uap->curregs[R3] = Rx8;
904 uap->curregs[R5] = Tx8 | RTS;
905 if (!ZS_IS_IRDA(uap))
906 uap->curregs[R5] |= DTR;
907 uap->curregs[R12] = 0;
908 uap->curregs[R13] = 0;
909 uap->curregs[R14] = BRENAB;
910
911 /* Clear handshaking, enable BREAK interrupts */
912 uap->curregs[R15] = BRKIE;
913
914 /* Master interrupt enable */
915 uap->curregs[R9] |= NV | MIE;
916
917 pmz_load_zsregs(uap, uap->curregs);
918
919 /* Enable receiver and transmitter. */
920 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
921 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
922
923 /* Remember status for DCD/CTS changes */
924 uap->prev_status = read_zsreg(uap, R0);
925
926 return pwr_delay;
927 }
928
929 static void pmz_irda_reset(struct uart_pmac_port *uap)
930 {
931 uap->curregs[R5] |= DTR;
932 write_zsreg(uap, R5, uap->curregs[R5]);
933 zssync(uap);
934 mdelay(110);
935 uap->curregs[R5] &= ~DTR;
936 write_zsreg(uap, R5, uap->curregs[R5]);
937 zssync(uap);
938 mdelay(10);
939 }
940
941 /*
942 * This is the "normal" startup routine, using the above one
943 * wrapped with the lock and doing a schedule delay
944 */
945 static int pmz_startup(struct uart_port *port)
946 {
947 struct uart_pmac_port *uap = to_pmz(port);
948 unsigned long flags;
949 int pwr_delay = 0;
950
951 pmz_debug("pmz: startup()\n");
952
953 if (ZS_IS_ASLEEP(uap))
954 return -EAGAIN;
955 if (uap->node == NULL)
956 return -ENODEV;
957
958 mutex_lock(&pmz_irq_mutex);
959
960 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
961
962 /* A console is never powered down. Else, power up and
963 * initialize the chip
964 */
965 if (!ZS_IS_CONS(uap)) {
966 spin_lock_irqsave(&port->lock, flags);
967 pwr_delay = __pmz_startup(uap);
968 spin_unlock_irqrestore(&port->lock, flags);
969 }
970
971 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
972 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
973 "SCC", uap)) {
974 pmz_error("Unable to register zs interrupt handler.\n");
975 pmz_set_scc_power(uap, 0);
976 mutex_unlock(&pmz_irq_mutex);
977 return -ENXIO;
978 }
979
980 mutex_unlock(&pmz_irq_mutex);
981
982 /* Right now, we deal with delay by blocking here, I'll be
983 * smarter later on
984 */
985 if (pwr_delay != 0) {
986 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
987 msleep(pwr_delay);
988 }
989
990 /* IrDA reset is done now */
991 if (ZS_IS_IRDA(uap))
992 pmz_irda_reset(uap);
993
994 /* Enable interrupts emission from the chip */
995 spin_lock_irqsave(&port->lock, flags);
996 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
997 if (!ZS_IS_EXTCLK(uap))
998 uap->curregs[R1] |= EXT_INT_ENAB;
999 write_zsreg(uap, R1, uap->curregs[R1]);
1000 spin_unlock_irqrestore(&port->lock, flags);
1001
1002 pmz_debug("pmz: startup() done.\n");
1003
1004 return 0;
1005 }
1006
1007 static void pmz_shutdown(struct uart_port *port)
1008 {
1009 struct uart_pmac_port *uap = to_pmz(port);
1010 unsigned long flags;
1011
1012 pmz_debug("pmz: shutdown()\n");
1013
1014 if (uap->node == NULL)
1015 return;
1016
1017 mutex_lock(&pmz_irq_mutex);
1018
1019 /* Release interrupt handler */
1020 free_irq(uap->port.irq, uap);
1021
1022 spin_lock_irqsave(&port->lock, flags);
1023
1024 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1025
1026 if (!ZS_IS_OPEN(uap->mate))
1027 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1028
1029 /* Disable interrupts */
1030 if (!ZS_IS_ASLEEP(uap)) {
1031 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1032 write_zsreg(uap, R1, uap->curregs[R1]);
1033 zssync(uap);
1034 }
1035
1036 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1037 spin_unlock_irqrestore(&port->lock, flags);
1038 mutex_unlock(&pmz_irq_mutex);
1039 return;
1040 }
1041
1042 /* Disable receiver and transmitter. */
1043 uap->curregs[R3] &= ~RxENABLE;
1044 uap->curregs[R5] &= ~TxENABLE;
1045
1046 /* Disable all interrupts and BRK assertion. */
1047 uap->curregs[R5] &= ~SND_BRK;
1048 pmz_maybe_update_regs(uap);
1049
1050 /* Shut the chip down */
1051 pmz_set_scc_power(uap, 0);
1052
1053 spin_unlock_irqrestore(&port->lock, flags);
1054
1055 mutex_unlock(&pmz_irq_mutex);
1056
1057 pmz_debug("pmz: shutdown() done.\n");
1058 }
1059
1060 /* Shared by TTY driver and serial console setup. The port lock is held
1061 * and local interrupts are disabled.
1062 */
1063 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1064 unsigned int iflag, unsigned long baud)
1065 {
1066 int brg;
1067
1068 /* Switch to external clocking for IrDA high clock rates. That
1069 * code could be re-used for Midi interfaces with different
1070 * multipliers
1071 */
1072 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1073 uap->curregs[R4] = X1CLK;
1074 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1075 uap->curregs[R14] = 0; /* BRG off */
1076 uap->curregs[R12] = 0;
1077 uap->curregs[R13] = 0;
1078 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1079 } else {
1080 switch (baud) {
1081 case ZS_CLOCK/16: /* 230400 */
1082 uap->curregs[R4] = X16CLK;
1083 uap->curregs[R11] = 0;
1084 uap->curregs[R14] = 0;
1085 break;
1086 case ZS_CLOCK/32: /* 115200 */
1087 uap->curregs[R4] = X32CLK;
1088 uap->curregs[R11] = 0;
1089 uap->curregs[R14] = 0;
1090 break;
1091 default:
1092 uap->curregs[R4] = X16CLK;
1093 uap->curregs[R11] = TCBR | RCBR;
1094 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1095 uap->curregs[R12] = (brg & 255);
1096 uap->curregs[R13] = ((brg >> 8) & 255);
1097 uap->curregs[R14] = BRENAB;
1098 }
1099 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1100 }
1101
1102 /* Character size, stop bits, and parity. */
1103 uap->curregs[3] &= ~RxN_MASK;
1104 uap->curregs[5] &= ~TxN_MASK;
1105
1106 switch (cflag & CSIZE) {
1107 case CS5:
1108 uap->curregs[3] |= Rx5;
1109 uap->curregs[5] |= Tx5;
1110 uap->parity_mask = 0x1f;
1111 break;
1112 case CS6:
1113 uap->curregs[3] |= Rx6;
1114 uap->curregs[5] |= Tx6;
1115 uap->parity_mask = 0x3f;
1116 break;
1117 case CS7:
1118 uap->curregs[3] |= Rx7;
1119 uap->curregs[5] |= Tx7;
1120 uap->parity_mask = 0x7f;
1121 break;
1122 case CS8:
1123 default:
1124 uap->curregs[3] |= Rx8;
1125 uap->curregs[5] |= Tx8;
1126 uap->parity_mask = 0xff;
1127 break;
1128 };
1129 uap->curregs[4] &= ~(SB_MASK);
1130 if (cflag & CSTOPB)
1131 uap->curregs[4] |= SB2;
1132 else
1133 uap->curregs[4] |= SB1;
1134 if (cflag & PARENB)
1135 uap->curregs[4] |= PAR_ENAB;
1136 else
1137 uap->curregs[4] &= ~PAR_ENAB;
1138 if (!(cflag & PARODD))
1139 uap->curregs[4] |= PAR_EVEN;
1140 else
1141 uap->curregs[4] &= ~PAR_EVEN;
1142
1143 uap->port.read_status_mask = Rx_OVR;
1144 if (iflag & INPCK)
1145 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1146 if (iflag & (BRKINT | PARMRK))
1147 uap->port.read_status_mask |= BRK_ABRT;
1148
1149 uap->port.ignore_status_mask = 0;
1150 if (iflag & IGNPAR)
1151 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1152 if (iflag & IGNBRK) {
1153 uap->port.ignore_status_mask |= BRK_ABRT;
1154 if (iflag & IGNPAR)
1155 uap->port.ignore_status_mask |= Rx_OVR;
1156 }
1157
1158 if ((cflag & CREAD) == 0)
1159 uap->port.ignore_status_mask = 0xff;
1160 }
1161
1162
1163 /*
1164 * Set the irda codec on the imac to the specified baud rate.
1165 */
1166 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1167 {
1168 u8 cmdbyte;
1169 int t, version;
1170
1171 switch (*baud) {
1172 /* SIR modes */
1173 case 2400:
1174 cmdbyte = 0x53;
1175 break;
1176 case 4800:
1177 cmdbyte = 0x52;
1178 break;
1179 case 9600:
1180 cmdbyte = 0x51;
1181 break;
1182 case 19200:
1183 cmdbyte = 0x50;
1184 break;
1185 case 38400:
1186 cmdbyte = 0x4f;
1187 break;
1188 case 57600:
1189 cmdbyte = 0x4e;
1190 break;
1191 case 115200:
1192 cmdbyte = 0x4d;
1193 break;
1194 /* The FIR modes aren't really supported at this point, how
1195 * do we select the speed ? via the FCR on KeyLargo ?
1196 */
1197 case 1152000:
1198 cmdbyte = 0;
1199 break;
1200 case 4000000:
1201 cmdbyte = 0;
1202 break;
1203 default: /* 9600 */
1204 cmdbyte = 0x51;
1205 *baud = 9600;
1206 break;
1207 }
1208
1209 /* Wait for transmitter to drain */
1210 t = 10000;
1211 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1212 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1213 if (--t <= 0) {
1214 pmz_error("transmitter didn't drain\n");
1215 return;
1216 }
1217 udelay(10);
1218 }
1219
1220 /* Drain the receiver too */
1221 t = 100;
1222 (void)read_zsdata(uap);
1223 (void)read_zsdata(uap);
1224 (void)read_zsdata(uap);
1225 mdelay(10);
1226 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1227 read_zsdata(uap);
1228 mdelay(10);
1229 if (--t <= 0) {
1230 pmz_error("receiver didn't drain\n");
1231 return;
1232 }
1233 }
1234
1235 /* Switch to command mode */
1236 uap->curregs[R5] |= DTR;
1237 write_zsreg(uap, R5, uap->curregs[R5]);
1238 zssync(uap);
1239 mdelay(1);
1240
1241 /* Switch SCC to 19200 */
1242 pmz_convert_to_zs(uap, CS8, 0, 19200);
1243 pmz_load_zsregs(uap, uap->curregs);
1244 mdelay(1);
1245
1246 /* Write get_version command byte */
1247 write_zsdata(uap, 1);
1248 t = 5000;
1249 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1250 if (--t <= 0) {
1251 pmz_error("irda_setup timed out on get_version byte\n");
1252 goto out;
1253 }
1254 udelay(10);
1255 }
1256 version = read_zsdata(uap);
1257
1258 if (version < 4) {
1259 pmz_info("IrDA: dongle version %d not supported\n", version);
1260 goto out;
1261 }
1262
1263 /* Send speed mode */
1264 write_zsdata(uap, cmdbyte);
1265 t = 5000;
1266 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1267 if (--t <= 0) {
1268 pmz_error("irda_setup timed out on speed mode byte\n");
1269 goto out;
1270 }
1271 udelay(10);
1272 }
1273 t = read_zsdata(uap);
1274 if (t != cmdbyte)
1275 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1276
1277 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1278 *baud, version);
1279
1280 (void)read_zsdata(uap);
1281 (void)read_zsdata(uap);
1282 (void)read_zsdata(uap);
1283
1284 out:
1285 /* Switch back to data mode */
1286 uap->curregs[R5] &= ~DTR;
1287 write_zsreg(uap, R5, uap->curregs[R5]);
1288 zssync(uap);
1289
1290 (void)read_zsdata(uap);
1291 (void)read_zsdata(uap);
1292 (void)read_zsdata(uap);
1293 }
1294
1295
1296 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1297 struct ktermios *old)
1298 {
1299 struct uart_pmac_port *uap = to_pmz(port);
1300 unsigned long baud;
1301
1302 pmz_debug("pmz: set_termios()\n");
1303
1304 if (ZS_IS_ASLEEP(uap))
1305 return;
1306
1307 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1308
1309 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1310 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1311 * about the FIR mode and high speed modes. So these are unused. For
1312 * implementing proper support for these, we should probably add some
1313 * DMA as well, at least on the Rx side, which isn't a simple thing
1314 * at this point.
1315 */
1316 if (ZS_IS_IRDA(uap)) {
1317 /* Calc baud rate */
1318 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1319 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1320 /* Cet the irda codec to the right rate */
1321 pmz_irda_setup(uap, &baud);
1322 /* Set final baud rate */
1323 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1324 pmz_load_zsregs(uap, uap->curregs);
1325 zssync(uap);
1326 } else {
1327 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1328 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1329 /* Make sure modem status interrupts are correctly configured */
1330 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1331 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1332 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1333 } else {
1334 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1335 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1336 }
1337
1338 /* Load registers to the chip */
1339 pmz_maybe_update_regs(uap);
1340 }
1341 uart_update_timeout(port, termios->c_cflag, baud);
1342
1343 pmz_debug("pmz: set_termios() done.\n");
1344 }
1345
1346 /* The port lock is not held. */
1347 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1348 struct ktermios *old)
1349 {
1350 struct uart_pmac_port *uap = to_pmz(port);
1351 unsigned long flags;
1352
1353 spin_lock_irqsave(&port->lock, flags);
1354
1355 /* Disable IRQs on the port */
1356 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1357 write_zsreg(uap, R1, uap->curregs[R1]);
1358
1359 /* Setup new port configuration */
1360 __pmz_set_termios(port, termios, old);
1361
1362 /* Re-enable IRQs on the port */
1363 if (ZS_IS_OPEN(uap)) {
1364 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1365 if (!ZS_IS_EXTCLK(uap))
1366 uap->curregs[R1] |= EXT_INT_ENAB;
1367 write_zsreg(uap, R1, uap->curregs[R1]);
1368 }
1369 spin_unlock_irqrestore(&port->lock, flags);
1370 }
1371
1372 static const char *pmz_type(struct uart_port *port)
1373 {
1374 struct uart_pmac_port *uap = to_pmz(port);
1375
1376 if (ZS_IS_IRDA(uap))
1377 return "Z85c30 ESCC - Infrared port";
1378 else if (ZS_IS_INTMODEM(uap))
1379 return "Z85c30 ESCC - Internal modem";
1380 return "Z85c30 ESCC - Serial port";
1381 }
1382
1383 /* We do not request/release mappings of the registers here, this
1384 * happens at early serial probe time.
1385 */
1386 static void pmz_release_port(struct uart_port *port)
1387 {
1388 }
1389
1390 static int pmz_request_port(struct uart_port *port)
1391 {
1392 return 0;
1393 }
1394
1395 /* These do not need to do anything interesting either. */
1396 static void pmz_config_port(struct uart_port *port, int flags)
1397 {
1398 }
1399
1400 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1401 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1402 {
1403 return -EINVAL;
1404 }
1405
1406 #ifdef CONFIG_CONSOLE_POLL
1407
1408 static int pmz_poll_get_char(struct uart_port *port)
1409 {
1410 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1411
1412 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
1413 udelay(5);
1414 return read_zsdata(uap);
1415 }
1416
1417 static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1418 {
1419 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1420
1421 /* Wait for the transmit buffer to empty. */
1422 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1423 udelay(5);
1424 write_zsdata(uap, c);
1425 }
1426
1427 #endif /* CONFIG_CONSOLE_POLL */
1428
1429 static struct uart_ops pmz_pops = {
1430 .tx_empty = pmz_tx_empty,
1431 .set_mctrl = pmz_set_mctrl,
1432 .get_mctrl = pmz_get_mctrl,
1433 .stop_tx = pmz_stop_tx,
1434 .start_tx = pmz_start_tx,
1435 .stop_rx = pmz_stop_rx,
1436 .enable_ms = pmz_enable_ms,
1437 .break_ctl = pmz_break_ctl,
1438 .startup = pmz_startup,
1439 .shutdown = pmz_shutdown,
1440 .set_termios = pmz_set_termios,
1441 .type = pmz_type,
1442 .release_port = pmz_release_port,
1443 .request_port = pmz_request_port,
1444 .config_port = pmz_config_port,
1445 .verify_port = pmz_verify_port,
1446 #ifdef CONFIG_CONSOLE_POLL
1447 .poll_get_char = pmz_poll_get_char,
1448 .poll_put_char = pmz_poll_put_char,
1449 #endif
1450 };
1451
1452 #ifdef CONFIG_PPC_PMAC
1453
1454 /*
1455 * Setup one port structure after probing, HW is down at this point,
1456 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1457 * register our console before uart_add_one_port() is called
1458 */
1459 static int __init pmz_init_port(struct uart_pmac_port *uap)
1460 {
1461 struct device_node *np = uap->node;
1462 const char *conn;
1463 const struct slot_names_prop {
1464 int count;
1465 char name[1];
1466 } *slots;
1467 int len;
1468 struct resource r_ports, r_rxdma, r_txdma;
1469
1470 /*
1471 * Request & map chip registers
1472 */
1473 if (of_address_to_resource(np, 0, &r_ports))
1474 return -ENODEV;
1475 uap->port.mapbase = r_ports.start;
1476 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1477
1478 uap->control_reg = uap->port.membase;
1479 uap->data_reg = uap->control_reg + 0x10;
1480
1481 /*
1482 * Request & map DBDMA registers
1483 */
1484 #ifdef HAS_DBDMA
1485 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1486 of_address_to_resource(np, 2, &r_rxdma) == 0)
1487 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1488 #else
1489 memset(&r_txdma, 0, sizeof(struct resource));
1490 memset(&r_rxdma, 0, sizeof(struct resource));
1491 #endif
1492 if (ZS_HAS_DMA(uap)) {
1493 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1494 if (uap->tx_dma_regs == NULL) {
1495 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1496 goto no_dma;
1497 }
1498 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1499 if (uap->rx_dma_regs == NULL) {
1500 iounmap(uap->tx_dma_regs);
1501 uap->tx_dma_regs = NULL;
1502 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1503 goto no_dma;
1504 }
1505 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1506 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1507 }
1508 no_dma:
1509
1510 /*
1511 * Detect port type
1512 */
1513 if (of_device_is_compatible(np, "cobalt"))
1514 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1515 conn = of_get_property(np, "AAPL,connector", &len);
1516 if (conn && (strcmp(conn, "infrared") == 0))
1517 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1518 uap->port_type = PMAC_SCC_ASYNC;
1519 /* 1999 Powerbook G3 has slot-names property instead */
1520 slots = of_get_property(np, "slot-names", &len);
1521 if (slots && slots->count > 0) {
1522 if (strcmp(slots->name, "IrDA") == 0)
1523 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1524 else if (strcmp(slots->name, "Modem") == 0)
1525 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1526 }
1527 if (ZS_IS_IRDA(uap))
1528 uap->port_type = PMAC_SCC_IRDA;
1529 if (ZS_IS_INTMODEM(uap)) {
1530 struct device_node* i2c_modem =
1531 of_find_node_by_name(NULL, "i2c-modem");
1532 if (i2c_modem) {
1533 const char* mid =
1534 of_get_property(i2c_modem, "modem-id", NULL);
1535 if (mid) switch(*mid) {
1536 case 0x04 :
1537 case 0x05 :
1538 case 0x07 :
1539 case 0x08 :
1540 case 0x0b :
1541 case 0x0c :
1542 uap->port_type = PMAC_SCC_I2S1;
1543 }
1544 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1545 mid ? (*mid) : 0);
1546 of_node_put(i2c_modem);
1547 } else {
1548 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1549 }
1550 }
1551
1552 /*
1553 * Init remaining bits of "port" structure
1554 */
1555 uap->port.iotype = UPIO_MEM;
1556 uap->port.irq = irq_of_parse_and_map(np, 0);
1557 uap->port.uartclk = ZS_CLOCK;
1558 uap->port.fifosize = 1;
1559 uap->port.ops = &pmz_pops;
1560 uap->port.type = PORT_PMAC_ZILOG;
1561 uap->port.flags = 0;
1562
1563 /*
1564 * Fixup for the port on Gatwick for which the device-tree has
1565 * missing interrupts. Normally, the macio_dev would contain
1566 * fixed up interrupt info, but we use the device-tree directly
1567 * here due to early probing so we need the fixup too.
1568 */
1569 if (uap->port.irq == NO_IRQ &&
1570 np->parent && np->parent->parent &&
1571 of_device_is_compatible(np->parent->parent, "gatwick")) {
1572 /* IRQs on gatwick are offset by 64 */
1573 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1574 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1575 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1576 }
1577
1578 /* Setup some valid baud rate information in the register
1579 * shadows so we don't write crap there before baud rate is
1580 * first initialized.
1581 */
1582 pmz_convert_to_zs(uap, CS8, 0, 9600);
1583
1584 return 0;
1585 }
1586
1587 /*
1588 * Get rid of a port on module removal
1589 */
1590 static void pmz_dispose_port(struct uart_pmac_port *uap)
1591 {
1592 struct device_node *np;
1593
1594 np = uap->node;
1595 iounmap(uap->rx_dma_regs);
1596 iounmap(uap->tx_dma_regs);
1597 iounmap(uap->control_reg);
1598 uap->node = NULL;
1599 of_node_put(np);
1600 memset(uap, 0, sizeof(struct uart_pmac_port));
1601 }
1602
1603 /*
1604 * Called upon match with an escc node in the device-tree.
1605 */
1606 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1607 {
1608 int i;
1609
1610 /* Iterate the pmz_ports array to find a matching entry
1611 */
1612 for (i = 0; i < MAX_ZS_PORTS; i++)
1613 if (pmz_ports[i].node == mdev->ofdev.node) {
1614 struct uart_pmac_port *uap = &pmz_ports[i];
1615
1616 uap->dev = mdev;
1617 dev_set_drvdata(&mdev->ofdev.dev, uap);
1618 if (macio_request_resources(uap->dev, "pmac_zilog"))
1619 printk(KERN_WARNING "%s: Failed to request resource"
1620 ", port still active\n",
1621 uap->node->name);
1622 else
1623 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1624 return 0;
1625 }
1626 return -ENODEV;
1627 }
1628
1629 /*
1630 * That one should not be called, macio isn't really a hotswap device,
1631 * we don't expect one of those serial ports to go away...
1632 */
1633 static int pmz_detach(struct macio_dev *mdev)
1634 {
1635 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1636
1637 if (!uap)
1638 return -ENODEV;
1639
1640 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1641 macio_release_resources(uap->dev);
1642 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1643 }
1644 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1645 uap->dev = NULL;
1646
1647 return 0;
1648 }
1649
1650
1651 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1652 {
1653 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1654 struct uart_state *state;
1655 unsigned long flags;
1656
1657 if (uap == NULL) {
1658 printk("HRM... pmz_suspend with NULL uap\n");
1659 return 0;
1660 }
1661
1662 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1663 return 0;
1664
1665 pmz_debug("suspend, switching to state %d\n", pm_state.event);
1666
1667 state = pmz_uart_reg.state + uap->port.line;
1668
1669 mutex_lock(&pmz_irq_mutex);
1670 mutex_lock(&state->port.mutex);
1671
1672 spin_lock_irqsave(&uap->port.lock, flags);
1673
1674 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1675 /* Disable receiver and transmitter. */
1676 uap->curregs[R3] &= ~RxENABLE;
1677 uap->curregs[R5] &= ~TxENABLE;
1678
1679 /* Disable all interrupts and BRK assertion. */
1680 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1681 uap->curregs[R5] &= ~SND_BRK;
1682 pmz_load_zsregs(uap, uap->curregs);
1683 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1684 mb();
1685 }
1686
1687 spin_unlock_irqrestore(&uap->port.lock, flags);
1688
1689 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1690 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1691 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1692 disable_irq(uap->port.irq);
1693 }
1694
1695 if (ZS_IS_CONS(uap))
1696 uap->port.cons->flags &= ~CON_ENABLED;
1697
1698 /* Shut the chip down */
1699 pmz_set_scc_power(uap, 0);
1700
1701 mutex_unlock(&state->port.mutex);
1702 mutex_unlock(&pmz_irq_mutex);
1703
1704 pmz_debug("suspend, switching complete\n");
1705
1706 mdev->ofdev.dev.power.power_state = pm_state;
1707
1708 return 0;
1709 }
1710
1711
1712 static int pmz_resume(struct macio_dev *mdev)
1713 {
1714 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1715 struct uart_state *state;
1716 unsigned long flags;
1717 int pwr_delay = 0;
1718
1719 if (uap == NULL)
1720 return 0;
1721
1722 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1723 return 0;
1724
1725 pmz_debug("resume, switching to state 0\n");
1726
1727 state = pmz_uart_reg.state + uap->port.line;
1728
1729 mutex_lock(&pmz_irq_mutex);
1730 mutex_lock(&state->port.mutex);
1731
1732 spin_lock_irqsave(&uap->port.lock, flags);
1733 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1734 spin_unlock_irqrestore(&uap->port.lock, flags);
1735 goto bail;
1736 }
1737 pwr_delay = __pmz_startup(uap);
1738
1739 /* Take care of config that may have changed while asleep */
1740 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1741
1742 if (ZS_IS_OPEN(uap)) {
1743 /* Enable interrupts */
1744 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1745 if (!ZS_IS_EXTCLK(uap))
1746 uap->curregs[R1] |= EXT_INT_ENAB;
1747 write_zsreg(uap, R1, uap->curregs[R1]);
1748 }
1749
1750 spin_unlock_irqrestore(&uap->port.lock, flags);
1751
1752 if (ZS_IS_CONS(uap))
1753 uap->port.cons->flags |= CON_ENABLED;
1754
1755 /* Re-enable IRQ on the controller */
1756 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1757 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1758 enable_irq(uap->port.irq);
1759 }
1760
1761 bail:
1762 mutex_unlock(&state->port.mutex);
1763 mutex_unlock(&pmz_irq_mutex);
1764
1765 /* Right now, we deal with delay by blocking here, I'll be
1766 * smarter later on
1767 */
1768 if (pwr_delay != 0) {
1769 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1770 msleep(pwr_delay);
1771 }
1772
1773 pmz_debug("resume, switching complete\n");
1774
1775 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1776
1777 return 0;
1778 }
1779
1780 /*
1781 * Probe all ports in the system and build the ports array, we register
1782 * with the serial layer at this point, the macio-type probing is only
1783 * used later to "attach" to the sysfs tree so we get power management
1784 * events
1785 */
1786 static int __init pmz_probe(void)
1787 {
1788 struct device_node *node_p, *node_a, *node_b, *np;
1789 int count = 0;
1790 int rc;
1791
1792 /*
1793 * Find all escc chips in the system
1794 */
1795 node_p = of_find_node_by_name(NULL, "escc");
1796 while (node_p) {
1797 /*
1798 * First get channel A/B node pointers
1799 *
1800 * TODO: Add routines with proper locking to do that...
1801 */
1802 node_a = node_b = NULL;
1803 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1804 if (strncmp(np->name, "ch-a", 4) == 0)
1805 node_a = of_node_get(np);
1806 else if (strncmp(np->name, "ch-b", 4) == 0)
1807 node_b = of_node_get(np);
1808 }
1809 if (!node_a && !node_b) {
1810 of_node_put(node_a);
1811 of_node_put(node_b);
1812 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1813 (!node_a) ? 'a' : 'b', node_p->full_name);
1814 goto next;
1815 }
1816
1817 /*
1818 * Fill basic fields in the port structures
1819 */
1820 pmz_ports[count].mate = &pmz_ports[count+1];
1821 pmz_ports[count+1].mate = &pmz_ports[count];
1822 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1823 pmz_ports[count].node = node_a;
1824 pmz_ports[count+1].node = node_b;
1825 pmz_ports[count].port.line = count;
1826 pmz_ports[count+1].port.line = count+1;
1827
1828 /*
1829 * Setup the ports for real
1830 */
1831 rc = pmz_init_port(&pmz_ports[count]);
1832 if (rc == 0 && node_b != NULL)
1833 rc = pmz_init_port(&pmz_ports[count+1]);
1834 if (rc != 0) {
1835 of_node_put(node_a);
1836 of_node_put(node_b);
1837 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1838 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1839 goto next;
1840 }
1841 count += 2;
1842 next:
1843 node_p = of_find_node_by_name(node_p, "escc");
1844 }
1845 pmz_ports_count = count;
1846
1847 return 0;
1848 }
1849
1850 #else
1851
1852 extern struct platform_device scc_a_pdev, scc_b_pdev;
1853
1854 static int __init pmz_init_port(struct uart_pmac_port *uap)
1855 {
1856 struct resource *r_ports;
1857 int irq;
1858
1859 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
1860 irq = platform_get_irq(uap->node, 0);
1861 if (!r_ports || !irq)
1862 return -ENODEV;
1863
1864 uap->port.mapbase = r_ports->start;
1865 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1866 uap->port.iotype = UPIO_MEM;
1867 uap->port.irq = irq;
1868 uap->port.uartclk = ZS_CLOCK;
1869 uap->port.fifosize = 1;
1870 uap->port.ops = &pmz_pops;
1871 uap->port.type = PORT_PMAC_ZILOG;
1872 uap->port.flags = 0;
1873
1874 uap->control_reg = uap->port.membase;
1875 uap->data_reg = uap->control_reg + 4;
1876 uap->port_type = 0;
1877
1878 pmz_convert_to_zs(uap, CS8, 0, 9600);
1879
1880 return 0;
1881 }
1882
1883 static int __init pmz_probe(void)
1884 {
1885 int err;
1886
1887 pmz_ports_count = 0;
1888
1889 pmz_ports[0].mate = &pmz_ports[1];
1890 pmz_ports[0].port.line = 0;
1891 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1892 pmz_ports[0].node = &scc_a_pdev;
1893 err = pmz_init_port(&pmz_ports[0]);
1894 if (err)
1895 return err;
1896 pmz_ports_count++;
1897
1898 pmz_ports[1].mate = &pmz_ports[0];
1899 pmz_ports[1].port.line = 1;
1900 pmz_ports[1].flags = 0;
1901 pmz_ports[1].node = &scc_b_pdev;
1902 err = pmz_init_port(&pmz_ports[1]);
1903 if (err)
1904 return err;
1905 pmz_ports_count++;
1906
1907 return 0;
1908 }
1909
1910 static void pmz_dispose_port(struct uart_pmac_port *uap)
1911 {
1912 memset(uap, 0, sizeof(struct uart_pmac_port));
1913 }
1914
1915 static int __init pmz_attach(struct platform_device *pdev)
1916 {
1917 int i;
1918
1919 for (i = 0; i < pmz_ports_count; i++)
1920 if (pmz_ports[i].node == pdev)
1921 return 0;
1922 return -ENODEV;
1923 }
1924
1925 static int __exit pmz_detach(struct platform_device *pdev)
1926 {
1927 return 0;
1928 }
1929
1930 #endif /* !CONFIG_PPC_PMAC */
1931
1932 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1933
1934 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1935 static int __init pmz_console_setup(struct console *co, char *options);
1936
1937 static struct console pmz_console = {
1938 .name = PMACZILOG_NAME,
1939 .write = pmz_console_write,
1940 .device = uart_console_device,
1941 .setup = pmz_console_setup,
1942 .flags = CON_PRINTBUFFER,
1943 .index = -1,
1944 .data = &pmz_uart_reg,
1945 };
1946
1947 #define PMACZILOG_CONSOLE &pmz_console
1948 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1949 #define PMACZILOG_CONSOLE (NULL)
1950 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1951
1952 /*
1953 * Register the driver, console driver and ports with the serial
1954 * core
1955 */
1956 static int __init pmz_register(void)
1957 {
1958 int i, rc;
1959
1960 pmz_uart_reg.nr = pmz_ports_count;
1961 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1962
1963 /*
1964 * Register this driver with the serial core
1965 */
1966 rc = uart_register_driver(&pmz_uart_reg);
1967 if (rc)
1968 return rc;
1969
1970 /*
1971 * Register each port with the serial core
1972 */
1973 for (i = 0; i < pmz_ports_count; i++) {
1974 struct uart_pmac_port *uport = &pmz_ports[i];
1975 /* NULL node may happen on wallstreet */
1976 if (uport->node != NULL)
1977 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1978 if (rc)
1979 goto err_out;
1980 }
1981
1982 return 0;
1983 err_out:
1984 while (i-- > 0) {
1985 struct uart_pmac_port *uport = &pmz_ports[i];
1986 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1987 }
1988 uart_unregister_driver(&pmz_uart_reg);
1989 return rc;
1990 }
1991
1992 #ifdef CONFIG_PPC_PMAC
1993
1994 static struct of_device_id pmz_match[] =
1995 {
1996 {
1997 .name = "ch-a",
1998 },
1999 {
2000 .name = "ch-b",
2001 },
2002 {},
2003 };
2004 MODULE_DEVICE_TABLE (of, pmz_match);
2005
2006 static struct macio_driver pmz_driver = {
2007 .name = "pmac_zilog",
2008 .match_table = pmz_match,
2009 .probe = pmz_attach,
2010 .remove = pmz_detach,
2011 .suspend = pmz_suspend,
2012 .resume = pmz_resume,
2013 };
2014
2015 #else
2016
2017 static struct platform_driver pmz_driver = {
2018 .remove = __exit_p(pmz_detach),
2019 .driver = {
2020 .name = "scc",
2021 .owner = THIS_MODULE,
2022 },
2023 };
2024
2025 #endif /* !CONFIG_PPC_PMAC */
2026
2027 static int __init init_pmz(void)
2028 {
2029 int rc, i;
2030 printk(KERN_INFO "%s\n", version);
2031
2032 /*
2033 * First, we need to do a direct OF-based probe pass. We
2034 * do that because we want serial console up before the
2035 * macio stuffs calls us back, and since that makes it
2036 * easier to pass the proper number of channels to
2037 * uart_register_driver()
2038 */
2039 if (pmz_ports_count == 0)
2040 pmz_probe();
2041
2042 /*
2043 * Bail early if no port found
2044 */
2045 if (pmz_ports_count == 0)
2046 return -ENODEV;
2047
2048 /*
2049 * Now we register with the serial layer
2050 */
2051 rc = pmz_register();
2052 if (rc) {
2053 printk(KERN_ERR
2054 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
2055 "pmac_zilog: Did another serial driver already claim the minors?\n");
2056 /* effectively "pmz_unprobe()" */
2057 for (i=0; i < pmz_ports_count; i++)
2058 pmz_dispose_port(&pmz_ports[i]);
2059 return rc;
2060 }
2061
2062 /*
2063 * Then we register the macio driver itself
2064 */
2065 #ifdef CONFIG_PPC_PMAC
2066 return macio_register_driver(&pmz_driver);
2067 #else
2068 return platform_driver_probe(&pmz_driver, pmz_attach);
2069 #endif
2070 }
2071
2072 static void __exit exit_pmz(void)
2073 {
2074 int i;
2075
2076 #ifdef CONFIG_PPC_PMAC
2077 /* Get rid of macio-driver (detach from macio) */
2078 macio_unregister_driver(&pmz_driver);
2079 #else
2080 platform_driver_unregister(&pmz_driver);
2081 #endif
2082
2083 for (i = 0; i < pmz_ports_count; i++) {
2084 struct uart_pmac_port *uport = &pmz_ports[i];
2085 if (uport->node != NULL) {
2086 uart_remove_one_port(&pmz_uart_reg, &uport->port);
2087 pmz_dispose_port(uport);
2088 }
2089 }
2090 /* Unregister UART driver */
2091 uart_unregister_driver(&pmz_uart_reg);
2092 }
2093
2094 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
2095
2096 static void pmz_console_putchar(struct uart_port *port, int ch)
2097 {
2098 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
2099
2100 /* Wait for the transmit buffer to empty. */
2101 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
2102 udelay(5);
2103 write_zsdata(uap, ch);
2104 }
2105
2106 /*
2107 * Print a string to the serial port trying not to disturb
2108 * any possible real use of the port...
2109 */
2110 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
2111 {
2112 struct uart_pmac_port *uap = &pmz_ports[con->index];
2113 unsigned long flags;
2114
2115 if (ZS_IS_ASLEEP(uap))
2116 return;
2117 spin_lock_irqsave(&uap->port.lock, flags);
2118
2119 /* Turn of interrupts and enable the transmitter. */
2120 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2121 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2122
2123 uart_console_write(&uap->port, s, count, pmz_console_putchar);
2124
2125 /* Restore the values in the registers. */
2126 write_zsreg(uap, R1, uap->curregs[1]);
2127 /* Don't disable the transmitter. */
2128
2129 spin_unlock_irqrestore(&uap->port.lock, flags);
2130 }
2131
2132 /*
2133 * Setup the serial console
2134 */
2135 static int __init pmz_console_setup(struct console *co, char *options)
2136 {
2137 struct uart_pmac_port *uap;
2138 struct uart_port *port;
2139 int baud = 38400;
2140 int bits = 8;
2141 int parity = 'n';
2142 int flow = 'n';
2143 unsigned long pwr_delay;
2144
2145 /*
2146 * XServe's default to 57600 bps
2147 */
2148 if (of_machine_is_compatible("RackMac1,1")
2149 || of_machine_is_compatible("RackMac1,2")
2150 || of_machine_is_compatible("MacRISC4"))
2151 baud = 57600;
2152
2153 /*
2154 * Check whether an invalid uart number has been specified, and
2155 * if so, search for the first available port that does have
2156 * console support.
2157 */
2158 if (co->index >= pmz_ports_count)
2159 co->index = 0;
2160 uap = &pmz_ports[co->index];
2161 if (uap->node == NULL)
2162 return -ENODEV;
2163 port = &uap->port;
2164
2165 /*
2166 * Mark port as beeing a console
2167 */
2168 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2169
2170 /*
2171 * Temporary fix for uart layer who didn't setup the spinlock yet
2172 */
2173 spin_lock_init(&port->lock);
2174
2175 /*
2176 * Enable the hardware
2177 */
2178 pwr_delay = __pmz_startup(uap);
2179 if (pwr_delay)
2180 mdelay(pwr_delay);
2181
2182 if (options)
2183 uart_parse_options(options, &baud, &parity, &bits, &flow);
2184
2185 return uart_set_options(port, co, baud, parity, bits, flow);
2186 }
2187
2188 static int __init pmz_console_init(void)
2189 {
2190 /* Probe ports */
2191 pmz_probe();
2192
2193 /* TODO: Autoprobe console based on OF */
2194 /* pmz_console.index = i; */
2195 register_console(&pmz_console);
2196
2197 return 0;
2198
2199 }
2200 console_initcall(pmz_console_init);
2201 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2202
2203 module_init(init_pmz);
2204 module_exit(exit_pmz);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree