arch/x86/pci/k8-bus_64.c

   1 #include <linux/init.h>
   2 #include <linux/pci.h>
   3 #include <asm/pci-direct.h>
   4 #include <asm/mpspec.h>
   5 #include <linux/cpumask.h>
   6 #include <linux/topology.h>
   7
   8 /*
   9  * This discovers the pcibus <-> node mapping on AMD K8.
  10  * also get peer root bus resource for io,mmio
  11  */
  12
  13
  14 /*
  15  * sub bus (transparent) will use entres from 3 to store extra from root,
  16  * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
  17  */
  18 #define RES_NUM 16
  19 struct pci_root_info {
  20         char name[12];
  21         unsigned int res_num;
  22         struct resource res[RES_NUM];
  23         int bus_min;
  24         int bus_max;
  25         int node;
  26         int link;
  27 };
  28
  29 /* 4 at this time, it may become to 32 */
  30 #define PCI_ROOT_NR 4
  31 static int pci_root_num;
  32 static struct pci_root_info pci_root_info[PCI_ROOT_NR];
  33
  34 #ifdef CONFIG_NUMA
  35
  36 #define BUS_NR 256
  37
  38 static int mp_bus_to_node[BUS_NR];
  39
  40 void set_mp_bus_to_node(int busnum, int node)
  41 {
  42         if (busnum >= 0 &&  busnum < BUS_NR)
  43                 mp_bus_to_node[busnum] = node;
  44 }
  45
  46 int get_mp_bus_to_node(int busnum)
  47 {
  48         int node = -1;
  49
  50         if (busnum < 0 || busnum > (BUS_NR - 1))
  51                 return node;
  52
  53         node = mp_bus_to_node[busnum];
  54
  55         /*
  56          * let numa_node_id to decide it later in dma_alloc_pages
  57          * if there is no ram on that node
  58          */
  59         if (node != -1 && !node_online(node))
  60                 node = -1;
  61
  62         return node;
  63 }
  64 #endif
  65
  66 void set_pci_bus_resources_arch_default(struct pci_bus *b)
  67 {
  68         int i;
  69         int j;
  70         struct pci_root_info *info;
  71
  72         /* if only one root bus, don't need to anything */
  73         if (pci_root_num < 2)
  74                 return;
  75
  76         for (i = 0; i < pci_root_num; i++) {
  77                 if (pci_root_info[i].bus_min == b->number)
  78                         break;
  79         }
  80
  81         if (i == pci_root_num)
  82                 return;
  83
  84         info = &pci_root_info[i];
  85         for (j = 0; j < info->res_num; j++) {
  86                 struct resource *res;
  87                 struct resource *root;
  88
  89                 res = &info->res[j];
  90                 b->resource[j] = res;
  91                 if (res->flags & IORESOURCE_IO)
  92                         root = &ioport_resource;
  93                 else
  94                         root = &iomem_resource;
  95                 insert_resource(root, res);
  96         }
  97 }
  98
  99 #define RANGE_NUM 16
 100
 101 struct res_range {
 102         size_t start;
 103         size_t end;
 104 };
 105
 106 static void __init update_range(struct res_range *range, size_t start,
 107                                 size_t end)
 108 {
 109         int i;
 110         int j;
 111
 112         for (j = 0; j < RANGE_NUM; j++) {
 113                 if (!range[j].end)
 114                         continue;
 115
 116                 if (start <= range[j].start && end >= range[j].end) {
 117                         range[j].start = 0;
 118                         range[j].end = 0;
 119                         continue;
 120                 }
 121
 122                 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
 123                         range[j].start = end + 1;
 124                         continue;
 125                 }
 126
 127
 128                 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
 129                         range[j].end = start - 1;
 130                         continue;
 131                 }
 132
 133                 if (start > range[j].start && end < range[j].end) {
 134                         /* find the new spare */
 135                         for (i = 0; i < RANGE_NUM; i++) {
 136                                 if (range[i].end == 0)
 137                                         break;
 138                         }
 139                         if (i < RANGE_NUM) {
 140                                 range[i].end = range[j].end;
 141                                 range[i].start = end + 1;
 142                         } else {
 143                                 printk(KERN_ERR "run of slot in ranges\n");
 144                         }
 145                         range[j].end = start - 1;
 146                         continue;
 147                 }
 148         }
 149 }
 150
 151 static void __init update_res(struct pci_root_info *info, size_t start,
 152                               size_t end, unsigned long flags, int merge)
 153 {
 154         int i;
 155         struct resource *res;
 156
 157         if (!merge)
 158                 goto addit;
 159
 160         /* try to merge it with old one */
 161         for (i = 0; i < info->res_num; i++) {
 162                 size_t final_start, final_end;
 163                 size_t common_start, common_end;
 164
 165                 res = &info->res[i];
 166                 if (res->flags != flags)
 167                         continue;
 168
 169                 common_start = max((size_t)res->start, start);
 170                 common_end = min((size_t)res->end, end);
 171                 if (common_start > common_end + 1)
 172                         continue;
 173
 174                 final_start = min((size_t)res->start, start);
 175                 final_end = max((size_t)res->end, end);
 176
 177                 res->start = final_start;
 178                 res->end = final_end;
 179                 return;
 180         }
 181
 182 addit:
 183
 184         /* need to add that */
 185         if (info->res_num >= RES_NUM)
 186                 return;
 187
 188         res = &info->res[info->res_num];
 189         res->name = info->name;
 190         res->flags = flags;
 191         res->start = start;
 192         res->end = end;
 193         res->child = NULL;
 194         info->res_num++;
 195 }
 196
 197 struct pci_hostbridge_probe {
 198         u32 bus;
 199         u32 slot;
 200         u32 vendor;
 201         u32 device;
 202 };
 203
 204 static struct pci_hostbridge_probe pci_probes[] __initdata = {
 205         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
 206         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 207         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 208         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
 209 };
 210
 211 static u64 __initdata fam10h_mmconf_start;
 212 static u64 __initdata fam10h_mmconf_end;
 213 static void __init get_pci_mmcfg_amd_fam10h_range(void)
 214 {
 215         u32 address;
 216         u64 base, msr;
 217         unsigned segn_busn_bits;
 218
 219         /* assume all cpus from fam10h have mmconf */
 220         if (boot_cpu_data.x86 < 0x10)
 221                 return;
 222
 223         address = MSR_FAM10H_MMIO_CONF_BASE;
 224         rdmsrl(address, msr);
 225
 226         /* mmconfig is not enable */
 227         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 228                 return;
 229
 230         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 231
 232         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 233                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 234
 235         fam10h_mmconf_start = base;
 236         fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 237 }
 238
 239 /**
 240  * early_fill_mp_bus_to_node()
 241  * called before pcibios_scan_root and pci_scan_bus
 242  * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 243  * Registers found in the K8 northbridge
 244  */
 245 static int __init early_fill_mp_bus_info(void)
 246 {
 247         int i;
 248         int j;
 249         unsigned bus;
 250         unsigned slot;
 251         int found;
 252         int node;
 253         int link;
 254         int def_node;
 255         int def_link;
 256         struct pci_root_info *info;
 257         u32 reg;
 258         struct resource *res;
 259         size_t start;
 260         size_t end;
 261         struct res_range range[RANGE_NUM];
 262         u64 val;
 263         u32 address;
 264
 265 #ifdef CONFIG_NUMA
 266         for (i = 0; i < BUS_NR; i++)
 267                 mp_bus_to_node[i] = -1;
 268 #endif
 269
 270         if (!early_pci_allowed())
 271                 return -1;
 272
 273         found = 0;
 274         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 275                 u32 id;
 276                 u16 device;
 277                 u16 vendor;
 278
 279                 bus = pci_probes[i].bus;
 280                 slot = pci_probes[i].slot;
 281                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 282
 283                 vendor = id & 0xffff;
 284                 device = (id>>16) & 0xffff;
 285                 if (pci_probes[i].vendor == vendor &&
 286                     pci_probes[i].device == device) {
 287                         found = 1;
 288                         break;
 289                 }
 290         }
 291
 292         if (!found)
 293                 return 0;
 294
 295         pci_root_num = 0;
 296         for (i = 0; i < 4; i++) {
 297                 int min_bus;
 298                 int max_bus;
 299                 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
 300
 301                 /* Check if that register is enabled for bus range */
 302                 if ((reg & 7) != 3)
 303                         continue;
 304
 305                 min_bus = (reg >> 16) & 0xff;
 306                 max_bus = (reg >> 24) & 0xff;
 307                 node = (reg >> 4) & 0x07;
 308 #ifdef CONFIG_NUMA
 309                 for (j = min_bus; j <= max_bus; j++)
 310                         mp_bus_to_node[j] = (unsigned char) node;
 311 #endif
 312                 link = (reg >> 8) & 0x03;
 313
 314                 info = &pci_root_info[pci_root_num];
 315                 info->bus_min = min_bus;
 316                 info->bus_max = max_bus;
 317                 info->node = node;
 318                 info->link = link;
 319                 sprintf(info->name, "PCI Bus #%02x", min_bus);
 320                 pci_root_num++;
 321         }
 322
 323         /* get the default node and link for left over res */
 324         reg = read_pci_config(bus, slot, 0, 0x60);
 325         def_node = (reg >> 8) & 0x07;
 326         reg = read_pci_config(bus, slot, 0, 0x64);
 327         def_link = (reg >> 8) & 0x03;
 328
 329         memset(range, 0, sizeof(range));
 330         range[0].end = 0xffff;
 331         /* io port resource */
 332         for (i = 0; i < 4; i++) {
 333                 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
 334                 if (!(reg & 3))
 335                         continue;
 336
 337                 start = reg & 0xfff000;
 338                 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
 339                 node = reg & 0x07;
 340                 link = (reg >> 4) & 0x03;
 341                 end = (reg & 0xfff000) | 0xfff;
 342
 343                 /* find the position */
 344                 for (j = 0; j < pci_root_num; j++) {
 345                         info = &pci_root_info[j];
 346                         if (info->node == node && info->link == link)
 347                                 break;
 348                 }
 349                 if (j == pci_root_num)
 350                         continue; /* not found */
 351
 352                 info = &pci_root_info[j];
 353                 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
 354                        node, link, (u64)start, (u64)end);
 355
 356                 /* kernel only handle 16 bit only */
 357                 if (end > 0xffff)
 358                         end = 0xffff;
 359                 update_res(info, start, end, IORESOURCE_IO, 1);
 360                 update_range(range, start, end);
 361         }
 362         /* add left over io port range to def node/link, [0, 0xffff] */
 363         /* find the position */
 364         for (j = 0; j < pci_root_num; j++) {
 365                 info = &pci_root_info[j];
 366                 if (info->node == def_node && info->link == def_link)
 367                         break;
 368         }
 369         if (j < pci_root_num) {
 370                 info = &pci_root_info[j];
 371                 for (i = 0; i < RANGE_NUM; i++) {
 372                         if (!range[i].end)
 373                                 continue;
 374
 375                         update_res(info, range[i].start, range[i].end,
 376                                    IORESOURCE_IO, 1);
 377                 }
 378         }
 379
 380         memset(range, 0, sizeof(range));
 381         /* 0xfd00000000-0xffffffffff for HT */
 382         range[0].end = (0xfdULL<<32) - 1;
 383
 384         /* need to take out [0, TOM) for RAM*/
 385         address = MSR_K8_TOP_MEM1;
 386         rdmsrl(address, val);
 387         end = (val & 0xffffff800000ULL);
 388         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
 389         if (end < (1ULL<<32))
 390                 update_range(range, 0, end - 1);
 391
 392         /* get mmconfig */
 393         get_pci_mmcfg_amd_fam10h_range();
 394         /* need to take out mmconf range */
 395         if (fam10h_mmconf_end) {
 396                 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
 397                 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
 398         }
 399
 400         /* mmio resource */
 401         for (i = 0; i < 8; i++) {
 402                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 403                 if (!(reg & 3))
 404                         continue;
 405
 406                 start = reg & 0xffffff00; /* 39:16 on 31:8*/
 407                 start <<= 8;
 408                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 409                 node = reg & 0x07;
 410                 link = (reg >> 4) & 0x03;
 411                 end = (reg & 0xffffff00);
 412                 end <<= 8;
 413                 end |= 0xffff;
 414
 415                 /* find the position */
 416                 for (j = 0; j < pci_root_num; j++) {
 417                         info = &pci_root_info[j];
 418                         if (info->node == node && info->link == link)
 419                                 break;
 420                 }
 421                 if (j == pci_root_num)
 422                         continue; /* not found */
 423
 424                 info = &pci_root_info[j];
 425
 426                 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
 427                        node, link, (u64)start, (u64)end);
 428                 /*
 429                  * some sick allocation would have range overlap with fam10h
 430                  * mmconf range, so need to update start and end.
 431                  */
 432                 if (fam10h_mmconf_end) {
 433                         int changed = 0;
 434                         u64 endx = 0;
 435                         if (start >= fam10h_mmconf_start &&
 436                             start <= fam10h_mmconf_end) {
 437                                 start = fam10h_mmconf_end + 1;
 438                                 changed = 1;
 439                         }
 440
 441                         if (end >= fam10h_mmconf_start &&
 442                             end <= fam10h_mmconf_end) {
 443                                 end = fam10h_mmconf_start - 1;
 444                                 changed = 1;
 445                         }
 446
 447                         if (start < fam10h_mmconf_start &&
 448                             end > fam10h_mmconf_end) {
 449                                 /* we got a hole */
 450                                 endx = fam10h_mmconf_start - 1;
 451                                 update_res(info, start, endx, IORESOURCE_MEM, 0);
 452                                 update_range(range, start, endx);
 453                                 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
 454                                 start = fam10h_mmconf_end + 1;
 455                                 changed = 1;
 456                         }
 457                         if (changed) {
 458                                 if (start <= end) {
 459                                         printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
 460                                 } else {
 461                                         printk(KERN_CONT "%s\n", endx?"":" ==> none");
 462                                         continue;
 463                                 }
 464                         }
 465                 }
 466
 467                 update_res(info, start, end, IORESOURCE_MEM, 1);
 468                 update_range(range, start, end);
 469                 printk(KERN_CONT "\n");
 470         }
 471
 472         /* need to take out [4G, TOM2) for RAM*/
 473         /* SYS_CFG */
 474         address = MSR_K8_SYSCFG;
 475         rdmsrl(address, val);
 476         /* TOP_MEM2 is enabled? */
 477         if (val & (1<<21)) {
 478                 /* TOP_MEM2 */
 479                 address = MSR_K8_TOP_MEM2;
 480                 rdmsrl(address, val);
 481                 end = (val & 0xffffff800000ULL);
 482                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
 483                 update_range(range, 1ULL<<32, end - 1);
 484         }
 485
 486         /*
 487          * add left over mmio range to def node/link ?
 488          * that is tricky, just record range in from start_min to 4G
 489          */
 490         for (j = 0; j < pci_root_num; j++) {
 491                 info = &pci_root_info[j];
 492                 if (info->node == def_node && info->link == def_link)
 493                         break;
 494         }
 495         if (j < pci_root_num) {
 496                 info = &pci_root_info[j];
 497
 498                 for (i = 0; i < RANGE_NUM; i++) {
 499                         if (!range[i].end)
 500                                 continue;
 501
 502                         update_res(info, range[i].start, range[i].end,
 503                                    IORESOURCE_MEM, 1);
 504                 }
 505         }
 506
 507         for (i = 0; i < pci_root_num; i++) {
 508                 int res_num;
 509                 int busnum;
 510
 511                 info = &pci_root_info[i];
 512                 res_num = info->res_num;
 513                 busnum = info->bus_min;
 514                 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
 515                        info->bus_min, info->bus_max, info->node, info->link);
 516                 for (j = 0; j < res_num; j++) {
 517                         res = &info->res[j];
 518                         printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
 519                                busnum, j,
 520                                (res->flags & IORESOURCE_IO)?"io port":"mmio",
 521                                res->start, res->end);
 522                 }
 523         }
 524
 525         return 0;
 526 }
 527
 528 postcore_initcall(early_fill_mp_bus_info);