1 /* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
2 * Copyright (c) 2008 - 2009, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * Moorestown platform Langwell chip.
20 * Medfield platform Penwell chip.
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/stddef.h>
30 #include <linux/interrupt.h>
31 #include <linux/init.h>
32 #include <linux/irq.h>
34 #include <linux/gpio.h>
35 #include <linux/slab.h>
38 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
39 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
40 * registers to control them, so we only define the order here instead of a
41 * structure, to get a bit offset for a pin (use GPDR as an example):
46 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
48 * so the bit of reg_addr is to control pin offset's GPDR feature
52 GPLR
= 0, /* pin level read-only */
53 GPDR
, /* pin direction */
56 GRER
, /* rising edge detect */
57 GFER
, /* falling edge detect */
58 GEDR
, /* edge detect result */
62 struct gpio_chip chip
;
68 static void __iomem
*gpio_reg(struct gpio_chip
*chip
, unsigned offset
,
69 enum GPIO_REG reg_type
)
71 struct lnw_gpio
*lnw
= container_of(chip
, struct lnw_gpio
, chip
);
72 unsigned nreg
= chip
->ngpio
/ 32;
76 ptr
= (void __iomem
*)(lnw
->reg_base
+ reg_type
* nreg
* 4 + reg
* 4);
80 static int lnw_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
82 void __iomem
*gplr
= gpio_reg(chip
, offset
, GPLR
);
84 return readl(gplr
) & BIT(offset
% 32);
87 static void lnw_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
89 void __iomem
*gpsr
, *gpcr
;
92 gpsr
= gpio_reg(chip
, offset
, GPSR
);
93 writel(BIT(offset
% 32), gpsr
);
95 gpcr
= gpio_reg(chip
, offset
, GPCR
);
96 writel(BIT(offset
% 32), gpcr
);
100 static int lnw_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
102 struct lnw_gpio
*lnw
= container_of(chip
, struct lnw_gpio
, chip
);
103 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
107 spin_lock_irqsave(&lnw
->lock
, flags
);
109 value
&= ~BIT(offset
% 32);
111 spin_unlock_irqrestore(&lnw
->lock
, flags
);
115 static int lnw_gpio_direction_output(struct gpio_chip
*chip
,
116 unsigned offset
, int value
)
118 struct lnw_gpio
*lnw
= container_of(chip
, struct lnw_gpio
, chip
);
119 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
122 lnw_gpio_set(chip
, offset
, value
);
123 spin_lock_irqsave(&lnw
->lock
, flags
);
125 value
|= BIT(offset
% 32);;
127 spin_unlock_irqrestore(&lnw
->lock
, flags
);
131 static int lnw_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
133 struct lnw_gpio
*lnw
= container_of(chip
, struct lnw_gpio
, chip
);
134 return lnw
->irq_base
+ offset
;
137 static int lnw_irq_type(unsigned irq
, unsigned type
)
139 struct lnw_gpio
*lnw
= get_irq_chip_data(irq
);
140 u32 gpio
= irq
- lnw
->irq_base
;
143 void __iomem
*grer
= gpio_reg(&lnw
->chip
, gpio
, GRER
);
144 void __iomem
*gfer
= gpio_reg(&lnw
->chip
, gpio
, GFER
);
146 if (gpio
>= lnw
->chip
.ngpio
)
148 spin_lock_irqsave(&lnw
->lock
, flags
);
149 if (type
& IRQ_TYPE_EDGE_RISING
)
150 value
= readl(grer
) | BIT(gpio
% 32);
152 value
= readl(grer
) & (~BIT(gpio
% 32));
155 if (type
& IRQ_TYPE_EDGE_FALLING
)
156 value
= readl(gfer
) | BIT(gpio
% 32);
158 value
= readl(gfer
) & (~BIT(gpio
% 32));
160 spin_unlock_irqrestore(&lnw
->lock
, flags
);
165 static void lnw_irq_unmask(unsigned irq
)
169 static void lnw_irq_mask(unsigned irq
)
173 static struct irq_chip lnw_irqchip
= {
175 .mask
= lnw_irq_mask
,
176 .unmask
= lnw_irq_unmask
,
177 .set_type
= lnw_irq_type
,
180 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids
) = { /* pin number */
181 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x080f), .driver_data
= 64 },
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081f), .driver_data
= 96 },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081a), .driver_data
= 96 },
186 MODULE_DEVICE_TABLE(pci
, lnw_gpio_ids
);
188 static void lnw_irq_handler(unsigned irq
, struct irq_desc
*desc
)
190 struct lnw_gpio
*lnw
= (struct lnw_gpio
*)get_irq_data(irq
);
195 /* check GPIO controller to check which pin triggered the interrupt */
196 for (base
= 0; base
< lnw
->chip
.ngpio
; base
+= 32) {
197 gedr
= gpio_reg(&lnw
->chip
, base
, GEDR
);
198 gedr_v
= readl(gedr
);
201 for (gpio
= base
; gpio
< base
+ 32; gpio
++)
202 if (gedr_v
& BIT(gpio
% 32)) {
203 pr_debug("pin %d triggered\n", gpio
);
204 generic_handle_irq(lnw
->irq_base
+ gpio
);
206 /* clear the edge detect status bit */
207 writel(gedr_v
, gedr
);
209 desc
->chip
->eoi(irq
);
212 static int __devinit
lnw_gpio_probe(struct pci_dev
*pdev
,
213 const struct pci_device_id
*id
)
217 resource_size_t start
, len
;
218 struct lnw_gpio
*lnw
;
223 retval
= pci_enable_device(pdev
);
227 retval
= pci_request_regions(pdev
, "langwell_gpio");
229 dev_err(&pdev
->dev
, "error requesting resources\n");
232 /* get the irq_base from bar1 */
233 start
= pci_resource_start(pdev
, 1);
234 len
= pci_resource_len(pdev
, 1);
235 base
= ioremap_nocache(start
, len
);
237 dev_err(&pdev
->dev
, "error mapping bar1\n");
240 irq_base
= *(u32
*)base
;
241 gpio_base
= *((u32
*)base
+ 1);
242 /* release the IO mapping, since we already get the info from bar1 */
244 /* get the register base from bar0 */
245 start
= pci_resource_start(pdev
, 0);
246 len
= pci_resource_len(pdev
, 0);
247 base
= ioremap_nocache(start
, len
);
249 dev_err(&pdev
->dev
, "error mapping bar0\n");
254 lnw
= kzalloc(sizeof(struct lnw_gpio
), GFP_KERNEL
);
256 dev_err(&pdev
->dev
, "can't allocate langwell_gpio chip data\n");
260 lnw
->reg_base
= base
;
261 lnw
->irq_base
= irq_base
;
262 lnw
->chip
.label
= dev_name(&pdev
->dev
);
263 lnw
->chip
.direction_input
= lnw_gpio_direction_input
;
264 lnw
->chip
.direction_output
= lnw_gpio_direction_output
;
265 lnw
->chip
.get
= lnw_gpio_get
;
266 lnw
->chip
.set
= lnw_gpio_set
;
267 lnw
->chip
.to_irq
= lnw_gpio_to_irq
;
268 lnw
->chip
.base
= gpio_base
;
269 lnw
->chip
.ngpio
= id
->driver_data
;
270 lnw
->chip
.can_sleep
= 0;
271 pci_set_drvdata(pdev
, lnw
);
272 retval
= gpiochip_add(&lnw
->chip
);
274 dev_err(&pdev
->dev
, "langwell gpiochip_add error %d\n", retval
);
277 set_irq_data(pdev
->irq
, lnw
);
278 set_irq_chained_handler(pdev
->irq
, lnw_irq_handler
);
279 for (i
= 0; i
< lnw
->chip
.ngpio
; i
++) {
280 set_irq_chip_and_handler_name(i
+ lnw
->irq_base
, &lnw_irqchip
,
281 handle_simple_irq
, "demux");
282 set_irq_chip_data(i
+ lnw
->irq_base
, lnw
);
285 spin_lock_init(&lnw
->lock
);
292 pci_release_regions(pdev
);
294 pci_disable_device(pdev
);
299 static struct pci_driver lnw_gpio_driver
= {
300 .name
= "langwell_gpio",
301 .id_table
= lnw_gpio_ids
,
302 .probe
= lnw_gpio_probe
,
306 static int __devinit
wp_gpio_probe(struct platform_device
*pdev
)
308 struct lnw_gpio
*lnw
;
309 struct gpio_chip
*gc
;
313 rc
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
317 lnw
= kzalloc(sizeof(struct lnw_gpio
), GFP_KERNEL
);
320 "can't allocate whitneypoint_gpio chip data\n");
323 lnw
->reg_base
= ioremap_nocache(rc
->start
, resource_size(rc
));
324 if (lnw
->reg_base
== NULL
) {
328 spin_lock_init(&lnw
->lock
);
330 gc
->label
= dev_name(&pdev
->dev
);
331 gc
->owner
= THIS_MODULE
;
332 gc
->direction_input
= lnw_gpio_direction_input
;
333 gc
->direction_output
= lnw_gpio_direction_output
;
334 gc
->get
= lnw_gpio_get
;
335 gc
->set
= lnw_gpio_set
;
340 retval
= gpiochip_add(gc
);
342 dev_err(&pdev
->dev
, "whitneypoint gpiochip_add error %d\n",
346 platform_set_drvdata(pdev
, lnw
);
349 iounmap(lnw
->reg_base
);
355 static int __devexit
wp_gpio_remove(struct platform_device
*pdev
)
357 struct lnw_gpio
*lnw
= platform_get_drvdata(pdev
);
359 err
= gpiochip_remove(&lnw
->chip
);
361 dev_err(&pdev
->dev
, "failed to remove gpio_chip.\n");
362 iounmap(lnw
->reg_base
);
364 platform_set_drvdata(pdev
, NULL
);
368 static struct platform_driver wp_gpio_driver
= {
369 .probe
= wp_gpio_probe
,
370 .remove
= __devexit_p(wp_gpio_remove
),
373 .owner
= THIS_MODULE
,
377 static int __init
lnw_gpio_init(void)
380 ret
= pci_register_driver(&lnw_gpio_driver
);
383 ret
= platform_driver_register(&wp_gpio_driver
);
385 pci_unregister_driver(&lnw_gpio_driver
);
389 device_initcall(lnw_gpio_init
);