arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <trace/power.h>
  13 #include <asm/system.h>
  14 #include <asm/apic.h>
  15 #include <asm/syscalls.h>
  16 #include <asm/idle.h>
  17 #include <asm/uaccess.h>
  18 #include <asm/i387.h>
  19 #include <asm/ds.h>
  20
  21 unsigned long idle_halt;
  22 EXPORT_SYMBOL(idle_halt);
  23 unsigned long idle_nomwait;
  24 EXPORT_SYMBOL(idle_nomwait);
  25
  26 struct kmem_cache *task_xstate_cachep;
  27
  28 DEFINE_TRACE(power_start);
  29 DEFINE_TRACE(power_end);
  30
  31 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  32 {
  33         *dst = *src;
  34         if (src->thread.xstate) {
  35                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  36                                                       GFP_KERNEL);
  37                 if (!dst->thread.xstate)
  38                         return -ENOMEM;
  39                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  40                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  41         }
  42         return 0;
  43 }
  44
  45 void free_thread_xstate(struct task_struct *tsk)
  46 {
  47         if (tsk->thread.xstate) {
  48                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  49                 tsk->thread.xstate = NULL;
  50         }
  51
  52         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  53 }
  54
  55 void free_thread_info(struct thread_info *ti)
  56 {
  57         free_thread_xstate(ti->task);
  58         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  59 }
  60
  61 void arch_task_cache_init(void)
  62 {
  63         task_xstate_cachep =
  64                 kmem_cache_create("task_xstate", xstate_size,
  65                                   __alignof__(union thread_xstate),
  66                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  67 }
  68
  69 /*
  70  * Free current thread data structures etc..
  71  */
  72 void exit_thread(void)
  73 {
  74         struct task_struct *me = current;
  75         struct thread_struct *t = &me->thread;
  76         unsigned long *bp = t->io_bitmap_ptr;
  77
  78         if (bp) {
  79                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  80
  81                 t->io_bitmap_ptr = NULL;
  82                 clear_thread_flag(TIF_IO_BITMAP);
  83                 /*
  84                  * Careful, clear this in the TSS too:
  85                  */
  86                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  87                 t->io_bitmap_max = 0;
  88                 put_cpu();
  89                 kfree(bp);
  90         }
  91 }
  92
  93 void flush_thread(void)
  94 {
  95         struct task_struct *tsk = current;
  96
  97 #ifdef CONFIG_X86_64
  98         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
  99                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 100                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 101                         clear_tsk_thread_flag(tsk, TIF_IA32);
 102                 } else {
 103                         set_tsk_thread_flag(tsk, TIF_IA32);
 104                         current_thread_info()->status |= TS_COMPAT;
 105                 }
 106         }
 107 #endif
 108
 109         clear_tsk_thread_flag(tsk, TIF_DEBUG);
 110
 111         tsk->thread.debugreg0 = 0;
 112         tsk->thread.debugreg1 = 0;
 113         tsk->thread.debugreg2 = 0;
 114         tsk->thread.debugreg3 = 0;
 115         tsk->thread.debugreg6 = 0;
 116         tsk->thread.debugreg7 = 0;
 117         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 118         /*
 119          * Forget coprocessor state..
 120          */
 121         tsk->fpu_counter = 0;
 122         clear_fpu(tsk);
 123         clear_used_math();
 124 }
 125
 126 static void hard_disable_TSC(void)
 127 {
 128         write_cr4(read_cr4() | X86_CR4_TSD);
 129 }
 130
 131 void disable_TSC(void)
 132 {
 133         preempt_disable();
 134         if (!test_and_set_thread_flag(TIF_NOTSC))
 135                 /*
 136                  * Must flip the CPU state synchronously with
 137                  * TIF_NOTSC in the current running context.
 138                  */
 139                 hard_disable_TSC();
 140         preempt_enable();
 141 }
 142
 143 static void hard_enable_TSC(void)
 144 {
 145         write_cr4(read_cr4() & ~X86_CR4_TSD);
 146 }
 147
 148 static void enable_TSC(void)
 149 {
 150         preempt_disable();
 151         if (test_and_clear_thread_flag(TIF_NOTSC))
 152                 /*
 153                  * Must flip the CPU state synchronously with
 154                  * TIF_NOTSC in the current running context.
 155                  */
 156                 hard_enable_TSC();
 157         preempt_enable();
 158 }
 159
 160 int get_tsc_mode(unsigned long adr)
 161 {
 162         unsigned int val;
 163
 164         if (test_thread_flag(TIF_NOTSC))
 165                 val = PR_TSC_SIGSEGV;
 166         else
 167                 val = PR_TSC_ENABLE;
 168
 169         return put_user(val, (unsigned int __user *)adr);
 170 }
 171
 172 int set_tsc_mode(unsigned int val)
 173 {
 174         if (val == PR_TSC_SIGSEGV)
 175                 disable_TSC();
 176         else if (val == PR_TSC_ENABLE)
 177                 enable_TSC();
 178         else
 179                 return -EINVAL;
 180
 181         return 0;
 182 }
 183
 184 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 185                       struct tss_struct *tss)
 186 {
 187         struct thread_struct *prev, *next;
 188
 189         prev = &prev_p->thread;
 190         next = &next_p->thread;
 191
 192         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 193             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 194                 ds_switch_to(prev_p, next_p);
 195         else if (next->debugctlmsr != prev->debugctlmsr)
 196                 update_debugctlmsr(next->debugctlmsr);
 197
 198         if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
 199                 set_debugreg(next->debugreg0, 0);
 200                 set_debugreg(next->debugreg1, 1);
 201                 set_debugreg(next->debugreg2, 2);
 202                 set_debugreg(next->debugreg3, 3);
 203                 /* no 4 and 5 */
 204                 set_debugreg(next->debugreg6, 6);
 205                 set_debugreg(next->debugreg7, 7);
 206         }
 207
 208         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 209             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 210                 /* prev and next are different */
 211                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 212                         hard_disable_TSC();
 213                 else
 214                         hard_enable_TSC();
 215         }
 216
 217         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 218                 /*
 219                  * Copy the relevant range of the IO bitmap.
 220                  * Normally this is 128 bytes or less:
 221                  */
 222                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 223                        max(prev->io_bitmap_max, next->io_bitmap_max));
 224         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 225                 /*
 226                  * Clear any possible leftover bits:
 227                  */
 228                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 229         }
 230 }
 231
 232 int sys_fork(struct pt_regs *regs)
 233 {
 234         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 235 }
 236
 237 /*
 238  * This is trivial, and on the face of it looks like it
 239  * could equally well be done in user mode.
 240  *
 241  * Not so, for quite unobvious reasons - register pressure.
 242  * In user mode vfork() cannot have a stack frame, and if
 243  * done by calling the "clone()" system call directly, you
 244  * do not have enough call-clobbered registers to hold all
 245  * the information you need.
 246  */
 247 int sys_vfork(struct pt_regs *regs)
 248 {
 249         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 250                        NULL, NULL);
 251 }
 252
 253
 254 /*
 255  * Idle related variables and functions
 256  */
 257 unsigned long boot_option_idle_override = 0;
 258 EXPORT_SYMBOL(boot_option_idle_override);
 259
 260 /*
 261  * Powermanagement idle function, if any..
 262  */
 263 void (*pm_idle)(void);
 264 EXPORT_SYMBOL(pm_idle);
 265
 266 #ifdef CONFIG_X86_32
 267 /*
 268  * This halt magic was a workaround for ancient floppy DMA
 269  * wreckage. It should be safe to remove.
 270  */
 271 static int hlt_counter;
 272 void disable_hlt(void)
 273 {
 274         hlt_counter++;
 275 }
 276 EXPORT_SYMBOL(disable_hlt);
 277
 278 void enable_hlt(void)
 279 {
 280         hlt_counter--;
 281 }
 282 EXPORT_SYMBOL(enable_hlt);
 283
 284 static inline int hlt_use_halt(void)
 285 {
 286         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 287 }
 288 #else
 289 static inline int hlt_use_halt(void)
 290 {
 291         return 1;
 292 }
 293 #endif
 294
 295 /*
 296  * We use this if we don't have any better
 297  * idle routine..
 298  */
 299 void default_idle(void)
 300 {
 301         if (hlt_use_halt()) {
 302                 struct power_trace it;
 303
 304                 trace_power_start(&it, POWER_CSTATE, 1);
 305                 current_thread_info()->status &= ~TS_POLLING;
 306                 /*
 307                  * TS_POLLING-cleared state must be visible before we
 308                  * test NEED_RESCHED:
 309                  */
 310                 smp_mb();
 311
 312                 if (!need_resched())
 313                         safe_halt();    /* enables interrupts racelessly */
 314                 else
 315                         local_irq_enable();
 316                 current_thread_info()->status |= TS_POLLING;
 317                 trace_power_end(&it);
 318         } else {
 319                 local_irq_enable();
 320                 /* loop is done by the caller */
 321                 cpu_relax();
 322         }
 323 }
 324 #ifdef CONFIG_APM_MODULE
 325 EXPORT_SYMBOL(default_idle);
 326 #endif
 327
 328 void stop_this_cpu(void *dummy)
 329 {
 330         local_irq_disable();
 331         /*
 332          * Remove this CPU:
 333          */
 334         set_cpu_online(smp_processor_id(), false);
 335         disable_local_APIC();
 336
 337         for (;;) {
 338                 if (hlt_works(smp_processor_id()))
 339                         halt();
 340         }
 341 }
 342
 343 static void do_nothing(void *unused)
 344 {
 345 }
 346
 347 /*
 348  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 349  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 350  * handler on SMP systems.
 351  *
 352  * Caller must have changed pm_idle to the new value before the call. Old
 353  * pm_idle value will not be used by any CPU after the return of this function.
 354  */
 355 void cpu_idle_wait(void)
 356 {
 357         smp_mb();
 358         /* kick all the CPUs so that they exit out of pm_idle */
 359         smp_call_function(do_nothing, NULL, 1);
 360 }
 361 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 362
 363 /*
 364  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 365  * which can obviate IPI to trigger checking of need_resched.
 366  * We execute MONITOR against need_resched and enter optimized wait state
 367  * through MWAIT. Whenever someone changes need_resched, we would be woken
 368  * up from MWAIT (without an IPI).
 369  *
 370  * New with Core Duo processors, MWAIT can take some hints based on CPU
 371  * capability.
 372  */
 373 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 374 {
 375         struct power_trace it;
 376
 377         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 378         if (!need_resched()) {
 379                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 380                         clflush((void *)&current_thread_info()->flags);
 381
 382                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 383                 smp_mb();
 384                 if (!need_resched())
 385                         __mwait(ax, cx);
 386         }
 387         trace_power_end(&it);
 388 }
 389
 390 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 391 static void mwait_idle(void)
 392 {
 393         struct power_trace it;
 394         if (!need_resched()) {
 395                 trace_power_start(&it, POWER_CSTATE, 1);
 396                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 397                         clflush((void *)&current_thread_info()->flags);
 398
 399                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 400                 smp_mb();
 401                 if (!need_resched())
 402                         __sti_mwait(0, 0);
 403                 else
 404                         local_irq_enable();
 405                 trace_power_end(&it);
 406         } else
 407                 local_irq_enable();
 408 }
 409
 410 /*
 411  * On SMP it's slightly faster (but much more power-consuming!)
 412  * to poll the ->work.need_resched flag instead of waiting for the
 413  * cross-CPU IPI to arrive. Use this option with caution.
 414  */
 415 static void poll_idle(void)
 416 {
 417         struct power_trace it;
 418
 419         trace_power_start(&it, POWER_CSTATE, 0);
 420         local_irq_enable();
 421         while (!need_resched())
 422                 cpu_relax();
 423         trace_power_end(&it);
 424 }
 425
 426 /*
 427  * mwait selection logic:
 428  *
 429  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 430  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 431  * then depend on a clock divisor and current Pstate of the core. If
 432  * all cores of a processor are in halt state (C1) the processor can
 433  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 434  * happen.
 435  *
 436  * idle=mwait overrides this decision and forces the usage of mwait.
 437  */
 438 static int __cpuinitdata force_mwait;
 439
 440 #define MWAIT_INFO                      0x05
 441 #define MWAIT_ECX_EXTENDED_INFO         0x01
 442 #define MWAIT_EDX_C1                    0xf0
 443
 444 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 445 {
 446         u32 eax, ebx, ecx, edx;
 447
 448         if (force_mwait)
 449                 return 1;
 450
 451         if (c->cpuid_level < MWAIT_INFO)
 452                 return 0;
 453
 454         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 455         /* Check, whether EDX has extended info about MWAIT */
 456         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 457                 return 1;
 458
 459         /*
 460          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 461          * C1  supports MWAIT
 462          */
 463         return (edx & MWAIT_EDX_C1);
 464 }
 465
 466 /*
 467  * Check for AMD CPUs, which have potentially C1E support
 468  */
 469 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 470 {
 471         if (c->x86_vendor != X86_VENDOR_AMD)
 472                 return 0;
 473
 474         if (c->x86 < 0x0F)
 475                 return 0;
 476
 477         /* Family 0x0f models < rev F do not have C1E */
 478         if (c->x86 == 0x0f && c->x86_model < 0x40)
 479                 return 0;
 480
 481         return 1;
 482 }
 483
 484 static cpumask_var_t c1e_mask;
 485 static int c1e_detected;
 486
 487 void c1e_remove_cpu(int cpu)
 488 {
 489         if (c1e_mask != NULL)
 490                 cpumask_clear_cpu(cpu, c1e_mask);
 491 }
 492
 493 /*
 494  * C1E aware idle routine. We check for C1E active in the interrupt
 495  * pending message MSR. If we detect C1E, then we handle it the same
 496  * way as C3 power states (local apic timer and TSC stop)
 497  */
 498 static void c1e_idle(void)
 499 {
 500         if (need_resched())
 501                 return;
 502
 503         if (!c1e_detected) {
 504                 u32 lo, hi;
 505
 506                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 507                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 508                         c1e_detected = 1;
 509                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 510                                 mark_tsc_unstable("TSC halt in AMD C1E");
 511                         printk(KERN_INFO "System has AMD C1E enabled\n");
 512                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 513                 }
 514         }
 515
 516         if (c1e_detected) {
 517                 int cpu = smp_processor_id();
 518
 519                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 520                         cpumask_set_cpu(cpu, c1e_mask);
 521                         /*
 522                          * Force broadcast so ACPI can not interfere.
 523                          */
 524                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 525                                            &cpu);
 526                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 527                                cpu);
 528                 }
 529                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 530
 531                 default_idle();
 532
 533                 /*
 534                  * The switch back from broadcast mode needs to be
 535                  * called with interrupts disabled.
 536                  */
 537                  local_irq_disable();
 538                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 539                  local_irq_enable();
 540         } else
 541                 default_idle();
 542 }
 543
 544 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 545 {
 546 #ifdef CONFIG_SMP
 547         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 548                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 549                         " performance may degrade.\n");
 550         }
 551 #endif
 552         if (pm_idle)
 553                 return;
 554
 555         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 556                 /*
 557                  * One CPU supports mwait => All CPUs supports mwait
 558                  */
 559                 printk(KERN_INFO "using mwait in idle threads.\n");
 560                 pm_idle = mwait_idle;
 561         } else if (check_c1e_idle(c)) {
 562                 printk(KERN_INFO "using C1E aware idle routine\n");
 563                 pm_idle = c1e_idle;
 564         } else
 565                 pm_idle = default_idle;
 566 }
 567
 568 void __init init_c1e_mask(void)
 569 {
 570         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 571         if (pm_idle == c1e_idle) {
 572                 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 573                 cpumask_clear(c1e_mask);
 574         }
 575 }
 576
 577 static int __init idle_setup(char *str)
 578 {
 579         if (!str)
 580                 return -EINVAL;
 581
 582         if (!strcmp(str, "poll")) {
 583                 printk("using polling idle threads.\n");
 584                 pm_idle = poll_idle;
 585         } else if (!strcmp(str, "mwait"))
 586                 force_mwait = 1;
 587         else if (!strcmp(str, "halt")) {
 588                 /*
 589                  * When the boot option of idle=halt is added, halt is
 590                  * forced to be used for CPU idle. In such case CPU C2/C3
 591                  * won't be used again.
 592                  * To continue to load the CPU idle driver, don't touch
 593                  * the boot_option_idle_override.
 594                  */
 595                 pm_idle = default_idle;
 596                 idle_halt = 1;
 597                 return 0;
 598         } else if (!strcmp(str, "nomwait")) {
 599                 /*
 600                  * If the boot option of "idle=nomwait" is added,
 601                  * it means that mwait will be disabled for CPU C2/C3
 602                  * states. In such case it won't touch the variable
 603                  * of boot_option_idle_override.
 604                  */
 605                 idle_nomwait = 1;
 606                 return 0;
 607         } else
 608                 return -1;
 609
 610         boot_option_idle_override = 1;
 611         return 0;
 612 }
 613 early_param("idle", idle_setup);
 614
 615 unsigned long arch_align_stack(unsigned long sp)
 616 {
 617         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 618                 sp -= get_random_int() % 8192;
 619         return sp & ~0xf;
 620 }
 621
 622 unsigned long arch_randomize_brk(struct mm_struct *mm)
 623 {
 624         unsigned long range_end = mm->brk + 0x02000000;
 625         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 626 }
 627