drivers/net/wireless/ath9k/core.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef CORE_H
  18 #define CORE_H
  19
  20 #include <linux/version.h>
  21 #include <linux/autoconf.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/ip.h>
  30 #include <linux/tcp.h>
  31 #include <linux/in.h>
  32 #include <linux/delay.h>
  33 #include <linux/wait.h>
  34 #include <linux/pci.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/sched.h>
  37 #include <linux/list.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/scatterlist.h>
  40 #include <asm/page.h>
  41 #include <net/mac80211.h>
  42 #include <linux/leds.h>
  43 #include <linux/rfkill.h>
  44
  45 #include "ath9k.h"
  46 #include "rc.h"
  47
  48 struct ath_node;
  49
  50 /******************/
  51 /* Utility macros */
  52 /******************/
  53
  54 /* Macro to expand scalars to 64-bit objects */
  55
  56 #define ito64(x) (sizeof(x) == 8) ?                     \
  57         (((unsigned long long int)(x)) & (0xff)) :      \
  58         (sizeof(x) == 16) ?                             \
  59         (((unsigned long long int)(x)) & 0xffff) :      \
  60         ((sizeof(x) == 32) ?                            \
  61          (((unsigned long long int)(x)) & 0xffffffff) : \
  62          (unsigned long long int)(x))
  63
  64 /* increment with wrap-around */
  65 #define INCR(_l, _sz)   do {                    \
  66                 (_l)++;                         \
  67                 (_l) &= ((_sz) - 1);            \
  68         } while (0)
  69
  70 /* decrement with wrap-around */
  71 #define DECR(_l,  _sz)  do {                    \
  72                 (_l)--;                         \
  73                 (_l) &= ((_sz) - 1);            \
  74         } while (0)
  75
  76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  77
  78 #define ASSERT(exp) do {                        \
  79                 if (unlikely(!(exp))) {         \
  80                         BUG();                  \
  81                 }                               \
  82         } while (0)
  83
  84 #define TSF_TO_TU(_h,_l) \
  85         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  86
  87 #define ATH_TXQ_SETUP(sc, i)        ((sc)->sc_txqsetup & (1<<i))
  88
  89 static inline unsigned long get_timestamp(void)
  90 {
  91         return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
  92 }
  93
  94 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  95
  96 /*************/
  97 /* Debugging */
  98 /*************/
  99
 100 enum ATH_DEBUG {
 101         ATH_DBG_RESET           = 0x00000001,
 102         ATH_DBG_PHY_IO          = 0x00000002,
 103         ATH_DBG_REG_IO          = 0x00000004,
 104         ATH_DBG_QUEUE           = 0x00000008,
 105         ATH_DBG_EEPROM          = 0x00000010,
 106         ATH_DBG_NF_CAL          = 0x00000020,
 107         ATH_DBG_CALIBRATE       = 0x00000040,
 108         ATH_DBG_CHANNEL         = 0x00000080,
 109         ATH_DBG_INTERRUPT       = 0x00000100,
 110         ATH_DBG_REGULATORY      = 0x00000200,
 111         ATH_DBG_ANI             = 0x00000400,
 112         ATH_DBG_POWER_MGMT      = 0x00000800,
 113         ATH_DBG_XMIT            = 0x00001000,
 114         ATH_DBG_BEACON          = 0x00002000,
 115         ATH_DBG_RATE            = 0x00004000,
 116         ATH_DBG_CONFIG          = 0x00008000,
 117         ATH_DBG_KEYCACHE        = 0x00010000,
 118         ATH_DBG_AGGR            = 0x00020000,
 119         ATH_DBG_FATAL           = 0x00040000,
 120         ATH_DBG_ANY             = 0xffffffff
 121 };
 122
 123 #define DBG_DEFAULT (ATH_DBG_FATAL)
 124
 125 #define DPRINTF(sc, _m, _fmt, ...) do {                 \
 126                 if (sc->sc_debug & (_m))                \
 127                         printk(_fmt , ##__VA_ARGS__);   \
 128         } while (0)
 129
 130 /***************************/
 131 /* Load-time Configuration */
 132 /***************************/
 133
 134 /* Per-instance load-time (note: NOT run-time) configurations
 135  * for Atheros Device */
 136 struct ath_config {
 137         u32 ath_aggr_prot;
 138         u16 txpowlimit;
 139         u16 txpowlimit_override;
 140         u8 cabqReadytime; /* Cabq Readytime % */
 141         u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
 142 };
 143
 144 /***********************/
 145 /* Chainmask Selection */
 146 /***********************/
 147
 148 #define ATH_CHAINMASK_SEL_TIMEOUT          6000
 149 /* Default - Number of last RSSI values that is used for
 150  * chainmask selection */
 151 #define ATH_CHAINMASK_SEL_RSSI_CNT         10
 152 /* Means use 3x3 chainmask instead of configured chainmask */
 153 #define ATH_CHAINMASK_SEL_3X3              7
 154 /* Default - Rssi threshold below which we have to switch to 3x3 */
 155 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES    20
 156 /* Default - Rssi threshold above which we have to switch to
 157  * user configured values */
 158 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES  35
 159 /* Struct to store the chainmask select related info */
 160 struct ath_chainmask_sel {
 161         struct timer_list timer;
 162         int cur_tx_mask;        /* user configured or 3x3 */
 163         int cur_rx_mask;        /* user configured or 3x3 */
 164         int tx_avgrssi;
 165         u8 switch_allowed:1,    /* timer will set this */
 166            cm_sel_enabled : 1;
 167 };
 168
 169 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
 170 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 171
 172 /*************************/
 173 /* Descriptor Management */
 174 /*************************/
 175
 176 #define ATH_TXBUF_RESET(_bf) do {                               \
 177                 (_bf)->bf_status = 0;                           \
 178                 (_bf)->bf_lastbf = NULL;                        \
 179                 (_bf)->bf_lastfrm = NULL;                       \
 180                 (_bf)->bf_next = NULL;                          \
 181                 memset(&((_bf)->bf_state), 0,                   \
 182                             sizeof(struct ath_buf_state));      \
 183         } while (0)
 184
 185 enum buffer_type {
 186         BUF_DATA                = BIT(0),
 187         BUF_AGGR                = BIT(1),
 188         BUF_AMPDU               = BIT(2),
 189         BUF_HT                  = BIT(3),
 190         BUF_RETRY               = BIT(4),
 191         BUF_XRETRY              = BIT(5),
 192         BUF_SHORT_PREAMBLE      = BIT(6),
 193         BUF_BAR                 = BIT(7),
 194         BUF_PSPOLL              = BIT(8),
 195         BUF_AGGR_BURST          = BIT(9),
 196         BUF_CALC_AIRTIME        = BIT(10),
 197 };
 198
 199 struct ath_buf_state {
 200         int bfs_nframes;                        /* # frames in aggregate */
 201         u16 bfs_al;                             /* length of aggregate */
 202         u16 bfs_frmlen;                         /* length of frame */
 203         int bfs_seqno;                          /* sequence number */
 204         int bfs_tidno;                          /* tid of this frame */
 205         int bfs_retries;                        /* current retries */
 206         struct ath_rc_series bfs_rcs[4];        /* rate series */
 207         u32 bf_type;                            /* BUF_* (enum buffer_type) */
 208         /* key type use to encrypt this frame */
 209         u32 bfs_keyix;
 210         enum ath9k_key_type bfs_keytype;
 211 };
 212
 213 #define bf_nframes              bf_state.bfs_nframes
 214 #define bf_al                   bf_state.bfs_al
 215 #define bf_frmlen               bf_state.bfs_frmlen
 216 #define bf_retries              bf_state.bfs_retries
 217 #define bf_seqno                bf_state.bfs_seqno
 218 #define bf_tidno                bf_state.bfs_tidno
 219 #define bf_rcs                  bf_state.bfs_rcs
 220 #define bf_keyix                bf_state.bfs_keyix
 221 #define bf_keytype              bf_state.bfs_keytype
 222 #define bf_isdata(bf)           (bf->bf_state.bf_type & BUF_DATA)
 223 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 224 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 225 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 226 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 227 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 228 #define bf_isshpreamble(bf)     (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
 229 #define bf_isbar(bf)            (bf->bf_state.bf_type & BUF_BAR)
 230 #define bf_ispspoll(bf)         (bf->bf_state.bf_type & BUF_PSPOLL)
 231 #define bf_isaggrburst(bf)      (bf->bf_state.bf_type & BUF_AGGR_BURST)
 232
 233 /*
 234  * Abstraction of a contiguous buffer to transmit/receive.  There is only
 235  * a single hw descriptor encapsulated here.
 236  */
 237 struct ath_buf {
 238         struct list_head list;
 239         struct list_head *last;
 240         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 241                                            an aggregate) */
 242         struct ath_buf *bf_lastfrm;     /* last buf of this frame */
 243         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 244         struct ath_buf *bf_rifslast;    /* last buf for RIFS burst */
 245         void *bf_mpdu;                  /* enclosing frame structure */
 246         struct ath_desc *bf_desc;       /* virtual addr of desc */
 247         dma_addr_t bf_daddr;            /* physical addr of desc */
 248         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 249         u32 bf_status;
 250         u16 bf_flags;                   /* tx descriptor flags */
 251         struct ath_buf_state bf_state;  /* buffer state */
 252         dma_addr_t bf_dmacontext;
 253 };
 254
 255 /*
 256  * reset the rx buffer.
 257  * any new fields added to the athbuf and require
 258  * reset need to be added to this macro.
 259  * currently bf_status is the only one requires that
 260  * requires reset.
 261  */
 262 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 263
 264 /* hw processing complete, desc processed by hal */
 265 #define ATH_BUFSTATUS_DONE      0x00000001
 266 /* hw processing complete, desc hold for hw */
 267 #define ATH_BUFSTATUS_STALE     0x00000002
 268 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
 269 #define ATH_BUFSTATUS_FREE      0x00000004
 270
 271 /* DMA state for tx/rx descriptors */
 272
 273 struct ath_descdma {
 274         const char *dd_name;
 275         struct ath_desc *dd_desc;       /* descriptors  */
 276         dma_addr_t dd_desc_paddr;       /* physical addr of dd_desc  */
 277         u32 dd_desc_len;                /* size of dd_desc  */
 278         struct ath_buf *dd_bufptr;      /* associated buffers */
 279         dma_addr_t dd_dmacontext;
 280 };
 281
 282 int ath_descdma_setup(struct ath_softc *sc,
 283                       struct ath_descdma *dd,
 284                       struct list_head *head,
 285                       const char *name,
 286                       int nbuf,
 287                       int ndesc);
 288 int ath_desc_alloc(struct ath_softc *sc);
 289 void ath_desc_free(struct ath_softc *sc);
 290 void ath_descdma_cleanup(struct ath_softc *sc,
 291                          struct ath_descdma *dd,
 292                          struct list_head *head);
 293
 294 /***********/
 295 /* RX / TX */
 296 /***********/
 297
 298 #define ATH_MAX_ANTENNA          3
 299 #define ATH_RXBUF                512
 300 #define WME_NUM_TID              16
 301
 302 int ath_startrecv(struct ath_softc *sc);
 303 bool ath_stoprecv(struct ath_softc *sc);
 304 void ath_flushrecv(struct ath_softc *sc);
 305 u32 ath_calcrxfilter(struct ath_softc *sc);
 306 int ath_rx_init(struct ath_softc *sc, int nbufs);
 307 void ath_rx_cleanup(struct ath_softc *sc);
 308 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 309
 310 #define ATH_TXBUF               512
 311 /* max number of transmit attempts (tries) */
 312 #define ATH_TXMAXTRY            13
 313 /* max number of 11n transmit attempts (tries) */
 314 #define ATH_11N_TXMAXTRY        10
 315 /* max number of tries for management and control frames */
 316 #define ATH_MGT_TXMAXTRY        4
 317 #define WME_BA_BMP_SIZE         64
 318 #define WME_MAX_BA              WME_BA_BMP_SIZE
 319 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 320 #define TID_TO_WME_AC(_tid)                             \
 321         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 322          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 323          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 324          WME_AC_VO)
 325
 326
 327 /* Wireless Multimedia Extension Defines */
 328 #define WME_AC_BE               0 /* best effort */
 329 #define WME_AC_BK               1 /* background */
 330 #define WME_AC_VI               2 /* video */
 331 #define WME_AC_VO               3 /* voice */
 332 #define WME_NUM_AC              4
 333
 334 /*
 335  * Data transmit queue state.  One of these exists for each
 336  * hardware transmit queue.  Packets sent to us from above
 337  * are assigned to queues based on their priority.  Not all
 338  * devices support a complete set of hardware transmit queues.
 339  * For those devices the array sc_ac2q will map multiple
 340  * priorities to fewer hardware queues (typically all to one
 341  * hardware queue).
 342  */
 343 struct ath_txq {
 344         u32 axq_qnum;                   /* hardware q number */
 345         u32 *axq_link;                  /* link ptr in last TX desc */
 346         struct list_head axq_q;         /* transmit queue */
 347         spinlock_t axq_lock;
 348         unsigned long axq_lockflags;    /* intr state when must cli */
 349         u32 axq_depth;                  /* queue depth */
 350         u8 axq_aggr_depth;              /* aggregates queued */
 351         u32 axq_totalqueued;            /* total ever queued */
 352
 353         bool stopped;                   /* Is mac80211 queue stopped ? */
 354         struct ath_buf *axq_linkbuf;    /* virtual addr of last buffer*/
 355
 356         /* first desc of the last descriptor that contains CTS */
 357         struct ath_desc *axq_lastdsWithCTS;
 358
 359         /* final desc of the gating desc that determines whether
 360            lastdsWithCTS has been DMA'ed or not */
 361         struct ath_desc *axq_gatingds;
 362
 363         struct list_head axq_acq;
 364 };
 365
 366 #define AGGR_CLEANUP         BIT(1)
 367 #define AGGR_ADDBA_COMPLETE  BIT(2)
 368 #define AGGR_ADDBA_PROGRESS  BIT(3)
 369
 370 /* per TID aggregate tx state for a destination */
 371 struct ath_atx_tid {
 372         struct list_head list;          /* round-robin tid entry */
 373         struct list_head buf_q;         /* pending buffers */
 374         struct ath_node *an;
 375         struct ath_atx_ac *ac;
 376         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
 377         u16 seq_start;
 378         u16 seq_next;
 379         u16 baw_size;
 380         int tidno;
 381         int baw_head;                   /* first un-acked tx buffer */
 382         int baw_tail;                   /* next unused tx buffer slot */
 383         int sched;
 384         int paused;
 385         u8 state;
 386         int addba_exchangeattempts;
 387 };
 388
 389 /* per access-category aggregate tx state for a destination */
 390 struct ath_atx_ac {
 391         int sched;                      /* dest-ac is scheduled */
 392         int qnum;                       /* H/W queue number associated
 393                                            with this AC */
 394         struct list_head list;          /* round-robin txq entry */
 395         struct list_head tid_q;         /* queue of TIDs with buffers */
 396 };
 397
 398 /* per dest tx state */
 399 struct ath_atx {
 400         struct ath_atx_tid tid[WME_NUM_TID];
 401         struct ath_atx_ac ac[WME_NUM_AC];
 402 };
 403
 404 /* per-frame tx control block */
 405 struct ath_tx_control {
 406         struct ath_txq *txq;
 407         int if_id;
 408 };
 409
 410 /* per frame tx status block */
 411 struct ath_xmit_status {
 412         int retries;    /* number of retries to successufully
 413                            transmit this frame */
 414         int flags;      /* status of transmit */
 415 #define ATH_TX_ERROR        0x01
 416 #define ATH_TX_XRETRY       0x02
 417 #define ATH_TX_BAR          0x04
 418 };
 419
 420 struct ath_tx_stat {
 421         int rssi;               /* RSSI (noise floor ajusted) */
 422         int rssictl[ATH_MAX_ANTENNA];   /* RSSI (noise floor ajusted) */
 423         int rssiextn[ATH_MAX_ANTENNA];  /* RSSI (noise floor ajusted) */
 424         int rateieee;           /* data rate xmitted (IEEE rate code) */
 425         int rateKbps;           /* data rate xmitted (Kbps) */
 426         int ratecode;           /* phy rate code */
 427         int flags;              /* validity flags */
 428 /* if any of ctl,extn chain rssis are valid */
 429 #define ATH_TX_CHAIN_RSSI_VALID 0x01
 430 /* if extn chain rssis are valid */
 431 #define ATH_TX_RSSI_EXTN_VALID  0x02
 432         u32 airtime;    /* time on air per final tx rate */
 433 };
 434
 435 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 436 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 437 int ath_tx_setup(struct ath_softc *sc, int haltype);
 438 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 439 void ath_tx_draintxq(struct ath_softc *sc,
 440                      struct ath_txq *txq, bool retry_tx);
 441 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 442 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 443 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
 444 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 445 int ath_tx_init(struct ath_softc *sc, int nbufs);
 446 int ath_tx_cleanup(struct ath_softc *sc);
 447 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
 448 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 449 int ath_txq_update(struct ath_softc *sc, int qnum,
 450                    struct ath9k_tx_queue_info *q);
 451 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
 452                  struct ath_tx_control *txctl);
 453 void ath_tx_tasklet(struct ath_softc *sc);
 454 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
 455 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
 456 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
 457 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 458                      struct ath_xmit_status *tx_status);
 459 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
 460
 461 /**********************/
 462 /* Node / Aggregation */
 463 /**********************/
 464
 465 #define ADDBA_EXCHANGE_ATTEMPTS    10
 466 #define ATH_AGGR_DELIM_SZ          4   /* delimiter size   */
 467 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 468 /* number of delimiters for encryption padding */
 469 #define ATH_AGGR_ENCRYPTDELIM      10
 470 /* minimum h/w qdepth to be sustained to maximize aggregation */
 471 #define ATH_AGGR_MIN_QDEPTH        2
 472 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 473 #define IEEE80211_SEQ_SEQ_SHIFT    4
 474 #define IEEE80211_SEQ_MAX          4096
 475 #define IEEE80211_MIN_AMPDU_BUF    0x8
 476 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 477
 478 /* return whether a bit at index _n in bitmap _bm is set
 479  * _sz is the size of the bitmap  */
 480 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 481                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 482
 483 /* return block-ack bitmap index given sequence and starting sequence */
 484 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 485
 486 /* returns delimiter padding required given the packet length */
 487 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 488         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 489           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 490
 491 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 492         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 493
 494 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 495 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
 496 #define ATH_DS_TX_BA(_ds)       ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 497 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 498
 499 enum ATH_AGGR_STATUS {
 500         ATH_AGGR_DONE,
 501         ATH_AGGR_BAW_CLOSED,
 502         ATH_AGGR_LIMITED,
 503         ATH_AGGR_SHORTPKT,
 504         ATH_AGGR_8K_LIMITED,
 505 };
 506
 507 struct aggr_rifs_param {
 508         int param_max_frames;
 509         int param_max_len;
 510         int param_rl;
 511         int param_al;
 512         struct ath_rc_series *param_rcs;
 513 };
 514
 515 /* Per-node aggregation state */
 516 struct ath_node_aggr {
 517         struct ath_atx tx;      /* node transmit state */
 518 };
 519
 520 /* driver-specific node state */
 521 struct ath_node {
 522         struct ath_softc *an_sc;
 523         struct ath_chainmask_sel an_chainmask_sel;
 524         struct ath_node_aggr an_aggr;
 525         u16 maxampdu;
 526         u8 mpdudensity;
 527 };
 528
 529 void ath_tx_resume_tid(struct ath_softc *sc,
 530         struct ath_atx_tid *tid);
 531 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 532 void ath_tx_aggr_teardown(struct ath_softc *sc,
 533         struct ath_node *an, u8 tidno);
 534 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 535                       u16 tid, u16 *ssn);
 536 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 537 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 538 void ath_newassoc(struct ath_softc *sc,
 539         struct ath_node *node, int isnew, int isuapsd);
 540 void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta);
 541 void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
 542
 543 /*******************/
 544 /* Beacon Handling */
 545 /*******************/
 546
 547 /*
 548  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 549  * number of BSSIDs) if a given beacon does not go out even after waiting this
 550  * number of beacon intervals, the game's up.
 551  */
 552 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 553 #define ATH_BCBUF                       4   /* number of beacon buffers */
 554 #define ATH_DEFAULT_BINTVAL             100 /* default beacon interval in TU */
 555 #define ATH_DEFAULT_BMISS_LIMIT         10
 556 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 557
 558 /* beacon configuration */
 559 struct ath_beacon_config {
 560         u16 beacon_interval;
 561         u16 listen_interval;
 562         u16 dtim_period;
 563         u16 bmiss_timeout;
 564         u8 dtim_count;
 565         u8 tim_offset;
 566         union {
 567                 u64 last_tsf;
 568                 u8 last_tstamp[8];
 569         } u; /* last received beacon/probe response timestamp of this BSS. */
 570 };
 571
 572 void ath9k_beacon_tasklet(unsigned long data);
 573 void ath_beacon_config(struct ath_softc *sc, int if_id);
 574 int ath_beaconq_setup(struct ath_hal *ah);
 575 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
 576 void ath_bstuck_process(struct ath_softc *sc);
 577 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
 578 void ath_beacon_sync(struct ath_softc *sc, int if_id);
 579 void ath_get_beaconconfig(struct ath_softc *sc,
 580                           int if_id,
 581                           struct ath_beacon_config *conf);
 582 /********/
 583 /* VAPs */
 584 /********/
 585
 586 /*
 587  * Define the scheme that we select MAC address for multiple
 588  * BSS on the same radio. The very first VAP will just use the MAC
 589  * address from the EEPROM. For the next 3 VAPs, we set the
 590  * U/L bit (bit 1) in MAC address, and use the next two bits as the
 591  * index of the VAP.
 592  */
 593
 594 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
 595         ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
 596
 597 /* driver-specific vap state */
 598 struct ath_vap {
 599         int av_bslot;                   /* beacon slot index */
 600         enum ath9k_opmode av_opmode;    /* VAP operational mode */
 601         struct ath_buf *av_bcbuf;       /* beacon buffer */
 602         struct ath_tx_control av_btxctl;  /* txctl information for beacon */
 603         struct ath_rate_node *rc_node;
 604 };
 605
 606 /*********************/
 607 /* Antenna diversity */
 608 /*********************/
 609
 610 #define ATH_ANT_DIV_MAX_CFG      2
 611 #define ATH_ANT_DIV_MIN_IDLE_US  1000000  /* us */
 612 #define ATH_ANT_DIV_MIN_SCAN_US  50000    /* us */
 613
 614 enum ATH_ANT_DIV_STATE{
 615         ATH_ANT_DIV_IDLE,
 616         ATH_ANT_DIV_SCAN,       /* evaluating antenna */
 617 };
 618
 619 struct ath_antdiv {
 620         struct ath_softc *antdiv_sc;
 621         u8 antdiv_start;
 622         enum ATH_ANT_DIV_STATE antdiv_state;
 623         u8 antdiv_num_antcfg;
 624         u8 antdiv_curcfg;
 625         u8 antdiv_bestcfg;
 626         int32_t antdivf_rssitrig;
 627         int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
 628         u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
 629         u64 antdiv_laststatetsf;
 630         u8 antdiv_bssid[ETH_ALEN];
 631 };
 632
 633 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
 634         struct ath_softc *sc, int32_t rssitrig);
 635 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
 636                             u8 num_antcfg,
 637                             const u8 *bssid);
 638 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
 639 void ath_slow_ant_div(struct ath_antdiv *antdiv,
 640                       struct ieee80211_hdr *wh,
 641                       struct ath_rx_status *rx_stats);
 642 void ath_setdefantenna(void *sc, u32 antenna);
 643
 644 /*******/
 645 /* ANI */
 646 /*******/
 647
 648 /* ANI values for STA only.
 649    FIXME: Add appropriate values for AP later */
 650
 651 #define ATH_ANI_POLLINTERVAL    100     /* 100 milliseconds between ANI poll */
 652 #define ATH_SHORT_CALINTERVAL   1000    /* 1 second between calibrations */
 653 #define ATH_LONG_CALINTERVAL    30000   /* 30 seconds between calibrations */
 654 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
 655
 656 struct ath_ani {
 657         bool sc_caldone;
 658         int16_t sc_noise_floor;
 659         unsigned int sc_longcal_timer;
 660         unsigned int sc_shortcal_timer;
 661         unsigned int sc_resetcal_timer;
 662         unsigned int sc_checkani_timer;
 663         struct timer_list timer;
 664 };
 665
 666 /********************/
 667 /*   LED Control    */
 668 /********************/
 669
 670 #define ATH_LED_PIN     1
 671
 672 enum ath_led_type {
 673         ATH_LED_RADIO,
 674         ATH_LED_ASSOC,
 675         ATH_LED_TX,
 676         ATH_LED_RX
 677 };
 678
 679 struct ath_led {
 680         struct ath_softc *sc;
 681         struct led_classdev led_cdev;
 682         enum ath_led_type led_type;
 683         char name[32];
 684         bool registered;
 685 };
 686
 687 /* Rfkill */
 688 #define ATH_RFKILL_POLL_INTERVAL        2000 /* msecs */
 689
 690 struct ath_rfkill {
 691         struct rfkill *rfkill;
 692         struct delayed_work rfkill_poll;
 693         char rfkill_name[32];
 694 };
 695
 696 /********************/
 697 /* Main driver core */
 698 /********************/
 699
 700 /*
 701  * Default cache line size, in bytes.
 702  * Used when PCI device not fully initialized by bootrom/BIOS
 703 */
 704 #define DEFAULT_CACHELINE       32
 705 #define ATH_DEFAULT_NOISE_FLOOR -95
 706 #define ATH_REGCLASSIDS_MAX     10
 707 #define ATH_CABQ_READY_TIME     80  /* % of beacon interval */
 708 #define ATH_MAX_SW_RETRIES      10
 709 #define ATH_CHAN_MAX            255
 710 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 711 #define IEEE80211_RATE_VAL      0x7f
 712 /*
 713  * The key cache is used for h/w cipher state and also for
 714  * tracking station state such as the current tx antenna.
 715  * We also setup a mapping table between key cache slot indices
 716  * and station state to short-circuit node lookups on rx.
 717  * Different parts have different size key caches.  We handle
 718  * up to ATH_KEYMAX entries (could dynamically allocate state).
 719  */
 720 #define ATH_KEYMAX              128        /* max key cache size we handle */
 721
 722 #define ATH_IF_ID_ANY           0xff
 723 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 724
 725 #define RSSI_LPF_THRESHOLD         -20
 726 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 727 #define ATH_RATE_DUMMY_MARKER      0
 728 #define ATH_RSSI_LPF_LEN           10
 729 #define ATH_RSSI_DUMMY_MARKER      0x127
 730
 731 #define ATH_EP_MUL(x, mul)         ((x) * (mul))
 732 #define ATH_EP_RND(x, mul)                                              \
 733         ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
 734 #define ATH_RSSI_OUT(x)                                                 \
 735         (((x) != ATH_RSSI_DUMMY_MARKER) ?                               \
 736          (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
 737 #define ATH_RSSI_IN(x)                                  \
 738         (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
 739 #define ATH_LPF_RSSI(x, y, len)                                         \
 740         ((x != ATH_RSSI_DUMMY_MARKER) ? \
 741                 (((x) * ((len) - 1) + (y)) / (len)) : (y))
 742 #define ATH_RSSI_LPF(x, y) do {                                         \
 743                 if ((y) >= RSSI_LPF_THRESHOLD)                          \
 744                         x = ATH_LPF_RSSI((x), \
 745                                 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
 746         } while (0)
 747
 748
 749 enum PROT_MODE {
 750         PROT_M_NONE = 0,
 751         PROT_M_RTSCTS,
 752         PROT_M_CTSONLY
 753 };
 754
 755 enum RATE_TYPE {
 756         NORMAL_RATE = 0,
 757         HALF_RATE,
 758         QUARTER_RATE
 759 };
 760
 761 struct ath_ht_info {
 762         enum ath9k_ht_macmode tx_chan_width;
 763         u8 ext_chan_offset;
 764 };
 765
 766 #define SC_OP_INVALID           BIT(0)
 767 #define SC_OP_BEACONS           BIT(1)
 768 #define SC_OP_RXAGGR            BIT(2)
 769 #define SC_OP_TXAGGR            BIT(3)
 770 #define SC_OP_CHAINMASK_UPDATE  BIT(4)
 771 #define SC_OP_FULL_RESET        BIT(5)
 772 #define SC_OP_NO_RESET          BIT(6)
 773 #define SC_OP_PREAMBLE_SHORT    BIT(7)
 774 #define SC_OP_PROTECT_ENABLE    BIT(8)
 775 #define SC_OP_RXFLUSH           BIT(9)
 776 #define SC_OP_LED_ASSOCIATED    BIT(10)
 777 #define SC_OP_RFKILL_REGISTERED BIT(11)
 778 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
 779 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
 780
 781 struct ath_softc {
 782         struct ieee80211_hw *hw;
 783         struct pci_dev *pdev;
 784         struct tasklet_struct intr_tq;
 785         struct tasklet_struct bcon_tasklet;
 786         struct ath_config sc_config;
 787         struct ath_hal *sc_ah;
 788         struct ath_rate_softc *sc_rc;
 789         void __iomem *mem;
 790
 791         u8 sc_curbssid[ETH_ALEN];
 792         u8 sc_myaddr[ETH_ALEN];
 793         u8 sc_bssidmask[ETH_ALEN];
 794
 795         int sc_debug;
 796         u32 sc_intrstatus;
 797         u32 sc_flags; /* SC_OP_* */
 798         unsigned int rx_filter;
 799         u16 sc_curtxpow;
 800         u16 sc_curaid;
 801         u16 sc_cachelsz;
 802         int sc_slotupdate;              /* slot to next advance fsm */
 803         int sc_slottime;
 804         int sc_bslot[ATH_BCBUF];
 805         u8 sc_tx_chainmask;
 806         u8 sc_rx_chainmask;
 807         enum ath9k_int sc_imask;
 808         enum wireless_mode sc_curmode;  /* current phy mode */
 809         enum PROT_MODE sc_protmode;
 810
 811         u8 sc_nbcnvaps;                 /* # of vaps sending beacons */
 812         u16 sc_nvaps;                   /* # of active virtual ap's */
 813         struct ieee80211_vif *sc_vaps[ATH_BCBUF];
 814
 815         u8 sc_mcastantenna;
 816         u8 sc_defant;                   /* current default antenna */
 817         u8 sc_rxotherant;               /* rx's on non-default antenna */
 818
 819         struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
 820         struct ath_ht_info sc_ht_info;
 821         enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
 822
 823 #ifdef CONFIG_SLOW_ANT_DIV
 824         struct ath_antdiv sc_antdiv;
 825 #endif
 826         enum {
 827                 OK,             /* no change needed */
 828                 UPDATE,         /* update pending */
 829                 COMMIT          /* beacon sent, commit change */
 830         } sc_updateslot;        /* slot time update fsm */
 831
 832         /* Crypto */
 833         u32 sc_keymax;          /* size of key cache */
 834         DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);  /* key use bit map */
 835         u8 sc_splitmic;         /* split TKIP MIC keys */
 836
 837         /* RX */
 838         struct list_head sc_rxbuf;
 839         struct ath_descdma sc_rxdma;
 840         int sc_rxbufsize;       /* rx size based on mtu */
 841         u32 *sc_rxlink;         /* link ptr in last RX desc */
 842
 843         /* TX */
 844         struct list_head sc_txbuf;
 845         struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
 846         struct ath_descdma sc_txdma;
 847         u32 sc_txqsetup;
 848         int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
 849         u16 seq_no; /* TX sequence number */
 850
 851         /* Beacon */
 852         struct ath9k_tx_queue_info sc_beacon_qi;
 853         struct ath_descdma sc_bdma;
 854         struct ath_txq *sc_cabq;
 855         struct list_head sc_bbuf;
 856         u32 sc_bhalq;
 857         u32 sc_bmisscount;
 858         u32 ast_be_xmit;        /* beacons transmitted */
 859         u64 bc_tstamp;
 860
 861         /* Rate */
 862         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 863         const struct ath9k_rate_table *sc_currates;
 864         u8 sc_protrix;          /* protection rate index */
 865         struct {
 866                 u32 rateKbps;   /* transfer rate in kbs */
 867                 u8 ieeerate;    /* IEEE rate */
 868         } sc_hwmap[256];        /* h/w rate ix mappings */
 869
 870         /* Channel, Band */
 871         struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
 872         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 873
 874         /* Locks */
 875         spinlock_t sc_rxflushlock;
 876         spinlock_t sc_rxbuflock;
 877         spinlock_t sc_txbuflock;
 878         spinlock_t sc_resetlock;
 879
 880         /* LEDs */
 881         struct ath_led radio_led;
 882         struct ath_led assoc_led;
 883         struct ath_led tx_led;
 884         struct ath_led rx_led;
 885
 886         /* Rfkill */
 887         struct ath_rfkill rf_kill;
 888
 889         /* ANI */
 890         struct ath_ani sc_ani;
 891 };
 892
 893 int ath_init(u16 devid, struct ath_softc *sc);
 894 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
 895 void ath_stop(struct ath_softc *sc);
 896 irqreturn_t ath_isr(int irq, void *dev);
 897 int ath_reset(struct ath_softc *sc, bool retry_tx);
 898 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
 899
 900 /*********************/
 901 /* Utility Functions */
 902 /*********************/
 903
 904 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
 905 int ath_keyset(struct ath_softc *sc,
 906                u16 keyix,
 907                struct ath9k_keyval *hk,
 908                const u8 mac[ETH_ALEN]);
 909 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 910 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 911 void ath_setslottime(struct ath_softc *sc);
 912 void ath_update_txpow(struct ath_softc *sc);
 913 int ath_cabq_update(struct ath_softc *);
 914 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
 915
 916 #endif /* CORE_H */