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staging: brcm80211: removed last amd64 compiler warnings
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
blobcdc57f9c914c340de5305bee12915f78b0e9389b
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/sched.h>
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_func.h>
26 #include <linux/semaphore.h>
27 #include <linux/firmware.h>
28 #include <asm/unaligned.h>
29 #include <defs.h>
30 #include <brcmu_wifi.h>
31 #include <brcmu_utils.h>
32 #include <brcm_hw_ids.h>
33 #include <soc.h>
34 #include "sdio_host.h"
35 #include "bcmsdbus.h"
36
37 /* register access macros */
38 #ifndef __BIG_ENDIAN
39 #ifndef __mips__
40 #define R_REG(r, typ) \
41 brcmf_sdcard_reg_read(NULL, (r), sizeof(typ))
42 #else /* __mips__ */
43 #define R_REG(r, typ) \
44 ({ \
45 __typeof(*(r)) __osl_v; \
46 __asm__ __volatile__("sync"); \
47 __osl_v = brcmf_sdcard_reg_read(NULL, (r),\
48 sizeof(typ)); \
49 __asm__ __volatile__("sync"); \
50 __osl_v; \
51 })
52 #endif /* __mips__ */
53
54 #define W_REG(r, v, typ) do { \
55 brcmf_sdcard_reg_write(NULL, (r), sizeof(typ), (v)); \
56 } while (0)
57 #else /* __BIG_ENDIAN */
58 #define R_REG(r, typ) \
59 brcmf_sdcard_reg_read(NULL, (r), sizeof(typ))
60 #define W_REG(r, v, typ) do { \
61 brcmf_sdcard_reg_write(NULL, (r), sizeof(typ), (v)); \
62 } while (0)
63 #endif /* __BIG_ENDIAN */
64
65 #define AND_REG(r, v, typ) W_REG((r), R_REG(r, typ) & (v), typ)
66 #define OR_REG(r, v, typ) W_REG((r), R_REG(r, typ) | (v), typ)
67
68 #define SET_REG(r, mask, val, typ) \
69 W_REG((r), ((R_REG(r) & ~(mask)) | (val)), typ)
70
71 #ifdef BCMDBG
72
73 /* ARM trap handling */
74
75 /* Trap types defined by ARM (see arminc.h) */
76
77 /* Trap locations in lo memory */
78 #define TRAP_STRIDE 4
79 #define FIRST_TRAP TR_RST
80 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
81
82 #if defined(__ARM_ARCH_4T__)
83 #define MAX_TRAP_TYPE (TR_FIQ + 1)
84 #elif defined(__ARM_ARCH_7M__)
85 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
86 #endif /* __ARM_ARCH_7M__ */
87
88 /* The trap structure is defined here as offsets for assembly */
89 #define TR_TYPE 0x00
90 #define TR_EPC 0x04
91 #define TR_CPSR 0x08
92 #define TR_SPSR 0x0c
93 #define TR_REGS 0x10
94 #define TR_REG(n) (TR_REGS + (n) * 4)
95 #define TR_SP TR_REG(13)
96 #define TR_LR TR_REG(14)
97 #define TR_PC TR_REG(15)
98
99 #define TRAP_T_SIZE 80
100
101 struct brcmf_trap {
102 u32 type;
103 u32 epc;
104 u32 cpsr;
105 u32 spsr;
106 u32 r0;
107 u32 r1;
108 u32 r2;
109 u32 r3;
110 u32 r4;
111 u32 r5;
112 u32 r6;
113 u32 r7;
114 u32 r8;
115 u32 r9;
116 u32 r10;
117 u32 r11;
118 u32 r12;
119 u32 r13;
120 u32 r14;
121 u32 pc;
122 };
123
124 #define CBUF_LEN (128)
125
126 #define LOG_BUF_LEN 1024
127
128 struct rte_log {
129 u32 buf; /* Can't be pointer on (64-bit) hosts */
130 uint buf_size;
131 uint idx;
132 char *_buf_compat; /* Redundant pointer for backward compat. */
133 };
134
135 struct rte_console {
136 /* Virtual UART
137 * When there is no UART (e.g. Quickturn),
138 * the host should write a complete
139 * input line directly into cbuf and then write
140 * the length into vcons_in.
141 * This may also be used when there is a real UART
142 * (at risk of conflicting with
143 * the real UART). vcons_out is currently unused.
144 */
145 volatile uint vcons_in;
146 volatile uint vcons_out;
147
148 /* Output (logging) buffer
149 * Console output is written to a ring buffer log_buf at index log_idx.
150 * The host may read the output when it sees log_idx advance.
151 * Output will be lost if the output wraps around faster than the host
152 * polls.
153 */
154 struct rte_log log;
155
156 /* Console input line buffer
157 * Characters are read one at a time into cbuf
158 * until <CR> is received, then
159 * the buffer is processed as a command line.
160 * Also used for virtual UART.
161 */
162 uint cbuf_idx;
163 char cbuf[CBUF_LEN];
164 };
165
166 #endif /* BCMDBG */
167 #include <chipcommon.h>
168
169 #include "sbsdio.h"
170
171 #include "dngl_stats.h"
172 #include "dhd.h"
173 #include "dhd_bus.h"
174 #include "dhd_proto.h"
175 #include "dhd_dbg.h"
176 #include <bcmchip.h>
177
178 #ifndef DHDSDIO_MEM_DUMP_FNAME
179 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
180 #endif
181
182 #define TXQLEN 2048 /* bulk tx queue length */
183 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
184 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
185 #define PRIOMASK 7
186
187 #define TXRETRIES 2 /* # of retries for tx frames */
188
189 #if defined(CONFIG_MACH_SANDGATE2G)
190 #define DHD_RXBOUND 250 /* Default for max rx frames in
191 one scheduling */
192 #else
193 #define DHD_RXBOUND 50 /* Default for max rx frames in
194 one scheduling */
195 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
196
197 #define DHD_TXBOUND 20 /* Default for max tx frames in
198 one scheduling */
199
200 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
201
202 #define MEMBLOCK 2048 /* Block size used for downloading
203 of dongle image */
204 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
205 biggest possible glom */
206
207 #ifndef BRCMF_FIRSTREAD
208 #define BRCMF_FIRSTREAD 32
209 #endif
210 #if !ISPOWEROF2(BRCMF_FIRSTREAD)
211 #error BRCMF_FIRSTREAD is not a power of 2!
212 #endif
213
214 /* Total length of frame header for dongle protocol */
215 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
216 #ifdef SDTEST
217 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + BRCMF_SDALIGN)
218 #else
219 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
220 #endif
221
222 /*
223 * Software allocation of To SB Mailbox resources
224 */
225
226 /* tosbmailbox bits corresponding to intstatus bits */
227 #define SMB_NAK (1 << 0) /* Frame NAK */
228 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
229 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
230 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
231
232 /* tosbmailboxdata */
233 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
234
235 /*
236 * Software allocation of To Host Mailbox resources
237 */
238
239 /* intstatus bits */
240 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
241 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
242 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
243 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
244
245 /* tohostmailboxdata */
246 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
247 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
248 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
249 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
250
251 #define HMB_DATA_FCDATA_MASK 0xff000000
252 #define HMB_DATA_FCDATA_SHIFT 24
253
254 #define HMB_DATA_VERSION_MASK 0x00ff0000
255 #define HMB_DATA_VERSION_SHIFT 16
256
257 /*
258 * Software-defined protocol header
259 */
260
261 /* Current protocol version */
262 #define SDPCM_PROT_VERSION 4
263
264 /* SW frame header */
265 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
266
267 #define SDPCM_CHANNEL_MASK 0x00000f00
268 #define SDPCM_CHANNEL_SHIFT 8
269 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
270
271 #define SDPCM_NEXTLEN_OFFSET 2
272
273 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
274 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
275 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
276 #define SDPCM_DOFFSET_MASK 0xff000000
277 #define SDPCM_DOFFSET_SHIFT 24
278 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
279 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
280 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
281 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
282
283 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
284
285 /* logical channel numbers */
286 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
287 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
288 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
289 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
290 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
291
292 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
293
294 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
295
296 /* For TEST_CHANNEL packets, define another 4-byte header */
297 #define SDPCM_TEST_HDRLEN 4 /*
298 * Generally: Cmd(1), Ext(1), Len(2);
299 * Semantics of Ext byte depend on
300 * command. Len is current or requested
301 * frame length, not including test
302 * header; sent little-endian.
303 */
304 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
305 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
306 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
307 #define SDPCM_TEST_BURST 0x04 /*
308 * Receiver to send a burst.
309 * Ext is a frame count
310 */
311 #define SDPCM_TEST_SEND 0x05 /*
312 * Receiver sets send mode.
313 * Ext is boolean on/off
314 */
315
316 /* Handy macro for filling in datagen packets with a pattern */
317 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
318
319 /*
320 * Shared structure between dongle and the host.
321 * The structure contains pointers to trap or assert information.
322 */
323 #define SDPCM_SHARED_VERSION 0x0002
324 #define SDPCM_SHARED_VERSION_MASK 0x00FF
325 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
326 #define SDPCM_SHARED_ASSERT 0x0200
327 #define SDPCM_SHARED_TRAP 0x0400
328
329
330 /* Space for header read, limit for data packets */
331 #ifndef MAX_HDR_READ
332 #define MAX_HDR_READ 32
333 #endif
334 #if !ISPOWEROF2(MAX_HDR_READ)
335 #error MAX_HDR_READ is not a power of 2!
336 #endif
337
338 #define MAX_RX_DATASZ 2048
339
340 /* Maximum milliseconds to wait for F2 to come up */
341 #define DHD_WAIT_F2RDY 3000
342
343 /* Bump up limit on waiting for HT to account for first startup;
344 * if the image is doing a CRC calculation before programming the PMU
345 * for HT availability, it could take a couple hundred ms more, so
346 * max out at a 1 second (1000000us).
347 */
348 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
349 #undef PMU_MAX_TRANSITION_DLY
350 #define PMU_MAX_TRANSITION_DLY 1000000
351 #endif
352
353 /* Value for ChipClockCSR during initial setup */
354 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
355 SBSDIO_ALP_AVAIL_REQ)
356 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
357
358 /* Flags for SDH calls */
359 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
360
361 /* sbimstate */
362 #define SBIM_IBE 0x20000 /* inbanderror */
363 #define SBIM_TO 0x40000 /* timeout */
364 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
365 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
366
367 /* sbtmstatelow */
368 #define SBTML_RESET 0x0001 /* reset */
369 #define SBTML_REJ_MASK 0x0006 /* reject field */
370 #define SBTML_REJ 0x0002 /* reject */
371 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
372
373 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
374
375 /* sbtmstatehigh */
376 #define SBTMH_SERR 0x0001 /* serror */
377 #define SBTMH_INT 0x0002 /* interrupt */
378 #define SBTMH_BUSY 0x0004 /* busy */
379 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
380
381 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
382
383 /* sbidlow */
384 #define SBIDL_INIT 0x80 /* initiator */
385
386 /* sbidhigh */
387 #define SBIDH_RC_MASK 0x000f /* revision code */
388 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
389 #define SBIDH_RCE_SHIFT 8
390 #define SBCOREREV(sbidh) \
391 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
392 #define SBIDH_CC_MASK 0x8ff0 /* core code */
393 #define SBIDH_CC_SHIFT 4
394 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
395 #define SBIDH_VC_SHIFT 16
396
397 /*
398 * Conversion of 802.1D priority to precedence level
399 */
400 #define PRIO2PREC(prio) \
401 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
402 ((prio^2)) : (prio))
403
404 BRCMF_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
405
406 /*
407 * Core reg address translation.
408 * Both macro's returns a 32 bits byte address on the backplane bus.
409 */
410 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
411 #define CORE_BUS_REG(base, field) \
412 (base + offsetof(struct sdpcmd_regs, field))
413 #define CORE_SB(base, field) \
414 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
415
416 /* core registers */
417 struct sdpcmd_regs {
418 u32 corecontrol; /* 0x00, rev8 */
419 u32 corestatus; /* rev8 */
420 u32 PAD[1];
421 u32 biststatus; /* rev8 */
422
423 /* PCMCIA access */
424 u16 pcmciamesportaladdr; /* 0x010, rev8 */
425 u16 PAD[1];
426 u16 pcmciamesportalmask; /* rev8 */
427 u16 PAD[1];
428 u16 pcmciawrframebc; /* rev8 */
429 u16 PAD[1];
430 u16 pcmciaunderflowtimer; /* rev8 */
431 u16 PAD[1];
432
433 /* interrupt */
434 u32 intstatus; /* 0x020, rev8 */
435 u32 hostintmask; /* rev8 */
436 u32 intmask; /* rev8 */
437 u32 sbintstatus; /* rev8 */
438 u32 sbintmask; /* rev8 */
439 u32 funcintmask; /* rev4 */
440 u32 PAD[2];
441 u32 tosbmailbox; /* 0x040, rev8 */
442 u32 tohostmailbox; /* rev8 */
443 u32 tosbmailboxdata; /* rev8 */
444 u32 tohostmailboxdata; /* rev8 */
445
446 /* synchronized access to registers in SDIO clock domain */
447 u32 sdioaccess; /* 0x050, rev8 */
448 u32 PAD[3];
449
450 /* PCMCIA frame control */
451 u8 pcmciaframectrl; /* 0x060, rev8 */
452 u8 PAD[3];
453 u8 pcmciawatermark; /* rev8 */
454 u8 PAD[155];
455
456 /* interrupt batching control */
457 u32 intrcvlazy; /* 0x100, rev8 */
458 u32 PAD[3];
459
460 /* counters */
461 u32 cmd52rd; /* 0x110, rev8 */
462 u32 cmd52wr; /* rev8 */
463 u32 cmd53rd; /* rev8 */
464 u32 cmd53wr; /* rev8 */
465 u32 abort; /* rev8 */
466 u32 datacrcerror; /* rev8 */
467 u32 rdoutofsync; /* rev8 */
468 u32 wroutofsync; /* rev8 */
469 u32 writebusy; /* rev8 */
470 u32 readwait; /* rev8 */
471 u32 readterm; /* rev8 */
472 u32 writeterm; /* rev8 */
473 u32 PAD[40];
474 u32 clockctlstatus; /* rev8 */
475 u32 PAD[7];
476
477 u32 PAD[128]; /* DMA engines */
478
479 /* SDIO/PCMCIA CIS region */
480 char cis[512]; /* 0x400-0x5ff, rev6 */
481
482 /* PCMCIA function control registers */
483 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
484 u16 PAD[55];
485
486 /* PCMCIA backplane access */
487 u16 backplanecsr; /* 0x76E, rev6 */
488 u16 backplaneaddr0; /* rev6 */
489 u16 backplaneaddr1; /* rev6 */
490 u16 backplaneaddr2; /* rev6 */
491 u16 backplaneaddr3; /* rev6 */
492 u16 backplanedata0; /* rev6 */
493 u16 backplanedata1; /* rev6 */
494 u16 backplanedata2; /* rev6 */
495 u16 backplanedata3; /* rev6 */
496 u16 PAD[31];
497
498 /* sprom "size" & "blank" info */
499 u16 spromstatus; /* 0x7BE, rev2 */
500 u32 PAD[464];
501
502 u16 PAD[0x80];
503 };
504
505 #ifdef BCMDBG
506 /* Device console log buffer state */
507 struct dhd_console {
508 uint count; /* Poll interval msec counter */
509 uint log_addr; /* Log struct address (fixed) */
510 struct rte_log log; /* Log struct (host copy) */
511 uint bufsize; /* Size of log buffer */
512 u8 *buf; /* Log buffer (host copy) */
513 uint last; /* Last buffer read index */
514 };
515 #endif /* BCMDBG */
516
517 struct sdpcm_shared {
518 u32 flags;
519 u32 trap_addr;
520 u32 assert_exp_addr;
521 u32 assert_file_addr;
522 u32 assert_line;
523 u32 console_addr; /* Address of struct rte_console */
524 u32 msgtrace_addr;
525 u8 tag[32];
526 };
527
528
529 /* misc chip info needed by some of the routines */
530 struct chip_info {
531 u32 chip;
532 u32 chiprev;
533 u32 cccorebase;
534 u32 ccrev;
535 u32 cccaps;
536 u32 buscorebase; /* 32 bits backplane bus address */
537 u32 buscorerev;
538 u32 buscoretype;
539 u32 ramcorebase;
540 u32 armcorebase;
541 u32 pmurev;
542 u32 ramsize;
543 };
544
545 /* Private data for SDIO bus interaction */
546 struct brcmf_bus {
547 struct brcmf_pub *drvr;
548
549 struct brcmf_sdio_card *card; /* Handle for sdio card calls */
550 struct chip_info *ci; /* Chip info struct */
551 char *vars; /* Variables (from CIS and/or other) */
552 uint varsz; /* Size of variables buffer */
553 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
554
555 uint sdpcmrev; /* SDIO core revision */
556 uint armrev; /* CPU core revision */
557 uint ramrev; /* SOCRAM core revision */
558 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
559 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
560
561 u32 bus; /* gSPI or SDIO bus */
562 u32 hostintmask; /* Copy of Host Interrupt Mask */
563 u32 intstatus; /* Intstatus bits (events) pending */
564 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
565 bool fcstate; /* State of dongle flow-control */
566
567 u16 cl_devid; /* cached devid for brcmf_sdio_probe_attach() */
568
569 uint blocksize; /* Block size of SDIO transfers */
570 uint roundup; /* Max roundup limit */
571
572 struct pktq txq; /* Queue length used for flow-control */
573 u8 flowcontrol; /* per prio flow control bitmask */
574 u8 tx_seq; /* Transmit sequence number (next) */
575 u8 tx_max; /* Maximum transmit sequence allowed */
576
577 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
578 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
579 u16 nextlen; /* Next Read Len from last header */
580 u8 rx_seq; /* Receive sequence number (expected) */
581 bool rxskip; /* Skip receive (awaiting NAK ACK) */
582
583 struct sk_buff *glomd; /* Packet containing glomming descriptor */
584 struct sk_buff *glom; /* Packet chain for glommed superframe */
585 uint glomerr; /* Glom packet read errors */
586
587 u8 *rxbuf; /* Buffer for receiving control packets */
588 uint rxblen; /* Allocated length of rxbuf */
589 u8 *rxctl; /* Aligned pointer into rxbuf */
590 u8 *databuf; /* Buffer for receiving big glom packet */
591 u8 *dataptr; /* Aligned pointer into databuf */
592 uint rxlen; /* Length of valid data in buffer */
593
594 u8 sdpcm_ver; /* Bus protocol reported by dongle */
595
596 bool intr; /* Use interrupts */
597 bool poll; /* Use polling */
598 bool ipend; /* Device interrupt is pending */
599 bool intdis; /* Interrupts disabled by isr */
600 uint intrcount; /* Count of device interrupt callbacks */
601 uint lastintrs; /* Count as of last watchdog timer */
602 uint spurious; /* Count of spurious interrupts */
603 uint pollrate; /* Ticks between device polls */
604 uint polltick; /* Tick counter */
605 uint pollcnt; /* Count of active polls */
606
607 #ifdef BCMDBG
608 struct dhd_console console; /* Console output polling support */
609 uint console_addr; /* Console address from shared struct */
610 #endif /* BCMDBG */
611
612 uint regfails; /* Count of R_REG/W_REG failures */
613
614 uint clkstate; /* State of sd and backplane clock(s) */
615 bool activity; /* Activity flag for clock down */
616 s32 idletime; /* Control for activity timeout */
617 s32 idlecount; /* Activity timeout counter */
618 s32 idleclock; /* How to set bus driver when idle */
619 s32 sd_rxchain;
620 bool use_rxchain; /* If dhd should use PKT chains */
621 bool sleeping; /* Is SDIO bus sleeping? */
622 bool rxflow_mode; /* Rx flow control mode */
623 bool rxflow; /* Is rx flow control on */
624 uint prev_rxlim_hit; /* Is prev rx limit exceeded
625 (per dpc schedule) */
626 bool alp_only; /* Don't use HT clock (ALP only) */
627 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
628 bool usebufpool;
629
630 #ifdef SDTEST
631 /* external loopback */
632 bool ext_loop;
633 u8 loopid;
634
635 /* pktgen configuration */
636 uint pktgen_freq; /* Ticks between bursts */
637 uint pktgen_count; /* Packets to send each burst */
638 uint pktgen_print; /* Bursts between count displays */
639 uint pktgen_total; /* Stop after this many */
640 uint pktgen_minlen; /* Minimum packet data len */
641 uint pktgen_maxlen; /* Maximum packet data len */
642 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
643 uint pktgen_stop; /* Number of tx failures causing stop */
644
645 /* active pktgen fields */
646 uint pktgen_tick; /* Tick counter for bursts */
647 uint pktgen_ptick; /* Burst counter for printing */
648 uint pktgen_sent; /* Number of test packets generated */
649 uint pktgen_rcvd; /* Number of test packets received */
650 uint pktgen_fail; /* Number of failed send attempts */
651 u16 pktgen_len; /* Length of next packet to send */
652 #endif /* SDTEST */
653
654 /* Some additional counters */
655 uint tx_sderrs; /* Count of tx attempts with sd errors */
656 uint fcqueued; /* Tx packets that got queued */
657 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
658 uint rx_toolong; /* Receive frames too long to receive */
659 uint rxc_errors; /* SDIO errors when reading control frames */
660 uint rx_hdrfail; /* SDIO errors on header reads */
661 uint rx_badhdr; /* Bad received headers (roosync?) */
662 uint rx_badseq; /* Mismatched rx sequence number */
663 uint fc_rcvd; /* Number of flow-control events received */
664 uint fc_xoff; /* Number which turned on flow-control */
665 uint fc_xon; /* Number which turned off flow-control */
666 uint rxglomfail; /* Failed deglom attempts */
667 uint rxglomframes; /* Number of glom frames (superframes) */
668 uint rxglompkts; /* Number of packets from glom frames */
669 uint f2rxhdrs; /* Number of header reads */
670 uint f2rxdata; /* Number of frame data reads */
671 uint f2txdata; /* Number of f2 frame writes */
672 uint f1regdata; /* Number of f1 register accesses */
673
674 u8 *ctrl_frame_buf;
675 u32 ctrl_frame_len;
676 bool ctrl_frame_stat;
677
678 spinlock_t txqlock;
679 wait_queue_head_t ctrl_wait;
680
681 struct timer_list timer;
682 struct completion watchdog_wait;
683 struct task_struct *watchdog_tsk;
684 bool wd_timer_valid;
685
686 struct tasklet_struct tasklet;
687 struct task_struct *dpc_tsk;
688 struct completion dpc_wait;
689
690 bool threads_only;
691 struct semaphore sdsem;
692 spinlock_t sdlock;
693
694 const char *fw_name;
695 const struct firmware *firmware;
696 const char *nv_name;
697 u32 fw_ptr;
698 };
699
700 struct sbconfig {
701 u32 PAD[2];
702 u32 sbipsflag; /* initiator port ocp slave flag */
703 u32 PAD[3];
704 u32 sbtpsflag; /* target port ocp slave flag */
705 u32 PAD[11];
706 u32 sbtmerrloga; /* (sonics >= 2.3) */
707 u32 PAD;
708 u32 sbtmerrlog; /* (sonics >= 2.3) */
709 u32 PAD[3];
710 u32 sbadmatch3; /* address match3 */
711 u32 PAD;
712 u32 sbadmatch2; /* address match2 */
713 u32 PAD;
714 u32 sbadmatch1; /* address match1 */
715 u32 PAD[7];
716 u32 sbimstate; /* initiator agent state */
717 u32 sbintvec; /* interrupt mask */
718 u32 sbtmstatelow; /* target state */
719 u32 sbtmstatehigh; /* target state */
720 u32 sbbwa0; /* bandwidth allocation table0 */
721 u32 PAD;
722 u32 sbimconfiglow; /* initiator configuration */
723 u32 sbimconfighigh; /* initiator configuration */
724 u32 sbadmatch0; /* address match0 */
725 u32 PAD;
726 u32 sbtmconfiglow; /* target configuration */
727 u32 sbtmconfighigh; /* target configuration */
728 u32 sbbconfig; /* broadcast configuration */
729 u32 PAD;
730 u32 sbbstate; /* broadcast state */
731 u32 PAD[3];
732 u32 sbactcnfg; /* activate configuration */
733 u32 PAD[3];
734 u32 sbflagst; /* current sbflags */
735 u32 PAD[3];
736 u32 sbidlow; /* identification */
737 u32 sbidhigh; /* identification */
738 };
739
740 /* clkstate */
741 #define CLK_NONE 0
742 #define CLK_SDONLY 1
743 #define CLK_PENDING 2 /* Not used yet */
744 #define CLK_AVAIL 3
745
746 #define DHD_NOPMU(dhd) (false)
747
748 #ifdef BCMDBG
749 static int qcount[NUMPRIO];
750 static int tx_packets[NUMPRIO];
751 #endif /* BCMDBG */
752
753 /* Deferred transmit */
754 uint brcmf_deferred_tx = 1;
755 module_param(brcmf_deferred_tx, uint, 0);
756
757 /* Watchdog thread priority, -1 to use kernel timer */
758 int brcmf_watchdog_prio = 97;
759 module_param(brcmf_watchdog_prio, int, 0);
760
761 /* Watchdog interval */
762 uint brcmf_watchdog_ms = 10;
763 module_param(brcmf_watchdog_ms, uint, 0);
764
765 /* DPC thread priority, -1 to use tasklet */
766 int brcmf_dpc_prio = 98;
767 module_param(brcmf_dpc_prio, int, 0);
768
769 #ifdef BCMDBG
770 /* Console poll interval */
771 uint brcmf_console_ms;
772 module_param(brcmf_console_ms, uint, 0);
773 #endif /* DHD_DEBUG */
774
775 /* Tx/Rx bounds */
776 uint brcmf_txbound;
777 uint brcmf_rxbound;
778 uint dhd_txminmax;
779
780 /* override the RAM size if possible */
781 #define DONGLE_MIN_MEMSIZE (128 * 1024)
782 int brcmf_dongle_memsize;
783
784 static bool brcmf_alignctl;
785
786 static bool sd1idle;
787
788 static bool retrydata;
789 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
790
791 static const uint watermark = 8;
792 static const uint firstread = BRCMF_FIRSTREAD;
793
794 #define HDATLEN (firstread - (SDPCM_HDRLEN))
795
796 /* Retry count for register access failures */
797 static const uint retry_limit = 2;
798
799 /* Force even SD lengths (some host controllers mess up on odd bytes) */
800 static bool forcealign;
801
802 #define ALIGNMENT 4
803
804 #define PKTALIGN(_p, _len, _align) \
805 do { \
806 uint datalign; \
807 datalign = (unsigned long)((_p)->data); \
808 datalign = roundup(datalign, (_align)) - datalign; \
809 ASSERT(datalign < (_align)); \
810 ASSERT((_p)->len >= ((_len) + datalign)); \
811 if (datalign) \
812 skb_pull((_p), datalign); \
813 __skb_trim((_p), (_len)); \
814 } while (0)
815
816 /* Limit on rounding up frames */
817 static const uint max_roundup = 512;
818
819 /* Try doing readahead */
820 static bool brcmf_readahead;
821
822 /* To check if there's window offered */
823 #define DATAOK(bus) \
824 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
825 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
826
827 /*
828 * Reads a register in the SDIO hardware block. This block occupies a series of
829 * adresses on the 32 bit backplane bus.
830 */
831 static void
832 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
833 {
834 *retryvar = 0;
835 do {
836 *regvar = R_REG(bus->ci->buscorebase + reg_offset, u32);
837 } while (brcmf_sdcard_regfail(bus->card) &&
838 (++(*retryvar) <= retry_limit));
839 if (*retryvar) {
840 bus->regfails += (*retryvar-1);
841 if (*retryvar > retry_limit) {
842 DHD_ERROR(("FAILED READ %Xh\n", reg_offset));
843 *regvar = 0;
844 }
845 }
846 }
847
848 static void
849 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
850 {
851 *retryvar = 0;
852 do {
853 W_REG(bus->ci->buscorebase + reg_offset, regval, u32);
854 } while (brcmf_sdcard_regfail(bus->card) &&
855 (++(*retryvar) <= retry_limit));
856 if (*retryvar) {
857 bus->regfails += (*retryvar-1);
858 if (*retryvar > retry_limit)
859 DHD_ERROR(("FAILED REGISTER WRITE %Xh\n", reg_offset));
860 }
861 }
862
863 #define DHD_BUS SDIO_BUS
864
865 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
866
867 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
868
869 #ifdef SDTEST
870 static void brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, void *pkt, uint seq);
871 static void brcmf_sdbrcm_sdtest_set(struct brcmf_bus *bus, bool start);
872 #endif
873
874 #ifdef BCMDBG
875 static int brcmf_sdbrcm_bus_console_in(struct brcmf_pub *drvr,
876 unsigned char *msg, uint msglen);
877 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size);
878 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus);
879 #endif /* BCMDBG */
880 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter);
881
882 static void brcmf_sdbrcm_release(struct brcmf_bus *bus);
883 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus);
884 static void brcmf_sdbrcm_disconnect(void *ptr);
885 static bool brcmf_sdbrcm_chipmatch(u16 chipid);
886 static bool brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, void *card,
887 u32 regsva, u16 devid);
888 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus, void *card);
889 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus, void *card);
890 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus);
891
892 static uint brcmf_process_nvram_vars(char *varbuf, uint len);
893
894 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size);
895 static int brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn,
896 uint flags, u8 *buf, uint nbytes,
897 struct sk_buff *pkt,
898 void (*complete)(void *handle, int status,
899 bool sync_waiting),
900 void *handle);
901
902 static bool brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus, void *card);
903 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus);
904
905 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus);
906 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus);
907
908 static void
909 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_card *card, u32 corebase);
910
911 static int brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs);
912
913 static void
914 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_card *card, u32 corebase);
915
916 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
917 u32 drivestrength);
918 static void brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus);
919 static void brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar);
920 static void brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus);
921 static void brcmf_sdbrcm_watchdog(unsigned long data);
922 static int brcmf_sdbrcm_watchdog_thread(void *data);
923 static int brcmf_sdbrcm_dpc_thread(void *data);
924 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data);
925 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus);
926 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus);
927 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus);
928 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus);
929
930 /* Packet free applicable unconditionally for sdio and sdspi.
931 * Conditional if bufpool was present for gspi bus.
932 */
933 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
934 {
935 if ((bus->bus != SPI_BUS) || bus->usebufpool)
936 brcmu_pkt_buf_free_skb(pkt);
937 }
938
939 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size)
940 {
941 s32 min_size = DONGLE_MIN_MEMSIZE;
942 /* Restrict the memsize to user specified limit */
943 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
944 brcmf_dongle_memsize, min_size));
945 if ((brcmf_dongle_memsize > min_size) &&
946 (brcmf_dongle_memsize < (s32) bus->orig_ramsize))
947 bus->ramsize = brcmf_dongle_memsize;
948 }
949
950 static int brcmf_sdbrcm_set_siaddr_window(struct brcmf_bus *bus, u32 address)
951 {
952 int err = 0;
953 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
954 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
955 if (!err)
956 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1,
957 SBSDIO_FUNC1_SBADDRMID,
958 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
959 if (!err)
960 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1,
961 SBSDIO_FUNC1_SBADDRHIGH,
962 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
963 &err);
964 return err;
965 }
966
967 /* Turn backplane clock on or off */
968 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
969 {
970 int err;
971 u8 clkctl, clkreq, devctl;
972 struct brcmf_sdio_card *card;
973
974 DHD_TRACE(("%s: Enter\n", __func__));
975
976 clkctl = 0;
977 card = bus->card;
978
979 if (on) {
980 /* Request HT Avail */
981 clkreq =
982 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
983
984 if ((bus->ci->chip == BCM4329_CHIP_ID)
985 && (bus->ci->chiprev == 0))
986 clkreq |= SBSDIO_FORCE_ALP;
987
988 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
989 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
990 if (err) {
991 DHD_ERROR(("%s: HT Avail request error: %d\n",
992 __func__, err));
993 return -EBADE;
994 }
995
996 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
997 && (bus->ci->buscorerev == 9))) {
998 u32 dummy, retries;
999 r_sdreg32(bus, &dummy,
1000 offsetof(struct sdpcmd_regs, clockctlstatus),
1001 &retries);
1002 }
1003
1004 /* Check current status */
1005 clkctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1006 SBSDIO_FUNC1_CHIPCLKCSR, &err);
1007 if (err) {
1008 DHD_ERROR(("%s: HT Avail read error: %d\n",
1009 __func__, err));
1010 return -EBADE;
1011 }
1012
1013 /* Go to pending and await interrupt if appropriate */
1014 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
1015 /* Allow only clock-available interrupt */
1016 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1017 SBSDIO_DEVICE_CTL, &err);
1018 if (err) {
1019 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
1020 __func__, err));
1021 return -EBADE;
1022 }
1023
1024 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
1025 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1026 SBSDIO_DEVICE_CTL, devctl, &err);
1027 DHD_INFO(("CLKCTL: set PENDING\n"));
1028 bus->clkstate = CLK_PENDING;
1029
1030 return 0;
1031 } else if (bus->clkstate == CLK_PENDING) {
1032 /* Cancel CA-only interrupt filter */
1033 devctl =
1034 brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1035 SBSDIO_DEVICE_CTL, &err);
1036 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1037 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1038 SBSDIO_DEVICE_CTL, devctl, &err);
1039 }
1040
1041 /* Otherwise, wait here (polling) for HT Avail */
1042 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1043 BRCMF_SPINWAIT_SLEEP(sdioh_spinwait_sleep,
1044 ((clkctl =
1045 brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1046 SBSDIO_FUNC1_CHIPCLKCSR,
1047 &err)),
1048 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
1049 PMU_MAX_TRANSITION_DLY);
1050 }
1051 if (err) {
1052 DHD_ERROR(("%s: HT Avail request error: %d\n",
1053 __func__, err));
1054 return -EBADE;
1055 }
1056 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1057 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
1058 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
1059 return -EBADE;
1060 }
1061
1062 /* Mark clock available */
1063 bus->clkstate = CLK_AVAIL;
1064 DHD_INFO(("CLKCTL: turned ON\n"));
1065
1066 #if defined(BCMDBG)
1067 if (bus->alp_only != true) {
1068 if (SBSDIO_ALPONLY(clkctl)) {
1069 DHD_ERROR(("%s: HT Clock should be on.\n",
1070 __func__));
1071 }
1072 }
1073 #endif /* defined (BCMDBG) */
1074
1075 bus->activity = true;
1076 } else {
1077 clkreq = 0;
1078
1079 if (bus->clkstate == CLK_PENDING) {
1080 /* Cancel CA-only interrupt filter */
1081 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1082 SBSDIO_DEVICE_CTL, &err);
1083 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1084 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1085 SBSDIO_DEVICE_CTL, devctl, &err);
1086 }
1087
1088 bus->clkstate = CLK_SDONLY;
1089 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1090 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
1091 DHD_INFO(("CLKCTL: turned OFF\n"));
1092 if (err) {
1093 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
1094 __func__, err));
1095 return -EBADE;
1096 }
1097 }
1098 return 0;
1099 }
1100
1101 /* Change idle/active SD state */
1102 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
1103 {
1104 DHD_TRACE(("%s: Enter\n", __func__));
1105
1106 if (on)
1107 bus->clkstate = CLK_SDONLY;
1108 else
1109 bus->clkstate = CLK_NONE;
1110
1111 return 0;
1112 }
1113
1114 /* Transition SD and backplane clock readiness */
1115 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
1116 {
1117 #ifdef BCMDBG
1118 uint oldstate = bus->clkstate;
1119 #endif /* BCMDBG */
1120
1121 DHD_TRACE(("%s: Enter\n", __func__));
1122
1123 /* Early exit if we're already there */
1124 if (bus->clkstate == target) {
1125 if (target == CLK_AVAIL) {
1126 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1127 bus->activity = true;
1128 }
1129 return 0;
1130 }
1131
1132 switch (target) {
1133 case CLK_AVAIL:
1134 /* Make sure SD clock is available */
1135 if (bus->clkstate == CLK_NONE)
1136 brcmf_sdbrcm_sdclk(bus, true);
1137 /* Now request HT Avail on the backplane */
1138 brcmf_sdbrcm_htclk(bus, true, pendok);
1139 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1140 bus->activity = true;
1141 break;
1142
1143 case CLK_SDONLY:
1144 /* Remove HT request, or bring up SD clock */
1145 if (bus->clkstate == CLK_NONE)
1146 brcmf_sdbrcm_sdclk(bus, true);
1147 else if (bus->clkstate == CLK_AVAIL)
1148 brcmf_sdbrcm_htclk(bus, false, false);
1149 else
1150 DHD_ERROR(("brcmf_sdbrcm_clkctl: request for %d -> %d"
1151 "\n", bus->clkstate, target));
1152 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1153 break;
1154
1155 case CLK_NONE:
1156 /* Make sure to remove HT request */
1157 if (bus->clkstate == CLK_AVAIL)
1158 brcmf_sdbrcm_htclk(bus, false, false);
1159 /* Now remove the SD clock */
1160 brcmf_sdbrcm_sdclk(bus, false);
1161 brcmf_sdbrcm_wd_timer(bus, 0);
1162 break;
1163 }
1164 #ifdef BCMDBG
1165 DHD_INFO(("brcmf_sdbrcm_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1166 #endif /* BCMDBG */
1167
1168 return 0;
1169 }
1170
1171 int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1172 {
1173 struct brcmf_sdio_card *card = bus->card;
1174 uint retries = 0;
1175
1176 DHD_INFO(("brcmf_sdbrcm_bussleep: request %s (currently %s)\n",
1177 (sleep ? "SLEEP" : "WAKE"),
1178 (bus->sleeping ? "SLEEP" : "WAKE")));
1179
1180 /* Done if we're already in the requested state */
1181 if (sleep == bus->sleeping)
1182 return 0;
1183
1184 /* Going to sleep: set the alarm and turn off the lights... */
1185 if (sleep) {
1186 /* Don't sleep if something is pending */
1187 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1188 return -EBUSY;
1189
1190 /* Disable SDIO interrupts (no longer interested) */
1191 brcmf_sdcard_intr_disable(bus->card);
1192
1193 /* Make sure the controller has the bus up */
1194 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1195
1196 /* Tell device to start using OOB wakeup */
1197 w_sdreg32(bus, SMB_USE_OOB,
1198 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1199 if (retries > retry_limit)
1200 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1201
1202 /* Turn off our contribution to the HT clock request */
1203 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1204
1205 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1206 SBSDIO_FUNC1_CHIPCLKCSR,
1207 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1208
1209 /* Isolate the bus */
1210 if (bus->ci->chip != BCM4329_CHIP_ID
1211 && bus->ci->chip != BCM4319_CHIP_ID) {
1212 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1213 SBSDIO_DEVICE_CTL,
1214 SBSDIO_DEVCTL_PADS_ISO, NULL);
1215 }
1216
1217 /* Change state */
1218 bus->sleeping = true;
1219
1220 } else {
1221 /* Waking up: bus power up is ok, set local state */
1222
1223 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1224 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1225
1226 /* Force pad isolation off if possible
1227 (in case power never toggled) */
1228 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1229 && (bus->ci->buscorerev >= 10))
1230 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1231 SBSDIO_DEVICE_CTL, 0, NULL);
1232
1233 /* Make sure the controller has the bus up */
1234 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1235
1236 /* Send misc interrupt to indicate OOB not needed */
1237 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1238 &retries);
1239 if (retries <= retry_limit)
1240 w_sdreg32(bus, SMB_DEV_INT,
1241 offsetof(struct sdpcmd_regs, tosbmailbox),
1242 &retries);
1243
1244 if (retries > retry_limit)
1245 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1246
1247 /* Make sure we have SD bus access */
1248 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1249
1250 /* Change state */
1251 bus->sleeping = false;
1252
1253 /* Enable interrupts again */
1254 if (bus->intr && (bus->drvr->busstate == DHD_BUS_DATA)) {
1255 bus->intdis = false;
1256 brcmf_sdcard_intr_enable(bus->card);
1257 }
1258 }
1259
1260 return 0;
1261 }
1262
1263 #define BUS_WAKE(bus) \
1264 do { \
1265 if ((bus)->sleeping) \
1266 brcmf_sdbrcm_bussleep((bus), false); \
1267 } while (0);
1268
1269 /* Writes a HW/SW header into the packet and sends it. */
1270 /* Assumes: (a) header space already there, (b) caller holds lock */
1271 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt, uint chan,
1272 bool free_pkt)
1273 {
1274 int ret;
1275 u8 *frame;
1276 u16 len, pad = 0;
1277 u32 swheader;
1278 uint retries = 0;
1279 struct brcmf_sdio_card *card;
1280 struct sk_buff *new;
1281 int i;
1282
1283 DHD_TRACE(("%s: Enter\n", __func__));
1284
1285 card = bus->card;
1286
1287 if (bus->drvr->dongle_reset) {
1288 ret = -EPERM;
1289 goto done;
1290 }
1291
1292 frame = (u8 *) (pkt->data);
1293
1294 /* Add alignment padding, allocate new packet if needed */
1295 pad = ((unsigned long)frame % BRCMF_SDALIGN);
1296 if (pad) {
1297 if (skb_headroom(pkt) < pad) {
1298 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1299 __func__, skb_headroom(pkt), pad));
1300 bus->drvr->tx_realloc++;
1301 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
1302 if (!new) {
1303 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1304 "packet\n",
1305 __func__, pkt->len + BRCMF_SDALIGN));
1306 ret = -ENOMEM;
1307 goto done;
1308 }
1309
1310 PKTALIGN(new, pkt->len, BRCMF_SDALIGN);
1311 memcpy(new->data, pkt->data, pkt->len);
1312 if (free_pkt)
1313 brcmu_pkt_buf_free_skb(pkt);
1314 /* free the pkt if canned one is not used */
1315 free_pkt = true;
1316 pkt = new;
1317 frame = (u8 *) (pkt->data);
1318 ASSERT(((unsigned long)frame % BRCMF_SDALIGN) == 0);
1319 pad = 0;
1320 } else {
1321 skb_push(pkt, pad);
1322 frame = (u8 *) (pkt->data);
1323
1324 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1325 memset(frame, 0, pad + SDPCM_HDRLEN);
1326 }
1327 }
1328 ASSERT(pad < BRCMF_SDALIGN);
1329
1330 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1331 len = (u16) (pkt->len);
1332 *(u16 *) frame = cpu_to_le16(len);
1333 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1334
1335 /* Software tag: channel, sequence number, data offset */
1336 swheader =
1337 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1338 (((pad +
1339 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1340
1341 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1342 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1343
1344 #ifdef BCMDBG
1345 tx_packets[pkt->priority]++;
1346 if (DHD_BYTES_ON() &&
1347 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1348 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1349 printk(KERN_DEBUG "Tx Frame:\n");
1350 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1351 } else if (DHD_HDRS_ON()) {
1352 printk(KERN_DEBUG "TxHdr:\n");
1353 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1354 frame, min_t(u16, len, 16));
1355 }
1356 #endif
1357
1358 /* Raise len to next SDIO block to eliminate tail command */
1359 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1360 u16 pad = bus->blocksize - (len % bus->blocksize);
1361 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1362 len += pad;
1363 } else if (len % BRCMF_SDALIGN) {
1364 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1365 }
1366
1367 /* Some controllers have trouble with odd bytes -- round to even */
1368 if (forcealign && (len & (ALIGNMENT - 1))) {
1369 len = roundup(len, ALIGNMENT);
1370 }
1371
1372 do {
1373 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(card),
1374 SDIO_FUNC_2, F2SYNC, frame, len, pkt, NULL, NULL);
1375 bus->f2txdata++;
1376 ASSERT(ret != -BCME_PENDING);
1377
1378 if (ret < 0) {
1379 /* On failure, abort the command
1380 and terminate the frame */
1381 DHD_INFO(("%s: sdio error %d, abort command and "
1382 "terminate frame.\n", __func__, ret));
1383 bus->tx_sderrs++;
1384
1385 brcmf_sdcard_abort(card, SDIO_FUNC_2);
1386 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1387 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1388 NULL);
1389 bus->f1regdata++;
1390
1391 for (i = 0; i < 3; i++) {
1392 u8 hi, lo;
1393 hi = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1394 SBSDIO_FUNC1_WFRAMEBCHI,
1395 NULL);
1396 lo = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
1397 SBSDIO_FUNC1_WFRAMEBCLO,
1398 NULL);
1399 bus->f1regdata += 2;
1400 if ((hi == 0) && (lo == 0))
1401 break;
1402 }
1403
1404 }
1405 if (ret == 0)
1406 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1407
1408 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1409
1410 done:
1411 /* restore pkt buffer pointer before calling tx complete routine */
1412 skb_pull(pkt, SDPCM_HDRLEN + pad);
1413 brcmf_sdbrcm_sdunlock(bus);
1414 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
1415 brcmf_sdbrcm_sdlock(bus);
1416
1417 if (free_pkt)
1418 brcmu_pkt_buf_free_skb(pkt);
1419
1420 return ret;
1421 }
1422
1423 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
1424 {
1425 int ret = -EBADE;
1426 uint datalen, prec;
1427
1428 DHD_TRACE(("%s: Enter\n", __func__));
1429
1430 datalen = pkt->len;
1431
1432 #ifdef SDTEST
1433 /* Push the test header if doing loopback */
1434 if (bus->ext_loop) {
1435 u8 *data;
1436 skb_push(pkt, SDPCM_TEST_HDRLEN);
1437 data = pkt->data;
1438 *data++ = SDPCM_TEST_ECHOREQ;
1439 *data++ = (u8) bus->loopid++;
1440 *data++ = (datalen >> 0);
1441 *data++ = (datalen >> 8);
1442 datalen += SDPCM_TEST_HDRLEN;
1443 }
1444 #endif /* SDTEST */
1445
1446 /* Add space for the header */
1447 skb_push(pkt, SDPCM_HDRLEN);
1448 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1449
1450 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1451
1452 /* Check for existing queue, current flow-control,
1453 pending event, or pending clock */
1454 if (brcmf_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1455 || bus->dpc_sched || (!DATAOK(bus))
1456 || (bus->flowcontrol & NBITVAL(prec))
1457 || (bus->clkstate != CLK_AVAIL)) {
1458 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1459 pktq_len(&bus->txq)));
1460 bus->fcqueued++;
1461
1462 /* Priority based enq */
1463 spin_lock_bh(&bus->txqlock);
1464 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
1465 skb_pull(pkt, SDPCM_HDRLEN);
1466 brcmf_txcomplete(bus->drvr, pkt, false);
1467 brcmu_pkt_buf_free_skb(pkt);
1468 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1469 ret = -ENOSR;
1470 } else {
1471 ret = 0;
1472 }
1473 spin_unlock_bh(&bus->txqlock);
1474
1475 if (pktq_len(&bus->txq) >= TXHI)
1476 brcmf_txflowcontrol(bus->drvr, 0, ON);
1477
1478 #ifdef BCMDBG
1479 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1480 qcount[prec] = pktq_plen(&bus->txq, prec);
1481 #endif
1482 /* Schedule DPC if needed to send queued packet(s) */
1483 if (brcmf_deferred_tx && !bus->dpc_sched) {
1484 bus->dpc_sched = true;
1485 brcmf_sdbrcm_sched_dpc(bus);
1486 }
1487 } else {
1488 /* Lock: we're about to use shared data/code (and SDIO) */
1489 brcmf_sdbrcm_sdlock(bus);
1490
1491 /* Otherwise, send it now */
1492 BUS_WAKE(bus);
1493 /* Make sure back plane ht clk is on, no pending allowed */
1494 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
1495
1496 #ifndef SDTEST
1497 DHD_TRACE(("%s: calling txpkt\n", __func__));
1498 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1499 #else
1500 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1501 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1502 SDPCM_DATA_CHANNEL), true);
1503 #endif
1504 if (ret)
1505 bus->drvr->tx_errors++;
1506 else
1507 bus->drvr->dstats.tx_bytes += datalen;
1508
1509 if (bus->idletime == BRCMF_IDLE_IMMEDIATE &&
1510 !bus->dpc_sched) {
1511 bus->activity = false;
1512 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1513 }
1514
1515 brcmf_sdbrcm_sdunlock(bus);
1516 }
1517
1518 return ret;
1519 }
1520
1521 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
1522 {
1523 struct sk_buff *pkt;
1524 u32 intstatus = 0;
1525 uint retries = 0;
1526 int ret = 0, prec_out;
1527 uint cnt = 0;
1528 uint datalen;
1529 u8 tx_prec_map;
1530
1531 struct brcmf_pub *drvr = bus->drvr;
1532
1533 DHD_TRACE(("%s: Enter\n", __func__));
1534
1535 tx_prec_map = ~bus->flowcontrol;
1536
1537 /* Send frames until the limit or some other event */
1538 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1539 spin_lock_bh(&bus->txqlock);
1540 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1541 if (pkt == NULL) {
1542 spin_unlock_bh(&bus->txqlock);
1543 break;
1544 }
1545 spin_unlock_bh(&bus->txqlock);
1546 datalen = pkt->len - SDPCM_HDRLEN;
1547
1548 #ifndef SDTEST
1549 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1550 #else
1551 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1552 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1553 SDPCM_DATA_CHANNEL), true);
1554 #endif
1555 if (ret)
1556 bus->drvr->tx_errors++;
1557 else
1558 bus->drvr->dstats.tx_bytes += datalen;
1559
1560 /* In poll mode, need to check for other events */
1561 if (!bus->intr && cnt) {
1562 /* Check device status, signal pending interrupt */
1563 r_sdreg32(bus, &intstatus,
1564 offsetof(struct sdpcmd_regs, intstatus),
1565 &retries);
1566 bus->f2txdata++;
1567 if (brcmf_sdcard_regfail(bus->card))
1568 break;
1569 if (intstatus & bus->hostintmask)
1570 bus->ipend = true;
1571 }
1572 }
1573
1574 /* Deflow-control stack if needed */
1575 if (drvr->up && (drvr->busstate == DHD_BUS_DATA) &&
1576 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
1577 brcmf_txflowcontrol(drvr, 0, OFF);
1578
1579 return cnt;
1580 }
1581
1582 int
1583 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1584 {
1585 u8 *frame;
1586 u16 len;
1587 u32 swheader;
1588 uint retries = 0;
1589 struct brcmf_sdio_card *card = bus->card;
1590 u8 doff = 0;
1591 int ret = -1;
1592 int i;
1593
1594 DHD_TRACE(("%s: Enter\n", __func__));
1595
1596 if (bus->drvr->dongle_reset)
1597 return -EIO;
1598
1599 /* Back the pointer to make a room for bus header */
1600 frame = msg - SDPCM_HDRLEN;
1601 len = (msglen += SDPCM_HDRLEN);
1602
1603 /* Add alignment padding (optional for ctl frames) */
1604 if (brcmf_alignctl) {
1605 doff = ((unsigned long)frame % BRCMF_SDALIGN);
1606 if (doff) {
1607 frame -= doff;
1608 len += doff;
1609 msglen += doff;
1610 memset(frame, 0, doff + SDPCM_HDRLEN);
1611 }
1612 ASSERT(doff < BRCMF_SDALIGN);
1613 }
1614 doff += SDPCM_HDRLEN;
1615
1616 /* Round send length to next SDIO block */
1617 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1618 u16 pad = bus->blocksize - (len % bus->blocksize);
1619 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1620 len += pad;
1621 } else if (len % BRCMF_SDALIGN) {
1622 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1623 }
1624
1625 /* Satisfy length-alignment requirements */
1626 if (forcealign && (len & (ALIGNMENT - 1)))
1627 len = roundup(len, ALIGNMENT);
1628
1629 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1630
1631 /* Need to lock here to protect txseq and SDIO tx calls */
1632 brcmf_sdbrcm_sdlock(bus);
1633
1634 BUS_WAKE(bus);
1635
1636 /* Make sure backplane clock is on */
1637 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1638
1639 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1640 *(u16 *) frame = cpu_to_le16((u16) msglen);
1641 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1642
1643 /* Software tag: channel, sequence number, data offset */
1644 swheader =
1645 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1646 SDPCM_CHANNEL_MASK)
1647 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1648 SDPCM_DOFFSET_MASK);
1649 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1650 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1651
1652 if (!DATAOK(bus)) {
1653 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1654 __func__, bus->tx_max, bus->tx_seq));
1655 bus->ctrl_frame_stat = true;
1656 /* Send from dpc */
1657 bus->ctrl_frame_buf = frame;
1658 bus->ctrl_frame_len = len;
1659
1660 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
1661
1662 if (bus->ctrl_frame_stat == false) {
1663 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1664 ret = 0;
1665 } else {
1666 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1667 ret = -1;
1668 }
1669 }
1670
1671 if (ret == -1) {
1672 #ifdef BCMDBG
1673 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1674 printk(KERN_DEBUG "Tx Frame:\n");
1675 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1676 frame, len);
1677 } else if (DHD_HDRS_ON()) {
1678 printk(KERN_DEBUG "TxHdr:\n");
1679 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1680 frame, min_t(u16, len, 16));
1681 }
1682 #endif
1683
1684 do {
1685 bus->ctrl_frame_stat = false;
1686 ret = brcmf_sdbrcm_send_buf(bus,
1687 brcmf_sdcard_cur_sbwad(card), SDIO_FUNC_2,
1688 F2SYNC, frame, len, NULL, NULL, NULL);
1689
1690 ASSERT(ret != -BCME_PENDING);
1691
1692 if (ret < 0) {
1693 /* On failure, abort the command and
1694 terminate the frame */
1695 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1696 __func__, ret));
1697 bus->tx_sderrs++;
1698
1699 brcmf_sdcard_abort(card, SDIO_FUNC_2);
1700
1701 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
1702 SBSDIO_FUNC1_FRAMECTRL,
1703 SFC_WF_TERM, NULL);
1704 bus->f1regdata++;
1705
1706 for (i = 0; i < 3; i++) {
1707 u8 hi, lo;
1708 hi = brcmf_sdcard_cfg_read(card,
1709 SDIO_FUNC_1,
1710 SBSDIO_FUNC1_WFRAMEBCHI,
1711 NULL);
1712 lo = brcmf_sdcard_cfg_read(card,
1713 SDIO_FUNC_1,
1714 SBSDIO_FUNC1_WFRAMEBCLO,
1715 NULL);
1716 bus->f1regdata += 2;
1717 if ((hi == 0) && (lo == 0))
1718 break;
1719 }
1720
1721 }
1722 if (ret == 0) {
1723 bus->tx_seq =
1724 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1725 }
1726 } while ((ret < 0) && retries++ < TXRETRIES);
1727 }
1728
1729 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1730 bus->activity = false;
1731 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1732 }
1733
1734 brcmf_sdbrcm_sdunlock(bus);
1735
1736 if (ret)
1737 bus->drvr->tx_ctlerrs++;
1738 else
1739 bus->drvr->tx_ctlpkts++;
1740
1741 return ret ? -EIO : 0;
1742 }
1743
1744 int brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1745 {
1746 int timeleft;
1747 uint rxlen = 0;
1748 bool pending;
1749
1750 DHD_TRACE(("%s: Enter\n", __func__));
1751
1752 if (bus->drvr->dongle_reset)
1753 return -EIO;
1754
1755 /* Wait until control frame is available */
1756 timeleft = brcmf_os_ioctl_resp_wait(bus->drvr, &bus->rxlen, &pending);
1757
1758 brcmf_sdbrcm_sdlock(bus);
1759 rxlen = bus->rxlen;
1760 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1761 bus->rxlen = 0;
1762 brcmf_sdbrcm_sdunlock(bus);
1763
1764 if (rxlen) {
1765 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1766 __func__, rxlen, msglen));
1767 } else if (timeleft == 0) {
1768 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1769 #ifdef BCMDBG
1770 brcmf_sdbrcm_sdlock(bus);
1771 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1772 brcmf_sdbrcm_sdunlock(bus);
1773 #endif /* DHD_DEBUG */
1774 } else if (pending == true) {
1775 DHD_CTL(("%s: cancelled\n", __func__));
1776 return -ERESTARTSYS;
1777 } else {
1778 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1779 #ifdef BCMDBG
1780 brcmf_sdbrcm_sdlock(bus);
1781 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1782 brcmf_sdbrcm_sdunlock(bus);
1783 #endif /* DHD_DEBUG */
1784 }
1785
1786 if (rxlen)
1787 bus->drvr->rx_ctlpkts++;
1788 else
1789 bus->drvr->rx_ctlerrs++;
1790
1791 return rxlen ? (int)rxlen : -ETIMEDOUT;
1792 }
1793
1794 /* IOVar table */
1795 enum {
1796 IOV_INTR = 1,
1797 IOV_POLLRATE,
1798 IOV_SDREG,
1799 IOV_SBREG,
1800 IOV_SDCIS,
1801 IOV_MEMBYTES,
1802 IOV_MEMSIZE,
1803 #ifdef BCMDBG
1804 IOV_CHECKDIED,
1805 IOV_CONS,
1806 IOV_DCONSOLE_POLL,
1807 #endif
1808 IOV_DOWNLOAD,
1809 IOV_FORCEEVEN,
1810 IOV_SDIOD_DRIVE,
1811 IOV_READAHEAD,
1812 IOV_SDRXCHAIN,
1813 IOV_ALIGNCTL,
1814 IOV_SDALIGN,
1815 IOV_DEVRESET,
1816 IOV_CPU,
1817 #ifdef SDTEST
1818 IOV_PKTGEN,
1819 IOV_EXTLOOP,
1820 #endif /* SDTEST */
1821 IOV_SPROM,
1822 IOV_TXBOUND,
1823 IOV_RXBOUND,
1824 IOV_TXMINMAX,
1825 IOV_IDLETIME,
1826 IOV_IDLECLOCK,
1827 IOV_SD1IDLE,
1828 IOV_SLEEP,
1829 IOV_WDTICK,
1830 IOV_VARS
1831 };
1832
1833 const struct brcmu_iovar dhdsdio_iovars[] = {
1834 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1835 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1836 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1837 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1838 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1839 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1840 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1841 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1842 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1843 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1844 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1845 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1846 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1847 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1848 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1849 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1850 {"wdtick", IOV_WDTICK, 0, IOVT_UINT32, 0},
1851 #ifdef BCMDBG
1852 {"cons", IOV_CONS, 0, IOVT_BUFFER, 0}
1853 ,
1854 {"dconpoll", IOV_DCONSOLE_POLL, 0, IOVT_UINT32, 0}
1855 ,
1856 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(struct brcmf_sdreg)}
1857 ,
1858 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(struct brcmf_sdreg)}
1859 ,
1860 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, BRCMF_IOCTL_MAXLEN}
1861 ,
1862 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1863 ,
1864 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1865 ,
1866 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1867 ,
1868 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1869 ,
1870 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1871 ,
1872 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1873 ,
1874 #endif /* BCMDBG */
1875 #ifdef SDTEST
1876 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1877 ,
1878 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(struct brcmf_pktgen)}
1879 ,
1880 #endif /* SDTEST */
1881
1882 {NULL, 0, 0, 0, 0}
1883 };
1884
1885 static void
1886 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1887 {
1888 uint q1, q2;
1889
1890 if (!div) {
1891 brcmu_bprintf(strbuf, "%s N/A", desc);
1892 } else {
1893 q1 = num / div;
1894 q2 = (100 * (num - (q1 * div))) / div;
1895 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1896 }
1897 }
1898
1899 void brcmf_sdbrcm_bus_dump(struct brcmf_pub *drvr, struct brcmu_strbuf *strbuf)
1900 {
1901 struct brcmf_bus *bus = drvr->bus;
1902
1903 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1904 brcmu_bprintf(strbuf,
1905 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1906 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1907 brcmu_bprintf(strbuf,
1908 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1909 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1910 bus->rxskip, bus->rxlen, bus->rx_seq);
1911 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1912 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1913 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1914 bus->pollrate, bus->pollcnt, bus->regfails);
1915
1916 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1917 brcmu_bprintf(strbuf,
1918 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1919 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1920 bus->rxc_errors);
1921 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1922 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1923 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1924 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1925 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1926 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1927 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1928 " %d\n",
1929 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1930 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1931 {
1932 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->drvr->rx_packets,
1933 (bus->f2rxhdrs + bus->f2rxdata));
1934 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->drvr->rx_packets,
1935 bus->f1regdata);
1936 dhd_dump_pct(strbuf, ", pkts/sd", bus->drvr->rx_packets,
1937 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1938 dhd_dump_pct(strbuf, ", pkts/int", bus->drvr->rx_packets,
1939 bus->intrcount);
1940 brcmu_bprintf(strbuf, "\n");
1941
1942 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1943 bus->drvr->rx_packets);
1944 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1945 bus->rxglomframes);
1946 brcmu_bprintf(strbuf, "\n");
1947
1948 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->drvr->tx_packets,
1949 bus->f2txdata);
1950 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->drvr->tx_packets,
1951 bus->f1regdata);
1952 dhd_dump_pct(strbuf, ", pkts/sd", bus->drvr->tx_packets,
1953 (bus->f2txdata + bus->f1regdata));
1954 dhd_dump_pct(strbuf, ", pkts/int", bus->drvr->tx_packets,
1955 bus->intrcount);
1956 brcmu_bprintf(strbuf, "\n");
1957
1958 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1959 (bus->drvr->tx_packets + bus->drvr->rx_packets),
1960 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1961 dhd_dump_pct(strbuf, ", pkts/f1sd",
1962 (bus->drvr->tx_packets + bus->drvr->rx_packets),
1963 bus->f1regdata);
1964 dhd_dump_pct(strbuf, ", pkts/sd",
1965 (bus->drvr->tx_packets + bus->drvr->rx_packets),
1966 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1967 bus->f1regdata));
1968 dhd_dump_pct(strbuf, ", pkts/int",
1969 (bus->drvr->tx_packets + bus->drvr->rx_packets),
1970 bus->intrcount);
1971 brcmu_bprintf(strbuf, "\n\n");
1972 }
1973
1974 #ifdef SDTEST
1975 if (bus->pktgen_count) {
1976 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1977 brcmu_bprintf(strbuf,
1978 "freq %d count %d print %d total %d min %d len %d\n",
1979 bus->pktgen_freq, bus->pktgen_count,
1980 bus->pktgen_print, bus->pktgen_total,
1981 bus->pktgen_minlen, bus->pktgen_maxlen);
1982 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1983 bus->pktgen_sent, bus->pktgen_rcvd,
1984 bus->pktgen_fail);
1985 }
1986 #endif /* SDTEST */
1987 #ifdef BCMDBG
1988 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1989 bus->dpc_sched, " not ");
1990 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1991 bus->roundup);
1992 #endif /* BCMDBG */
1993 brcmu_bprintf(strbuf,
1994 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1995 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1996 bus->sleeping);
1997 }
1998
1999 void brcmf_bus_clearcounts(struct brcmf_pub *drvr)
2000 {
2001 struct brcmf_bus *bus = (struct brcmf_bus *) drvr->bus;
2002
2003 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
2004 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
2005 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
2006 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
2007 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
2008 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
2009 }
2010
2011 #ifdef SDTEST
2012 static int brcmf_sdbrcm_pktgen_get(struct brcmf_bus *bus, u8 *arg)
2013 {
2014 struct brcmf_pktgen pktgen;
2015
2016 pktgen.version = BRCMF_PKTGEN_VERSION;
2017 pktgen.freq = bus->pktgen_freq;
2018 pktgen.count = bus->pktgen_count;
2019 pktgen.print = bus->pktgen_print;
2020 pktgen.total = bus->pktgen_total;
2021 pktgen.minlen = bus->pktgen_minlen;
2022 pktgen.maxlen = bus->pktgen_maxlen;
2023 pktgen.numsent = bus->pktgen_sent;
2024 pktgen.numrcvd = bus->pktgen_rcvd;
2025 pktgen.numfail = bus->pktgen_fail;
2026 pktgen.mode = bus->pktgen_mode;
2027 pktgen.stop = bus->pktgen_stop;
2028
2029 memcpy(arg, &pktgen, sizeof(pktgen));
2030
2031 return 0;
2032 }
2033
2034 static int brcmf_sdbrcm_pktgen_set(struct brcmf_bus *bus, u8 *arg)
2035 {
2036 struct brcmf_pktgen pktgen;
2037 uint oldcnt, oldmode;
2038
2039 memcpy(&pktgen, arg, sizeof(pktgen));
2040 if (pktgen.version != BRCMF_PKTGEN_VERSION)
2041 return -EINVAL;
2042
2043 oldcnt = bus->pktgen_count;
2044 oldmode = bus->pktgen_mode;
2045
2046 bus->pktgen_freq = pktgen.freq;
2047 bus->pktgen_count = pktgen.count;
2048 bus->pktgen_print = pktgen.print;
2049 bus->pktgen_total = pktgen.total;
2050 bus->pktgen_minlen = pktgen.minlen;
2051 bus->pktgen_maxlen = pktgen.maxlen;
2052 bus->pktgen_mode = pktgen.mode;
2053 bus->pktgen_stop = pktgen.stop;
2054
2055 bus->pktgen_tick = bus->pktgen_ptick = 0;
2056 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
2057 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
2058
2059 /* Clear counts for a new pktgen (mode change, or was stopped) */
2060 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
2061 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
2062
2063 return 0;
2064 }
2065 #endif /* SDTEST */
2066
2067 static int
2068 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2069 uint size)
2070 {
2071 int bcmerror = 0;
2072 u32 sdaddr;
2073 uint dsize;
2074
2075 /* Determine initial transfer parameters */
2076 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2077 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2078 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2079 else
2080 dsize = size;
2081
2082 /* Set the backplane window to include the start address */
2083 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
2084 if (bcmerror) {
2085 DHD_ERROR(("%s: window change failed\n", __func__));
2086 goto xfer_done;
2087 }
2088
2089 /* Do the transfer(s) */
2090 while (size) {
2091 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
2092 __func__, (write ? "write" : "read"), dsize,
2093 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
2094 bcmerror =
2095 brcmf_sdcard_rwdata(bus->card, write, sdaddr, data, dsize);
2096 if (bcmerror) {
2097 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2098 break;
2099 }
2100
2101 /* Adjust for next transfer (if any) */
2102 size -= dsize;
2103 if (size) {
2104 data += dsize;
2105 address += dsize;
2106 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
2107 if (bcmerror) {
2108 DHD_ERROR(("%s: window change failed\n",
2109 __func__));
2110 break;
2111 }
2112 sdaddr = 0;
2113 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2114 }
2115 }
2116
2117 xfer_done:
2118 /* Return the window to backplane enumeration space for core access */
2119 if (brcmf_sdbrcm_set_siaddr_window(bus,
2120 brcmf_sdcard_cur_sbwad(bus->card))) {
2121 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2122 __func__, brcmf_sdcard_cur_sbwad(bus->card)));
2123 }
2124
2125 return bcmerror;
2126 }
2127
2128 #ifdef BCMDBG
2129 static int brcmf_sdbrcm_readshared(struct brcmf_bus *bus, struct sdpcm_shared *sh)
2130 {
2131 u32 addr;
2132 int rv;
2133
2134 /* Read last word in memory to determine address of
2135 sdpcm_shared structure */
2136 rv = brcmf_sdbrcm_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr,
2137 4);
2138 if (rv < 0)
2139 return rv;
2140
2141 addr = le32_to_cpu(addr);
2142
2143 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2144
2145 /*
2146 * Check if addr is valid.
2147 * NVRAM length at the end of memory should have been overwritten.
2148 */
2149 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2150 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2151 __func__, addr));
2152 return -EBADE;
2153 }
2154
2155 /* Read rte_shared structure */
2156 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *) sh,
2157 sizeof(struct sdpcm_shared));
2158 if (rv < 0)
2159 return rv;
2160
2161 /* Endianness */
2162 sh->flags = le32_to_cpu(sh->flags);
2163 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2164 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2165 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2166 sh->assert_line = le32_to_cpu(sh->assert_line);
2167 sh->console_addr = le32_to_cpu(sh->console_addr);
2168 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2169
2170 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2171 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2172 "is different than sdpcm_shared version %d in dongle\n",
2173 __func__, SDPCM_SHARED_VERSION,
2174 sh->flags & SDPCM_SHARED_VERSION_MASK));
2175 return -EBADE;
2176 }
2177
2178 return 0;
2179 }
2180
2181 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size)
2182 {
2183 int bcmerror = 0;
2184 uint msize = 512;
2185 char *mbuffer = NULL;
2186 uint maxstrlen = 256;
2187 char *str = NULL;
2188 struct brcmf_trap tr;
2189 struct sdpcm_shared sdpcm_shared;
2190 struct brcmu_strbuf strbuf;
2191
2192 DHD_TRACE(("%s: Enter\n", __func__));
2193
2194 if (data == NULL) {
2195 /*
2196 * Called after a rx ctrl timeout. "data" is NULL.
2197 * allocate memory to trace the trap or assert.
2198 */
2199 size = msize;
2200 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2201 if (mbuffer == NULL) {
2202 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2203 msize));
2204 bcmerror = -ENOMEM;
2205 goto done;
2206 }
2207 }
2208
2209 str = kmalloc(maxstrlen, GFP_ATOMIC);
2210 if (str == NULL) {
2211 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2212 bcmerror = -ENOMEM;
2213 goto done;
2214 }
2215
2216 bcmerror = brcmf_sdbrcm_readshared(bus, &sdpcm_shared);
2217 if (bcmerror < 0)
2218 goto done;
2219
2220 brcmu_binit(&strbuf, data, size);
2221
2222 brcmu_bprintf(&strbuf,
2223 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2224 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2225
2226 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2227 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2228 * (Avoids conflict with real asserts for programmatic
2229 * parsing of output.)
2230 */
2231 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2232 }
2233
2234 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2235 0) {
2236 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2237 * (Avoids conflict with real asserts for programmatic
2238 * parsing of output.)
2239 */
2240 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2241 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2242 ? "/assrt" : "");
2243 } else {
2244 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2245 /* Download assert */
2246 brcmu_bprintf(&strbuf, "Dongle assert");
2247 if (sdpcm_shared.assert_exp_addr != 0) {
2248 str[0] = '\0';
2249 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2250 sdpcm_shared.assert_exp_addr,
2251 (u8 *) str, maxstrlen);
2252 if (bcmerror < 0)
2253 goto done;
2254
2255 str[maxstrlen - 1] = '\0';
2256 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2257 }
2258
2259 if (sdpcm_shared.assert_file_addr != 0) {
2260 str[0] = '\0';
2261 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2262 sdpcm_shared.assert_file_addr,
2263 (u8 *) str, maxstrlen);
2264 if (bcmerror < 0)
2265 goto done;
2266
2267 str[maxstrlen - 1] = '\0';
2268 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2269 }
2270
2271 brcmu_bprintf(&strbuf, " line %d ",
2272 sdpcm_shared.assert_line);
2273 }
2274
2275 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2276 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2277 sdpcm_shared.trap_addr, (u8 *)&tr,
2278 sizeof(struct brcmf_trap));
2279 if (bcmerror < 0)
2280 goto done;
2281
2282 brcmu_bprintf(&strbuf,
2283 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2284 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2285 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2286 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2287 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2288 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2289 tr.r6, tr.r7);
2290 }
2291 }
2292
2293 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2294 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2295
2296 #ifdef BCMDBG
2297 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2298 /* Mem dump to a file on device */
2299 brcmf_sdbrcm_mem_dump(bus);
2300 }
2301 #endif /* BCMDBG */
2302
2303 done:
2304 kfree(mbuffer);
2305 kfree(str);
2306
2307 return bcmerror;
2308 }
2309
2310 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus)
2311 {
2312 int ret = 0;
2313 int size; /* Full mem size */
2314 int start = 0; /* Start address */
2315 int read_size = 0; /* Read size of each iteration */
2316 u8 *buf = NULL, *databuf = NULL;
2317
2318 /* Get full mem size */
2319 size = bus->ramsize;
2320 buf = kmalloc(size, GFP_ATOMIC);
2321 if (!buf) {
2322 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2323 return -1;
2324 }
2325
2326 /* Read mem content */
2327 printk(KERN_DEBUG "Dump dongle memory");
2328 databuf = buf;
2329 while (size) {
2330 read_size = min(MEMBLOCK, size);
2331 ret = brcmf_sdbrcm_membytes(bus, false, start, databuf,
2332 read_size);
2333 if (ret) {
2334 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2335 kfree(buf);
2336 return -1;
2337 }
2338 printk(".");
2339
2340 /* Decrement size and increment start address */
2341 size -= read_size;
2342 start += read_size;
2343 databuf += read_size;
2344 }
2345 printk(KERN_DEBUG "Done\n");
2346
2347 /* free buf before return !!! */
2348 if (brcmf_write_to_file(bus->drvr, buf, bus->ramsize)) {
2349 DHD_ERROR(("%s: Error writing to files\n", __func__));
2350 return -1;
2351 }
2352
2353 /* buf free handled in brcmf_write_to_file, not here */
2354 return 0;
2355 }
2356
2357 #define CONSOLE_LINE_MAX 192
2358
2359 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2360 {
2361 struct dhd_console *c = &bus->console;
2362 u8 line[CONSOLE_LINE_MAX], ch;
2363 u32 n, idx, addr;
2364 int rv;
2365
2366 /* Don't do anything until FWREADY updates console address */
2367 if (bus->console_addr == 0)
2368 return 0;
2369
2370 /* Read console log struct */
2371 addr = bus->console_addr + offsetof(struct rte_console, log);
2372 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log,
2373 sizeof(c->log));
2374 if (rv < 0)
2375 return rv;
2376
2377 /* Allocate console buffer (one time only) */
2378 if (c->buf == NULL) {
2379 c->bufsize = le32_to_cpu(c->log.buf_size);
2380 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2381 if (c->buf == NULL)
2382 return -ENOMEM;
2383 }
2384
2385 idx = le32_to_cpu(c->log.idx);
2386
2387 /* Protect against corrupt value */
2388 if (idx > c->bufsize)
2389 return -EBADE;
2390
2391 /* Skip reading the console buffer if the index pointer
2392 has not moved */
2393 if (idx == c->last)
2394 return 0;
2395
2396 /* Read the console buffer */
2397 addr = le32_to_cpu(c->log.buf);
2398 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2399 if (rv < 0)
2400 return rv;
2401
2402 while (c->last != idx) {
2403 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2404 if (c->last == idx) {
2405 /* This would output a partial line.
2406 * Instead, back up
2407 * the buffer pointer and output this
2408 * line next time around.
2409 */
2410 if (c->last >= n)
2411 c->last -= n;
2412 else
2413 c->last = c->bufsize - n;
2414 goto break2;
2415 }
2416 ch = c->buf[c->last];
2417 c->last = (c->last + 1) % c->bufsize;
2418 if (ch == '\n')
2419 break;
2420 line[n] = ch;
2421 }
2422
2423 if (n > 0) {
2424 if (line[n - 1] == '\r')
2425 n--;
2426 line[n] = 0;
2427 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2428 }
2429 }
2430 break2:
2431
2432 return 0;
2433 }
2434 #endif /* BCMDBG */
2435
2436 int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
2437 {
2438 int bcmerror = 0;
2439
2440 DHD_TRACE(("%s: Enter\n", __func__));
2441
2442 /* Basic sanity checks */
2443 if (bus->drvr->up) {
2444 bcmerror = -EISCONN;
2445 goto err;
2446 }
2447 if (!len) {
2448 bcmerror = -EOVERFLOW;
2449 goto err;
2450 }
2451
2452 /* Free the old ones and replace with passed variables */
2453 kfree(bus->vars);
2454
2455 bus->vars = kmalloc(len, GFP_ATOMIC);
2456 bus->varsz = bus->vars ? len : 0;
2457 if (bus->vars == NULL) {
2458 bcmerror = -ENOMEM;
2459 goto err;
2460 }
2461
2462 /* Copy the passed variables, which should include the
2463 terminating double-null */
2464 memcpy(bus->vars, arg, bus->varsz);
2465 err:
2466 return bcmerror;
2467 }
2468
2469 static int
2470 brcmf_sdbrcm_doiovar(struct brcmf_bus *bus, const struct brcmu_iovar *vi, u32 actionid,
2471 const char *name, void *params, int plen, void *arg, int len,
2472 int val_size)
2473 {
2474 int bcmerror = 0;
2475 s32 int_val = 0;
2476 bool bool_val = 0;
2477
2478 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2479 "len %d val_size %d\n",
2480 __func__, actionid, name, params, plen, arg, len, val_size));
2481
2482 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2483 if (bcmerror != 0)
2484 goto exit;
2485
2486 if (plen >= (int)sizeof(int_val))
2487 memcpy(&int_val, params, sizeof(int_val));
2488
2489 bool_val = (int_val != 0) ? true : false;
2490
2491 /* Some ioctls use the bus */
2492 brcmf_sdbrcm_sdlock(bus);
2493
2494 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2495 if (bus->drvr->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2496 actionid == IOV_GVAL(IOV_DEVRESET))) {
2497 bcmerror = -EPERM;
2498 goto exit;
2499 }
2500
2501 /* Handle sleep stuff before any clock mucking */
2502 if (vi->varid == IOV_SLEEP) {
2503 if (IOV_ISSET(actionid)) {
2504 bcmerror = brcmf_sdbrcm_bussleep(bus, bool_val);
2505 } else {
2506 int_val = (s32) bus->sleeping;
2507 memcpy(arg, &int_val, val_size);
2508 }
2509 goto exit;
2510 }
2511
2512 /* Request clock to allow SDIO accesses */
2513 if (!bus->drvr->dongle_reset) {
2514 BUS_WAKE(bus);
2515 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2516 }
2517
2518 switch (actionid) {
2519 case IOV_GVAL(IOV_INTR):
2520 int_val = (s32) bus->intr;
2521 memcpy(arg, &int_val, val_size);
2522 break;
2523
2524 case IOV_SVAL(IOV_INTR):
2525 bus->intr = bool_val;
2526 bus->intdis = false;
2527 if (bus->drvr->up) {
2528 if (bus->intr) {
2529 DHD_INTR(("%s: enable SDIO device interrupts\n",
2530 __func__));
2531 brcmf_sdcard_intr_enable(bus->card);
2532 } else {
2533 DHD_INTR(("%s: disable SDIO interrupts\n",
2534 __func__));
2535 brcmf_sdcard_intr_disable(bus->card);
2536 }
2537 }
2538 break;
2539
2540 case IOV_GVAL(IOV_POLLRATE):
2541 int_val = (s32) bus->pollrate;
2542 memcpy(arg, &int_val, val_size);
2543 break;
2544
2545 case IOV_SVAL(IOV_POLLRATE):
2546 bus->pollrate = (uint) int_val;
2547 bus->poll = (bus->pollrate != 0);
2548 break;
2549
2550 case IOV_GVAL(IOV_IDLETIME):
2551 int_val = bus->idletime;
2552 memcpy(arg, &int_val, val_size);
2553 break;
2554
2555 case IOV_SVAL(IOV_IDLETIME):
2556 if ((int_val < 0) && (int_val != BRCMF_IDLE_IMMEDIATE))
2557 bcmerror = -EINVAL;
2558 else
2559 bus->idletime = int_val;
2560 break;
2561
2562 case IOV_GVAL(IOV_IDLECLOCK):
2563 int_val = (s32) bus->idleclock;
2564 memcpy(arg, &int_val, val_size);
2565 break;
2566
2567 case IOV_SVAL(IOV_IDLECLOCK):
2568 bus->idleclock = int_val;
2569 break;
2570
2571 case IOV_GVAL(IOV_SD1IDLE):
2572 int_val = (s32) sd1idle;
2573 memcpy(arg, &int_val, val_size);
2574 break;
2575
2576 case IOV_SVAL(IOV_SD1IDLE):
2577 sd1idle = bool_val;
2578 break;
2579
2580 case IOV_SVAL(IOV_MEMBYTES):
2581 case IOV_GVAL(IOV_MEMBYTES):
2582 {
2583 u32 address;
2584 uint size, dsize;
2585 u8 *data;
2586
2587 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2588
2589 ASSERT(plen >= 2 * sizeof(int));
2590
2591 address = (u32) int_val;
2592 memcpy(&int_val, (char *)params + sizeof(int_val),
2593 sizeof(int_val));
2594 size = (uint) int_val;
2595
2596 /* Do some validation */
2597 dsize = set ? plen - (2 * sizeof(int)) : len;
2598 if (dsize < size) {
2599 DHD_ERROR(("%s: error on %s membytes, addr "
2600 "0x%08x size %d dsize %d\n",
2601 __func__, (set ? "set" : "get"),
2602 address, size, dsize));
2603 bcmerror = -EINVAL;
2604 break;
2605 }
2606
2607 DHD_INFO(("%s: Request to %s %d bytes at address "
2608 "0x%08x\n",
2609 __func__, (set ? "write" : "read"), size, address));
2610
2611 /* If we know about SOCRAM, check for a fit */
2612 if ((bus->orig_ramsize) &&
2613 ((address > bus->orig_ramsize)
2614 || (address + size > bus->orig_ramsize))) {
2615 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2616 "bytes at 0x%08x\n",
2617 __func__, bus->orig_ramsize, size, address));
2618 bcmerror = -EINVAL;
2619 break;
2620 }
2621
2622 /* Generate the actual data pointer */
2623 data =
2624 set ? (u8 *) params +
2625 2 * sizeof(int) : (u8 *) arg;
2626
2627 /* Call to do the transfer */
2628 bcmerror = brcmf_sdbrcm_membytes(bus, set, address,
2629 data, size);
2630
2631 break;
2632 }
2633
2634 case IOV_GVAL(IOV_MEMSIZE):
2635 int_val = (s32) bus->ramsize;
2636 memcpy(arg, &int_val, val_size);
2637 break;
2638
2639 case IOV_GVAL(IOV_SDIOD_DRIVE):
2640 int_val = (s32) brcmf_sdiod_drive_strength;
2641 memcpy(arg, &int_val, val_size);
2642 break;
2643
2644 case IOV_SVAL(IOV_SDIOD_DRIVE):
2645 brcmf_sdiod_drive_strength = int_val;
2646 brcmf_sdbrcm_sdiod_drive_strength_init(bus,
2647 brcmf_sdiod_drive_strength);
2648 break;
2649
2650 case IOV_SVAL(IOV_DOWNLOAD):
2651 bcmerror = brcmf_sdbrcm_download_state(bus, bool_val);
2652 break;
2653
2654 case IOV_SVAL(IOV_VARS):
2655 bcmerror = brcmf_sdbrcm_downloadvars(bus, arg, len);
2656 break;
2657
2658 case IOV_GVAL(IOV_READAHEAD):
2659 int_val = (s32) brcmf_readahead;
2660 memcpy(arg, &int_val, val_size);
2661 break;
2662
2663 case IOV_SVAL(IOV_READAHEAD):
2664 if (bool_val && !brcmf_readahead)
2665 bus->nextlen = 0;
2666 brcmf_readahead = bool_val;
2667 break;
2668
2669 case IOV_GVAL(IOV_SDRXCHAIN):
2670 int_val = (s32) bus->use_rxchain;
2671 memcpy(arg, &int_val, val_size);
2672 break;
2673
2674 case IOV_SVAL(IOV_SDRXCHAIN):
2675 if (bool_val && !bus->sd_rxchain)
2676 bcmerror = -ENOTSUPP;
2677 else
2678 bus->use_rxchain = bool_val;
2679 break;
2680 case IOV_GVAL(IOV_ALIGNCTL):
2681 int_val = (s32) brcmf_alignctl;
2682 memcpy(arg, &int_val, val_size);
2683 break;
2684
2685 case IOV_SVAL(IOV_ALIGNCTL):
2686 brcmf_alignctl = bool_val;
2687 break;
2688
2689 case IOV_GVAL(IOV_SDALIGN):
2690 int_val = BRCMF_SDALIGN;
2691 memcpy(arg, &int_val, val_size);
2692 break;
2693
2694 #ifdef BCMDBG
2695 case IOV_GVAL(IOV_VARS):
2696 if (bus->varsz < (uint) len)
2697 memcpy(arg, bus->vars, bus->varsz);
2698 else
2699 bcmerror = -EOVERFLOW;
2700 break;
2701 #endif /* BCMDBG */
2702
2703 #ifdef BCMDBG
2704 case IOV_GVAL(IOV_DCONSOLE_POLL):
2705 int_val = (s32) brcmf_console_ms;
2706 memcpy(arg, &int_val, val_size);
2707 break;
2708
2709 case IOV_SVAL(IOV_DCONSOLE_POLL):
2710 brcmf_console_ms = (uint) int_val;
2711 break;
2712
2713 case IOV_SVAL(IOV_CONS):
2714 if (len > 0)
2715 bcmerror = brcmf_sdbrcm_bus_console_in(bus->drvr,
2716 arg, len - 1);
2717 break;
2718
2719 case IOV_GVAL(IOV_SDREG):
2720 {
2721 struct brcmf_sdreg *sd_ptr;
2722 u32 addr, size;
2723
2724 sd_ptr = (struct brcmf_sdreg *) params;
2725
2726 addr = bus->ci->buscorebase + sd_ptr->offset;
2727 size = sd_ptr->func;
2728 int_val = (s32) brcmf_sdcard_reg_read(bus->card, addr,
2729 size);
2730 if (brcmf_sdcard_regfail(bus->card))
2731 bcmerror = -EIO;
2732 memcpy(arg, &int_val, sizeof(s32));
2733 break;
2734 }
2735
2736 case IOV_SVAL(IOV_SDREG):
2737 {
2738 struct brcmf_sdreg *sd_ptr;
2739 u32 addr, size;
2740
2741 sd_ptr = (struct brcmf_sdreg *) params;
2742
2743 addr = bus->ci->buscorebase + sd_ptr->offset;
2744 size = sd_ptr->func;
2745 brcmf_sdcard_reg_write(bus->card, addr, size,
2746 sd_ptr->value);
2747 if (brcmf_sdcard_regfail(bus->card))
2748 bcmerror = -EIO;
2749 break;
2750 }
2751
2752 /* Same as above, but offset is not backplane
2753 (not SDIO core) */
2754 case IOV_GVAL(IOV_SBREG):
2755 {
2756 struct brcmf_sdreg sdreg;
2757 u32 addr, size;
2758
2759 memcpy(&sdreg, params, sizeof(sdreg));
2760
2761 addr = SI_ENUM_BASE + sdreg.offset;
2762 size = sdreg.func;
2763 int_val = (s32) brcmf_sdcard_reg_read(bus->card, addr,
2764 size);
2765 if (brcmf_sdcard_regfail(bus->card))
2766 bcmerror = -EIO;
2767 memcpy(arg, &int_val, sizeof(s32));
2768 break;
2769 }
2770
2771 case IOV_SVAL(IOV_SBREG):
2772 {
2773 struct brcmf_sdreg sdreg;
2774 u32 addr, size;
2775
2776 memcpy(&sdreg, params, sizeof(sdreg));
2777
2778 addr = SI_ENUM_BASE + sdreg.offset;
2779 size = sdreg.func;
2780 brcmf_sdcard_reg_write(bus->card, addr, size,
2781 sdreg.value);
2782 if (brcmf_sdcard_regfail(bus->card))
2783 bcmerror = -EIO;
2784 break;
2785 }
2786
2787 case IOV_GVAL(IOV_SDCIS):
2788 {
2789 *(char *)arg = 0;
2790
2791 strcat(arg, "\nFunc 0\n");
2792 brcmf_sdcard_cis_read(bus->card, 0x10,
2793 (u8 *) arg + strlen(arg),
2794 SBSDIO_CIS_SIZE_LIMIT);
2795 strcat(arg, "\nFunc 1\n");
2796 brcmf_sdcard_cis_read(bus->card, 0x11,
2797 (u8 *) arg + strlen(arg),
2798 SBSDIO_CIS_SIZE_LIMIT);
2799 strcat(arg, "\nFunc 2\n");
2800 brcmf_sdcard_cis_read(bus->card, 0x12,
2801 (u8 *) arg + strlen(arg),
2802 SBSDIO_CIS_SIZE_LIMIT);
2803 break;
2804 }
2805
2806 case IOV_GVAL(IOV_FORCEEVEN):
2807 int_val = (s32) forcealign;
2808 memcpy(arg, &int_val, val_size);
2809 break;
2810
2811 case IOV_SVAL(IOV_FORCEEVEN):
2812 forcealign = bool_val;
2813 break;
2814
2815 case IOV_GVAL(IOV_TXBOUND):
2816 int_val = (s32) brcmf_txbound;
2817 memcpy(arg, &int_val, val_size);
2818 break;
2819
2820 case IOV_SVAL(IOV_TXBOUND):
2821 brcmf_txbound = (uint) int_val;
2822 break;
2823
2824 case IOV_GVAL(IOV_RXBOUND):
2825 int_val = (s32) brcmf_rxbound;
2826 memcpy(arg, &int_val, val_size);
2827 break;
2828
2829 case IOV_SVAL(IOV_RXBOUND):
2830 brcmf_rxbound = (uint) int_val;
2831 break;
2832
2833 case IOV_GVAL(IOV_TXMINMAX):
2834 int_val = (s32) dhd_txminmax;
2835 memcpy(arg, &int_val, val_size);
2836 break;
2837
2838 case IOV_SVAL(IOV_TXMINMAX):
2839 dhd_txminmax = (uint) int_val;
2840 break;
2841 #endif /* BCMDBG */
2842
2843 #ifdef SDTEST
2844 case IOV_GVAL(IOV_EXTLOOP):
2845 int_val = (s32) bus->ext_loop;
2846 memcpy(arg, &int_val, val_size);
2847 break;
2848
2849 case IOV_SVAL(IOV_EXTLOOP):
2850 bus->ext_loop = bool_val;
2851 break;
2852
2853 case IOV_GVAL(IOV_PKTGEN):
2854 bcmerror = brcmf_sdbrcm_pktgen_get(bus, arg);
2855 break;
2856
2857 case IOV_SVAL(IOV_PKTGEN):
2858 bcmerror = brcmf_sdbrcm_pktgen_set(bus, arg);
2859 break;
2860 #endif /* SDTEST */
2861
2862 case IOV_SVAL(IOV_DEVRESET):
2863 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2864 "busstate=%d\n",
2865 __func__, bool_val, bus->drvr->dongle_reset,
2866 bus->drvr->busstate));
2867
2868 brcmf_bus_devreset(bus->drvr, (u8) bool_val);
2869
2870 break;
2871
2872 case IOV_GVAL(IOV_DEVRESET):
2873 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2874
2875 /* Get its status */
2876 int_val = (bool) bus->drvr->dongle_reset;
2877 memcpy(arg, &int_val, val_size);
2878
2879 break;
2880
2881 case IOV_GVAL(IOV_WDTICK):
2882 int_val = (s32) brcmf_watchdog_ms;
2883 memcpy(arg, &int_val, val_size);
2884 break;
2885
2886 case IOV_SVAL(IOV_WDTICK):
2887 if (!bus->drvr->up) {
2888 bcmerror = -ENOLINK;
2889 break;
2890 }
2891 brcmf_sdbrcm_wd_timer(bus, (uint) int_val);
2892 break;
2893
2894 default:
2895 bcmerror = -ENOTSUPP;
2896 break;
2897 }
2898
2899 exit:
2900 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2901 bus->activity = false;
2902 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2903 }
2904
2905 brcmf_sdbrcm_sdunlock(bus);
2906
2907 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2908 brcmf_c_preinit_ioctls(bus->drvr);
2909
2910 return bcmerror;
2911 }
2912
2913 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
2914 {
2915 int bcmerror = 0;
2916 u32 varsize;
2917 u32 varaddr;
2918 u8 *vbuffer;
2919 u32 varsizew;
2920 #ifdef BCMDBG
2921 char *nvram_ularray;
2922 #endif /* BCMDBG */
2923
2924 /* Even if there are no vars are to be written, we still
2925 need to set the ramsize. */
2926 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2927 varaddr = (bus->ramsize - 4) - varsize;
2928
2929 if (bus->vars) {
2930 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2931 if (!vbuffer)
2932 return -ENOMEM;
2933
2934 memcpy(vbuffer, bus->vars, bus->varsz);
2935
2936 /* Write the vars list */
2937 bcmerror =
2938 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
2939 #ifdef BCMDBG
2940 /* Verify NVRAM bytes */
2941 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2942 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2943 if (!nvram_ularray)
2944 return -ENOMEM;
2945
2946 /* Upload image to verify downloaded contents. */
2947 memset(nvram_ularray, 0xaa, varsize);
2948
2949 /* Read the vars list to temp buffer for comparison */
2950 bcmerror =
2951 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
2952 varsize);
2953 if (bcmerror) {
2954 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2955 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2956 }
2957 /* Compare the org NVRAM with the one read from RAM */
2958 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2959 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2960 __func__));
2961 } else
2962 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2963 __func__));
2964
2965 kfree(nvram_ularray);
2966 #endif /* BCMDBG */
2967
2968 kfree(vbuffer);
2969 }
2970
2971 /* adjust to the user specified RAM */
2972 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2973 bus->orig_ramsize, bus->ramsize));
2974 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2975 varsize = ((bus->orig_ramsize - 4) - varaddr);
2976
2977 /*
2978 * Determine the length token:
2979 * Varsize, converted to words, in lower 16-bits, checksum
2980 * in upper 16-bits.
2981 */
2982 if (bcmerror) {
2983 varsizew = 0;
2984 } else {
2985 varsizew = varsize / 4;
2986 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2987 varsizew = cpu_to_le32(varsizew);
2988 }
2989
2990 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2991 varsizew));
2992
2993 /* Write the length token to the last word */
2994 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->orig_ramsize - 4),
2995 (u8 *)&varsizew, 4);
2996
2997 return bcmerror;
2998 }
2999
3000 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3001 {
3002 uint retries;
3003 u32 regdata;
3004 int bcmerror = 0;
3005
3006 /* To enter download state, disable ARM and reset SOCRAM.
3007 * To exit download state, simply reset ARM (default is RAM boot).
3008 */
3009 if (enter) {
3010 bus->alp_only = true;
3011
3012 brcmf_sdbrcm_chip_disablecore(bus->card, bus->ci->armcorebase);
3013
3014 brcmf_sdbrcm_chip_resetcore(bus->card, bus->ci->ramcorebase);
3015
3016 /* Clear the top bit of memory */
3017 if (bus->ramsize) {
3018 u32 zeros = 0;
3019 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3020 (u8 *)&zeros, 4);
3021 }
3022 } else {
3023 regdata = brcmf_sdcard_reg_read(bus->card,
3024 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3025 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3026 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3027 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3028 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
3029 __func__));
3030 bcmerror = -EBADE;
3031 goto fail;
3032 }
3033
3034 bcmerror = brcmf_sdbrcm_write_vars(bus);
3035 if (bcmerror) {
3036 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
3037 bcmerror = 0;
3038 }
3039
3040 w_sdreg32(bus, 0xFFFFFFFF,
3041 offsetof(struct sdpcmd_regs, intstatus), &retries);
3042
3043 brcmf_sdbrcm_chip_resetcore(bus->card, bus->ci->armcorebase);
3044
3045 /* Allow HT Clock now that the ARM is running. */
3046 bus->alp_only = false;
3047
3048 bus->drvr->busstate = DHD_BUS_LOAD;
3049 }
3050 fail:
3051 return bcmerror;
3052 }
3053
3054 int
3055 brcmf_sdbrcm_bus_iovar_op(struct brcmf_pub *drvr, const char *name,
3056 void *params, int plen, void *arg, int len, bool set)
3057 {
3058 struct brcmf_bus *bus = drvr->bus;
3059 const struct brcmu_iovar *vi = NULL;
3060 int bcmerror = 0;
3061 int val_size;
3062 u32 actionid;
3063
3064 DHD_TRACE(("%s: Enter\n", __func__));
3065
3066 ASSERT(name);
3067 ASSERT(len >= 0);
3068
3069 /* Get MUST have return space */
3070 ASSERT(set || (arg && len));
3071
3072 /* Set does NOT take qualifiers */
3073 ASSERT(!set || (!params && !plen));
3074
3075 /* Look up var locally; if not found pass to host driver */
3076 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
3077 if (vi == NULL) {
3078 brcmf_sdbrcm_sdlock(bus);
3079
3080 BUS_WAKE(bus);
3081
3082 /* Turn on clock in case SD command needs backplane */
3083 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3084
3085 bcmerror = brcmf_sdcard_iovar_op(bus->card, name, params, plen,
3086 arg, len, set);
3087
3088 /* Similar check for blocksize change */
3089 if (set && strcmp(name, "sd_blocksize") == 0) {
3090 s32 fnum = 2;
3091 if (brcmf_sdcard_iovar_op
3092 (bus->card, "sd_blocksize", &fnum, sizeof(s32),
3093 &bus->blocksize, sizeof(s32),
3094 false) != 0) {
3095 bus->blocksize = 0;
3096 DHD_ERROR(("%s: fail on %s get\n", __func__,
3097 "sd_blocksize"));
3098 } else {
3099 DHD_INFO(("%s: noted %s update, value now %d\n",
3100 __func__, "sd_blocksize",
3101 bus->blocksize));
3102 }
3103 }
3104 bus->roundup = min(max_roundup, bus->blocksize);
3105
3106 if (bus->idletime == BRCMF_IDLE_IMMEDIATE &&
3107 !bus->dpc_sched) {
3108 bus->activity = false;
3109 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3110 }
3111
3112 brcmf_sdbrcm_sdunlock(bus);
3113 goto exit;
3114 }
3115
3116 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
3117 name, (set ? "set" : "get"), len, plen));
3118
3119 /* set up 'params' pointer in case this is a set command so that
3120 * the convenience int and bool code can be common to set and get
3121 */
3122 if (params == NULL) {
3123 params = arg;
3124 plen = len;
3125 }
3126
3127 if (vi->type == IOVT_VOID)
3128 val_size = 0;
3129 else if (vi->type == IOVT_BUFFER)
3130 val_size = len;
3131 else
3132 /* all other types are integer sized */
3133 val_size = sizeof(int);
3134
3135 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3136 bcmerror = brcmf_sdbrcm_doiovar(bus, vi, actionid, name, params, plen,
3137 arg, len, val_size);
3138
3139 exit:
3140 return bcmerror;
3141 }
3142
3143 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus, bool enforce_mutex)
3144 {
3145 u32 local_hostintmask;
3146 u8 saveclk;
3147 uint retries;
3148 int err;
3149
3150 DHD_TRACE(("%s: Enter\n", __func__));
3151
3152 if (enforce_mutex)
3153 brcmf_sdbrcm_sdlock(bus);
3154
3155 BUS_WAKE(bus);
3156
3157 /* Enable clock for device interrupts */
3158 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3159
3160 if (bus->watchdog_tsk) {
3161 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3162 kthread_stop(bus->watchdog_tsk);
3163 bus->watchdog_tsk = NULL;
3164 }
3165
3166 if (bus->dpc_tsk) {
3167 send_sig(SIGTERM, bus->dpc_tsk, 1);
3168 kthread_stop(bus->dpc_tsk);
3169 bus->dpc_tsk = NULL;
3170 } else
3171 tasklet_kill(&bus->tasklet);
3172
3173 /* Disable and clear interrupts at the chip level also */
3174 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3175 local_hostintmask = bus->hostintmask;
3176 bus->hostintmask = 0;
3177
3178 /* Change our idea of bus state */
3179 bus->drvr->busstate = DHD_BUS_DOWN;
3180
3181 /* Force clocks on backplane to be sure F2 interrupt propagates */
3182 saveclk = brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_1,
3183 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3184 if (!err) {
3185 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1,
3186 SBSDIO_FUNC1_CHIPCLKCSR,
3187 (saveclk | SBSDIO_FORCE_HT), &err);
3188 }
3189 if (err) {
3190 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3191 __func__, err));
3192 }
3193
3194 /* Turn off the bus (F2), free any pending packets */
3195 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3196 brcmf_sdcard_intr_disable(bus->card);
3197 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3198 SDIO_FUNC_ENABLE_1, NULL);
3199
3200 /* Clear any pending interrupts now that F2 is disabled */
3201 w_sdreg32(bus, local_hostintmask,
3202 offsetof(struct sdpcmd_regs, intstatus), &retries);
3203
3204 /* Turn off the backplane clock (only) */
3205 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3206
3207 /* Clear the data packet queues */
3208 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3209
3210 /* Clear any held glomming stuff */
3211 if (bus->glomd)
3212 brcmu_pkt_buf_free_skb(bus->glomd);
3213
3214 if (bus->glom)
3215 brcmu_pkt_buf_free_skb(bus->glom);
3216
3217 bus->glom = bus->glomd = NULL;
3218
3219 /* Clear rx control and wake any waiters */
3220 bus->rxlen = 0;
3221 brcmf_os_ioctl_resp_wake(bus->drvr);
3222
3223 /* Reset some F2 state stuff */
3224 bus->rxskip = false;
3225 bus->tx_seq = bus->rx_seq = 0;
3226
3227 if (enforce_mutex)
3228 brcmf_sdbrcm_sdunlock(bus);
3229 }
3230
3231 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr, bool enforce_mutex)
3232 {
3233 struct brcmf_bus *bus = drvr->bus;
3234 struct brcmf_timeout tmo;
3235 uint retries = 0;
3236 u8 ready, enable;
3237 int err, ret = 0;
3238 u8 saveclk;
3239
3240 DHD_TRACE(("%s: Enter\n", __func__));
3241
3242 /* try to download image and nvram to the dongle */
3243 if (drvr->busstate == DHD_BUS_DOWN) {
3244 if (!(brcmf_sdbrcm_download_firmware(bus, bus->card)))
3245 return -1;
3246 }
3247
3248 ASSERT(bus->drvr);
3249 if (!bus->drvr)
3250 return 0;
3251
3252 /* Start the watchdog timer */
3253 bus->drvr->tickcnt = 0;
3254 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
3255
3256 if (enforce_mutex)
3257 brcmf_sdbrcm_sdlock(bus);
3258
3259 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3260 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3261 if (bus->clkstate != CLK_AVAIL)
3262 goto exit;
3263
3264 /* Force clocks on backplane to be sure F2 interrupt propagates */
3265 saveclk =
3266 brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_1,
3267 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3268 if (!err) {
3269 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1,
3270 SBSDIO_FUNC1_CHIPCLKCSR,
3271 (saveclk | SBSDIO_FORCE_HT), &err);
3272 }
3273 if (err) {
3274 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3275 __func__, err));
3276 goto exit;
3277 }
3278
3279 /* Enable function 2 (frame transfers) */
3280 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3281 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3282 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3283
3284 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3285 NULL);
3286
3287 /* Give the dongle some time to do its thing and set IOR2 */
3288 brcmf_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3289
3290 ready = 0;
3291 while (ready != enable && !brcmf_timeout_expired(&tmo))
3292 ready = brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_0,
3293 SDIO_CCCR_IORx, NULL);
3294
3295 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3296 __func__, enable, ready, tmo.elapsed));
3297
3298 /* If F2 successfully enabled, set core and enable interrupts */
3299 if (ready == enable) {
3300 /* Set up the interrupt mask and enable interrupts */
3301 bus->hostintmask = HOSTINTMASK;
3302 w_sdreg32(bus, bus->hostintmask,
3303 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3304
3305 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_WATERMARK,
3306 (u8) watermark, &err);
3307
3308 /* Set bus state according to enable result */
3309 drvr->busstate = DHD_BUS_DATA;
3310
3311 bus->intdis = false;
3312 if (bus->intr) {
3313 DHD_INTR(("%s: enable SDIO device interrupts\n",
3314 __func__));
3315 brcmf_sdcard_intr_enable(bus->card);
3316 } else {
3317 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3318 brcmf_sdcard_intr_disable(bus->card);
3319 }
3320
3321 }
3322
3323 else {
3324 /* Disable F2 again */
3325 enable = SDIO_FUNC_ENABLE_1;
3326 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3327 enable, NULL);
3328 }
3329
3330 /* Restore previous clock setting */
3331 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3332 saveclk, &err);
3333
3334 #if defined(OOB_INTR_ONLY)
3335 /* Host registration for OOB interrupt */
3336 if (brcmf_sdio_register_oob_intr(bus->dhd)) {
3337 brcmf_sdbrcm_wd_timer(bus, 0);
3338 DHD_ERROR(("%s Host failed to resgister for OOB\n", __func__));
3339 ret = -ENODEV;
3340 goto exit;
3341 }
3342
3343 /* Enable oob at firmware */
3344 brcmf_sdbrcm_enable_oob_intr(bus, true);
3345 #endif /* defined(OOB_INTR_ONLY) */
3346
3347 /* If we didn't come up, turn off backplane clock */
3348 if (drvr->busstate != DHD_BUS_DATA)
3349 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3350
3351 exit:
3352 if (enforce_mutex)
3353 brcmf_sdbrcm_sdunlock(bus);
3354
3355 return ret;
3356 }
3357
3358 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
3359 {
3360 struct brcmf_sdio_card *card = bus->card;
3361 uint retries = 0;
3362 u16 lastrbc;
3363 u8 hi, lo;
3364 int err;
3365
3366 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3367 (abort ? "abort command, " : ""),
3368 (rtx ? ", send NAK" : "")));
3369
3370 if (abort)
3371 brcmf_sdcard_abort(card, SDIO_FUNC_2);
3372
3373 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
3374 SFC_RF_TERM, &err);
3375 bus->f1regdata++;
3376
3377 /* Wait until the packet has been flushed (device/FIFO stable) */
3378 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3379 hi = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
3380 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
3381 lo = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
3382 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
3383 bus->f1regdata += 2;
3384
3385 if ((hi == 0) && (lo == 0))
3386 break;
3387
3388 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3389 DHD_ERROR(("%s: count growing: last 0x%04x now "
3390 "0x%04x\n",
3391 __func__, lastrbc, ((hi << 8) + lo)));
3392 }
3393 lastrbc = (hi << 8) + lo;
3394 }
3395
3396 if (!retries) {
3397 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3398 __func__, lastrbc));
3399 } else {
3400 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3401 (0xffff - retries)));
3402 }
3403
3404 if (rtx) {
3405 bus->rxrtx++;
3406 w_sdreg32(bus, SMB_NAK,
3407 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
3408
3409 bus->f1regdata++;
3410 if (retries <= retry_limit)
3411 bus->rxskip = true;
3412 }
3413
3414 /* Clear partial in any case */
3415 bus->nextlen = 0;
3416
3417 /* If we can't reach the device, signal failure */
3418 if (err || brcmf_sdcard_regfail(card))
3419 bus->drvr->busstate = DHD_BUS_DOWN;
3420 }
3421
3422 static void
3423 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
3424 {
3425 struct brcmf_sdio_card *card = bus->card;
3426 uint rdlen, pad;
3427
3428 int sdret;
3429
3430 DHD_TRACE(("%s: Enter\n", __func__));
3431
3432 /* Control data already received in aligned rxctl */
3433 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3434 goto gotpkt;
3435
3436 ASSERT(bus->rxbuf);
3437 /* Set rxctl for frame (w/optional alignment) */
3438 bus->rxctl = bus->rxbuf;
3439 if (brcmf_alignctl) {
3440 bus->rxctl += firstread;
3441 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
3442 if (pad)
3443 bus->rxctl += (BRCMF_SDALIGN - pad);
3444 bus->rxctl -= firstread;
3445 }
3446 ASSERT(bus->rxctl >= bus->rxbuf);
3447
3448 /* Copy the already-read portion over */
3449 memcpy(bus->rxctl, hdr, firstread);
3450 if (len <= firstread)
3451 goto gotpkt;
3452
3453 /* Copy the full data pkt in gSPI case and process ioctl. */
3454 if (bus->bus == SPI_BUS) {
3455 memcpy(bus->rxctl, hdr, len);
3456 goto gotpkt;
3457 }
3458
3459 /* Raise rdlen to next SDIO block to avoid tail command */
3460 rdlen = len - firstread;
3461 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3462 pad = bus->blocksize - (rdlen % bus->blocksize);
3463 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3464 ((len + pad) < bus->drvr->maxctl))
3465 rdlen += pad;
3466 } else if (rdlen % BRCMF_SDALIGN) {
3467 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
3468 }
3469
3470 /* Satisfy length-alignment requirements */
3471 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3472 rdlen = roundup(rdlen, ALIGNMENT);
3473
3474 /* Drop if the read is too big or it exceeds our maximum */
3475 if ((rdlen + firstread) > bus->drvr->maxctl) {
3476 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3477 __func__, rdlen, bus->drvr->maxctl));
3478 bus->drvr->rx_errors++;
3479 brcmf_sdbrcm_rxfail(bus, false, false);
3480 goto done;
3481 }
3482
3483 if ((len - doff) > bus->drvr->maxctl) {
3484 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3485 "%d-byte limit\n",
3486 __func__, len, (len - doff), bus->drvr->maxctl));
3487 bus->drvr->rx_errors++;
3488 bus->rx_toolong++;
3489 brcmf_sdbrcm_rxfail(bus, false, false);
3490 goto done;
3491 }
3492
3493 /* Read remainder of frame body into the rxctl buffer */
3494 sdret = brcmf_sdcard_recv_buf(card, brcmf_sdcard_cur_sbwad(card),
3495 SDIO_FUNC_2,
3496 F2SYNC, (bus->rxctl + firstread), rdlen,
3497 NULL, NULL, NULL);
3498 bus->f2rxdata++;
3499 ASSERT(sdret != -BCME_PENDING);
3500
3501 /* Control frame failures need retransmission */
3502 if (sdret < 0) {
3503 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3504 __func__, rdlen, sdret));
3505 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3506 brcmf_sdbrcm_rxfail(bus, true, true);
3507 goto done;
3508 }
3509
3510 gotpkt:
3511
3512 #ifdef BCMDBG
3513 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3514 printk(KERN_DEBUG "RxCtrl:\n");
3515 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3516 }
3517 #endif
3518
3519 /* Point to valid data and indicate its length */
3520 bus->rxctl += doff;
3521 bus->rxlen = len - doff;
3522
3523 done:
3524 /* Awake any waiters */
3525 brcmf_os_ioctl_resp_wake(bus->drvr);
3526 }
3527
3528 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
3529 {
3530 u16 dlen, totlen;
3531 u8 *dptr, num = 0;
3532
3533 u16 sublen, check;
3534 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3535
3536 int errcode;
3537 u8 chan, seq, doff, sfdoff;
3538 u8 txmax;
3539
3540 int ifidx = 0;
3541 bool usechain = bus->use_rxchain;
3542
3543 /* If packets, issue read(s) and send up packet chain */
3544 /* Return sequence numbers consumed? */
3545
3546 DHD_TRACE(("brcmf_sdbrcm_rxglom: start: glomd %p glom %p\n", bus->glomd,
3547 bus->glom));
3548
3549 /* If there's a descriptor, generate the packet chain */
3550 if (bus->glomd) {
3551 pfirst = plast = pnext = NULL;
3552 dlen = (u16) (bus->glomd->len);
3553 dptr = bus->glomd->data;
3554 if (!dlen || (dlen & 1)) {
3555 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3556 __func__, dlen));
3557 dlen = 0;
3558 }
3559
3560 for (totlen = num = 0; dlen; num++) {
3561 /* Get (and move past) next length */
3562 sublen = get_unaligned_le16(dptr);
3563 dlen -= sizeof(u16);
3564 dptr += sizeof(u16);
3565 if ((sublen < SDPCM_HDRLEN) ||
3566 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3567 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3568 __func__, num, sublen));
3569 pnext = NULL;
3570 break;
3571 }
3572 if (sublen % BRCMF_SDALIGN) {
3573 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3574 __func__, sublen, BRCMF_SDALIGN));
3575 usechain = false;
3576 }
3577 totlen += sublen;
3578
3579 /* For last frame, adjust read len so total
3580 is a block multiple */
3581 if (!dlen) {
3582 sublen +=
3583 (roundup(totlen, bus->blocksize) - totlen);
3584 totlen = roundup(totlen, bus->blocksize);
3585 }
3586
3587 /* Allocate/chain packet for next subframe */
3588 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
3589 if (pnext == NULL) {
3590 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3591 "num %d len %d\n", __func__,
3592 num, sublen));
3593 break;
3594 }
3595 ASSERT(!(pnext->prev));
3596 if (!pfirst) {
3597 ASSERT(!plast);
3598 pfirst = plast = pnext;
3599 } else {
3600 ASSERT(plast);
3601 plast->next = pnext;
3602 plast = pnext;
3603 }
3604
3605 /* Adhere to start alignment requirements */
3606 PKTALIGN(pnext, sublen, BRCMF_SDALIGN);
3607 }
3608
3609 /* If all allocations succeeded, save packet chain
3610 in bus structure */
3611 if (pnext) {
3612 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3613 "subframes\n", __func__, totlen, num));
3614 if (DHD_GLOM_ON() && bus->nextlen) {
3615 if (totlen != bus->nextlen) {
3616 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3617 __func__, bus->nextlen,
3618 totlen, rxseq));
3619 }
3620 }
3621 bus->glom = pfirst;
3622 pfirst = pnext = NULL;
3623 } else {
3624 if (pfirst)
3625 brcmu_pkt_buf_free_skb(pfirst);
3626 bus->glom = NULL;
3627 num = 0;
3628 }
3629
3630 /* Done with descriptor packet */
3631 brcmu_pkt_buf_free_skb(bus->glomd);
3632 bus->glomd = NULL;
3633 bus->nextlen = 0;
3634 }
3635
3636 /* Ok -- either we just generated a packet chain,
3637 or had one from before */
3638 if (bus->glom) {
3639 if (DHD_GLOM_ON()) {
3640 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3641 __func__));
3642 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3643 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3644 pnext, (u8 *) (pnext->data),
3645 pnext->len, pnext->len));
3646 }
3647 }
3648
3649 pfirst = bus->glom;
3650 dlen = (u16) brcmu_pkttotlen(pfirst);
3651
3652 /* Do an SDIO read for the superframe. Configurable iovar to
3653 * read directly into the chained packet, or allocate a large
3654 * packet and and copy into the chain.
3655 */
3656 if (usechain) {
3657 errcode = brcmf_sdcard_recv_buf(bus->card,
3658 brcmf_sdcard_cur_sbwad(bus->card),
3659 SDIO_FUNC_2,
3660 F2SYNC, (u8 *) pfirst->data, dlen,
3661 pfirst, NULL, NULL);
3662 } else if (bus->dataptr) {
3663 errcode = brcmf_sdcard_recv_buf(bus->card,
3664 brcmf_sdcard_cur_sbwad(bus->card),
3665 SDIO_FUNC_2,
3666 F2SYNC, bus->dataptr, dlen,
3667 NULL, NULL, NULL);
3668 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3669 bus->dataptr);
3670 if (sublen != dlen) {
3671 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3672 __func__, dlen, sublen));
3673 errcode = -1;
3674 }
3675 pnext = NULL;
3676 } else {
3677 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3678 dlen));
3679 errcode = -1;
3680 }
3681 bus->f2rxdata++;
3682 ASSERT(errcode != -BCME_PENDING);
3683
3684 /* On failure, kill the superframe, allow a couple retries */
3685 if (errcode < 0) {
3686 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3687 __func__, dlen, errcode));
3688 bus->drvr->rx_errors++;
3689
3690 if (bus->glomerr++ < 3) {
3691 brcmf_sdbrcm_rxfail(bus, true, true);
3692 } else {
3693 bus->glomerr = 0;
3694 brcmf_sdbrcm_rxfail(bus, true, false);
3695 brcmu_pkt_buf_free_skb(bus->glom);
3696 bus->rxglomfail++;
3697 bus->glom = NULL;
3698 }
3699 return 0;
3700 }
3701 #ifdef BCMDBG
3702 if (DHD_GLOM_ON()) {
3703 printk(KERN_DEBUG "SUPERFRAME:\n");
3704 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3705 pfirst->data, min_t(int, pfirst->len, 48));
3706 }
3707 #endif
3708
3709 /* Validate the superframe header */
3710 dptr = (u8 *) (pfirst->data);
3711 sublen = get_unaligned_le16(dptr);
3712 check = get_unaligned_le16(dptr + sizeof(u16));
3713
3714 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3715 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3716 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3717 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3718 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3719 __func__, bus->nextlen, seq));
3720 bus->nextlen = 0;
3721 }
3722 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3723 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3724
3725 errcode = 0;
3726 if ((u16)~(sublen ^ check)) {
3727 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3728 "0x%04x/0x%04x\n", __func__, sublen, check));
3729 errcode = -1;
3730 } else if (roundup(sublen, bus->blocksize) != dlen) {
3731 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3732 "0x%04x, expect 0x%04x\n",
3733 __func__, sublen,
3734 roundup(sublen, bus->blocksize), dlen));
3735 errcode = -1;
3736 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3737 SDPCM_GLOM_CHANNEL) {
3738 DHD_ERROR(("%s (superframe): bad channel %d\n",
3739 __func__,
3740 SDPCM_PACKET_CHANNEL(&dptr
3741 [SDPCM_FRAMETAG_LEN])));
3742 errcode = -1;
3743 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3744 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3745 __func__));
3746 errcode = -1;
3747 } else if ((doff < SDPCM_HDRLEN) ||
3748 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3749 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3750 "pkt %d min %d\n",
3751 __func__, doff, sublen,
3752 pfirst->len, SDPCM_HDRLEN));
3753 errcode = -1;
3754 }
3755
3756 /* Check sequence number of superframe SW header */
3757 if (rxseq != seq) {
3758 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3759 __func__, seq, rxseq));
3760 bus->rx_badseq++;
3761 rxseq = seq;
3762 }
3763
3764 /* Check window for sanity */
3765 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3766 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3767 __func__, txmax, bus->tx_seq));
3768 txmax = bus->tx_seq + 2;
3769 }
3770 bus->tx_max = txmax;
3771
3772 /* Remove superframe header, remember offset */
3773 skb_pull(pfirst, doff);
3774 sfdoff = doff;
3775
3776 /* Validate all the subframe headers */
3777 for (num = 0, pnext = pfirst; pnext && !errcode;
3778 num++, pnext = pnext->next) {
3779 dptr = (u8 *) (pnext->data);
3780 dlen = (u16) (pnext->len);
3781 sublen = get_unaligned_le16(dptr);
3782 check = get_unaligned_le16(dptr + sizeof(u16));
3783 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3784 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3785 #ifdef BCMDBG
3786 if (DHD_GLOM_ON()) {
3787 printk(KERN_DEBUG "subframe:\n");
3788 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3789 dptr, 32);
3790 }
3791 #endif
3792
3793 if ((u16)~(sublen ^ check)) {
3794 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3795 "len/check 0x%04x/0x%04x\n",
3796 __func__, num, sublen, check));
3797 errcode = -1;
3798 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3799 DHD_ERROR(("%s (subframe %d): length mismatch: "
3800 "len 0x%04x, expect 0x%04x\n",
3801 __func__, num, sublen, dlen));
3802 errcode = -1;
3803 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3804 (chan != SDPCM_EVENT_CHANNEL)) {
3805 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3806 __func__, num, chan));
3807 errcode = -1;
3808 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3809 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3810 __func__, num, doff, sublen,
3811 SDPCM_HDRLEN));
3812 errcode = -1;
3813 }
3814 }
3815
3816 if (errcode) {
3817 /* Terminate frame on error, request
3818 a couple retries */
3819 if (bus->glomerr++ < 3) {
3820 /* Restore superframe header space */
3821 skb_push(pfirst, sfdoff);
3822 brcmf_sdbrcm_rxfail(bus, true, true);
3823 } else {
3824 bus->glomerr = 0;
3825 brcmf_sdbrcm_rxfail(bus, true, false);
3826 brcmu_pkt_buf_free_skb(bus->glom);
3827 bus->rxglomfail++;
3828 bus->glom = NULL;
3829 }
3830 bus->nextlen = 0;
3831 return 0;
3832 }
3833
3834 /* Basic SD framing looks ok - process each packet (header) */
3835 save_pfirst = pfirst;
3836 bus->glom = NULL;
3837 plast = NULL;
3838
3839 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3840 pnext = pfirst->next;
3841 pfirst->next = NULL;
3842
3843 dptr = (u8 *) (pfirst->data);
3844 sublen = get_unaligned_le16(dptr);
3845 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3846 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3847 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3848
3849 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3850 "chan %d seq %d\n",
3851 __func__, num, pfirst, pfirst->data,
3852 pfirst->len, sublen, chan, seq));
3853
3854 ASSERT((chan == SDPCM_DATA_CHANNEL)
3855 || (chan == SDPCM_EVENT_CHANNEL));
3856
3857 if (rxseq != seq) {
3858 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3859 __func__, seq, rxseq));
3860 bus->rx_badseq++;
3861 rxseq = seq;
3862 }
3863 #ifdef BCMDBG
3864 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3865 printk(KERN_DEBUG "Rx Subframe Data:\n");
3866 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3867 dptr, dlen);
3868 }
3869 #endif
3870
3871 __skb_trim(pfirst, sublen);
3872 skb_pull(pfirst, doff);
3873
3874 if (pfirst->len == 0) {
3875 brcmu_pkt_buf_free_skb(pfirst);
3876 if (plast) {
3877 plast->next = pnext;
3878 } else {
3879 ASSERT(save_pfirst == pfirst);
3880 save_pfirst = pnext;
3881 }
3882 continue;
3883 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pfirst)
3884 != 0) {
3885 DHD_ERROR(("%s: rx protocol error\n",
3886 __func__));
3887 bus->drvr->rx_errors++;
3888 brcmu_pkt_buf_free_skb(pfirst);
3889 if (plast) {
3890 plast->next = pnext;
3891 } else {
3892 ASSERT(save_pfirst == pfirst);
3893 save_pfirst = pnext;
3894 }
3895 continue;
3896 }
3897
3898 /* this packet will go up, link back into
3899 chain and count it */
3900 pfirst->next = pnext;
3901 plast = pfirst;
3902 num++;
3903
3904 #ifdef BCMDBG
3905 if (DHD_GLOM_ON()) {
3906 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3907 "nxt/lnk %p/%p\n",
3908 __func__, num, pfirst, pfirst->data,
3909 pfirst->len, pfirst->next,
3910 pfirst->prev));
3911 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3912 pfirst->data,
3913 min_t(int, pfirst->len, 32));
3914 }
3915 #endif /* BCMDBG */
3916 }
3917 if (num) {
3918 brcmf_sdbrcm_sdunlock(bus);
3919 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
3920 brcmf_sdbrcm_sdlock(bus);
3921 }
3922
3923 bus->rxglomframes++;
3924 bus->rxglompkts += num;
3925 }
3926 return num;
3927 }
3928
3929 /* Return true if there may be more frames to read */
3930 static uint
3931 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
3932 {
3933 struct brcmf_sdio_card *card = bus->card;
3934
3935 u16 len, check; /* Extracted hardware header fields */
3936 u8 chan, seq, doff; /* Extracted software header fields */
3937 u8 fcbits; /* Extracted fcbits from software header */
3938
3939 struct sk_buff *pkt; /* Packet for event or data frames */
3940 u16 pad; /* Number of pad bytes to read */
3941 u16 rdlen; /* Total number of bytes to read */
3942 u8 rxseq; /* Next sequence number to expect */
3943 uint rxleft = 0; /* Remaining number of frames allowed */
3944 int sdret; /* Return code from calls */
3945 u8 txmax; /* Maximum tx sequence offered */
3946 bool len_consistent; /* Result of comparing readahead len and
3947 len from hw-hdr */
3948 u8 *rxbuf;
3949 int ifidx = 0;
3950 uint rxcount = 0; /* Total frames read */
3951
3952 #if defined(BCMDBG) || defined(SDTEST)
3953 bool sdtest = false; /* To limit message spew from test mode */
3954 #endif
3955
3956 DHD_TRACE(("%s: Enter\n", __func__));
3957
3958 ASSERT(maxframes);
3959
3960 #ifdef SDTEST
3961 /* Allow pktgen to override maxframes */
3962 if (bus->pktgen_count && (bus->pktgen_mode == BRCMF_PKTGEN_RECV)) {
3963 maxframes = bus->pktgen_count;
3964 sdtest = true;
3965 }
3966 #endif
3967
3968 /* Not finished unless we encounter no more frames indication */
3969 *finished = false;
3970
3971 for (rxseq = bus->rx_seq, rxleft = maxframes;
3972 !bus->rxskip && rxleft && bus->drvr->busstate != DHD_BUS_DOWN;
3973 rxseq++, rxleft--) {
3974
3975 /* Handle glomming separately */
3976 if (bus->glom || bus->glomd) {
3977 u8 cnt;
3978 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3979 __func__, bus->glomd, bus->glom));
3980 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
3981 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3982 rxseq += cnt - 1;
3983 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3984 continue;
3985 }
3986
3987 /* Try doing single read if we can */
3988 if (brcmf_readahead && bus->nextlen) {
3989 u16 nextlen = bus->nextlen;
3990 bus->nextlen = 0;
3991
3992 if (bus->bus == SPI_BUS) {
3993 rdlen = len = nextlen;
3994 } else {
3995 rdlen = len = nextlen << 4;
3996
3997 /* Pad read to blocksize for efficiency */
3998 if (bus->roundup && bus->blocksize
3999 && (rdlen > bus->blocksize)) {
4000 pad =
4001 bus->blocksize -
4002 (rdlen % bus->blocksize);
4003 if ((pad <= bus->roundup)
4004 && (pad < bus->blocksize)
4005 && ((rdlen + pad + firstread) <
4006 MAX_RX_DATASZ))
4007 rdlen += pad;
4008 } else if (rdlen % BRCMF_SDALIGN) {
4009 rdlen +=
4010 BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
4011 }
4012 }
4013
4014 /* We use bus->rxctl buffer in WinXP for initial
4015 * control pkt receives.
4016 * Later we use buffer-poll for data as well
4017 * as control packets.
4018 * This is required because dhd receives full
4019 * frame in gSPI unlike SDIO.
4020 * After the frame is received we have to
4021 * distinguish whether it is data
4022 * or non-data frame.
4023 */
4024 /* Allocate a packet buffer */
4025 pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
4026 if (!pkt) {
4027 if (bus->bus == SPI_BUS) {
4028 bus->usebufpool = false;
4029 bus->rxctl = bus->rxbuf;
4030 if (brcmf_alignctl) {
4031 bus->rxctl += firstread;
4032 pad = ((unsigned long)bus->rxctl %
4033 BRCMF_SDALIGN);
4034 if (pad)
4035 bus->rxctl +=
4036 (BRCMF_SDALIGN - pad);
4037 bus->rxctl -= firstread;
4038 }
4039 ASSERT(bus->rxctl >= bus->rxbuf);
4040 rxbuf = bus->rxctl;
4041 /* Read the entire frame */
4042 sdret = brcmf_sdcard_recv_buf(card,
4043 brcmf_sdcard_cur_sbwad(card),
4044 SDIO_FUNC_2, F2SYNC,
4045 rxbuf, rdlen,
4046 NULL, NULL, NULL);
4047 bus->f2rxdata++;
4048 ASSERT(sdret != -BCME_PENDING);
4049
4050 /* Control frame failures need
4051 retransmission */
4052 if (sdret < 0) {
4053 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
4054 __func__,
4055 rdlen, sdret));
4056 /* dhd.rx_ctlerrs is higher */
4057 bus->rxc_errors++;
4058 brcmf_sdbrcm_rxfail(bus, true,
4059 (bus->bus ==
4060 SPI_BUS) ? false
4061 : true);
4062 continue;
4063 }
4064 } else {
4065 /* Give up on data,
4066 request rtx of events */
4067 DHD_ERROR(("%s (nextlen): "
4068 "brcmu_pkt_buf_get_skb "
4069 "failed:"
4070 " len %d rdlen %d expected"
4071 " rxseq %d\n", __func__,
4072 len, rdlen, rxseq));
4073 continue;
4074 }
4075 } else {
4076 if (bus->bus == SPI_BUS)
4077 bus->usebufpool = true;
4078
4079 ASSERT(!(pkt->prev));
4080 PKTALIGN(pkt, rdlen, BRCMF_SDALIGN);
4081 rxbuf = (u8 *) (pkt->data);
4082 /* Read the entire frame */
4083 sdret = brcmf_sdcard_recv_buf(card,
4084 brcmf_sdcard_cur_sbwad(card),
4085 SDIO_FUNC_2, F2SYNC,
4086 rxbuf, rdlen,
4087 pkt, NULL, NULL);
4088 bus->f2rxdata++;
4089 ASSERT(sdret != -BCME_PENDING);
4090
4091 if (sdret < 0) {
4092 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
4093 __func__, rdlen, sdret));
4094 brcmu_pkt_buf_free_skb(pkt);
4095 bus->drvr->rx_errors++;
4096 /* Force retry w/normal header read.
4097 * Don't attempt NAK for
4098 * gSPI
4099 */
4100 brcmf_sdbrcm_rxfail(bus, true,
4101 (bus->bus ==
4102 SPI_BUS) ? false :
4103 true);
4104 continue;
4105 }
4106 }
4107
4108 /* Now check the header */
4109 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
4110
4111 /* Extract hardware header fields */
4112 len = get_unaligned_le16(bus->rxhdr);
4113 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4114
4115 /* All zeros means readahead info was bad */
4116 if (!(len | check)) {
4117 DHD_INFO(("%s (nextlen): read zeros in HW "
4118 "header???\n", __func__));
4119 brcmf_sdbrcm_pktfree2(bus, pkt);
4120 continue;
4121 }
4122
4123 /* Validate check bytes */
4124 if ((u16)~(len ^ check)) {
4125 DHD_ERROR(("%s (nextlen): HW hdr error:"
4126 " nextlen/len/check"
4127 " 0x%04x/0x%04x/0x%04x\n",
4128 __func__, nextlen, len, check));
4129 bus->rx_badhdr++;
4130 brcmf_sdbrcm_rxfail(bus, false, false);
4131 brcmf_sdbrcm_pktfree2(bus, pkt);
4132 continue;
4133 }
4134
4135 /* Validate frame length */
4136 if (len < SDPCM_HDRLEN) {
4137 DHD_ERROR(("%s (nextlen): HW hdr length "
4138 "invalid: %d\n", __func__, len));
4139 brcmf_sdbrcm_pktfree2(bus, pkt);
4140 continue;
4141 }
4142
4143 /* Check for consistency withreadahead info */
4144 len_consistent = (nextlen != (roundup(len, 16) >> 4));
4145 if (len_consistent) {
4146 /* Mismatch, force retry w/normal
4147 header (may be >4K) */
4148 DHD_ERROR(("%s (nextlen): mismatch, "
4149 "nextlen %d len %d rnd %d; "
4150 "expected rxseq %d\n",
4151 __func__, nextlen,
4152 len, roundup(len, 16), rxseq));
4153 brcmf_sdbrcm_rxfail(bus, true,
4154 bus->bus != SPI_BUS);
4155 brcmf_sdbrcm_pktfree2(bus, pkt);
4156 continue;
4157 }
4158
4159 /* Extract software header fields */
4160 chan = SDPCM_PACKET_CHANNEL(
4161 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4162 seq = SDPCM_PACKET_SEQUENCE(
4163 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4164 doff = SDPCM_DOFFSET_VALUE(
4165 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4166 txmax = SDPCM_WINDOW_VALUE(
4167 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4168
4169 bus->nextlen =
4170 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4171 SDPCM_NEXTLEN_OFFSET];
4172 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4173 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4174 __func__, bus->nextlen, seq));
4175 bus->nextlen = 0;
4176 }
4177
4178 bus->drvr->rx_readahead_cnt++;
4179
4180 /* Handle Flow Control */
4181 fcbits = SDPCM_FCMASK_VALUE(
4182 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4183
4184 if (bus->flowcontrol != fcbits) {
4185 if (~bus->flowcontrol & fcbits)
4186 bus->fc_xoff++;
4187
4188 if (bus->flowcontrol & ~fcbits)
4189 bus->fc_xon++;
4190
4191 bus->fc_rcvd++;
4192 bus->flowcontrol = fcbits;
4193 }
4194
4195 /* Check and update sequence number */
4196 if (rxseq != seq) {
4197 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4198 "%d\n", __func__, seq, rxseq));
4199 bus->rx_badseq++;
4200 rxseq = seq;
4201 }
4202
4203 /* Check window for sanity */
4204 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4205 DHD_ERROR(("%s: got unlikely tx max %d with "
4206 "tx_seq %d\n",
4207 __func__, txmax, bus->tx_seq));
4208 txmax = bus->tx_seq + 2;
4209 }
4210 bus->tx_max = txmax;
4211
4212 #ifdef BCMDBG
4213 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4214 printk(KERN_DEBUG "Rx Data:\n");
4215 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4216 rxbuf, len);
4217 } else if (DHD_HDRS_ON()) {
4218 printk(KERN_DEBUG "RxHdr:\n");
4219 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4220 bus->rxhdr, SDPCM_HDRLEN);
4221 }
4222 #endif
4223
4224 if (chan == SDPCM_CONTROL_CHANNEL) {
4225 if (bus->bus == SPI_BUS) {
4226 brcmf_sdbrcm_read_control(bus, rxbuf,
4227 len, doff);
4228 } else {
4229 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4230 __func__, seq));
4231 /* Force retry w/normal header read */
4232 bus->nextlen = 0;
4233 brcmf_sdbrcm_rxfail(bus, false, true);
4234 }
4235 brcmf_sdbrcm_pktfree2(bus, pkt);
4236 continue;
4237 }
4238
4239 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4240 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4241 len, chan));
4242 continue;
4243 }
4244
4245 /* Validate data offset */
4246 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4247 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4248 __func__, doff, len, SDPCM_HDRLEN));
4249 brcmf_sdbrcm_rxfail(bus, false, false);
4250 brcmf_sdbrcm_pktfree2(bus, pkt);
4251 continue;
4252 }
4253
4254 /* All done with this one -- now deliver the packet */
4255 goto deliver;
4256 }
4257 /* gSPI frames should not be handled in fractions */
4258 if (bus->bus == SPI_BUS)
4259 break;
4260
4261 /* Read frame header (hardware and software) */
4262 sdret = brcmf_sdcard_recv_buf(card,
4263 brcmf_sdcard_cur_sbwad(card),
4264 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4265 NULL, NULL, NULL);
4266 bus->f2rxhdrs++;
4267 ASSERT(sdret != -BCME_PENDING);
4268
4269 if (sdret < 0) {
4270 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4271 sdret));
4272 bus->rx_hdrfail++;
4273 brcmf_sdbrcm_rxfail(bus, true, true);
4274 continue;
4275 }
4276 #ifdef BCMDBG
4277 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4278 printk(KERN_DEBUG "RxHdr:\n");
4279 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4280 bus->rxhdr, SDPCM_HDRLEN);
4281 }
4282 #endif
4283
4284 /* Extract hardware header fields */
4285 len = get_unaligned_le16(bus->rxhdr);
4286 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4287
4288 /* All zeros means no more frames */
4289 if (!(len | check)) {
4290 *finished = true;
4291 break;
4292 }
4293
4294 /* Validate check bytes */
4295 if ((u16) ~(len ^ check)) {
4296 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4297 __func__, len, check));
4298 bus->rx_badhdr++;
4299 brcmf_sdbrcm_rxfail(bus, false, false);
4300 continue;
4301 }
4302
4303 /* Validate frame length */
4304 if (len < SDPCM_HDRLEN) {
4305 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4306 __func__, len));
4307 continue;
4308 }
4309
4310 /* Extract software header fields */
4311 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4312 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4313 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4314 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4315
4316 /* Validate data offset */
4317 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4318 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4319 "seq %d\n",
4320 __func__, doff, len, SDPCM_HDRLEN, seq));
4321 bus->rx_badhdr++;
4322 ASSERT(0);
4323 brcmf_sdbrcm_rxfail(bus, false, false);
4324 continue;
4325 }
4326
4327 /* Save the readahead length if there is one */
4328 bus->nextlen =
4329 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4330 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4331 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4332 "(%d), seq %d\n",
4333 __func__, bus->nextlen, seq));
4334 bus->nextlen = 0;
4335 }
4336
4337 /* Handle Flow Control */
4338 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4339
4340 if (bus->flowcontrol != fcbits) {
4341 if (~bus->flowcontrol & fcbits)
4342 bus->fc_xoff++;
4343
4344 if (bus->flowcontrol & ~fcbits)
4345 bus->fc_xon++;
4346
4347 bus->fc_rcvd++;
4348 bus->flowcontrol = fcbits;
4349 }
4350
4351 /* Check and update sequence number */
4352 if (rxseq != seq) {
4353 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4354 seq, rxseq));
4355 bus->rx_badseq++;
4356 rxseq = seq;
4357 }
4358
4359 /* Check window for sanity */
4360 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4361 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4362 __func__, txmax, bus->tx_seq));
4363 txmax = bus->tx_seq + 2;
4364 }
4365 bus->tx_max = txmax;
4366
4367 /* Call a separate function for control frames */
4368 if (chan == SDPCM_CONTROL_CHANNEL) {
4369 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
4370 continue;
4371 }
4372
4373 ASSERT((chan == SDPCM_DATA_CHANNEL)
4374 || (chan == SDPCM_EVENT_CHANNEL)
4375 || (chan == SDPCM_TEST_CHANNEL)
4376 || (chan == SDPCM_GLOM_CHANNEL));
4377
4378 /* Length to read */
4379 rdlen = (len > firstread) ? (len - firstread) : 0;
4380
4381 /* May pad read to blocksize for efficiency */
4382 if (bus->roundup && bus->blocksize &&
4383 (rdlen > bus->blocksize)) {
4384 pad = bus->blocksize - (rdlen % bus->blocksize);
4385 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4386 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4387 rdlen += pad;
4388 } else if (rdlen % BRCMF_SDALIGN) {
4389 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
4390 }
4391
4392 /* Satisfy length-alignment requirements */
4393 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4394 rdlen = roundup(rdlen, ALIGNMENT);
4395
4396 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4397 /* Too long -- skip this frame */
4398 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4399 __func__, len, rdlen));
4400 bus->drvr->rx_errors++;
4401 bus->rx_toolong++;
4402 brcmf_sdbrcm_rxfail(bus, false, false);
4403 continue;
4404 }
4405
4406 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + BRCMF_SDALIGN);
4407 if (!pkt) {
4408 /* Give up on data, request rtx of events */
4409 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4410 " chan %d\n", __func__, rdlen, chan));
4411 bus->drvr->rx_dropped++;
4412 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
4413 continue;
4414 }
4415
4416 ASSERT(!(pkt->prev));
4417
4418 /* Leave room for what we already read, and align remainder */
4419 ASSERT(firstread < pkt->len);
4420 skb_pull(pkt, firstread);
4421 PKTALIGN(pkt, rdlen, BRCMF_SDALIGN);
4422
4423 /* Read the remaining frame data */
4424 sdret = brcmf_sdcard_recv_buf(card,
4425 brcmf_sdcard_cur_sbwad(card),
4426 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
4427 rdlen, pkt, NULL, NULL);
4428 bus->f2rxdata++;
4429 ASSERT(sdret != -BCME_PENDING);
4430
4431 if (sdret < 0) {
4432 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4433 __func__, rdlen,
4434 ((chan ==
4435 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4436 SDPCM_DATA_CHANNEL)
4437 ? "data" : "test")),
4438 sdret));
4439 brcmu_pkt_buf_free_skb(pkt);
4440 bus->drvr->rx_errors++;
4441 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
4442 continue;
4443 }
4444
4445 /* Copy the already-read portion */
4446 skb_push(pkt, firstread);
4447 memcpy(pkt->data, bus->rxhdr, firstread);
4448
4449 #ifdef BCMDBG
4450 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4451 printk(KERN_DEBUG "Rx Data:\n");
4452 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4453 pkt->data, len);
4454 }
4455 #endif
4456
4457 deliver:
4458 /* Save superframe descriptor and allocate packet frame */
4459 if (chan == SDPCM_GLOM_CHANNEL) {
4460 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4461 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4462 __func__, len));
4463 #ifdef BCMDBG
4464 if (DHD_GLOM_ON()) {
4465 printk(KERN_DEBUG "Glom Data:\n");
4466 print_hex_dump_bytes("",
4467 DUMP_PREFIX_OFFSET,
4468 pkt->data, len);
4469 }
4470 #endif
4471 __skb_trim(pkt, len);
4472 ASSERT(doff == SDPCM_HDRLEN);
4473 skb_pull(pkt, SDPCM_HDRLEN);
4474 bus->glomd = pkt;
4475 } else {
4476 DHD_ERROR(("%s: glom superframe w/o "
4477 "descriptor!\n", __func__));
4478 brcmf_sdbrcm_rxfail(bus, false, false);
4479 }
4480 continue;
4481 }
4482
4483 /* Fill in packet len and prio, deliver upward */
4484 __skb_trim(pkt, len);
4485 skb_pull(pkt, doff);
4486
4487 #ifdef SDTEST
4488 /* Test channel packets are processed separately */
4489 if (chan == SDPCM_TEST_CHANNEL) {
4490 brcmf_sdbrcm_checkdied(bus, pkt, seq);
4491 continue;
4492 }
4493 #endif /* SDTEST */
4494
4495 if (pkt->len == 0) {
4496 brcmu_pkt_buf_free_skb(pkt);
4497 continue;
4498 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
4499 DHD_ERROR(("%s: rx protocol error\n", __func__));
4500 brcmu_pkt_buf_free_skb(pkt);
4501 bus->drvr->rx_errors++;
4502 continue;
4503 }
4504
4505 /* Unlock during rx call */
4506 brcmf_sdbrcm_sdunlock(bus);
4507 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
4508 brcmf_sdbrcm_sdlock(bus);
4509 }
4510 rxcount = maxframes - rxleft;
4511 #ifdef BCMDBG
4512 /* Message if we hit the limit */
4513 if (!rxleft && !sdtest)
4514 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4515 maxframes));
4516 else
4517 #endif /* BCMDBG */
4518 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4519 /* Back off rxseq if awaiting rtx, update rx_seq */
4520 if (bus->rxskip)
4521 rxseq--;
4522 bus->rx_seq = rxseq;
4523
4524 return rxcount;
4525 }
4526
4527 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
4528 {
4529 u32 intstatus = 0;
4530 u32 hmb_data;
4531 u8 fcbits;
4532 uint retries = 0;
4533
4534 DHD_TRACE(("%s: Enter\n", __func__));
4535
4536 /* Read mailbox data and ack that we did so */
4537 r_sdreg32(bus, &hmb_data,
4538 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
4539
4540 if (retries <= retry_limit)
4541 w_sdreg32(bus, SMB_INT_ACK,
4542 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
4543 bus->f1regdata += 2;
4544
4545 /* Dongle recomposed rx frames, accept them again */
4546 if (hmb_data & HMB_DATA_NAKHANDLED) {
4547 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4548 bus->rx_seq));
4549 if (!bus->rxskip)
4550 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4551
4552 bus->rxskip = false;
4553 intstatus |= I_HMB_FRAME_IND;
4554 }
4555
4556 /*
4557 * DEVREADY does not occur with gSPI.
4558 */
4559 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4560 bus->sdpcm_ver =
4561 (hmb_data & HMB_DATA_VERSION_MASK) >>
4562 HMB_DATA_VERSION_SHIFT;
4563 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4564 DHD_ERROR(("Version mismatch, dongle reports %d, "
4565 "expecting %d\n",
4566 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4567 else
4568 DHD_INFO(("Dongle ready, protocol version %d\n",
4569 bus->sdpcm_ver));
4570 }
4571
4572 /*
4573 * Flow Control has been moved into the RX headers and this out of band
4574 * method isn't used any more.
4575 * remaining backward compatible with older dongles.
4576 */
4577 if (hmb_data & HMB_DATA_FC) {
4578 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4579 HMB_DATA_FCDATA_SHIFT;
4580
4581 if (fcbits & ~bus->flowcontrol)
4582 bus->fc_xoff++;
4583
4584 if (bus->flowcontrol & ~fcbits)
4585 bus->fc_xon++;
4586
4587 bus->fc_rcvd++;
4588 bus->flowcontrol = fcbits;
4589 }
4590
4591 /* Shouldn't be any others */
4592 if (hmb_data & ~(HMB_DATA_DEVREADY |
4593 HMB_DATA_NAKHANDLED |
4594 HMB_DATA_FC |
4595 HMB_DATA_FWREADY |
4596 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4597 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4598 }
4599
4600 return intstatus;
4601 }
4602
4603 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
4604 {
4605 struct brcmf_sdio_card *card = bus->card;
4606 u32 intstatus, newstatus = 0;
4607 uint retries = 0;
4608 uint rxlimit = brcmf_rxbound; /* Rx frames to read before resched */
4609 uint txlimit = brcmf_txbound; /* Tx frames to send before resched */
4610 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4611 bool rxdone = true; /* Flag for no more read data */
4612 bool resched = false; /* Flag indicating resched wanted */
4613
4614 DHD_TRACE(("%s: Enter\n", __func__));
4615
4616 /* Start with leftover status bits */
4617 intstatus = bus->intstatus;
4618
4619 brcmf_sdbrcm_sdlock(bus);
4620
4621 /* If waiting for HTAVAIL, check status */
4622 if (bus->clkstate == CLK_PENDING) {
4623 int err;
4624 u8 clkctl, devctl = 0;
4625
4626 #ifdef BCMDBG
4627 /* Check for inconsistent device control */
4628 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
4629 SBSDIO_DEVICE_CTL, &err);
4630 if (err) {
4631 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4632 __func__, err));
4633 bus->drvr->busstate = DHD_BUS_DOWN;
4634 } else {
4635 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4636 }
4637 #endif /* BCMDBG */
4638
4639 /* Read CSR, if clock on switch to AVAIL, else ignore */
4640 clkctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
4641 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4642 if (err) {
4643 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4644 err));
4645 bus->drvr->busstate = DHD_BUS_DOWN;
4646 }
4647
4648 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4649 clkctl));
4650
4651 if (SBSDIO_HTAV(clkctl)) {
4652 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
4653 SBSDIO_DEVICE_CTL, &err);
4654 if (err) {
4655 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4656 __func__, err));
4657 bus->drvr->busstate = DHD_BUS_DOWN;
4658 }
4659 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4660 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
4661 SBSDIO_DEVICE_CTL, devctl, &err);
4662 if (err) {
4663 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4664 __func__, err));
4665 bus->drvr->busstate = DHD_BUS_DOWN;
4666 }
4667 bus->clkstate = CLK_AVAIL;
4668 } else {
4669 goto clkwait;
4670 }
4671 }
4672
4673 BUS_WAKE(bus);
4674
4675 /* Make sure backplane clock is on */
4676 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
4677 if (bus->clkstate == CLK_PENDING)
4678 goto clkwait;
4679
4680 /* Pending interrupt indicates new device status */
4681 if (bus->ipend) {
4682 bus->ipend = false;
4683 r_sdreg32(bus, &newstatus,
4684 offsetof(struct sdpcmd_regs, intstatus), &retries);
4685 bus->f1regdata++;
4686 if (brcmf_sdcard_regfail(bus->card))
4687 newstatus = 0;
4688 newstatus &= bus->hostintmask;
4689 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4690 if (newstatus) {
4691 w_sdreg32(bus, newstatus,
4692 offsetof(struct sdpcmd_regs, intstatus),
4693 &retries);
4694 bus->f1regdata++;
4695 }
4696 }
4697
4698 /* Merge new bits with previous */
4699 intstatus |= newstatus;
4700 bus->intstatus = 0;
4701
4702 /* Handle flow-control change: read new state in case our ack
4703 * crossed another change interrupt. If change still set, assume
4704 * FC ON for safety, let next loop through do the debounce.
4705 */
4706 if (intstatus & I_HMB_FC_CHANGE) {
4707 intstatus &= ~I_HMB_FC_CHANGE;
4708 w_sdreg32(bus, I_HMB_FC_CHANGE,
4709 offsetof(struct sdpcmd_regs, intstatus), &retries);
4710
4711 r_sdreg32(bus, &newstatus,
4712 offsetof(struct sdpcmd_regs, intstatus), &retries);
4713 bus->f1regdata += 2;
4714 bus->fcstate =
4715 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4716 intstatus |= (newstatus & bus->hostintmask);
4717 }
4718
4719 /* Handle host mailbox indication */
4720 if (intstatus & I_HMB_HOST_INT) {
4721 intstatus &= ~I_HMB_HOST_INT;
4722 intstatus |= brcmf_sdbrcm_hostmail(bus);
4723 }
4724
4725 /* Generally don't ask for these, can get CRC errors... */
4726 if (intstatus & I_WR_OOSYNC) {
4727 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4728 intstatus &= ~I_WR_OOSYNC;
4729 }
4730
4731 if (intstatus & I_RD_OOSYNC) {
4732 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4733 intstatus &= ~I_RD_OOSYNC;
4734 }
4735
4736 if (intstatus & I_SBINT) {
4737 DHD_ERROR(("Dongle reports SBINT\n"));
4738 intstatus &= ~I_SBINT;
4739 }
4740
4741 /* Would be active due to wake-wlan in gSPI */
4742 if (intstatus & I_CHIPACTIVE) {
4743 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4744 intstatus &= ~I_CHIPACTIVE;
4745 }
4746
4747 /* Ignore frame indications if rxskip is set */
4748 if (bus->rxskip)
4749 intstatus &= ~I_HMB_FRAME_IND;
4750
4751 /* On frame indication, read available frames */
4752 if (PKT_AVAILABLE()) {
4753 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
4754 if (rxdone || bus->rxskip)
4755 intstatus &= ~I_HMB_FRAME_IND;
4756 rxlimit -= min(framecnt, rxlimit);
4757 }
4758
4759 /* Keep still-pending events for next scheduling */
4760 bus->intstatus = intstatus;
4761
4762 clkwait:
4763 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4764 * or clock availability. (Allows tx loop to check ipend if desired.)
4765 * (Unless register access seems hosed, as we may not be able to ACK...)
4766 */
4767 if (bus->intr && bus->intdis && !brcmf_sdcard_regfail(card)) {
4768 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4769 __func__, rxdone, framecnt));
4770 bus->intdis = false;
4771 brcmf_sdcard_intr_enable(card);
4772 }
4773
4774 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4775 (bus->clkstate == CLK_AVAIL)) {
4776 int ret, i;
4777
4778 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(card),
4779 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
4780 (u32) bus->ctrl_frame_len, NULL, NULL, NULL);
4781 ASSERT(ret != -BCME_PENDING);
4782
4783 if (ret < 0) {
4784 /* On failure, abort the command and
4785 terminate the frame */
4786 DHD_INFO(("%s: sdio error %d, abort command and "
4787 "terminate frame.\n", __func__, ret));
4788 bus->tx_sderrs++;
4789
4790 brcmf_sdcard_abort(card, SDIO_FUNC_2);
4791
4792 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1,
4793 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4794 NULL);
4795 bus->f1regdata++;
4796
4797 for (i = 0; i < 3; i++) {
4798 u8 hi, lo;
4799 hi = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
4800 SBSDIO_FUNC1_WFRAMEBCHI,
4801 NULL);
4802 lo = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
4803 SBSDIO_FUNC1_WFRAMEBCLO,
4804 NULL);
4805 bus->f1regdata += 2;
4806 if ((hi == 0) && (lo == 0))
4807 break;
4808 }
4809
4810 }
4811 if (ret == 0)
4812 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4813
4814 DHD_INFO(("Return_dpc value is : %d\n", ret));
4815 bus->ctrl_frame_stat = false;
4816 brcmf_sdbrcm_wait_event_wakeup(bus);
4817 }
4818 /* Send queued frames (limit 1 if rx may still be pending) */
4819 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4820 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4821 && DATAOK(bus)) {
4822 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4823 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
4824 txlimit -= framecnt;
4825 }
4826
4827 /* Resched if events or tx frames are pending,
4828 else await next interrupt */
4829 /* On failed register access, all bets are off:
4830 no resched or interrupts */
4831 if ((bus->drvr->busstate == DHD_BUS_DOWN) ||
4832 brcmf_sdcard_regfail(card)) {
4833 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4834 "operation %d\n", __func__,
4835 brcmf_sdcard_regfail(card)));
4836 bus->drvr->busstate = DHD_BUS_DOWN;
4837 bus->intstatus = 0;
4838 } else if (bus->clkstate == CLK_PENDING) {
4839 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4840 "I_CHIPACTIVE interrupt\n", __func__));
4841 resched = true;
4842 } else if (bus->intstatus || bus->ipend ||
4843 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4844 && DATAOK(bus)) || PKT_AVAILABLE()) {
4845 resched = true;
4846 }
4847
4848 bus->dpc_sched = resched;
4849
4850 /* If we're done for now, turn off clock request. */
4851 if ((bus->clkstate != CLK_PENDING)
4852 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
4853 bus->activity = false;
4854 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4855 }
4856
4857 brcmf_sdbrcm_sdunlock(bus);
4858
4859 return resched;
4860 }
4861
4862 void brcmf_sdbrcm_isr(void *arg)
4863 {
4864 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
4865 struct brcmf_sdio_card *card;
4866
4867 DHD_TRACE(("%s: Enter\n", __func__));
4868
4869 if (!bus) {
4870 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4871 return;
4872 }
4873 card = bus->card;
4874
4875 if (bus->drvr->busstate == DHD_BUS_DOWN) {
4876 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4877 __func__));
4878 return;
4879 }
4880 /* Count the interrupt call */
4881 bus->intrcount++;
4882 bus->ipend = true;
4883
4884 /* Shouldn't get this interrupt if we're sleeping? */
4885 if (bus->sleeping) {
4886 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4887 return;
4888 }
4889
4890 /* Disable additional interrupts (is this needed now)? */
4891 if (bus->intr)
4892 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4893 else
4894 DHD_ERROR(("brcmf_sdbrcm_isr() w/o interrupt configured!\n"));
4895
4896 brcmf_sdcard_intr_disable(card);
4897 bus->intdis = true;
4898
4899 #if defined(SDIO_ISR_THREAD)
4900 DHD_TRACE(("Calling brcmf_sdbrcm_dpc() from %s\n", __func__));
4901 while (brcmf_sdbrcm_dpc(bus))
4902 ;
4903 #else
4904 bus->dpc_sched = true;
4905 brcmf_sdbrcm_sched_dpc(bus);
4906 #endif
4907
4908 }
4909
4910 #ifdef SDTEST
4911 static void brcmf_sdbrcm_pktgen_init(struct brcmf_bus *bus)
4912 {
4913 /* Default to specified length, or full range */
4914 if (brcmf_pktgen_len) {
4915 bus->pktgen_maxlen = min(brcmf_pktgen_len,
4916 BRCMF_MAX_PKTGEN_LEN);
4917 bus->pktgen_minlen = bus->pktgen_maxlen;
4918 } else {
4919 bus->pktgen_maxlen = BRCMF_MAX_PKTGEN_LEN;
4920 bus->pktgen_minlen = 0;
4921 }
4922 bus->pktgen_len = (u16) bus->pktgen_minlen;
4923
4924 /* Default to per-watchdog burst with 10s print time */
4925 bus->pktgen_freq = 1;
4926 bus->pktgen_print = 10000 / brcmf_watchdog_ms;
4927 bus->pktgen_count = (brcmf_pktgen * brcmf_watchdog_ms + 999) / 1000;
4928
4929 /* Default to echo mode */
4930 bus->pktgen_mode = BRCMF_PKTGEN_ECHO;
4931 bus->pktgen_stop = 1;
4932 }
4933
4934 static void brcmf_sdbrcm_pktgen(struct brcmf_bus *bus)
4935 {
4936 struct sk_buff *pkt;
4937 u8 *data;
4938 uint pktcount;
4939 uint fillbyte;
4940 u16 len;
4941
4942 /* Display current count if appropriate */
4943 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4944 bus->pktgen_ptick = 0;
4945 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4946 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4947 }
4948
4949 /* For recv mode, just make sure dongle has started sending */
4950 if (bus->pktgen_mode == BRCMF_PKTGEN_RECV) {
4951 if (!bus->pktgen_rcvd)
4952 brcmf_sdbrcm_sdtest_set(bus, true);
4953 return;
4954 }
4955
4956 /* Otherwise, generate or request the specified number of packets */
4957 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4958 /* Stop if total has been reached */
4959 if (bus->pktgen_total
4960 && (bus->pktgen_sent >= bus->pktgen_total)) {
4961 bus->pktgen_count = 0;
4962 break;
4963 }
4964
4965 /* Allocate an appropriate-sized packet */
4966 len = bus->pktgen_len;
4967 pkt = brcmu_pkt_buf_get_skb(
4968 len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + BRCMF_SDALIGN,
4969 true);
4970 if (!pkt) {
4971 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4972 __func__));
4973 break;
4974 }
4975 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4976 BRCMF_SDALIGN);
4977 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4978
4979 /* Write test header cmd and extra based on mode */
4980 switch (bus->pktgen_mode) {
4981 case BRCMF_PKTGEN_ECHO:
4982 *data++ = SDPCM_TEST_ECHOREQ;
4983 *data++ = (u8) bus->pktgen_sent;
4984 break;
4985
4986 case BRCMF_PKTGEN_SEND:
4987 *data++ = SDPCM_TEST_DISCARD;
4988 *data++ = (u8) bus->pktgen_sent;
4989 break;
4990
4991 case BRCMF_PKTGEN_RXBURST:
4992 *data++ = SDPCM_TEST_BURST;
4993 *data++ = (u8) bus->pktgen_count;
4994 break;
4995
4996 default:
4997 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4998 bus->pktgen_mode));
4999 brcmu_pkt_buf_free_skb(pkt, true);
5000 bus->pktgen_count = 0;
5001 return;
5002 }
5003
5004 /* Write test header length field */
5005 *data++ = (len >> 0);
5006 *data++ = (len >> 8);
5007
5008 /* Then fill in the remainder -- N/A for burst,
5009 but who cares... */
5010 for (fillbyte = 0; fillbyte < len; fillbyte++)
5011 *data++ =
5012 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
5013
5014 #ifdef BCMDBG
5015 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
5016 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
5017 printk(KERN_DEBUG "brcmf_sdbrcm_pktgen: Tx Data:\n");
5018 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
5019 pkt->len - SDPCM_HDRLEN);
5020 }
5021 #endif
5022
5023 /* Send it */
5024 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
5025 bus->pktgen_fail++;
5026 if (bus->pktgen_stop
5027 && bus->pktgen_stop == bus->pktgen_fail)
5028 bus->pktgen_count = 0;
5029 }
5030 bus->pktgen_sent++;
5031
5032 /* Bump length if not fixed, wrap at max */
5033 if (++bus->pktgen_len > bus->pktgen_maxlen)
5034 bus->pktgen_len = (u16) bus->pktgen_minlen;
5035
5036 /* Special case for burst mode: just send one request! */
5037 if (bus->pktgen_mode == BRCMF_PKTGEN_RXBURST)
5038 break;
5039 }
5040 }
5041
5042 static void brcmf_sdbrcm_sdtest_set(struct brcmf_bus *bus, bool start)
5043 {
5044 struct sk_buff *pkt;
5045 u8 *data;
5046
5047 /* Allocate the packet */
5048 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
5049 BRCMF_SDALIGN, true);
5050 if (!pkt) {
5051 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
5052 return;
5053 }
5054 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), BRCMF_SDALIGN);
5055 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
5056
5057 /* Fill in the test header */
5058 *data++ = SDPCM_TEST_SEND;
5059 *data++ = start;
5060 *data++ = (bus->pktgen_maxlen >> 0);
5061 *data++ = (bus->pktgen_maxlen >> 8);
5062
5063 /* Send it */
5064 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
5065 bus->pktgen_fail++;
5066 }
5067
5068 static void
5069 brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, struct sk_buff *pkt, uint seq)
5070 {
5071 u8 *data;
5072 uint pktlen;
5073
5074 u8 cmd;
5075 u8 extra;
5076 u16 len;
5077 u16 offset;
5078
5079 /* Check for min length */
5080 pktlen = pkt->len;
5081 if (pktlen < SDPCM_TEST_HDRLEN) {
5082 DHD_ERROR(("brcmf_sdbrcm_checkdied: toss runt frame, pktlen "
5083 "%d\n", pktlen));
5084 brcmu_pkt_buf_free_skb(pkt, false);
5085 return;
5086 }
5087
5088 /* Extract header fields */
5089 data = pkt->data;
5090 cmd = *data++;
5091 extra = *data++;
5092 len = *data++;
5093 len += *data++ << 8;
5094
5095 /* Check length for relevant commands */
5096 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
5097 || cmd == SDPCM_TEST_ECHORSP) {
5098 if (pktlen != len + SDPCM_TEST_HDRLEN) {
5099 DHD_ERROR(("brcmf_sdbrcm_checkdied: frame length "
5100 "mismatch, pktlen %d seq %d" " cmd %d extra %d "
5101 "len %d\n",
5102 pktlen, seq, cmd, extra, len));
5103 brcmu_pkt_buf_free_skb(pkt, false);
5104 return;
5105 }
5106 }
5107
5108 /* Process as per command */
5109 switch (cmd) {
5110 case SDPCM_TEST_ECHOREQ:
5111 /* Rx->Tx turnaround ok (even on NDIS w/current
5112 implementation) */
5113 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
5114 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0)
5115 bus->pktgen_sent++;
5116 else {
5117 bus->pktgen_fail++;
5118 brcmu_pkt_buf_free_skb(pkt, false);
5119 }
5120 bus->pktgen_rcvd++;
5121 break;
5122
5123 case SDPCM_TEST_ECHORSP:
5124 if (bus->ext_loop) {
5125 brcmu_pkt_buf_free_skb(pkt, false);
5126 bus->pktgen_rcvd++;
5127 break;
5128 }
5129
5130 for (offset = 0; offset < len; offset++, data++) {
5131 if (*data != SDPCM_TEST_FILL(offset, extra)) {
5132 DHD_ERROR(("brcmf_sdbrcm_checkdied: echo data "
5133 "mismatch: " "offset %d (len %d) "
5134 "expect 0x%02x rcvd 0x%02x\n",
5135 offset, len,
5136 SDPCM_TEST_FILL(offset, extra),
5137 *data));
5138 break;
5139 }
5140 }
5141 brcmu_pkt_buf_free_skb(pkt, false);
5142 bus->pktgen_rcvd++;
5143 break;
5144
5145 case SDPCM_TEST_DISCARD:
5146 brcmu_pkt_buf_free_skb(pkt, false);
5147 bus->pktgen_rcvd++;
5148 break;
5149
5150 case SDPCM_TEST_BURST:
5151 case SDPCM_TEST_SEND:
5152 default:
5153 DHD_INFO(("brcmf_sdbrcm_checkdied: unsupported or unknown "
5154 "command, pktlen %d seq %d" " cmd %d extra %d len %d\n",
5155 pktlen, seq, cmd, extra, len));
5156 brcmu_pkt_buf_free_skb(pkt, false);
5157 break;
5158 }
5159
5160 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5161 if (bus->pktgen_mode == BRCMF_PKTGEN_RECV) {
5162 if (bus->pktgen_total
5163 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5164 bus->pktgen_count = 0;
5165 brcmf_sdbrcm_sdtest_set(bus, false);
5166 }
5167 }
5168 }
5169 #endif /* SDTEST */
5170
5171 extern bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
5172 {
5173 struct brcmf_bus *bus;
5174
5175 DHD_TIMER(("%s: Enter\n", __func__));
5176
5177 bus = drvr->bus;
5178
5179 if (bus->drvr->dongle_reset)
5180 return false;
5181
5182 /* Ignore the timer if simulating bus down */
5183 if (bus->sleeping)
5184 return false;
5185
5186 brcmf_sdbrcm_sdlock(bus);
5187
5188 /* Poll period: check device if appropriate. */
5189 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5190 u32 intstatus = 0;
5191
5192 /* Reset poll tick */
5193 bus->polltick = 0;
5194
5195 /* Check device if no interrupts */
5196 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5197
5198 if (!bus->dpc_sched) {
5199 u8 devpend;
5200 devpend = brcmf_sdcard_cfg_read(bus->card,
5201 SDIO_FUNC_0, SDIO_CCCR_INTx,
5202 NULL);
5203 intstatus =
5204 devpend & (INTR_STATUS_FUNC1 |
5205 INTR_STATUS_FUNC2);
5206 }
5207
5208 /* If there is something, make like the ISR and
5209 schedule the DPC */
5210 if (intstatus) {
5211 bus->pollcnt++;
5212 bus->ipend = true;
5213 if (bus->intr)
5214 brcmf_sdcard_intr_disable(bus->card);
5215
5216 bus->dpc_sched = true;
5217 brcmf_sdbrcm_sched_dpc(bus);
5218
5219 }
5220 }
5221
5222 /* Update interrupt tracking */
5223 bus->lastintrs = bus->intrcount;
5224 }
5225 #ifdef BCMDBG
5226 /* Poll for console output periodically */
5227 if (drvr->busstate == DHD_BUS_DATA && brcmf_console_ms != 0) {
5228 bus->console.count += brcmf_watchdog_ms;
5229 if (bus->console.count >= brcmf_console_ms) {
5230 bus->console.count -= brcmf_console_ms;
5231 /* Make sure backplane clock is on */
5232 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5233 if (brcmf_sdbrcm_readconsole(bus) < 0)
5234 brcmf_console_ms = 0; /* On error,
5235 stop trying */
5236 }
5237 }
5238 #endif /* BCMDBG */
5239
5240 #ifdef SDTEST
5241 /* Generate packets if configured */
5242 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5243 /* Make sure backplane clock is on */
5244 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5245 bus->pktgen_tick = 0;
5246 brcmf_sdbrcm_pktgen(bus);
5247 }
5248 #endif
5249
5250 /* On idle timeout clear activity flag and/or turn off clock */
5251 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5252 if (++bus->idlecount >= bus->idletime) {
5253 bus->idlecount = 0;
5254 if (bus->activity) {
5255 bus->activity = false;
5256 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
5257 } else {
5258 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5259 }
5260 }
5261 }
5262
5263 brcmf_sdbrcm_sdunlock(bus);
5264
5265 return bus->ipend;
5266 }
5267
5268 #ifdef BCMDBG
5269 static int brcmf_sdbrcm_bus_console_in(struct brcmf_pub *drvr,
5270 unsigned char *msg, uint msglen)
5271 {
5272 struct brcmf_bus *bus = drvr->bus;
5273 u32 addr, val;
5274 int rv;
5275 struct sk_buff *pkt;
5276
5277 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5278 if (bus->console_addr == 0)
5279 return -ENOTSUPP;
5280
5281 /* Exclusive bus access */
5282 brcmf_sdbrcm_sdlock(bus);
5283
5284 /* Don't allow input if dongle is in reset */
5285 if (bus->drvr->dongle_reset) {
5286 brcmf_sdbrcm_sdunlock(bus);
5287 return -EPERM;
5288 }
5289
5290 /* Request clock to allow SDIO accesses */
5291 BUS_WAKE(bus);
5292 /* No pend allowed since txpkt is called later, ht clk has to be on */
5293 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5294
5295 /* Zero cbuf_index */
5296 addr = bus->console_addr + offsetof(struct rte_console, cbuf_idx);
5297 val = cpu_to_le32(0);
5298 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5299 if (rv < 0)
5300 goto done;
5301
5302 /* Write message into cbuf */
5303 addr = bus->console_addr + offsetof(struct rte_console, cbuf);
5304 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)msg, msglen);
5305 if (rv < 0)
5306 goto done;
5307
5308 /* Write length into vcons_in */
5309 addr = bus->console_addr + offsetof(struct rte_console, vcons_in);
5310 val = cpu_to_le32(msglen);
5311 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5312 if (rv < 0)
5313 goto done;
5314
5315 /* Bump dongle by sending an empty event pkt.
5316 * sdpcm_sendup (RX) checks for virtual console input.
5317 */
5318 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5319 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5320 brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5321
5322 done:
5323 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5324 bus->activity = false;
5325 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
5326 }
5327
5328 brcmf_sdbrcm_sdunlock(bus);
5329
5330 return rv;
5331 }
5332 #endif /* BCMDBG */
5333
5334 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
5335 {
5336 if (chipid == BCM4325_CHIP_ID)
5337 return true;
5338 if (chipid == BCM4329_CHIP_ID)
5339 return true;
5340 if (chipid == BCM4319_CHIP_ID)
5341 return true;
5342 return false;
5343 }
5344
5345 static void *brcmf_sdbrcm_probe(u16 venid, u16 devid, u16 bus_no,
5346 u16 slot, u16 func, uint bustype, u32 regsva,
5347 void *card)
5348 {
5349 int ret;
5350 struct brcmf_bus *bus;
5351
5352 /* Init global variables at run-time, not as part of the declaration.
5353 * This is required to support init/de-init of the driver.
5354 * Initialization
5355 * of globals as part of the declaration results in non-deterministic
5356 * behavior since the value of the globals may be different on the
5357 * first time that the driver is initialized vs subsequent
5358 * initializations.
5359 */
5360 brcmf_txbound = DHD_TXBOUND;
5361 brcmf_rxbound = DHD_RXBOUND;
5362 brcmf_alignctl = true;
5363 sd1idle = true;
5364 brcmf_readahead = true;
5365 retrydata = false;
5366 brcmf_dongle_memsize = 0;
5367 dhd_txminmax = DHD_TXMINMAX;
5368
5369 forcealign = true;
5370
5371 brcmf_c_init();
5372
5373 DHD_TRACE(("%s: Enter\n", __func__));
5374 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5375
5376 /* We make assumptions about address window mappings */
5377 ASSERT(regsva == SI_ENUM_BASE);
5378
5379 /* SDIO car passes venid and devid based on CIS parsing -- but
5380 * low-power start
5381 * means early parse could fail, so here we should get either an ID
5382 * we recognize OR (-1) indicating we must request power first.
5383 */
5384 /* Check the Vendor ID */
5385 switch (venid) {
5386 case 0x0000:
5387 case PCI_VENDOR_ID_BROADCOM:
5388 break;
5389 default:
5390 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5391 return NULL;
5392 }
5393
5394 /* Check the Device ID and make sure it's one that we support */
5395 switch (devid) {
5396 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5397 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5398 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5399 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5400 break;
5401 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5402 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5403 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5404 case 0x4329:
5405 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5406 break;
5407 case BCM4319_D11N_ID: /* 4319 802.11n id */
5408 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5409 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5410 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5411 break;
5412 case 0:
5413 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5414 __func__));
5415 break;
5416
5417 default:
5418 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5419 __func__, venid, devid));
5420 return NULL;
5421 }
5422
5423 /* Allocate private bus interface state */
5424 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
5425 if (!bus) {
5426 DHD_ERROR(("%s: kmalloc of struct dhd_bus failed\n", __func__));
5427 goto fail;
5428 }
5429 bus->card = card;
5430 bus->cl_devid = (u16) devid;
5431 bus->bus = DHD_BUS;
5432 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5433 bus->usebufpool = false; /* Use bufpool if allocated,
5434 else use locally malloced rxbuf */
5435
5436 /* attempt to attach to the dongle */
5437 if (!(brcmf_sdbrcm_probe_attach(bus, card, regsva, devid))) {
5438 DHD_ERROR(("%s: brcmf_sdbrcm_probe_attach failed\n", __func__));
5439 goto fail;
5440 }
5441
5442 spin_lock_init(&bus->txqlock);
5443 init_waitqueue_head(&bus->ctrl_wait);
5444
5445 /* Set up the watchdog timer */
5446 init_timer(&bus->timer);
5447 bus->timer.data = (unsigned long)bus;
5448 bus->timer.function = brcmf_sdbrcm_watchdog;
5449
5450 /* Initialize thread based operation and lock */
5451 if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)) {
5452 bus->threads_only = true;
5453 sema_init(&bus->sdsem, 1);
5454 } else {
5455 bus->threads_only = false;
5456 spin_lock_init(&bus->sdlock);
5457 }
5458
5459 if (brcmf_dpc_prio >= 0) {
5460 /* Initialize watchdog thread */
5461 init_completion(&bus->watchdog_wait);
5462 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
5463 bus, "brcmf_watchdog");
5464 if (IS_ERR(bus->watchdog_tsk)) {
5465 printk(KERN_WARNING
5466 "brcmf_watchdog thread failed to start\n");
5467 bus->watchdog_tsk = NULL;
5468 }
5469 } else
5470 bus->watchdog_tsk = NULL;
5471
5472 /* Set up the bottom half handler */
5473 if (brcmf_dpc_prio >= 0) {
5474 /* Initialize DPC thread */
5475 init_completion(&bus->dpc_wait);
5476 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
5477 bus, "dhd_dpc");
5478 if (IS_ERR(bus->dpc_tsk)) {
5479 printk(KERN_WARNING
5480 "dhd_dpc thread failed to start\n");
5481 bus->dpc_tsk = NULL;
5482 }
5483 } else {
5484 tasklet_init(&bus->tasklet, brcmf_sdbrcm_dpc_tasklet,
5485 (unsigned long)bus);
5486 bus->dpc_tsk = NULL;
5487 }
5488
5489 /* Attach to the dhd/OS/network interface */
5490 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
5491 if (!bus->drvr) {
5492 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5493 goto fail;
5494 }
5495
5496 /* Allocate buffers */
5497 if (!(brcmf_sdbrcm_probe_malloc(bus, card))) {
5498 DHD_ERROR(("%s: brcmf_sdbrcm_probe_malloc failed\n", __func__));
5499 goto fail;
5500 }
5501
5502 if (!(brcmf_sdbrcm_probe_init(bus, card))) {
5503 DHD_ERROR(("%s: brcmf_sdbrcm_probe_init failed\n", __func__));
5504 goto fail;
5505 }
5506
5507 /* Register interrupt callback, but mask it (not operational yet). */
5508 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5509 __func__));
5510 brcmf_sdcard_intr_disable(card);
5511 ret = brcmf_sdcard_intr_reg(card, brcmf_sdbrcm_isr, bus);
5512 if (ret != 0) {
5513 DHD_ERROR(("%s: FAILED: sdcard_intr_reg returned %d\n",
5514 __func__, ret));
5515 goto fail;
5516 }
5517 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5518
5519 DHD_INFO(("%s: completed!!\n", __func__));
5520
5521 /* if firmware path present try to download and bring up bus */
5522 ret = brcmf_bus_start(bus->drvr);
5523 if (ret != 0) {
5524 if (ret == -ENOLINK) {
5525 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5526 goto fail;
5527 }
5528 }
5529 /* Ok, have the per-port tell the stack we're open for business */
5530 if (brcmf_net_attach(bus->drvr, 0) != 0) {
5531 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5532 goto fail;
5533 }
5534
5535 return bus;
5536
5537 fail:
5538 brcmf_sdbrcm_release(bus);
5539 return NULL;
5540 }
5541
5542 static bool
5543 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, void *card, u32 regsva,
5544 u16 devid)
5545 {
5546 u8 clkctl = 0;
5547 int err = 0;
5548
5549 bus->alp_only = true;
5550
5551 /* Return the window to backplane enumeration space for core access */
5552 if (brcmf_sdbrcm_set_siaddr_window(bus, SI_ENUM_BASE))
5553 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5554
5555 #ifdef BCMDBG
5556 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5557 brcmf_sdcard_reg_read(bus->card, SI_ENUM_BASE, 4));
5558
5559 #endif /* BCMDBG */
5560
5561 /*
5562 * Force PLL off until brcmf_sdbrcm_chip_attach()
5563 * programs PLL control regs
5564 */
5565
5566 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5567 DHD_INIT_CLKCTL1, &err);
5568 if (!err)
5569 clkctl =
5570 brcmf_sdcard_cfg_read(card, SDIO_FUNC_1,
5571 SBSDIO_FUNC1_CHIPCLKCSR, &err);
5572
5573 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5574 DHD_ERROR(("brcmf_sdbrcm_probe: ChipClkCSR access: err %d wrote"
5575 " 0x%02x read 0x%02x\n",
5576 err, DHD_INIT_CLKCTL1, clkctl));
5577 goto fail;
5578 }
5579
5580 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
5581 DHD_ERROR(("%s: brcmf_sdbrcm_chip_attach failed!\n", __func__));
5582 goto fail;
5583 }
5584
5585 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
5586 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5587 __func__, bus->ci->chip));
5588 goto fail;
5589 }
5590
5591 brcmf_sdbrcm_sdiod_drive_strength_init(bus, brcmf_sdiod_drive_strength);
5592
5593 /* Get info on the ARM and SOCRAM cores... */
5594 if (!DHD_NOPMU(bus)) {
5595 bus->armrev = SBCOREREV(brcmf_sdcard_reg_read(bus->card,
5596 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5597 bus->orig_ramsize = bus->ci->ramsize;
5598 if (!(bus->orig_ramsize)) {
5599 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5600 __func__));
5601 goto fail;
5602 }
5603 bus->ramsize = bus->orig_ramsize;
5604 if (brcmf_dongle_memsize)
5605 brcmf_sdbrcm_setmemsize(bus, brcmf_dongle_memsize);
5606
5607 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5608 bus->ramsize, bus->orig_ramsize));
5609 }
5610
5611 /* Set core control so an SDIO reset does a backplane reset */
5612 OR_REG(bus->ci->buscorebase + offsetof(struct sdpcmd_regs,
5613 corecontrol),
5614 CC_BPRESEN, u32);
5615
5616 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5617
5618 /* Locate an appropriately-aligned portion of hdrbuf */
5619 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
5620 BRCMF_SDALIGN);
5621
5622 /* Set the poll and/or interrupt flags */
5623 bus->intr = (bool) brcmf_intr;
5624 bus->poll = (bool) brcmf_poll;
5625 if (bus->poll)
5626 bus->pollrate = 1;
5627
5628 return true;
5629
5630 fail:
5631 return false;
5632 }
5633
5634 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus, void *card)
5635 {
5636 DHD_TRACE(("%s: Enter\n", __func__));
5637
5638 if (bus->drvr->maxctl) {
5639 bus->rxblen =
5640 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
5641 ALIGNMENT) + BRCMF_SDALIGN;
5642 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5643 if (!(bus->rxbuf)) {
5644 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5645 __func__, bus->rxblen));
5646 goto fail;
5647 }
5648 }
5649
5650 /* Allocate buffer to receive glomed packet */
5651 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5652 if (!(bus->databuf)) {
5653 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5654 __func__, MAX_DATA_BUF));
5655 /* release rxbuf which was already located as above */
5656 if (!bus->rxblen)
5657 kfree(bus->rxbuf);
5658 goto fail;
5659 }
5660
5661 /* Align the buffer */
5662 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
5663 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
5664 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
5665 else
5666 bus->dataptr = bus->databuf;
5667
5668 return true;
5669
5670 fail:
5671 return false;
5672 }
5673
5674 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus, void *card)
5675 {
5676 s32 fnum;
5677
5678 DHD_TRACE(("%s: Enter\n", __func__));
5679
5680 #ifdef SDTEST
5681 brcmf_sdbrcm_pktgen_init(bus);
5682 #endif /* SDTEST */
5683
5684 /* Disable F2 to clear any intermediate frame state on the dongle */
5685 brcmf_sdcard_cfg_write(card, SDIO_FUNC_0, SDIO_CCCR_IOEx,
5686 SDIO_FUNC_ENABLE_1, NULL);
5687
5688 bus->drvr->busstate = DHD_BUS_DOWN;
5689 bus->sleeping = false;
5690 bus->rxflow = false;
5691 bus->prev_rxlim_hit = 0;
5692
5693 /* Done with backplane-dependent accesses, can drop clock... */
5694 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
5695 NULL);
5696
5697 /* ...and initialize clock/power states */
5698 bus->clkstate = CLK_SDONLY;
5699 bus->idletime = (s32) brcmf_idletime;
5700 bus->idleclock = BRCMF_IDLE_ACTIVE;
5701
5702 /* Query the F2 block size, set roundup accordingly */
5703 fnum = 2;
5704 if (brcmf_sdcard_iovar_op(card, "sd_blocksize", &fnum, sizeof(s32),
5705 &bus->blocksize, sizeof(s32), false) != 0) {
5706 bus->blocksize = 0;
5707 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5708 } else {
5709 DHD_INFO(("%s: Initial value for %s is %d\n",
5710 __func__, "sd_blocksize", bus->blocksize));
5711 }
5712 bus->roundup = min(max_roundup, bus->blocksize);
5713
5714 /* Query if bus module supports packet chaining,
5715 default to use if supported */
5716 if (brcmf_sdcard_iovar_op(card, "sd_rxchain", NULL, 0,
5717 &bus->sd_rxchain, sizeof(s32),
5718 false) != 0) {
5719 bus->sd_rxchain = false;
5720 } else {
5721 DHD_INFO(("%s: bus module (through sdiocard API) %s chaining\n",
5722 __func__,
5723 (bus->sd_rxchain ? "supports" : "does not support")));
5724 }
5725 bus->use_rxchain = (bool) bus->sd_rxchain;
5726
5727 return true;
5728 }
5729
5730 static bool
5731 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus, void *card)
5732 {
5733 bool ret;
5734
5735 /* Download the firmware */
5736 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5737
5738 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
5739
5740 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
5741
5742 return ret;
5743 }
5744
5745 /* Detach and free everything */
5746 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
5747 {
5748 DHD_TRACE(("%s: Enter\n", __func__));
5749
5750 if (bus) {
5751 /* De-register interrupt handler */
5752 brcmf_sdcard_intr_disable(bus->card);
5753 brcmf_sdcard_intr_dereg(bus->card);
5754
5755 if (bus->drvr) {
5756 brcmf_detach(bus->drvr);
5757 brcmf_sdbrcm_release_dongle(bus);
5758 bus->drvr = NULL;
5759 }
5760
5761 brcmf_sdbrcm_release_malloc(bus);
5762
5763 kfree(bus);
5764 }
5765
5766 DHD_TRACE(("%s: Disconnected\n", __func__));
5767 }
5768
5769 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
5770 {
5771 DHD_TRACE(("%s: Enter\n", __func__));
5772
5773 if (bus->drvr && bus->drvr->dongle_reset)
5774 return;
5775
5776 kfree(bus->rxbuf);
5777 bus->rxctl = bus->rxbuf = NULL;
5778 bus->rxlen = 0;
5779
5780 kfree(bus->databuf);
5781 bus->databuf = NULL;
5782 }
5783
5784 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
5785 {
5786 DHD_TRACE(("%s: Enter\n", __func__));
5787
5788 if (bus->drvr && bus->drvr->dongle_reset)
5789 return;
5790
5791 if (bus->ci) {
5792 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5793 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5794 brcmf_sdbrcm_chip_detach(bus);
5795 if (bus->vars && bus->varsz)
5796 kfree(bus->vars);
5797 bus->vars = NULL;
5798 }
5799
5800 DHD_TRACE(("%s: Disconnected\n", __func__));
5801 }
5802
5803 static void brcmf_sdbrcm_disconnect(void *ptr)
5804 {
5805 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
5806
5807 DHD_TRACE(("%s: Enter\n", __func__));
5808
5809 if (bus) {
5810 ASSERT(bus->drvr);
5811 brcmf_sdbrcm_release(bus);
5812 }
5813
5814 DHD_TRACE(("%s: Disconnected\n", __func__));
5815 }
5816
5817 /* Register/Unregister functions are called by the main DHD entry
5818 * point (e.g. module insertion) to link with the bus driver, in
5819 * order to look for or await the device.
5820 */
5821
5822 static struct brcmf_sdioh_driver dhd_sdio = {
5823 brcmf_sdbrcm_probe,
5824 brcmf_sdbrcm_disconnect
5825 };
5826
5827 int brcmf_bus_register(void)
5828 {
5829 DHD_TRACE(("%s: Enter\n", __func__));
5830
5831 /* Sanity check on the module parameters */
5832 do {
5833 /* Both watchdog and DPC as tasklets are ok */
5834 if ((brcmf_watchdog_prio < 0) && (brcmf_dpc_prio < 0))
5835 break;
5836
5837 /* If both watchdog and DPC are threads, TX must be deferred */
5838 if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)
5839 && brcmf_deferred_tx)
5840 break;
5841
5842 DHD_ERROR(("Invalid module parameters.\n"));
5843 return -EINVAL;
5844 } while (0);
5845
5846 return brcmf_sdio_register(&dhd_sdio);
5847 }
5848
5849 void brcmf_bus_unregister(void)
5850 {
5851 DHD_TRACE(("%s: Enter\n", __func__));
5852
5853 brcmf_sdio_unregister();
5854 }
5855
5856 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
5857 {
5858 int offset = 0;
5859 uint len;
5860 u8 *memblock = NULL, *memptr;
5861 int ret;
5862
5863 DHD_INFO(("%s: Enter\n", __func__));
5864
5865 bus->fw_name = BCM4329_FW_NAME;
5866 ret = request_firmware(&bus->firmware, bus->fw_name,
5867 &gInstance->func[2]->dev);
5868 if (ret) {
5869 DHD_ERROR(("%s: Fail to request firmware %d\n", __func__, ret));
5870 return ret;
5871 }
5872 bus->fw_ptr = 0;
5873
5874 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
5875 if (memblock == NULL) {
5876 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5877 __func__, MEMBLOCK));
5878 ret = -ENOMEM;
5879 goto err;
5880 }
5881 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
5882 memptr += (BRCMF_SDALIGN -
5883 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
5884
5885 /* Download image */
5886 while ((len =
5887 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
5888 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
5889 if (ret) {
5890 DHD_ERROR(("%s: error %d on writing %d membytes at "
5891 "0x%08x\n", __func__, ret, MEMBLOCK, offset));
5892 goto err;
5893 }
5894
5895 offset += MEMBLOCK;
5896 }
5897
5898 err:
5899 kfree(memblock);
5900
5901 release_firmware(bus->firmware);
5902 bus->fw_ptr = 0;
5903
5904 return ret;
5905 }
5906
5907 /*
5908 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5909 * and ending in a NUL.
5910 * Removes carriage returns, empty lines, comment lines, and converts
5911 * newlines to NULs.
5912 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5913 * by two NULs.
5914 */
5915
5916 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
5917 {
5918 char *dp;
5919 bool findNewline;
5920 int column;
5921 uint buf_len, n;
5922
5923 dp = varbuf;
5924
5925 findNewline = false;
5926 column = 0;
5927
5928 for (n = 0; n < len; n++) {
5929 if (varbuf[n] == 0)
5930 break;
5931 if (varbuf[n] == '\r')
5932 continue;
5933 if (findNewline && varbuf[n] != '\n')
5934 continue;
5935 findNewline = false;
5936 if (varbuf[n] == '#') {
5937 findNewline = true;
5938 continue;
5939 }
5940 if (varbuf[n] == '\n') {
5941 if (column == 0)
5942 continue;
5943 *dp++ = 0;
5944 column = 0;
5945 continue;
5946 }
5947 *dp++ = varbuf[n];
5948 column++;
5949 }
5950 buf_len = dp - varbuf;
5951
5952 while (dp < varbuf + n)
5953 *dp++ = 0;
5954
5955 return buf_len;
5956 }
5957
5958 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
5959 {
5960 uint len;
5961 char *memblock = NULL;
5962 char *bufp;
5963 int ret;
5964
5965 bus->nv_name = BCM4329_NV_NAME;
5966 ret = request_firmware(&bus->firmware, bus->nv_name,
5967 &gInstance->func[2]->dev);
5968 if (ret) {
5969 DHD_ERROR(("%s: Fail to request nvram %d\n", __func__, ret));
5970 return ret;
5971 }
5972 bus->fw_ptr = 0;
5973
5974 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5975 if (memblock == NULL) {
5976 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5977 __func__, MEMBLOCK));
5978 ret = -ENOMEM;
5979 goto err;
5980 }
5981
5982 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
5983
5984 if (len > 0 && len < MEMBLOCK) {
5985 bufp = (char *)memblock;
5986 bufp[len] = 0;
5987 len = brcmf_process_nvram_vars(bufp, len);
5988 bufp += len;
5989 *bufp++ = 0;
5990 if (len)
5991 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
5992 if (ret)
5993 DHD_ERROR(("%s: error downloading vars: %d\n",
5994 __func__, ret));
5995 } else {
5996 DHD_ERROR(("%s: error reading nvram file: %d\n",
5997 __func__, len));
5998 ret = -EIO;
5999 }
6000
6001 err:
6002 kfree(memblock);
6003
6004 release_firmware(bus->firmware);
6005 bus->fw_ptr = 0;
6006
6007 return ret;
6008 }
6009
6010 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
6011 {
6012 int bcmerror = -1;
6013
6014 /* Keep arm in reset */
6015 if (brcmf_sdbrcm_download_state(bus, true)) {
6016 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
6017 goto err;
6018 }
6019
6020 /* External image takes precedence if specified */
6021 if (brcmf_sdbrcm_download_code_file(bus)) {
6022 DHD_ERROR(("%s: dongle image file download failed\n",
6023 __func__));
6024 goto err;
6025 }
6026
6027 /* EXAMPLE: nvram_array */
6028 /* If a valid nvram_arry is specified as above, it can be passed
6029 down to dongle */
6030 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
6031
6032 /* External nvram takes precedence if specified */
6033 if (brcmf_sdbrcm_download_nvram(bus)) {
6034 DHD_ERROR(("%s: dongle nvram file download failed\n",
6035 __func__));
6036 }
6037
6038 /* Take arm out of reset */
6039 if (brcmf_sdbrcm_download_state(bus, false)) {
6040 DHD_ERROR(("%s: error getting out of ARM core reset\n",
6041 __func__));
6042 goto err;
6043 }
6044
6045 bcmerror = 0;
6046
6047 err:
6048 return bcmerror;
6049 }
6050
6051
6052 static int
6053 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
6054 u8 *buf, uint nbytes, struct sk_buff *pkt,
6055 void (*complete)(void *handle, int status,
6056 bool sync_waiting),
6057 void *handle)
6058 {
6059 return brcmf_sdcard_send_buf
6060 (bus->card, addr, fn, flags, buf, nbytes, pkt, complete,
6061 handle);
6062 }
6063
6064 int brcmf_bus_devreset(struct brcmf_pub *drvr, u8 flag)
6065 {
6066 int bcmerror = 0;
6067 struct brcmf_bus *bus;
6068
6069 bus = drvr->bus;
6070
6071 if (flag == true) {
6072 brcmf_sdbrcm_wd_timer(bus, 0);
6073 if (!bus->drvr->dongle_reset) {
6074 /* Expect app to have torn down any
6075 connection before calling */
6076 /* Stop the bus, disable F2 */
6077 brcmf_sdbrcm_bus_stop(bus, false);
6078
6079 /* Clean tx/rx buffer pointers,
6080 detach from the dongle */
6081 brcmf_sdbrcm_release_dongle(bus);
6082
6083 bus->drvr->dongle_reset = true;
6084 bus->drvr->up = false;
6085
6086 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6087 /* App can now remove power from device */
6088 } else
6089 bcmerror = -EIO;
6090 } else {
6091 /* App must have restored power to device before calling */
6092
6093 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6094
6095 if (bus->drvr->dongle_reset) {
6096 /* Turn on WLAN */
6097
6098 /* Attempt to re-attach & download */
6099 if (brcmf_sdbrcm_probe_attach(bus, bus->card,
6100 SI_ENUM_BASE,
6101 bus->cl_devid)) {
6102 /* Attempt to download binary to the dongle */
6103 if (brcmf_sdbrcm_probe_init(bus, bus->card)) {
6104 /* Re-init bus, enable F2 transfer */
6105 brcmf_sdbrcm_bus_init(bus->drvr, false);
6106
6107 bus->drvr->dongle_reset = false;
6108 bus->drvr->up = true;
6109
6110 DHD_TRACE(("%s: WLAN ON DONE\n",
6111 __func__));
6112 } else
6113 bcmerror = -EIO;
6114 } else
6115 bcmerror = -EIO;
6116 } else {
6117 bcmerror = -EISCONN;
6118 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6119 "is on\n", __func__));
6120 bcmerror = -EIO;
6121 }
6122 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
6123 }
6124 return bcmerror;
6125 }
6126
6127 static int
6128 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_card *card,
6129 struct chip_info *ci, u32 regs)
6130 {
6131 u32 regdata;
6132
6133 /*
6134 * Get CC core rev
6135 * Chipid is assume to be at offset 0 from regs arg
6136 * For different chiptypes or old sdio hosts w/o chipcommon,
6137 * other ways of recognition should be added here.
6138 */
6139 ci->cccorebase = regs;
6140 regdata = brcmf_sdcard_reg_read(card,
6141 CORE_CC_REG(ci->cccorebase, chipid), 4);
6142 ci->chip = regdata & CID_ID_MASK;
6143 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6144
6145 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6146 __func__, ci->chip, ci->chiprev));
6147
6148 /* Address of cores for new chips should be added here */
6149 switch (ci->chip) {
6150 case BCM4329_CHIP_ID:
6151 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6152 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6153 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6154 ci->ramsize = BCM4329_RAMSIZE;
6155 break;
6156 default:
6157 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6158 __func__, ci->chip));
6159 return -ENODEV;
6160 }
6161
6162 regdata = brcmf_sdcard_reg_read(card,
6163 CORE_SB(ci->cccorebase, sbidhigh), 4);
6164 ci->ccrev = SBCOREREV(regdata);
6165
6166 regdata = brcmf_sdcard_reg_read(card,
6167 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6168 ci->pmurev = regdata & PCAP_REV_MASK;
6169
6170 regdata = brcmf_sdcard_reg_read(card,
6171 CORE_SB(ci->buscorebase, sbidhigh), 4);
6172 ci->buscorerev = SBCOREREV(regdata);
6173 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6174
6175 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6176 __func__, ci->ccrev, ci->pmurev,
6177 ci->buscorerev, ci->buscoretype));
6178
6179 /* get chipcommon capabilites */
6180 ci->cccaps = brcmf_sdcard_reg_read(card,
6181 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6182
6183 return 0;
6184 }
6185
6186 static void
6187 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_card *card, u32 corebase)
6188 {
6189 u32 regdata;
6190
6191 regdata = brcmf_sdcard_reg_read(card,
6192 CORE_SB(corebase, sbtmstatelow), 4);
6193 if (regdata & SBTML_RESET)
6194 return;
6195
6196 regdata = brcmf_sdcard_reg_read(card,
6197 CORE_SB(corebase, sbtmstatelow), 4);
6198 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6199 /*
6200 * set target reject and spin until busy is clear
6201 * (preserve core-specific bits)
6202 */
6203 regdata = brcmf_sdcard_reg_read(card,
6204 CORE_SB(corebase, sbtmstatelow), 4);
6205 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatelow), 4,
6206 regdata | SBTML_REJ);
6207
6208 regdata = brcmf_sdcard_reg_read(card,
6209 CORE_SB(corebase, sbtmstatelow), 4);
6210 udelay(1);
6211 SPINWAIT((brcmf_sdcard_reg_read(card,
6212 CORE_SB(corebase, sbtmstatehigh), 4) &
6213 SBTMH_BUSY), 100000);
6214
6215 regdata = brcmf_sdcard_reg_read(card,
6216 CORE_SB(corebase, sbtmstatehigh), 4);
6217 if (regdata & SBTMH_BUSY)
6218 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6219
6220 regdata = brcmf_sdcard_reg_read(card,
6221 CORE_SB(corebase, sbidlow), 4);
6222 if (regdata & SBIDL_INIT) {
6223 regdata = brcmf_sdcard_reg_read(card,
6224 CORE_SB(corebase, sbimstate), 4) |
6225 SBIM_RJ;
6226 brcmf_sdcard_reg_write(card,
6227 CORE_SB(corebase, sbimstate), 4,
6228 regdata);
6229 regdata = brcmf_sdcard_reg_read(card,
6230 CORE_SB(corebase, sbimstate), 4);
6231 udelay(1);
6232 SPINWAIT((brcmf_sdcard_reg_read(card,
6233 CORE_SB(corebase, sbimstate), 4) &
6234 SBIM_BY), 100000);
6235 }
6236
6237 /* set reset and reject while enabling the clocks */
6238 brcmf_sdcard_reg_write(card,
6239 CORE_SB(corebase, sbtmstatelow), 4,
6240 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6241 SBTML_REJ | SBTML_RESET));
6242 regdata = brcmf_sdcard_reg_read(card,
6243 CORE_SB(corebase, sbtmstatelow), 4);
6244 udelay(10);
6245
6246 /* clear the initiator reject bit */
6247 regdata = brcmf_sdcard_reg_read(card,
6248 CORE_SB(corebase, sbidlow), 4);
6249 if (regdata & SBIDL_INIT) {
6250 regdata = brcmf_sdcard_reg_read(card,
6251 CORE_SB(corebase, sbimstate), 4) &
6252 ~SBIM_RJ;
6253 brcmf_sdcard_reg_write(card,
6254 CORE_SB(corebase, sbimstate), 4,
6255 regdata);
6256 }
6257 }
6258
6259 /* leave reset and reject asserted */
6260 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatelow), 4,
6261 (SBTML_REJ | SBTML_RESET));
6262 udelay(1);
6263 }
6264
6265 static int
6266 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
6267 {
6268 struct chip_info *ci;
6269 int err;
6270 u8 clkval, clkset;
6271
6272 DHD_TRACE(("%s: Enter\n", __func__));
6273
6274 /* alloc chip_info_t */
6275 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6276 if (NULL == ci) {
6277 DHD_ERROR(("%s: malloc failed!\n", __func__));
6278 return -ENOMEM;
6279 }
6280
6281 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6282
6283 /* bus/core/clk setup for register access */
6284 /* Try forcing SDIO core to do ALPAvail request only */
6285 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6286 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6287 clkset, &err);
6288 if (err) {
6289 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6290 goto fail;
6291 }
6292
6293 /* If register supported, wait for ALPAvail and then force ALP */
6294 /* This may take up to 15 milliseconds */
6295 clkval = brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_1,
6296 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6297 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6298 SPINWAIT(((clkval =
6299 brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_1,
6300 SBSDIO_FUNC1_CHIPCLKCSR,
6301 NULL)),
6302 !SBSDIO_ALPAV(clkval)),
6303 PMU_MAX_TRANSITION_DLY);
6304 if (!SBSDIO_ALPAV(clkval)) {
6305 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6306 __func__, clkval));
6307 err = -EBUSY;
6308 goto fail;
6309 }
6310 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6311 SBSDIO_FORCE_ALP;
6312 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1,
6313 SBSDIO_FUNC1_CHIPCLKCSR,
6314 clkset, &err);
6315 udelay(65);
6316 } else {
6317 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6318 __func__, clkset, clkval));
6319 err = -EACCES;
6320 goto fail;
6321 }
6322
6323 /* Also, disable the extra SDIO pull-ups */
6324 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP,
6325 0, NULL);
6326
6327 err = brcmf_sdbrcm_chip_recognition(bus->card, ci, regs);
6328 if (err)
6329 goto fail;
6330
6331 /*
6332 * Make sure any on-chip ARM is off (in case strapping is wrong),
6333 * or downloaded code was already running.
6334 */
6335 brcmf_sdbrcm_chip_disablecore(bus->card, ci->armcorebase);
6336
6337 brcmf_sdcard_reg_write(bus->card,
6338 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6339 brcmf_sdcard_reg_write(bus->card,
6340 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6341
6342 /* Disable F2 to clear any intermediate frame state on the dongle */
6343 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6344 SDIO_FUNC_ENABLE_1, NULL);
6345
6346 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6347 clkval = brcmf_sdcard_cfg_read(bus->card, SDIO_FUNC_1,
6348 0, NULL);
6349
6350 /* Done with backplane-dependent accesses, can drop clock... */
6351 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6352 0, NULL);
6353
6354 bus->ci = ci;
6355 return 0;
6356 fail:
6357 bus->ci = NULL;
6358 kfree(ci);
6359 return err;
6360 }
6361
6362 static void
6363 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_card *card, u32 corebase)
6364 {
6365 u32 regdata;
6366
6367 /*
6368 * Must do the disable sequence first to work for
6369 * arbitrary current core state.
6370 */
6371 brcmf_sdbrcm_chip_disablecore(card, corebase);
6372
6373 /*
6374 * Now do the initialization sequence.
6375 * set reset while enabling the clock and
6376 * forcing them on throughout the core
6377 */
6378 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatelow), 4,
6379 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6380 SBTML_RESET);
6381 udelay(1);
6382
6383 regdata = brcmf_sdcard_reg_read(card, CORE_SB(corebase, sbtmstatehigh),
6384 4);
6385 if (regdata & SBTMH_SERR)
6386 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatehigh),
6387 4, 0);
6388
6389 regdata = brcmf_sdcard_reg_read(card, CORE_SB(corebase, sbimstate), 4);
6390 if (regdata & (SBIM_IBE | SBIM_TO))
6391 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbimstate), 4,
6392 regdata & ~(SBIM_IBE | SBIM_TO));
6393
6394 /* clear reset and allow it to propagate throughout the core */
6395 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatelow), 4,
6396 (SICF_FGC << SBTML_SICF_SHIFT) |
6397 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6398 udelay(1);
6399
6400 /* leave clock enabled */
6401 brcmf_sdcard_reg_write(card, CORE_SB(corebase, sbtmstatelow), 4,
6402 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6403 udelay(1);
6404 }
6405
6406 /* SDIO Pad drive strength to select value mappings */
6407 struct sdiod_drive_str {
6408 u8 strength; /* Pad Drive Strength in mA */
6409 u8 sel; /* Chip-specific select value */
6410 };
6411
6412 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6413 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6414 {
6415 4, 0x2}, {
6416 2, 0x3}, {
6417 1, 0x0}, {
6418 0, 0x0}
6419 };
6420
6421 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6422 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6423 {
6424 12, 0x7}, {
6425 10, 0x6}, {
6426 8, 0x5}, {
6427 6, 0x4}, {
6428 4, 0x2}, {
6429 2, 0x1}, {
6430 0, 0x0}
6431 };
6432
6433 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6434 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6435 {
6436 32, 0x7}, {
6437 26, 0x6}, {
6438 22, 0x5}, {
6439 16, 0x4}, {
6440 12, 0x3}, {
6441 8, 0x2}, {
6442 4, 0x1}, {
6443 0, 0x0}
6444 };
6445
6446 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6447
6448 static void
6449 brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus, u32 drivestrength) {
6450 struct sdiod_drive_str *str_tab = NULL;
6451 u32 str_mask = 0;
6452 u32 str_shift = 0;
6453 char chn[8];
6454
6455 if (!(bus->ci->cccaps & CC_CAP_PMU))
6456 return;
6457
6458 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6459 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6460 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6461 str_mask = 0x30000000;
6462 str_shift = 28;
6463 break;
6464 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6465 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6466 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6467 str_mask = 0x00003800;
6468 str_shift = 11;
6469 break;
6470 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6471 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6472 str_mask = 0x00003800;
6473 str_shift = 11;
6474 break;
6475 default:
6476 DHD_ERROR(("No SDIO Drive strength init"
6477 "done for chip %s rev %d pmurev %d\n",
6478 brcmu_chipname(bus->ci->chip, chn, 8),
6479 bus->ci->chiprev, bus->ci->pmurev));
6480 break;
6481 }
6482
6483 if (str_tab != NULL) {
6484 u32 drivestrength_sel = 0;
6485 u32 cc_data_temp;
6486 int i;
6487
6488 for (i = 0; str_tab[i].strength != 0; i++) {
6489 if (drivestrength >= str_tab[i].strength) {
6490 drivestrength_sel = str_tab[i].sel;
6491 break;
6492 }
6493 }
6494
6495 brcmf_sdcard_reg_write(bus->card,
6496 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6497 4, 1);
6498 cc_data_temp = brcmf_sdcard_reg_read(bus->card,
6499 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6500 cc_data_temp &= ~str_mask;
6501 drivestrength_sel <<= str_shift;
6502 cc_data_temp |= drivestrength_sel;
6503 brcmf_sdcard_reg_write(bus->card,
6504 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6505 4, cc_data_temp);
6506
6507 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6508 drivestrength, cc_data_temp));
6509 }
6510 }
6511
6512 static void
6513 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
6514 {
6515 DHD_TRACE(("%s: Enter\n", __func__));
6516
6517 kfree(bus->ci);
6518 bus->ci = NULL;
6519 }
6520
6521 static void
6522 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
6523 {
6524 brcmf_sdbrcm_sdunlock(bus);
6525 wait_event_interruptible_timeout(bus->ctrl_wait,
6526 (*lockvar == false), HZ * 2);
6527 brcmf_sdbrcm_sdlock(bus);
6528 return;
6529 }
6530
6531 static void
6532 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
6533 {
6534 if (waitqueue_active(&bus->ctrl_wait))
6535 wake_up_interruptible(&bus->ctrl_wait);
6536 return;
6537 }
6538
6539 static int
6540 brcmf_sdbrcm_watchdog_thread(void *data)
6541 {
6542 struct brcmf_bus *bus = (struct brcmf_bus *)data;
6543
6544 /* This thread doesn't need any user-level access,
6545 * so get rid of all our resources
6546 */
6547 if (brcmf_watchdog_prio > 0) {
6548 struct sched_param param;
6549 param.sched_priority = (brcmf_watchdog_prio < MAX_RT_PRIO) ?
6550 brcmf_watchdog_prio : (MAX_RT_PRIO - 1);
6551 sched_setscheduler(current, SCHED_FIFO, &param);
6552 }
6553
6554 allow_signal(SIGTERM);
6555 /* Run until signal received */
6556 while (1) {
6557 if (kthread_should_stop())
6558 break;
6559 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
6560 if (bus->drvr->dongle_reset == false)
6561 brcmf_sdbrcm_bus_watchdog(bus->drvr);
6562 /* Count the tick for reference */
6563 bus->drvr->tickcnt++;
6564 } else
6565 break;
6566 }
6567 return 0;
6568 }
6569
6570 static void
6571 brcmf_sdbrcm_watchdog(unsigned long data)
6572 {
6573 struct brcmf_bus *bus = (struct brcmf_bus *)data;
6574
6575 if (brcmf_watchdog_prio >= 0) {
6576 if (bus->watchdog_tsk)
6577 complete(&bus->watchdog_wait);
6578 else
6579 return;
6580 } else {
6581 brcmf_sdbrcm_bus_watchdog(bus->drvr);
6582
6583 /* Count the tick for reference */
6584 bus->drvr->tickcnt++;
6585 }
6586
6587 /* Reschedule the watchdog */
6588 if (bus->wd_timer_valid)
6589 mod_timer(&bus->timer, jiffies + brcmf_watchdog_ms * HZ / 1000);
6590 }
6591
6592 void
6593 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
6594 {
6595 static uint save_ms;
6596
6597 /* don't start the wd until fw is loaded */
6598 if (bus->drvr->busstate == DHD_BUS_DOWN)
6599 return;
6600
6601 /* Totally stop the timer */
6602 if (!wdtick && bus->wd_timer_valid == true) {
6603 del_timer_sync(&bus->timer);
6604 bus->wd_timer_valid = false;
6605 save_ms = wdtick;
6606 return;
6607 }
6608
6609 if (wdtick) {
6610 brcmf_watchdog_ms = (uint) wdtick;
6611
6612 if (save_ms != brcmf_watchdog_ms) {
6613 if (bus->wd_timer_valid == true)
6614 /* Stop timer and restart at new value */
6615 del_timer_sync(&bus->timer);
6616
6617 /* Create timer again when watchdog period is
6618 dynamically changed or in the first instance
6619 */
6620 bus->timer.expires =
6621 jiffies + brcmf_watchdog_ms * HZ / 1000;
6622 add_timer(&bus->timer);
6623
6624 } else {
6625 /* Re arm the timer, at last watchdog period */
6626 mod_timer(&bus->timer,
6627 jiffies + brcmf_watchdog_ms * HZ / 1000);
6628 }
6629
6630 bus->wd_timer_valid = true;
6631 save_ms = wdtick;
6632 }
6633 }
6634
6635 static int brcmf_sdbrcm_dpc_thread(void *data)
6636 {
6637 struct brcmf_bus *bus = (struct brcmf_bus *) data;
6638
6639 /* This thread doesn't need any user-level access,
6640 * so get rid of all our resources
6641 */
6642 if (brcmf_dpc_prio > 0) {
6643 struct sched_param param;
6644 param.sched_priority = (brcmf_dpc_prio < MAX_RT_PRIO) ?
6645 brcmf_dpc_prio : (MAX_RT_PRIO - 1);
6646 sched_setscheduler(current, SCHED_FIFO, &param);
6647 }
6648
6649 allow_signal(SIGTERM);
6650 /* Run until signal received */
6651 while (1) {
6652 if (kthread_should_stop())
6653 break;
6654 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
6655 /* Call bus dpc unless it indicated down
6656 (then clean stop) */
6657 if (bus->drvr->busstate != DHD_BUS_DOWN) {
6658 if (brcmf_sdbrcm_dpc(bus))
6659 complete(&bus->dpc_wait);
6660 } else {
6661 brcmf_sdbrcm_bus_stop(bus, true);
6662 }
6663 } else
6664 break;
6665 }
6666 return 0;
6667 }
6668
6669 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data)
6670 {
6671 struct brcmf_bus *bus = (struct brcmf_bus *) data;
6672
6673 /* Call bus dpc unless it indicated down (then clean stop) */
6674 if (bus->drvr->busstate != DHD_BUS_DOWN) {
6675 if (brcmf_sdbrcm_dpc(bus))
6676 tasklet_schedule(&bus->tasklet);
6677 } else
6678 brcmf_sdbrcm_bus_stop(bus, true);
6679 }
6680
6681 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus)
6682 {
6683 if (bus->dpc_tsk) {
6684 complete(&bus->dpc_wait);
6685 return;
6686 }
6687
6688 tasklet_schedule(&bus->tasklet);
6689 }
6690
6691 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus)
6692 {
6693 if (bus->threads_only)
6694 down(&bus->sdsem);
6695 else
6696 spin_lock_bh(&bus->sdlock);
6697 }
6698
6699 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus)
6700 {
6701 if (bus->threads_only)
6702 up(&bus->sdsem);
6703 else
6704 spin_unlock_bh(&bus->sdlock);
6705 }
6706
6707 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
6708 {
6709 if (bus->firmware->size < bus->fw_ptr + len)
6710 len = bus->firmware->size - bus->fw_ptr;
6711
6712 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
6713 bus->fw_ptr += len;
6714 return len;
6715 }
6716
6717 MODULE_FIRMWARE(BCM4329_FW_NAME);
6718 MODULE_FIRMWARE(BCM4329_NV_NAME);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree